Video output circuit of a dsc decoder, dsc decoder system and video output method

Abstract

The present application relates to the technical field of DSC decoder, and particularly relates to a video output circuit of a DSC decoder, a DSC decoder system and a video output method. The circuit comprises a homologous clock module, a synchronous clock sampling module and a pixel unpacking module. The synchronous clock sampling module is used for sampling the decoding data packet of the one-third pixel clock domain output by the DSC decoder based on the pixel clock signal of the homologous clock module, and storing the sampling decoding data packet on the sampling register of the synchronous clock sampling module. At the same time, an indication signal indicating the validity of the decoding data packet on the sampling register is output. The pixel unpacking module is used for generating a pixel counter based on the indication signal and the pixel clock signal, and unpacking the decoding data packet based on the value of the pixel counter under each beat pixel clock to generate target data. In the scheme, the synchronous clock sampling module replaces the asynchronous FIFO, which can greatly save the chip area and chip cost.

Description

Technical Field

[0001] This invention relates to the field of DSC decoder technology, and in particular to a video output circuit, DSC decoder system, and video output method for a DSC decoder. Background Technology

[0002] Since DSC (Display Stream Compression) decoders typically operate in the one-third pixel clock domain, decoding three pixels per clock cycle, and DSC decoders are usually connected to other video processing modules that typically operate in the pixel clock domain, processing one pixel per clock cycle, a video output circuit is usually designed after the DSC decoder to perform the clock domain conversion in order to convert video image data from the one-third pixel clock domain to the pixel clock domain.

[0003] However, existing DSC decoders typically use asynchronous FIFOs (first-in-first-out data buffers) to convert video data from one-third of the pixel clock domain to the pixel clock domain. To reduce the probability of metastability, asynchronous FIFOs are usually configured with multiple deep registers to slow down the rate of register changes, thereby reducing the probability of reading incorrect data when registers change. This requires more registers and combinational logic, resulting in a larger chip area and higher chip cost for the video output circuitry of existing DSC decoders.

[0004] Therefore, there is an urgent need for a new video output circuit for a DSC decoder. Summary of the Invention

[0005] To address the issues of large chip area and high chip cost required for the video output circuit of existing DSC decoders, embodiments of the present invention provide a video output circuit, a DSC decoder system, and a video output method for a DSC decoder.

[0006] In a first aspect, embodiments of the present invention provide a video output circuit for a DSC decoder, comprising: a synchronous clock module, a synchronous clock sampling module, and a pixel unpacking module; wherein...

[0007] The same source clock module is connected to the DSC decoder, the synchronous clock sampling module, the pixel unpacking module, and other external video processing modules respectively. The same source clock module is used to generate pixel clock signals and generate one-third pixel clock signals based on the pixel clock signals and the frequency relationship between one-third pixel clock domain and pixel clock domain.

[0008] The synchronous clock sampling module is connected between the pixel packing module and the DSC decoder. Based on the pixel clock signal, the synchronous clock sampling module directly samples the decoded data packet of one-third of the pixel clock domain output by the DSC decoder, and stores the sampled decoded data packet in the sampling register of the synchronous clock sampling module for output to the pixel unpacking module. Simultaneously, after sampling the decoded data packet, for each pixel clock cycle, an indication signal is output to indicate that the decoded data packet in the sampling register is valid. The width of the decoded data packet is 3 pixels, and the number of sampling registers is 1.

[0009] The pixel unpacking module is connected between the synchronous clock sampling module and the other video processing modules. The pixel unpacking module is used to generate a pixel counter based on the indication signal and the pixel clock signal, and to unpack the decoded data packet based on the value of the pixel counter under each pixel clock frame to generate target data with a width of 1 pixel.

[0010] Secondly, embodiments of the present invention also provide a DSC decoder system, including: a DSC decoder, other video processing modules, and a video output circuit as described in any embodiment of this specification;

[0011] The DSC decoder is connected to the input terminal of the video output circuit and is used to output a decoded data packet of one-third of the pixel clock domain to the video output circuit.

[0012] The other video processing modules are connected to the output terminal of the video output circuit and are used to receive the target data output by the video output circuit.

[0013] Thirdly, embodiments of the present invention also provide a video output method based on the video output circuit described in any embodiment of this specification, including:

[0014] The same source clock module generates the same source pixel clock signal and one-third pixel clock signal, and sends the pixel clock signal and the one-third pixel clock signal to the DSC decoder, the synchronous clock sampling module, the pixel unpacking module, and other external video processing modules respectively.

[0015] The synchronous clock sampling module samples the decoded data packets of one-third of the pixel clock domain output by the DSC decoder based on the pixel clock signal, and stores the sampled decoded data packets in the sampling register for output to the pixel unpacking module. At the same time, for each pixel clock after sampling the decoded data packets, an indication signal is output to indicate that the decoded data packets in the sampling register are valid; wherein, the width of the decoded data packets is 3 pixels, and the number of sampling registers is 1.

[0016] The pixel unpacking module generates a pixel counter based on the indication signal and the pixel clock signal, and unpacks the decoded data packet based on the value of the pixel counter under each pixel clock cycle to generate target data with a width of 1 pixel.

[0017] This invention provides a video output circuit, system, and method for a DSC decoder. First, a synchronous clock module generates a one-third pixel clock signal and a pixel clock signal with a strictly constant frequency relationship. Then, a synchronous clock sampling module can directly sample the three-pixel-width decoded data packet in the one-third pixel clock domain output by the DSC decoder using the pixel clock signal. This eliminates the need for the buffering function of multiple depth registers in an asynchronous FIFO, avoiding the reading of erroneous data when registers change. Therefore, the synchronous clock sampling module only needs to configure one sampling register to achieve clock domain conversion. Compared to the asynchronous FIFO used in traditional video output circuits, the synchronous clock sampling module eliminates the asynchronous FIFO read / write pointers and combinational logic, and also reduces the use of registers. Therefore, this solution can save a significant amount of chip area, thereby reducing chip cost and power consumption. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the video output circuit of a DSC decoder in the prior art;

[0020] Figure 2 This is a waveform diagram of the video output circuit of a DSC decoder in the prior art;

[0021] Figure 3 This is a schematic diagram of an asynchronous FIFO storage method in the prior art;

[0022] Figure 4 This is a schematic diagram of the composition of a video output circuit of a DSC decoder according to an embodiment of the present invention;

[0023] Figure 5 This is a waveform diagram of a synchronous clock sampling module provided in an embodiment of the present invention;

[0024] Figure 6 This is a waveform diagram of the video output circuit of a DSC decoder provided in an embodiment of the present invention;

[0025] Figure 7 This is a flowchart of a video output method provided in an embodiment of the present invention. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0027] like Figure 1 As shown, the video output circuit of existing DSC decoders typically includes an asynchronous FIFO and a pixel unpacking module, as referenced in the figure. Figure 2 The waveform diagram shows that `dsc_pixel_clock` is the one-third pixel clock. The DSC decoder outputs a 3-pixel decoded data packet `dsc_pixel_data` in each `dsc_pixel_clock` frame. `dsc_data_en` is an indicator signal used to indicate whether the decoded data packet output by the DSC decoder is valid; `dsc_pixel_data` is valid only when `dsc_data_en` is high. The standard asynchronous FIFO in the video output circuit is the clock domain conversion module of the video output circuit. The input port of the asynchronous FIFO, i.e., the write port, operates in the one-third pixel clock domain. The write-valid port of the asynchronous FIFO input port is connected to the `dsc_data_en` signal, the write data port of the asynchronous FIFO input port is connected to the `dsc_pixel_data` signal, and the write clock of the asynchronous FIFO input port is connected to the one-third pixel clock signal `dsc_pixel_clock`.

[0028] Figure 2In this context, `pixel_clock` is the pixel clock, which is also the read clock for the asynchronous FIFO output port. `pixel_data_3p` and `pixel_data_en_3p` are the read data and read data validity indication signals output by the asynchronous FIFO in the video output circuit. `pixel_data_3p` has a width of 3 pixels and outputs 3 pixels only on the third clock cycle of every 3 pixel clock cycles. The `pixel_data_3p` and `pixel_data_en_3p` signals output from the asynchronous FIFO are input to the pixel unpacking module, where they are decrypted into... Figure 2 The `pixel_data` and `pixel_data_en` signals are outputs of the pixel unpacking module and also operate in the pixel clock domain. `pixel_data` is the video data output by the pixel unpacking module, with a width of one pixel. The `pixel_data_en` signal indicates whether the `pixel_data` video data is valid; it is valid when `pixel_data_en` is high. Thus, through a single video output circuit, the conversion of video data from one-third of the pixel clock domain to the pixel clock domain is completed, providing the required video format for other video processing modules.

[0029] Typically, an asynchronous FIFO will receive two clock domain signals: one is the pixel clock domain, and the other is the one-third pixel clock domain. Since these two clock domain signals may not be from the same source, due to clock errors or error accumulation, the DSC decoder may sample data in a metastable state, i.e., reading data when the register changes. Therefore, it is necessary to set a multi-depth register to buffer the decoded data packets in order to reduce the probability of metastability.

[0030] For example, each pixel_data_3p will be stored sequentially in the asynchronous FIFO register in the output order, such as... Figure 3 As shown, the asynchronous FIFO has registers with 8 depths. Data packets pixels 0, 1, 2 and pixels 3, 4, 5 are written to registers 0 and 1 respectively. After the decoded data packet is written to register 7, it is written back to register 0, overwriting the original video data stored in register 0. Similarly, reading data also starts from the beginning after one cycle. This multi-depth register configuration of the asynchronous FIFO slows down the rate of register changes. Originally, writing occurred every three pixel clock cycles, meaning the data in the register changed every three pixel clock cycles. Now, by writing in one cycle, the data in each register changes only once every twenty-four pixel clock cycles. This slower register change avoids reading during register changes.

[0031] Therefore, traditional video output circuits use asynchronous FIFOs to complete the conversion of video data from one-third of the pixel clock domain to the pixel clock domain. In order to reduce the probability of metastability, asynchronous FIFOs are usually configured with multiple deep registers to slow down the change rate of the registers, thereby reducing the probability of reading incorrect data when the registers change. However, asynchronous FIFOs require more registers and combinational logic, which leads to a larger chip area and chip cost required for the video output circuit of existing DSC decoders.

[0032] To address the aforementioned technical issues, the inventors could consider using a synchronous clock module to generate pixel clock signals and one-third pixel clock signals with strictly unchanged frequency relationships. This would allow for precise control of the DSC decoder to prevent data reading when the sampling register changes. This eliminates the need for multiple registers and control logic in an asynchronous FIFO to buffer data packets. The pixel clock signals can then be used to directly sample the decoded data packets in the one-third pixel clock domain output by the DSC decoder, and the sampled decoded data packets can be stored in the single sampling register of the synchronous clock sampling module. This solution replaces the asynchronous FIFO with a synchronous clock sampling module and appropriately modifies the pixel unpacking module. Furthermore, the internal implementation of the synchronous clock sampling module and the newly added synchronous clock module is very simple, far less complex than the asynchronous FIFO logic. Furthermore, by directly sampling the width data of 3 pixels under one-third of the pixel clock domain using the pixel clock signal, taking a single pixel width of 24 bits as an example, the synchronous clock module only samples 3 pixels under every 3 pixel clock signals and buffers these 3 pixels for 1 clock cycle using the sampling register, which means there is only 1*3*24=72 bits of sampling register storage space. However, the depth of the asynchronous FIFO is usually set to 8, so the asynchronous FIFO requires 8*3*24=576 bits of register storage space. Moreover, the read / write pointers and control logic in the asynchronous FIFO also require a large number of registers and combinational logic. Therefore, this solution can greatly reduce the chip area, chip cost and power consumption of the video output circuit.

[0033] Please refer to Figure 4 This invention provides a video output circuit for a DSC decoder, comprising: a synchronous clock module, a synchronous clock sampling module, and a pixel unpacking module; wherein,

[0034] The same source clock module is connected to the DSC decoder, the synchronous clock sampling module, the pixel unpacking module, and other external video processing modules respectively. The same source clock module is used to generate pixel clock signals and generates one-third pixel clock signals based on the pixel clock signals and the frequency relationship between one-third pixel clock domain and pixel clock domain.

[0035] The synchronous clock sampling module is connected between the pixel packing module and the DSC decoder. Based on the pixel clock signal, the synchronous clock sampling module directly samples the decoded data packets of one-third of the pixel clock domain output by the DSC decoder and stores the sampled decoded data packets in the sampling register of the synchronous clock sampling module for output to the pixel unpacking module. Simultaneously, after sampling the decoded data packets, an indication signal is output for each pixel clock cycle to indicate that the decoded data packets in the sampling register are valid. The width of the decoded data packets is 3 pixels, and the number of sampling registers is 1.

[0036] The pixel unpacking module is connected between the synchronous clock sampling module and other video processing modules. The pixel unpacking module is used to generate a pixel counter based on the indicator signal and the pixel clock signal, and to unpack the decoded data packet based on the value of the pixel counter under each pixel clock frame to generate target data with a width of 1 pixel.

[0037] In this embodiment of the invention, firstly, a pixel clock signal is generated using a co-source clock module. Simultaneously, a one-third pixel clock signal is generated based on the pixel clock signal and the frequency relationship between the one-third pixel clock domain and the pixel clock domain, providing corresponding clock signals for the DSC decoder, the synchronous clock sampling module, the pixel unpacking module, and other external video processing modules. Then, the synchronous clock sampling module samples the decoded data packets of the one-third pixel clock domain output by the DSC decoder based on the pixel clock signal, and stores the sampled decoded data packets in a sampling register for output to the pixel unpacking module. Simultaneously, for each pixel clock cycle after sampling the decoded data packets, an indication signal is output to indicate that the decoded data packets in the sampling register are valid. The width of the decoded data packets is 3 pixels, and the number of sampling registers is 1. Finally, the pixel unpacking module generates a pixel counter based on the indication signal and the pixel clock signal, and unpacks the decoded data packets based on the value of the pixel counter at each pixel clock cycle, generating target data with a width of 1 pixel. In this solution, since the frequency relationship between the one-third pixel clock signal generated by the same-source clock module and the pixel clock signal remains strictly unchanged, the synchronous clock sampling module can directly sample the 3-pixel-width decoded data packet in the one-third pixel clock domain output by the DSC decoder using the pixel clock signal. This eliminates the need for the buffering function of multiple depth registers in the asynchronous FIFO, thus avoiding the reading of erroneous data when registers change. Therefore, the synchronous clock sampling module only needs to be configured with one sampling register to achieve clock domain conversion. It is evident that compared to the asynchronous FIFO used in traditional video output circuits, the synchronous clock sampling module eliminates the read / write pointers and combinational logic required by the asynchronous FIFO, and also reduces the use of registers. Therefore, this solution can save a significant amount of chip area, thereby reducing chip cost and power consumption.

[0038] In this embodiment of the invention, there are at least three ways to generate the one-third pixel clock signal in the same-source clock module:

[0039] The first method involves counting the pixel clock signals, generating a one-third pixel clock signal every three pixel clock signals.

[0040] In this embodiment, since the frequency of the one-third pixel clock signal is one-third of the pixel clock signal frequency, the pixel clock signals generated by the same source clock module can be counted. Every three pixel clock signals generate a one-third pixel clock signal output, thereby generating the same one-third pixel clock signal and the pixel clock signal. It can be seen that the logic of the counter method in this embodiment is relatively simple and easier to implement.

[0041] The second method involves inputting the pixel clock signal into a phase-locked loop (PLL) and configuring the PLL's output clock to be one-third the frequency of the input clock to generate a one-third pixel clock signal.

[0042] It is understandable that, while ensuring a strict one-third ratio clock relationship, other methods can also be used to generate one-third pixel clock signals. In this embodiment, a phase-locked loop (PLL) is used. The input pixel clock can be configured to output a one-third pixel clock signal at one-third the frequency of the input clock, which can be achieved once the PLL is locked.

[0043] The third method involves using a clock divider to divide the pixel clock by three, generating a one-third pixel clock signal.

[0044] In this embodiment, a dedicated clock divider is used to divide the pixel clock by three to generate one-third pixel clock signals.

[0045] In some implementations, when the synchronous clock sampling module samples the decoded data packets of one-third of the pixel clock domain output by the DSC decoder based on the pixel clock signal, it may include:

[0046] The target pixel clock signal is determined based on the pixel clock signal corresponding to the starting rising edge of the one-third pixel clock signal corresponding to the first decoded data packet output by the DSC decoder.

[0047] Upon receiving the target pixel clock signal, sampling of the decoded data packets output by the DSC decoder begins, with one decoded data packet sampled every three pixel clock signals.

[0048] In this embodiment, the target pixel clock signal is the next pixel clock signal corresponding to the starting rising edge of the pixel clock signal corresponding to the first one-third pixel clock signal of the decoded data packet.

[0049] You can refer to this. Figure 5 Since the synchronous clock sampling module can directly sample the decoded data packets of one-third pixel clock domain output by the DSC decoder, the starting time of the synchronous clock sampling module needs to be later than the rising edge of the starting edge of each decoded data packet dsc_pixel_data output by the DSC decoder. Therefore, it is necessary to first determine the pixel clock signal corresponding to the rising edge of the one-third pixel clock signal dsc_pixel_clock corresponding to pixels 0, 1, 2 in the first decoded data packet dsc_pixel_data output by the DSC decoder. The target pixel clock signal used as the starting time of the synchronous clock sampling module can be the next pixel clock signal corresponding to the rising edge of the one-third pixel clock signal dsc_pixel_clock corresponding to pixels 0, 1, 2 in the first decoded data packet dsc_pixel_data. Figure 5 The pixel clock signals corresponding to the rising edges of pixels 0, 1, and 2 in `pixel_data` are defined as follows: Upon receiving the target pixel clock signal, the synchronous clock sampling module begins sampling the decoded data packets output by the DSC decoder. This sampling occurs every three pixel clock cycles, with each sampled data packet stored in the sampling register of the synchronous clock sampling module for output to the pixel unpacking module. Simultaneously, after sampling the decoded data packets, an indicator signal `pixel_data_en` is output for each subsequent pixel clock cycle to indicate the validity of the decoded data packet in the sampling register. The width of the decoded data packet is 3 pixels, and the number of sampling registers is 1.

[0050] It is understandable that the target pixel clock signal can be delayed by two clock cycles to the pixel clock signal corresponding to the rising edge of the first one-third pixel clock signal of the first decoded data packet, or it can be delayed by three clock cycles.

[0051] In some implementations, the pixel unpacking module, when performing the process of generating a pixel counter based on an indication signal and a pixel clock signal, and unpacking the decoded data packet based on the value of the pixel counter at each pixel clock cycle to generate target data with a width of 1 pixel, includes:

[0052] The initial value of the pixel counter is set to 0. When the indicator signal is high, the value of the pixel counter is incremented by 1 for each subsequent pixel clock signal. Whenever the value increases to 2, the value of the pixel counter is reset to 0 for the next pixel clock signal.

[0053] For each received decoded data packet, perform the following:

[0054] When the pixel counter value is 0, the first pixel of the currently decoded data packet will be output as the target data under the next pixel clock signal;

[0055] When the pixel counter value is 1, the second pixel of the currently decoded data packet will be output as the target data under the next pixel clock signal;

[0056] When the pixel counter value is 2, the third pixel of the currently decoded data packet will be output as the target data under the next pixel clock signal.

[0057] You can refer to this. Figure 6 In this embodiment, after the decoded data packet pixel_data_3p and the indication signal pixel_data_en_3p are input to the pixel unpacking module, the pixel unpacking module constructs a pixel counter pixel_cnt based on the indication signal pixel_data_en_3p. The pixel counter pixel_cnt is initially 0. After pixel_data_en_3p goes high, the pixel clock signal is incremented by 1 for each frame. When it reaches 2, the pixel clock signal becomes 0 again for the next frame. Pixel_data represents the target data for the pixel clock field, which is one pixel wide. It selects which pixel to output in the next frame for each decoded data packet (pixel_data_3p) based on the value of the pixel counter (pixel_cnt). For each decoded data packet, the following steps are performed: when pixel_cnt is 0, the first pixel of the current decoded data packet is output in the next frame's pixel clock signal; when pixel_cnt is 1, the second pixel is output; and when pixel_cnt is 2, the third pixel is output. The Pixel_data_en signal is an indication of whether the target data of pixel_data is valid, and it is output one frame later than pixel_data_en_3p. Through this circuitry, the pixel unpacking module decodes the target data of the pixel clock field required by other video processing modules.

[0058] In some implementations, the sampling register needs to meet the setup and hold time requirements of the sampling register design.

[0059] In this embodiment, the synchronous clock sampling module must check the setup and hold times of the sampling register. That is, the pixel clock and the one-third pixel clock are synchronous clocks, and the sampling register located at the clock boundary between the pixel clock and the one-third pixel clock must meet the setup and hold time requirements of the register design so that the video data can be sampled correctly.

[0060] refer to Figure 4 The present invention also provides a DSC decoder system, including: a DSC decoder, other video processing modules, and a video output circuit as described in any embodiment of this specification;

[0061] The DSC decoder is connected to the input terminal of the video output circuit and is used to output decoded data packets of one-third of the pixel clock domain to the video output circuit.

[0062] Other video processing modules are connected to the output terminals of the video output circuit to receive the target data output by the video output circuit.

[0063] Since the above system is based on the same concept as the circuit embodiment of the present invention, the specific details can be found in the description of the circuit embodiment of the present invention, and will not be repeated here.

[0064] like Figure 7 As shown, this embodiment of the invention also provides a video output method based on a video output circuit according to any embodiment of this specification, including:

[0065] Step 700: Generate a pixel clock signal and a one-third pixel clock signal from the same source using the same source clock module, and send the pixel clock signal and the one-third pixel clock signal to the DSC decoder, the synchronous clock sampling module, the pixel unpacking module, and other external video processing modules respectively.

[0066] Step 702: The synchronous clock sampling module samples the decoded data packets of one-third of the pixel clock domain output by the DSC decoder based on the pixel clock signal, and stores the sampled decoded data packets in the sampling register for output to the pixel unpacking module. At the same time, after sampling the decoded data packets, an indication signal is output for each pixel clock cycle to indicate that the decoded data packets in the sampling register are valid. The width of the decoded data packets is 3 pixels, and the number of sampling registers is 1.

[0067] Step 704: The pixel unpacking module generates a pixel counter based on the indicator signal and the pixel clock signal, and unpacks the decoded data packet based on the value of the pixel counter under each pixel clock cycle to generate target data with a width of 1 pixel.

[0068] Since the above method is based on the same concept as the circuit embodiment of the present invention, the specific details can be found in the description of the circuit embodiment of the present invention, and will not be repeated here.

[0069] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0070] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as ROM, RAM, magnetic disk, or optical disk.

[0071] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A video output circuit for a DSC decoder, characterized in that, include: The system comprises a common clock module, a synchronous clock sampling module, and a pixel unpacking module; among which, The same source clock module is connected to the DSC decoder, the synchronous clock sampling module, the pixel unpacking module, and other external video processing modules respectively. The same source clock module is used to generate pixel clock signals and generate one-third pixel clock signals based on the pixel clock signals and the frequency relationship between one-third pixel clock domain and pixel clock domain. The synchronous clock sampling module is connected between the pixel unpacking module and the DSC decoder. Based on the pixel clock signal, the synchronous clock sampling module directly samples the decoded data packet of one-third of the pixel clock domain output by the DSC decoder, and stores the sampled decoded data packet in the sampling register of the synchronous clock sampling module for output to the pixel unpacking module. Simultaneously, after sampling the decoded data packet, for each pixel clock cycle, an indication signal is output to indicate that the decoded data packet in the sampling register is valid. The width of the decoded data packet is 3 pixels, and the number of sampling registers is 1. The pixel unpacking module is connected between the synchronous clock sampling module and the other video processing modules. The pixel unpacking module is used to generate a pixel counter based on the indication signal and the pixel clock signal, and to unpack the decoded data packet based on the value of the pixel counter under each pixel clock frame to generate target data with a width of 1 pixel. When the pixel unpacking module performs the process of generating a pixel counter based on the indication signal and the pixel clock signal, and unpacking the decoded data packet based on the value of the pixel counter at each pixel clock cycle to generate target data with a width of 1 pixel, the process includes: The initial value of the pixel counter is set to 0. When the indication signal is high, the value of the pixel counter is incremented by 1 for each subsequent pixel clock signal. Whenever the value increases to 2, the value of the pixel counter is reset to 0 for the next pixel clock signal. For each received decoded data packet, perform the following: When the value of the pixel counter is 0, the first pixel of the current decoded data packet is output as the target data under the next pixel clock signal; When the value of the pixel counter is 1, the second pixel of the current decoded data packet is output as the target data under the next pixel clock signal; When the value of the pixel counter is 2, the third pixel of the currently decoded data packet is output as the target data under the next pixel clock signal.

2. The circuit according to claim 1, characterized in that, The one-third pixel clock signal in the same clock module is generated in the following manner: The pixel clock signals are counted, and a third pixel clock signal is generated every three pixel clock signals.

3. The circuit according to claim 1, characterized in that, The one-third pixel clock signal in the same clock module is generated in the following manner: The pixel clock signal is input into the phase-locked loop (PLL), and the output clock of the PLL is configured to be one-third of the frequency of the input clock to generate a one-third pixel clock signal.

4. The circuit according to claim 1, characterized in that, The one-third pixel clock signal in the same clock module is generated in the following manner: The pixel clock is divided by three using a clock divider to generate one-third of the pixel clock signal.

5. The circuit according to claim 1, characterized in that, When the synchronous clock sampling module performs the step of directly sampling the decoded data packet of one-third of the pixel clock domain output by the DSC decoder based on the pixel clock signal, it includes: The target pixel clock signal is determined based on the pixel clock signal corresponding to the starting rising edge of the one-third pixel clock signal corresponding to the first decoded data packet output by the DSC decoder. Upon receiving the target pixel clock signal, sampling of the decoded data packets output by the DSC decoder begins, with one decoded data packet sampled every three pixel clock signals.

6. The circuit according to claim 5, characterized in that, The target pixel clock signal is the next pixel clock signal corresponding to the rising edge of the first one-third pixel clock signal of the first decoded data packet.

7. A DSC decoder system, characterized in that, include: DSC decoder, other video processing modules, and video output circuit as described in any one of claims 1-6; The DSC decoder is connected to the input terminal of the video output circuit and is used to output a decoded data packet of one-third of the pixel clock domain to the video output circuit. The other video processing modules are connected to the output terminal of the video output circuit and are used to receive the target data output by the video output circuit.

8. A video output method based on the video output circuit according to any one of claims 1-6, characterized in that, include: The same source clock module generates the same source pixel clock signal and one-third pixel clock signal, and sends the pixel clock signal and the one-third pixel clock signal to the DSC decoder, the synchronous clock sampling module, the pixel unpacking module, and other external video processing modules respectively. The synchronous clock sampling module samples the decoded data packets of one-third of the pixel clock domain output by the DSC decoder based on the pixel clock signal, and stores the sampled decoded data packets in the sampling register for output to the pixel unpacking module. At the same time, for each pixel clock after sampling the decoded data packets, an indication signal is output to indicate that the decoded data packets in the sampling register are valid; wherein, the width of the decoded data packets is 3 pixels, and the number of sampling registers is 1. The pixel unpacking module generates a pixel counter based on the indication signal and the pixel clock signal, and unpacks the decoded data packet based on the value of the pixel counter under each pixel clock cycle to generate target data with a width of 1 pixel.

Images