Solid-state low-light image sensor with charge-domain amplification and voltage-domain multiple sampling

Abstract

The application discloses a solid-state micro-light image sensor with charge domain amplification and voltage domain multiple sampling, and is characterized by comprising a pixel part, a charge domain gain control structure, a horizontal transfer channel and a multiple sampling circuit; the pixel part adopts a pinned photodiode, four-phase vertical transfer gates transfer the accumulated charges in the photodiode to the vertical transfer channel; the charge domain gain control structure comprises a gain gate, and the programmable gain control of the charge domain is realized in the transfer process of the vertical transfer channel; the horizontal transfer channel transfers the charge packet to a charge detection node SN through the time sequence control of the gate, and converts the charge packet into a reset level signal through a reset and buried groove source follower amplification circuit; the multiple sampling circuit samples the converted voltage signal multiple times, and an external differential input ADC completes analog-digital conversion. The application fully utilizes the signal charge amplification advantage of electron multiplication, and reduces 1 / f noise and RTS noise.

Description

Technical Field

[0001] This invention belongs to the field of low-light imaging technology, and specifically relates to a solid-state low-light image sensor with charge domain amplification and voltage domain multiple sampling. Background Technology

[0002] To achieve clear imaging under low-light conditions, solid-state low-light image sensors mainly address two issues: signal and noise. They amplify the signal or reduce noise to achieve high signal-to-noise ratio imaging.

[0003] There are currently three technical approaches:

[0004] Firstly, EMCCD image sensor technology utilizes avalanche amplification of the signal during charge level readout through a physical mechanism of collisional ionization, overcoming the noise floor of the output stage source follower amplifier circuit. By enhancing the signal level, high signal-to-noise ratio imaging is achieved.

[0005] Secondly, low-light CMOS image sensor technology first improves the conversion gain by reducing the capacitance of the sense node (SN). Next, it reduces the 1 / f noise and RTS noise of the source follower amplifier circuit through buried trenches or PMOS source follower circuits. Finally, it employs correlated multiple sampling circuitry to further reduce thermal noise, 1 / f noise, and RTS noise in the signal link. By reducing noise, high signal-to-noise ratio imaging is achieved.

[0006] Thirdly, SPAD (Single Photon Avalanche Photodiode) image sensor technology replaces the original photodiode with an APD operating in Geiger mode. A single photon incident can trigger an avalanche. Through peripheral circuits such as passive quenching, active reset, and 1-bit memory, the system can statistically analyze photon incident events, achieving high signal-to-noise ratio imaging in a completely digital manner.

[0007] The three technical approaches mentioned above also face different problems in achieving low-light imaging:

[0008] In EMCCD image sensors, the multiplication structure is placed after the horizontal shift register. To increase the frame rate, a high-frequency (≥10MHz) multiplication drive signal is required, and this frequency increases with resolution. This leads to higher power consumption in the drive circuit and greater difficulty in circuit implementation. The heat generated by the high-frequency circuit causes a degradation in the device's dark current, reducing the signal-to-noise ratio. This often requires the device to operate under cooling conditions, further increasing the camera's power consumption.

[0009] In low-light CMOS image sensors, reducing the signal-to-noise (SN) capacitance decreases the full-well capacitance and reduces the dynamic range of the image. Furthermore, parallel voltage-domain amplifier circuits amplify noise along with the signal, requiring complex bandwidth control and other circuit structures to compensate for these drawbacks.

[0010] The SPAD image sensor currently suffers from low pixel fill factor and dark count rate issues, which affect the signal-to-noise ratio of the image. It is still in the process of breaking through many key technologies and has not yet formed a mass-produced practical product. However, as a fully digital image sensor, it has development prospects. Summary of the Invention

[0011] The purpose of this invention is to provide a solid-state low-light image sensor with charge domain amplification and voltage domain multiple sampling, which solves two problems: first, the requirement for high-frequency and high-voltage driving of EMCCD, and the negative impact of high power consumption and heat generation; second, the noise amplification problem caused by the parallel voltage domain amplification circuit, which affects the final signal-to-noise ratio.

[0012] The technical solution of this invention is:

[0013] A solid-state low-light image sensor with charge domain amplification and voltage domain multiple sampling includes a pixel section, a charge domain gain control structure, a horizontal transfer channel, and a multiple sampling circuit.

[0014] The pixel portion adopts a pinned photodiode and a four-phase transfer structure. The four-phase transfer structure includes vertical transfer gates V1, V2, V3, and V4, which transfer the accumulated charge in the photodiode to the vertical transfer channel.

[0015] The charge domain gain control structure includes gain gates EM1S, EM2B, EM2S and EM1B. During the vertical transfer channel transfer process, the gain gates achieve controllable avalanche gain through impact ionization, realizing programmable gain control in the charge domain.

[0016] The horizontal transfer channel includes a horizontal shift register. After gain amplification, the charge enters the horizontal shift register of the horizontal transfer channel. The charge packet is transferred to the charge detection node SN by the timing control of gates H1S, H1B, H2S and H2B. The charge packet is converted into a reset level signal by the reset and buried trench source follower amplifier circuit.

[0017] The multiple sampling circuit samples the converted voltage signal multiple times, and the analog-to-digital conversion is completed by the external differential input ADC.

[0018] Preferably, after the pinned photodiode has been exposed, the vertical transfer gates V1, V2, V3, and V4 are pulled up to transfer the accumulated charge in the pinned photodiode to the vertical transfer channel.

[0019] Preferably, the vertical transfer gates V1, V2, V3, V4 and the gain gates EM1S, EM2B, EM2S, EM1B are alternated in high and low levels to transfer signal charge to the charge domain gain control structure.

[0020] Preferably, the maximum gain M of the charge domain gain control structure is 16 times, and the total gain level N is calculated using the gain coefficient G of each level, where M = G. N .

[0021] Preferably, the multiple sampling circuit includes a switching transistor. Op-amp A1, sampling capacitors C1, C2, C SS C SR ;

[0022] The reset level signal and the reference signal are respectively passed through the switching transistor. Connect one end of the sampling capacitor C1; the other end of the sampling capacitor C1 is connected through... Grounding, through Connect the inverting input terminal of op-amp A1; ground the non-inverting input terminal of op-amp A1; connect a switching transistor in parallel between the inverting input terminal and the output terminal of op-amp A1. Sampling capacitor C2;

[0023] The output of op-amp A1 is connected to a series of switching transistors. Sampling capacitor C SS Switching transistor Grounding, one path through the sequentially connected switching transistors Sampling capacitor C SR Switching transistor Grounding;

[0024] Sampling capacitor C SS C SR The input terminal is connected to a switching transistor. The connection and output terminals are respectively connected through switching transistors. Connect the two-phase input terminals of the external differential amplifier circuit.

[0025] Preferably, the multiple sampling circuit first closes the switching transistor. Clear the charge on the sampling capacitor C2; simultaneously switch the transistor. When closed, the reset level is sampled once by the sampling capacitor C1;

[0026] Next, the switching transistor Turn on, switch tube When closed, the signal on sampling capacitor C1 is transferred to sampling capacitor C2;

[0027] Switching transistor and switching transistor The reset signal is sampled T times by alternating between opening and closing the switch T times.

[0028] The final reset level signal is used in the sampling capacitor C. SRSimilarly, the signal is also sampled T times at the sampling capacitor C. SS Top; Switching transistor The output of the final signal is controlled by an external differential input ADC, which performs analog-to-digital conversion.

[0029] The advantages of this invention are:

[0030] 1. In the solid-state low-light image sensor of the present invention, during the vertical transfer of signal charge, by controlling the vertical transfer gates V1, V2, V3, V4, and the gain gates EM1S, EM2B, EM2S, and EM1B, controllable avalanche gain is achieved through collisional ionization during the transfer process, thereby realizing programmable gain control of the charge domain. This part of the structure makes full use of the advantage of electron multiplication that amplifies only the signal charge.

[0031] 2. When the amplified charge enters the horizontal transfer channel, the present invention transfers the charge packet to the SN node through the timing control of H1S, H1B, H2S and H2B. The charge packet is converted into a voltage signal through the reset and buried trench source follower amplifier circuit, thereby reducing 1 / f noise and RTS noise.

[0032] 3. The multiple sampling circuit of the present invention samples the reset level signal multiple times. The specific number of samplings is related to the frequency of horizontal readout, which effectively reduces thermal noise and is also beneficial to 1 / f noise and RTS noise. Attached Figure Description

[0033] The present invention will be further described below with reference to the accompanying drawings and embodiments:

[0034] Figure 1 A schematic diagram of the solid-state low-light image sensor of the present invention;

[0035] Figure 2 Timing diagram of the charge domain gain control structure;

[0036] Figure 3 Schematic diagram of a multiple sampling circuit. Detailed Implementation

[0037] like Figure 1 As shown, the solid-state low-light image sensor of the present invention, which features charge domain amplification and voltage domain multiple sampling, includes a pixel portion, a charge domain gain control structure, a horizontal transfer channel, and a multiple sampling circuit.

[0038] The pixel portion employs pinned photodiodes and a four-phase transfer structure. The four-phase transfer structure includes vertical transfer gates V1, V2, V3, and V4. After the pinned photodiodes are exposed, the vertical transfer gates V1, V2, V3, and V4 are pulled up, transferring the accumulated charge in the pinned photodiodes to the vertical transfer channel.

[0039] The charge domain gain control structure includes gain gates EM1S, EM2B, EM2S, and EM1B. For example... Figure 2 As shown, during the vertical transfer of signal charge, by controlling the vertical transfer gates V1, V2, V3, and V4, and the gain gates EM1S, EM2B, EM2S, and EM1B with alternating high and low levels, controllable avalanche gain is achieved through collisional ionization during the transfer process, realizing programmable gain control in the charge domain. This part of the structure fully utilizes the advantage of electron multiplication, which amplifies only the signal charge.

[0040] The maximum gain of the charge domain gain control structure is M = 16 times. The total gain level N is calculated using the gain coefficient G of each level, where M = G. N Here, the gain coefficient G for each stage is set to 1.0105, and the total number of stages is 265. The corresponding number of gain stages is drawn in the layout design.

[0041] The horizontal transfer channel includes a horizontal shift register. The charge packet enters the horizontal shift register after passing through the charge domain gain control structure. The charge packet is transferred to the charge detection node SN by the timing control of gates H1S, H1B, H2S and H2B. The charge packet is converted into a reset level signal by the reset and buried trench source follower amplifier circuit, thereby reducing 1 / f noise and RTS noise.

[0042] The multiple sampling circuit samples the converted voltage signal multiple times, and the analog-to-digital conversion is completed by an external differential input ADC. The specific number of samplings is related to the horizontal readout frequency, which effectively reduces thermal noise and is also beneficial for 1 / f noise and RTS noise.

[0043] like Figure 3 As shown, the multiple sampling circuit includes a switching transistor. Op-amp A1, sampling capacitors C1, C2, C SS C SR ;

[0044] The reset level signal and the reference signal are respectively passed through the switching transistor. Connect one end of the sampling capacitor C1; the other end of the sampling capacitor C1 is connected through... Grounding, through Connect the inverting input terminal of op-amp A1; ground the non-inverting input terminal of op-amp A1; connect a switching transistor in parallel between the inverting input terminal and the output terminal of op-amp A1. Sampling capacitor C2;

[0045] The output of op-amp A1 is connected to a series of switching transistors. Sampling capacitor C SS Switching transistor Grounding, one path through the sequentially connected switching transistors Sampling capacitor C SR Switching transistor Grounding;

[0046] Sampling capacitor C SS C SR The input terminal is connected to a switching transistor. The connection and output terminals are respectively connected through switching transistors. Connect the two-phase input terminals of the external differential amplifier circuit.

[0047] The multiple sampling circuit first closes the switching transistor. Clear the charge on the sampling capacitor C2; simultaneously switch the transistor. When closed, the reset level is sampled once by the sampling capacitor C1;

[0048] Next, the switching transistor Turn on, switch tube When closed, the signal on sampling capacitor C1 is transferred to sampling capacitor C2;

[0049] Switching transistor and switching transistor The reset signal is sampled T times by alternating between opening and closing the switch T times.

[0050] The final reset level signal is used in the sampling capacitor C. SR Similarly, the signal is also sampled T times at the sampling capacitor C. SS Top; Switching transistor The output of the final signal is controlled by an external differential input ADC, which performs analog-to-digital conversion.

[0051] Through the aforementioned device operation process, higher signal-to-noise ratio imaging effects can be achieved under low-light conditions.

[0052] The above embodiments are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All modifications made according to the spirit and essence of the main technical solution of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A solid-state low-light image sensor with charge-domain amplification and voltage-domain multiple sampling, characterized in that, This includes the pixel portion, charge domain gain control structure, horizontal transfer channel, and multiple sampling circuit; The pixel portion adopts a pinned photodiode and a four-phase transfer structure. The four-phase transfer structure includes vertical transfer gates V1, V2, V3, and V4, which transfer the accumulated charge in the photodiode to the vertical transfer channel. The charge domain gain control structure includes gain gates EM1S, EM2B, EM2S and EM1B. During the vertical transfer channel transfer process, the gain gates achieve controllable avalanche gain through impact ionization, realizing programmable gain control of the charge domain. The horizontal transfer channel includes a horizontal shift register. After gain amplification, the charge enters the horizontal shift register of the horizontal transfer channel. The charge packet is transferred to the charge detection node SN by the timing control of gates H1S, H1B, H2S and H2B. The charge packet is converted into a reset level signal by the reset and buried trench source follower amplifier circuit. The multiple sampling circuit samples the converted voltage signal multiple times, and the analog-to-digital conversion is completed by the external differential input ADC.

2. The solid-state low-light image sensor with charge domain amplification and voltage domain multiple sampling according to claim 1, characterized in that, After the pinned photodiode is exposed, the vertical transfer gates V1, V2, V3, and V4 are pulled up to transfer the accumulated charge in the pinned photodiode to the vertical transfer channel.

3. The solid-state low-light image sensor with charge domain amplification and voltage domain multiple sampling according to claim 2, characterized in that, The vertical transfer gates V1, V2, V3, V4 and the gain gates EM1S, EM2B, EM2S, EM1B are interleaved at high and low levels to transfer signal charge to the charge domain gain control structure.

4. The solid-state low-light image sensor with charge domain amplification and voltage domain multiple sampling according to claim 3, characterized in that, The maximum gain M of the charge domain gain control structure is 16 times. The total gain level N is calculated using the gain coefficient G of each level. .

5. The solid-state low-light image sensor with charge domain amplification and voltage domain multiple sampling according to claim 3, characterized in that, The multiple sampling circuit includes a switching transistor. , , , , , , , , , , , Op-amp A1, sampling capacitor , , , ; The reset level signal and the reference signal are respectively passed through the switching transistor. , Connect sampling capacitor One end; sampling capacitor The other end through Grounding, through Connect the inverting input terminal of op-amp A1; ground the non-inverting input terminal of op-amp A1; connect a switching transistor in parallel between the inverting input terminal and the output terminal of op-amp A1. Sampling capacitor ; The output of op-amp A1 is connected to a series of switching transistors. Sampling capacitor Switching transistor Grounding, one path through the sequentially connected switching transistors Sampling capacitor Switching transistor Grounding; sampling capacitor , The input terminal is connected to a switching transistor. The connection and output terminals are respectively connected through switching transistors. , Connect the two-phase input terminals of the external differential amplifier circuit.

6. The solid-state low-light image sensor with charge domain amplification and voltage domain multiple sampling according to claim 5, characterized in that, The multiple sampling circuit first closes the switching transistor. Clear the sampling capacitor The charge on the transistor; and the switching transistor , Closed, the reset level is determined by the sampling capacitor. One sample is taken. Next, the switching transistor , Turn on, switch tube , Close, sampling capacitor The signal is transferred to the sampling capacitor. superior; Switching transistor , and switching transistor , The reset signal is sampled T times by alternating between opening and closing the switch T times. The final reset level signal is used in the sampling capacitor. Similarly, the signal is also sampled T times at the sampling capacitor. Top; Switching transistor , , The output of the final signal is controlled by an external differential input ADC, which performs analog-to-digital conversion.

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