Semiconductor structure and method of manufacturing the same
By forming a vertically arranged transistor structure on the substrate, the problem of low integration density of DRAM memory cells is solved, realizing a high-density and high-capacity semiconductor structure design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- RUILI INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2023-07-12
- Publication Date
- 2026-07-31
AI Technical Summary
The planar arrangement of transistors in existing DRAM memory cells results in low integration density and insufficient storage capacity.
By forming trenches extending in both horizontal and vertical directions on a substrate, a first transistor structure in the horizontal direction and a second transistor structure in the vertical direction are respectively set, so that the transistor structures are perpendicular to each other, reducing the area occupied.
It increases the integration density and storage capacity of semiconductor structures, enhances the stability of transistor structures, and reduces coupling effects.
Smart Images
Figure CN116709773B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor fabrication technology, and in particular to a semiconductor structure and its fabrication method. Background Technology
[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor storage device in computers, consisting of many repeating memory cells. In one type of DRAM, each memory cell may include two transistors, and is called a 2T0C (T stands for transistor, C stands for capacitor) memory cell.
[0003] As semiconductor technology continues to mature, the demands for high-density and high-capacity memory cells are increasing. Currently, the two transistors in a memory cell are typically arranged in a planar configuration, occupying a large area, resulting in low integration density and consequently low storage capacity.
[0004] The information disclosed in the background section is only intended to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute related technology known to those skilled in the art. Summary of the Invention
[0005] This disclosure provides a semiconductor structure and its fabrication method, which can improve integration density and capacity.
[0006] This disclosure provides a semiconductor structure, including a substrate, a first transistor structure, and a second transistor structure.
[0007] The substrate includes a first trench extending in a horizontal direction and a second trench extending in a vertical direction, wherein the opening of the first trench faces the second trench and communicates with one side of the second trench.
[0008] A first transistor structure is disposed in the first trench along the horizontal direction. The first transistor structure includes a first oxide semiconductor layer, a first gate dielectric layer, and a first gate electrode stacked from the inner wall of the first trench.
[0009] The second transistor structure is disposed in the second trench along the vertical direction. The second transistor structure includes a second oxide semiconductor layer, a second gate dielectric layer and a second gate stacked on the first sidewall of the second trench away from the first transistor structure. The second oxide semiconductor layer is connected to the first gate.
[0010] In some embodiments of this disclosure, the semiconductor structure further includes: a first insulating layer located at the bottom of the second trench, and the top surface of the first insulating layer reaching the first gate; the second oxide semiconductor layer, the second gate dielectric layer and the second gate layer of a portion of the second transistor structure are stacked on the first insulating layer.
[0011] In some embodiments of this disclosure, the semiconductor structure further includes a second insulating layer located in the remaining space of the second trench having the second gate, insulating and isolating the second gate from the first gate.
[0012] In some embodiments of this disclosure, in the second transistor structure: the second oxide semiconductor layer is located on the first sidewall of the second trench away from the first transistor structure and on the top surface covering the first insulating layer to the surface connected to the first gate; the second gate dielectric layer is located on the second oxide semiconductor layer; and the second gate is located between the second gate dielectric layer and the second insulating layer.
[0013] In some embodiments of this disclosure, the material of the first insulating layer includes at least one of silicon nitride, silicon oxide, and silicon oxynitride; and / or, the material of the second insulating layer includes at least one of a low-k dielectric material and silicon nitride.
[0014] In some embodiments of this disclosure, in the first transistor structure: the first oxide semiconductor layer is located on the inner wall of the first trench and on the second sidewall of the second trench near the first transistor structure; the first gate dielectric layer is located on the first oxide semiconductor layer in the first trench; and the first gate is located on the first gate dielectric layer.
[0015] In some embodiments of this disclosure, the materials of the first oxide semiconductor layer and the second oxide semiconductor layer respectively include at least one of indium gallium zinc oxide and gallium-doped zinc oxide.
[0016] In some embodiments of this disclosure, the semiconductor structure further includes: a third oxide semiconductor layer located on the substrate on the side of the second trench near the first transistor structure, the third oxide semiconductor layer being connected to the first oxide semiconductor layer; and / or, a fourth oxide semiconductor layer located on the substrate on the side of the second trench near the second transistor structure, the fourth oxide semiconductor layer being connected to the second oxide semiconductor layer.
[0017] This disclosure also provides a method for fabricating a semiconductor structure, comprising: providing a substrate and forming a first trench extending in a horizontal direction and a second trench extending in a vertical direction on the substrate, wherein the opening of the first trench faces the second trench and communicates with one side of the second trench; forming a first transistor structure extending in the horizontal direction in the first trench, comprising: forming a first oxide semiconductor layer, a first gate dielectric layer and a first gate stacked from the inner wall of the first trench; forming a second transistor structure disposed in the vertical direction in the second trench, comprising: forming a second oxide semiconductor layer, a second gate dielectric layer and a second gate stacked from a first sidewall of the second trench away from the first transistor, wherein the second oxide semiconductor layer is connected to the first gate.
[0018] In some embodiments of this disclosure, before forming the second transistor structure disposed along the vertical direction in the second trench, the method further includes: forming a first insulating layer at the bottom of the second trench, such that the top surface of the first insulating layer reaches the first gate; forming the second transistor structure disposed along the vertical direction in the second trench includes: forming a stacked second oxide semiconductor layer, a second gate dielectric layer, and a second gate layer on the first insulating layer, which partially constitute the second transistor structure.
[0019] In some embodiments of this disclosure, after forming a second transistor structure disposed in the vertical direction in the second trench, the method includes: forming a second insulating layer in the remaining space of the second trench having the second gate to insulate and isolate the second gate from the first gate.
[0020] In some embodiments of this disclosure, forming a first oxide semiconductor layer, a first gate dielectric layer, and a first gate from the inner wall of the first trench includes: forming a first oxide semiconductor layer on the inner wall of the first trench and on a second sidewall of the second trench near the first transistor structure; forming a first gate dielectric layer on the first oxide semiconductor layer located in the first trench; and filling the first gate in the first trench in which the first gate dielectric layer is formed.
[0021] In some embodiments of this disclosure, forming a first trench extending horizontally on the substrate includes: forming a barrier layer on the substrate to shield a portion of the substrate; injecting oxygen into the exposed substrate using an oxygen injection isolation process to form a silicon oxide layer between a first preset depth and a second preset depth of the substrate; forming a second trench extending vertically on one side of the silicon oxide layer, with one end of the silicon oxide layer exposed in the second trench; and etching a portion of the silicon oxide layer from the second trench along the horizontal direction to form the first trench.
[0022] As can be seen from the above technical solutions, the transistor structure of this disclosure embodiment has at least one of the following advantages and positive effects:
[0023] In this embodiment, the first transistor structure is disposed horizontally in the first trench, and the second transistor structure is disposed vertically in the second trench, such that the first transistor structure and the second transistor structure are arranged perpendicularly to each other, which saves the area occupied on the substrate and thereby increases the integration density of the semiconductor structure and increases the storage capacity. Attached Figure Description
[0024] The above and other features and advantages of this disclosure will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.
[0025] Figure 1 This is a schematic diagram of a substrate shown in some embodiments of this disclosure;
[0026] Figure 2 This is a schematic diagram illustrating the formation of a shielding layer and a first photoresist layer on a substrate, as shown in some embodiments of this disclosure.
[0027] Figure 3 This is a schematic diagram illustrating the removal of a portion of the shielding layer and the exposure of a portion of the substrate, as shown in some embodiments of this disclosure;
[0028] Figure 4 This is a schematic diagram illustrating the process of injecting oxygen into the substrate to form a silicon oxide layer, as shown in some embodiments of this disclosure;
[0029] Figure 5 This is a schematic diagram illustrating the formation of a silicon oxide layer in a substrate and the removal of a barrier layer, as shown in some embodiments of this disclosure;
[0030] Figure 6 This is a schematic diagram illustrating the formation of a silicon oxide layer and a silicon nitride layer on the surface of a substrate according to some embodiments of this disclosure;
[0031] Figure 7 This is a schematic diagram illustrating the formation of a second photoresist layer with a second trench pattern on the surface of a silicon nitride layer, as shown in some embodiments of this disclosure.
[0032] Figure 8 This is a schematic diagram illustrating the formation of a second trench according to some embodiments of this disclosure;
[0033] Figure 9 This is a schematic diagram illustrating the removal of the silicon oxide layer and silicon nitride layer located on the substrate surface, as shown in some embodiments of this disclosure;
[0034] Figure 10 This is a schematic diagram illustrating the formation of a second trench according to some embodiments of this disclosure;
[0035] Figure 11 This is a schematic diagram illustrating the formation of a first transistor structure according to some embodiments of this disclosure;
[0036] Figure 12 This is a schematic diagram illustrating the formation of a first insulating layer in a second trench, as shown in some embodiments of this disclosure;
[0037] Figure 13 This is a schematic diagram illustrating the formation of a second transistor structure, a third oxide semiconductor layer, and a fourth oxide semiconductor layer, as shown in some embodiments of this disclosure.
[0038] Figure 14 Circuit diagrams illustrating semiconductor structures in some embodiments of this disclosure;
[0039] Figure 15 This is a flowchart illustrating a method for fabricating a semiconductor structure according to some embodiments of this disclosure.
[0040] Explanation of reference numerals in the attached figures:
[0041] 1. Substrate; 2. Barrier layer; 3. First photoresist layer; 4. Silicon oxide layer; 5. Oxide layer; 6. Silicon nitride layer; 7. Second photoresist layer; 8. First transistor structure; 801. First oxide semiconductor layer; 802. First gate dielectric layer; 803. First gate; 804. Third oxide semiconductor layer; 9. Second transistor structure; 901. Second oxide semiconductor layer; 902. Second gate dielectric layer; 904. Fourth oxide semiconductor layer; 903. Second gate; 10. First insulating layer; 11. Second insulating layer; 21. First sidewall; 22. Second sidewall; d1. First preset depth; d2. Second preset depth; g1. First trench; g2. Second trench; X. Horizontal direction; Y. Vertical direction; WWL. Write word line; WBL. Write bit line; RWL. Read word line; RBL. Read bit line. Detailed Implementation
[0042] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.
[0043] In the following description of various exemplary embodiments of the present disclosure, reference is made to the accompanying drawings, which form part of the present disclosure and illustrate, by way of example, different exemplary structures that can implement various aspects of the present disclosure. It should be understood that other specific embodiments of components, structures, exemplary devices, systems, and steps may be used, and structural and functional modifications may be made without departing from the scope of the present disclosure. Furthermore, while the terms “above,” “between,” “within,” etc., may be used in this specification to describe various exemplary features and elements of the present disclosure, these terms are used herein only for convenience, such as according to the orientation of the examples in the drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of the present disclosure. Moreover, the terms “first,” “second,” etc., in the claims are used only as illustrative marks and not as numerical limitations on the object.
[0044] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.
[0045] In addition, in the description of this disclosure, "multiple" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.
[0046] like Figure 13 As shown, this disclosure provides a semiconductor structure including a substrate 1, a first transistor structure 8, and a second transistor structure 9.
[0047] like Figure 13 As shown, substrate 1 includes a first trench g1 extending along a first horizontal direction X and a second trench g2 extending along a vertical direction Y. The opening of the first trench g1 faces the second trench g2 and communicates with one side of the second trench g2. A first transistor structure 8 is located in the first trench g1 and is disposed along the horizontal direction X, and a second transistor is located in the second trench g2 and is disposed along the vertical direction Y. Therefore, in this embodiment, the first transistor structure 8 and the second transistor structure 9 are perpendicular to each other, and the second transistor structure 9 is vertically disposed, which can reduce the area occupied on substrate 1, thereby increasing the integration density of the semiconductor structure and thus increasing the storage capacity.
[0048] The semiconductor structure of the embodiments of this disclosure will be described in detail below.
[0049] It should be noted that in this embodiment, "horizontal direction X" can be understood as a direction parallel to the surface of substrate 1, and "vertical direction Y" can be understood as a direction perpendicular to the surface of substrate 1. Horizontal direction X and vertical direction Y are perpendicular to each other. The terms horizontal direction X and vertical direction Y are used merely for ease of description and are not intended to be limiting.
[0050] like Figure 13 As shown, the first transistor structure 8 includes a first oxide semiconductor layer 801, a first gate dielectric layer 802, and a first gate 803 stacked from the inner wall of the first trench g1. Specifically, the first oxide semiconductor layer 801 is conformally located on the inner wall of the first trench g1, the first gate dielectric layer 802 is located on the first oxide semiconductor layer 801, and the first gate 803 is located on the first gate dielectric layer 802. Here, "conformally located" can be understood as being along the inner wall of the first trench g1.
[0051] In some embodiments, the material of the first oxide semiconductor layer 801 may include at least one of indium gallium zinc oxide and gallium-doped oxide. The material of the first gate dielectric layer 802 may be at least one of silicon oxide, silicon nitride, silicon oxynitride, and high-k materials. The material of the first gate 803 may be at least one of polysilicon, metal, metal compound, and silicide. For example, the metal may be at least one of tungsten (W), copper (Cu), and aluminum (Al), and the metal compound may be at least one of titanium nitride (TiN) and tantalum nitride (TaN). Those skilled in the art can choose according to the actual situation, and no limitation is made here.
[0052] In some embodiments, such as Figure 13 As shown, in the first transistor structure 8, a first oxide semiconductor layer 801 is located on the inner wall of the first trench g1 and on the second sidewall 22 of the second trench g2 near the first transistor structure 8. A first gate dielectric layer 802 is located on the first oxide semiconductor layer 801 in the first trench g1. A first gate 803 is located on the first gate dielectric layer 802. A portion of the first oxide semiconductor layer 801 is disposed on the second sidewall 22 of the second trench g2 to facilitate connection with the source and drain of the first transistor structure 8.
[0053] In some embodiments, such as Figure 13 As shown, the second transistor structure 9 is disposed in the second trench g2 along the vertical direction Y. The second transistor structure 9 includes a second oxide semiconductor layer 901, a second gate dielectric layer 902 and a second gate 903 stacked on the first sidewall 21 of the second trench g2 away from the first transistor structure 8. The second oxide semiconductor layer 901 is connected to the first gate 803.
[0054] The second trench g2 has opposing first sidewalls 21 and second sidewalls 22, the first sidewall 21 being located on the side of the second trench g2 away from the first transistor structure 8, and the second sidewall 22 being located on the side of the second trench g2 closer to the first transistor structure 8. For example... Figure 13 As shown, a portion of the second transistor structure 9 is located on the first sidewall 21, that is, the second oxide semiconductor layer 901 is located on the first sidewall 21, the second gate dielectric layer 902 is located on the second oxide semiconductor layer 901, and the second gate 903 is located on the second gate dielectric layer 902.
[0055] In some embodiments, the material of the second oxide semiconductor layer 901 may include at least one of indium gallium zinc oxide and gallium-doped oxide, and the material of the second oxide semiconductor layer 901 may be the same as the material of the first oxide semiconductor layer 801. The material of the second gate dielectric layer 902 may be at least one of silicon oxide, silicon nitride, silicon oxynitride, and high-k materials, and the material of the second gate dielectric layer 902 may be the same as the material of the first gate dielectric layer 802. The material of the second gate 903 may be at least one of polysilicon, metal, metal compound, and silicide. For example, the metal may be at least one of tungsten (W), copper (Cu), and aluminum (Al), and the metal compound may be at least one of titanium nitride (TiN) and tantalum nitride (TaN). The material of the second gate 903 may be the same as the material of the first gate 803.
[0056] In some embodiments, such as Figure 13 As shown, the semiconductor structure also includes a first insulating layer 10 located at the bottom of the second trench g2, and the top surface of the first insulating layer 10 reaches the first gate 803. A portion of the second transistor structure 9 consists of a second oxide semiconductor layer 901, a second gate dielectric layer 902, and a second gate 903 layer stacked on the first insulating layer 10.
[0057] like Figure 13 As shown, the first insulating layer 10 is located at the bottom of the second trench g2, and a portion of the transistors are located on the first insulating layer 10, so that the first insulating layer 10 supports the second transistor structure 9. In some embodiments, the top surface of the first insulating layer 10 reaches the first gate 803, that is, in the vertical direction Y, the top surface of the first insulating layer 10 is located within the range of the first gate 803. The second oxide semiconductor layer 901 of the portion of the second transistor structure 9 is located on the first insulating layer 10 and extends directly to connect with the surface of the first gate 803. The second gate dielectric layer 902 is located on the second oxide semiconductor layer 901, and the second gate 903 is located on the second gate dielectric layer 902. The second gate 903 is not connected to the first gate 803 to prevent short circuit between them.
[0058] In some embodiments, the material of the first insulating layer 10 includes at least one of silicon nitride, silicon oxide, and silicon oxynitride. Since the first oxide semiconductor layer 801 and the second oxide semiconductor layer 901 are sensitive to water and oxygen, the first insulating layer 10 can block water and oxygen in the air, reduce the impact of water and oxygen on the first oxide semiconductor layer 801 and the second oxide semiconductor layer 901, and enhance the stability of the first transistor structure 8 and the second transistor structure 9.
[0059] In some embodiments, such as Figure 13 As shown, the semiconductor structure also includes a second insulating layer 11 located in the remaining space of the second trench g2 having a second gate 903, which insulates the second gate 903 from the first gate 803.
[0060] like Figure 13 As shown, in some embodiments, the second insulating layer 11 is formed on the second oxide semiconductor layer 802 located on the first insulating layer 10, and the second gate 903 is insulated and isolated from the first gate 803 and the first oxide semiconductor layer 801 located on the second sidewall 22.
[0061] In some embodiments, the material of the second insulating layer 11 includes at least one of a low-k dielectric material and silicon nitride. By providing the second insulating layer 11, coupling between the first transistor structure 8 and the second transistor structure 9 can be avoided, reducing the coupling effect between the first transistor structure 8 and the second transistor structure 9.
[0062] In some embodiments, such as Figure 13 As shown, in the second transistor structure 9, the second oxide semiconductor layer 901 is located on the first sidewall 21 of the second trench g2 away from the first transistor structure 8 and on the top surface covering the first insulating layer 10 to the surface connected to the first gate 803. The second gate dielectric layer 902 is located on the second oxide semiconductor layer 901. The second gate 903 is located between the second gate dielectric layer 902 and the second insulating layer 11. That is, the second transistor structure 9 and the first transistor structure 8 are spaced apart, and the second oxide semiconductor layer 901 of the second transistor structure 9 is connected to the first gate 803 of the first transistor structure 8 to realize the establishment of a storage node between the second transistor structure 9 and the first transistor structure 8.
[0063] In some embodiments, such as Figure 13As shown, the semiconductor structure further includes a third oxide semiconductor layer 804, located on the substrate 1 of the second trench g2 near the side of the first transistor structure 8, and the third oxide semiconductor layer 804 is connected to the first oxide semiconductor layer 801. The semiconductor structure may also include a fourth oxide semiconductor layer 904, located on the substrate 1 of the second trench g2 near the side of the second transistor structure 9, and the fourth oxide semiconductor layer 904 is connected to the second oxide semiconductor layer 901.
[0064] like Figure 13 As shown, the third oxide semiconductor layer 804 is located on the substrate 1 near the first transistor structure 8, and the third oxide semiconductor layer 804 is connected to the first oxide semiconductor layer 801 located on the second sidewall 22 of the second trench g2. The third oxide semiconductor layer 804 can serve as a lead to electrically connect the first oxide semiconductor layer 801 to the source and drain of the first transistor structure 8 (not shown in the figure). The fourth oxide semiconductor layer 904 is connected to the second oxide semiconductor layer 901 located on the first sidewall 21 of the second trench g2. The fourth oxide semiconductor layer 904 can also serve as a lead to electrically connect the second oxide semiconductor layer 901 to the source and drain of the second transistor structure 9 (not shown in the figure). Thus, the semiconductor structure of this embodiment can be a 2T0C memory cell.
[0065] like Figure 14 The diagram illustrates a semiconductor structure as a 2TOC memory cell according to an embodiment of the present disclosure. The first transistor structure 8 can serve as a read transistor, and the second transistor structure 9 can serve as a write transistor. One of the source and drain terminals of the write transistor is electrically connected to the gate of the read transistor (i.e., the second oxide semiconductor layer 901 of the second transistor structure 9 is connected to the first gate 803 of the first transistor structure 8), the other of the source and drain terminals of the write transistor is electrically connected to the write bit line WBL, and the gate of the write transistor is electrically connected to the write word line WWL. One of the source and drain terminals of the read transistor is electrically connected to the read bit line RBL, and the other of the source and drain terminals of the read transistor is electrically connected to the read word line RWL.
[0066] During a write operation, the voltage of the read bit line RBL is 0, the read transistor is not working, and a first write word line control signal is provided to the write word line WWL, which turns on the write transistor. When writing the first logic information, such as "0", the first write bit line control signal is provided to the write bit line WBL, and the first write bit line control signal is written to node N through the write transistor. When writing the second logic information, such as "1", the second write bit line control signal is provided to the write bit line WBL, and the second write bit line control signal is written to node N through the write transistor. After the write operation is completed, a read operation is performed. During the read operation, a second write word line control signal is provided to the write word line WWL, which turns off the write transistor, making it no longer working. At this time, the potential of the storage node N is unaffected. A read word line control signal is provided to the read word line RWL, and the stored logic information is determined based on the current level on the read bit line RBL, and then read. For example, when the logic information stored in memory node N is "0", the control signal of the read word line RWL turns on the read transistor, causing the voltage on the read bit line RBL to increase and the current to increase. When the logic information stored in memory node N is "1", the control signal of the read word line RWL turns off the read transistor, causing the voltage on the read bit line RBL to be 0 and the current to be smaller.
[0067] In some embodiments, the material of the third semiconductor oxide layer 5 can be the same as the material of the first oxide semiconductor layer 801, and the material of the fourth oxide semiconductor layer 904 can be the same as the material of the second oxide semiconductor layer 901, which is beneficial for the electrical connection between the two.
[0068] In summary, in the semiconductor structure of this embodiment, the first transistor structure 8 is disposed in the first trench g1 along the horizontal direction X, and the second transistor structure 9 is disposed in the second trench g2 along the vertical direction Y, so that the first transistor structure 8 and the second transistor structure 9 are arranged perpendicular to each other, saving the area occupied on the substrate 1, thereby improving the integration density of the semiconductor structure and increasing the storage capacity.
[0069] This disclosure also provides a method for fabricating a semiconductor structure, such as... Figures 1 to 13 A schematic diagram of the semiconductor structure during the fabrication process is shown. Figure 15 A flowchart of the preparation method is shown.
[0070] like Figure 15 As shown, the preparation method includes the following steps S151 to S153.
[0071] S151: Provide a substrate 1, and form a first trench g1 extending in the horizontal direction X and a second trench g2 extending in the vertical direction Y on the substrate 1, wherein the opening of the first trench g1 faces the second trench g2 and communicates with one side of the second trench g2.
[0072] like Figure 1 As shown, the material of substrate 1 can be silicon, silicon carbide, silicon-on-insulator, silicon-on-insulator stacked, silicon-germanium-on-insulator stacked, silicon-germanium-on-insulator, or germanium-on-insulator, etc. Substrate 1 can also be implanted with certain dopants to change the electrical parameters according to design requirements.
[0073] Shallow trench isolation is formed in substrate 1, and active regions are disposed between the shallow trench isolations. Substrate 1 also has word line structures and bit line structures (not shown in the figure), which are located at different heights in substrate 1, and both word line structures and bit line structures are connected to the active regions. The word line structure includes write word lines and read word lines, and the bit line structure includes write bit lines and read bit lines.
[0074] The formation of a first trench g1 extending in the horizontal direction X on the substrate 1 includes the following contents A1 to A4.
[0075] A1: A barrier layer 2 is formed on substrate 1 to block part of substrate 1.
[0076] like Figure 2 As shown, a barrier layer 2 covering the surface of substrate 1 can be formed using a deposition process, and then a first photoresist layer 3 can be formed on a portion of the barrier layer 2, such as... Figure 3 As shown, the barrier layer 2 that is not covered by the first photoresist can be removed by an etching process, exposing part of the surface of the substrate 1.
[0077] The deposition process can be at least one of chemical vapor deposition, physical vapor deposition, and atomic layer deposition. The etching process can be either wet etching or dry etching, and those skilled in the art can choose according to the actual situation; no limitation is made here.
[0078] A2: Oxygen is injected into the exposed substrate 1 using an oxygen injection isolation process to form a silicon oxide layer 4 between the first preset depth d1 and the second preset depth d2 of the substrate 1.
[0079] Oxygen-on-Insulator (SOI) technology involves embedding a layer of silicon oxide as an insulating layer in a silicon substrate. For example... Figure 4 As shown, oxygen is injected into the exposed substrate 1 using an oxygen injection isolation process. The injected oxygen reacts with the silicon substrate 1 to generate a silicon oxide layer 4, so that the silicon oxide layer 4 is formed between the first preset depth d1 and the second preset depth d2 in the substrate 1, that is, a silicon oxide layer 4 is buried in the substrate 1.
[0080] In some embodiments, the first pre-examination depth d1 and the second preset depth d2 can be adjusted according to the parameters of the oxygen injection isolation process. Those skilled in the art can adjust them according to the actual situation, and no special limitation is made here.
[0081] A3: A second trench g2 extending in the vertical direction Y is formed on one side of the silicon oxide layer 4, and one end of the silicon oxide layer 4 is exposed in the second trench g2.
[0082] like Figure 5 As shown, after forming the silicon oxide layer 4, the remaining barrier layer 2 is removed, exposing the surface of the substrate 1, as follows. Figure 6 As shown, a mask layer is then formed on the surface of substrate 1 using a deposition process. The mask layer may include an oxide layer 5 and a silicon nitride layer 6 sequentially stacked on substrate 1. The oxide layer 5 may be made of at least one of silicon oxide and silicon oxynitride.
[0083] like Figure 7 As shown, a second photoresist layer 7 with a second trench g2 pattern can be formed on the mask layer using a deposition process, such as... Figure 8 As shown, the pattern of the second trench g2 is transferred to a mask layer, and the substrate 1 is etched downwards using this mask layer to form the second trench g2 in the substrate 1. (Continue to refer to...) Figure 8 The second trench g2 has opposing first sidewalls 21 and second sidewalls 22, wherein the first sidewall 21 is a sidewall away from the silicon oxide layer 4, and the second sidewall 22 is a sidewall close to the silicon oxide layer 4, and the second sidewall 22 exposes the silicon oxide layer 4, that is, the silicon oxide layer 4 can be part of the second sidewall 22. Figure 9 As shown, the mask layer located on the surface of substrate 1 is removed to expose the surface of substrate 1.
[0084] A4: A portion of the silicon oxide layer 4 is etched along the horizontal direction X from the second trench g2 to form the first trench g1.
[0085] like Figure 10 As shown, a wet etching process can be used to etch the silicon oxide layer 4 embedded in the substrate 1 along the horizontal direction X. After etching to a certain extent, a portion of the silicon oxide layer 4 is retained, and the space formed after etching is the first trench g1. In some embodiments, hydrofluoric acid solution can be used as the etchant, which has a high etch selectivity for silicon oxide. Therefore, during etching, only the silicon oxide layer 4 is etched, and the substrate 1 is not etched. This avoids damage to the substrate 1 while forming the first trench g1.
[0086] S152: A first transistor structure 8 extending in the horizontal direction X is formed in the first trench g1, including: a first oxide semiconductor layer 801, a first gate dielectric layer 802 and a first gate 803 formed from the inner wall of the first trench g1.
[0087] S152 may include the following contents B1 to B3.
[0088] B1: A first oxide semiconductor layer 801 is formed on the inner wall of the first trench g1 and on the second sidewall 22 of the second trench g2 near the first transistor structure 8.
[0089] like Figure 11 As shown, for example, an atomic layer deposition process can be used to form a first oxide semiconductor layer 801 on the inner wall of the first trench g1 and the second sidewall 22 of the second trench g2. Forming the first oxide semiconductor layer 801 on the second sidewall 22 of the second trench g2 allows the first oxide semiconductor layer 801 to be extended, facilitating its connection to the source and drain of the first transistor structure 8.
[0090] B2: A first gate dielectric layer 802 is formed on the first oxide semiconductor layer 801 located in the first trench g1.
[0091] Continue to refer to Figure 11 A deposition process can be used to form the first gate dielectric layer 802 only on the first oxide semiconductor layer 801 located within the first trench g1. In some embodiments, the material of the first gate dielectric layer 802 may be at least one of silicon oxide, silicon nitride, silicon oxynitride, and high-k materials.
[0092] B3: Fill the first gate 803 in the first trench g1 that forms the first gate dielectric layer 802.
[0093] Continue to refer to Figure 11 After the gate dielectric layer is formed, a first gate 803 can be formed in the first trench g1 using a deposition process. In some embodiments, in the vertical direction Y, the exposed surface of the first gate 803 is flush with the surface of the first oxide semiconductor layer 801 located on the second sidewall 22 to avoid affecting the formation of the second transistor structure 9.
[0094] S153: A second transistor structure 9 is formed in the second trench g2 along the vertical direction Y, including: a second oxide semiconductor layer 901, a second gate dielectric layer 902 and a second gate 903 are formed on the first sidewall 21 of the second trench g2 away from the first transistor, and the second oxide semiconductor layer 901 is connected to the first gate 803.
[0095] In some embodiments, the second transistor structure 9 may be formed only on the first sidewall 21 of the second trench g2. For example, a second oxide semiconductor layer 901 may be formed on the first sidewall 21 using a deposition process, followed by a second gate dielectric layer 902 on the second oxide semiconductor layer 901, and then a second gate 903 on the gate dielectric layer. It should be noted that the second gate 903 does not contact the bottom wall of the substrate 1 to avoid short circuits. The second gate dielectric layer 902 may be formed on the bottom wall of the second trench g2, such that the second gate dielectric layer 902 insulates the bottom end of the second gate 903 from the substrate 1 portion of the bottom wall of the second trench g2. Simultaneously, the second oxide semiconductor layer 901 may be electrically connected to the first gate 803.
[0096] In other embodiments, such as Figure 12 As shown, before forming the second transistor structure 9 arranged in the vertical direction Y in the second trench g2, the fabrication method further includes: forming a first insulating layer 10 at the bottom of the second trench g2, and making the top surface of the first insulating layer 10 reach the first gate 803.
[0097] like Figure 12 As shown, a first insulating layer 10 can be formed at the bottom of the second trench g2 using a deposition process, and the top surface of the first insulating layer 10 can reach the first gate 803, so as to provide support for the subsequently formed second transistor structure 9.
[0098] After forming the first insulating layer 10, forming a second transistor structure 9 arranged in the vertical direction Y in the second trench g2 includes: forming a second oxide semiconductor layer 901, a second gate dielectric layer 902 and a second gate 903 layer, which are partially stacked on the first insulating layer 10, to form a portion of the second transistor structure 9.
[0099] That is, after the first insulating layer 10 is formed, the second transistor structure 9 is formed on the first sidewall 21 of the second trench g2 and the first insulating layer 10. For example... Figure 13As shown, a first oxide semiconductor layer 801 is formed on the first sidewall 21 of the second trench g2 and the first insulating layer 10. The first oxide semiconductor layer 801 on the first insulating layer 10 extends horizontally in the direction X to connect with the first gate 803, thereby setting a storage node between the first transistor structure 8 and the second transistor structure 9. A second gate dielectric layer 902 can then be formed on the second oxide semiconductor layer 901, and then a second gate 903 can be formed on the second gate dielectric layer 902. It should be noted that there is a gap between the second gate 903 and the first gate 803 to prevent electrical connection between them. The formation of the first insulating layer 10, in addition to supporting the second transistor structure 9, also blocks water and oxygen in the air, reducing the impact of water and oxygen on the first oxide semiconductor layer 801 and the second oxide semiconductor layer 901, and enhancing the stability of the first transistor structure 8 and the second transistor structure 9.
[0100] In some embodiments, such as Figure 13 As shown, after forming a second transistor structure 9 disposed in the vertical direction Y in the second trench g2, the process includes: forming a second insulating layer 11 in the remaining space of the second trench g2 having a second gate 903 to insulate and isolate the second gate 903 from the first gate 803.
[0101] like Figure 13 As shown, after forming the second transistor structure 9, a second insulating layer 11 can be formed in the remaining space of the second trench g2 using a deposition process. The second insulating layer 11 can insulate and isolate the second gate 903 from the first transistor structure 8. In addition, the second insulating layer 11 can also prevent the first transistor structure 8 and the second transistor structure 9 from coupling, reducing the coupling effect between the first transistor structure 8 and the second transistor structure 9.
[0102] In some embodiments, the material of the second insulating layer 11 may include at least one of a low-k dielectric material and silicon nitride.
[0103] In some embodiments, the method for fabricating the semiconductor structure further includes: forming a third oxide semiconductor layer 804 and a fourth oxide semiconductor layer 904 on the surface of a substrate 1 using a deposition process. Wherein, as... Figure 13As shown, the third oxide semiconductor layer 804 is located on the substrate 1 of the second trench g2 near the side of the first transistor structure 8. One end of the third oxide semiconductor layer 804 is connected to the first oxide semiconductor layer 801, and the other end of the third oxide semiconductor layer 804 is connected to the source and drain of the first transistor structure 8. That is, the third oxide semiconductor layer 804 acts as a lead, enabling the first oxide semiconductor layer 801 of the first transistor structure 8 to be electrically connected to its source and drain. The fourth oxide semiconductor layer 904 is located on the substrate 1 of the second trench g2 near the side of the second transistor structure 9. One end of the fourth oxide semiconductor layer 904 is connected to the second oxide semiconductor layer 901, and the other end can be connected to the source and drain of the second transistor structure 9. That is, the fourth oxide semiconductor layer 904 can act as a lead, enabling the second oxide semiconductor layer 901 of the second transistor structure 9 to be electrically connected to its source and drain.
[0104] In some embodiments, the first oxide semiconductor layer 801, the second oxide semiconductor layer 901, the third oxide semiconductor layer 804, and the fourth oxide semiconductor layer 904 can be made of the same material. This avoids the need to change materials during the process, and the third oxide semiconductor layer 804 and the fourth oxide semiconductor layer 904 can be formed in one step using the same deposition process, simplifying the process. Simultaneously, it makes the connection between the first oxide semiconductor layer 801 and the third oxide semiconductor layer 804, the second oxide semiconductor layer 901, and the fourth oxide semiconductor layer 904 more stable, thereby making the electrical performance of the entire semiconductor structure more stable. Of course, the materials of the first to fourth oxide semiconductor layers can also be different or partially the same; those skilled in the art can choose according to the actual situation, and this is not limited here.
[0105] In summary, the semiconductor structure fabrication method of this disclosure involves forming a first transistor structure 8 disposed in a first trench g1 along the horizontal direction X, and forming a second transistor structure 9 disposed in a second trench g2 along the vertical direction Y, such that the first transistor structure 8 and the second transistor structure 9 are arranged perpendicularly to each other, saving the area occupied on the substrate 1, thereby improving the integration density of the semiconductor structure and increasing the storage capacity.
[0106] It should be understood that this disclosure is not limited to the detailed structure and arrangement of the components presented in this specification. This disclosure is capable of other embodiments and can be implemented and performed in various ways. The foregoing variations and modifications fall within the scope of this disclosure. It should be understood that this disclosure, as disclosed and defined in this specification, extends to all alternative combinations of two or more individual features mentioned or apparent in the text and / or drawings. All these different combinations constitute multiple alternative aspects of this disclosure. The embodiments described in this specification illustrate the best known mode for implementing this disclosure and will enable those skilled in the art to adopt this disclosure.
Claims
1. A semiconductor structure, characterized in that, include: The substrate includes a first trench extending in a horizontal direction and a second trench extending in a vertical direction, wherein the opening of the first trench faces the second trench and communicates with one side of the second trench; A first transistor structure is disposed in the first trench along the horizontal direction. The first transistor structure includes a first oxide semiconductor layer, a first gate dielectric layer and a first gate stacked from the inner wall of the first trench. The second transistor structure is disposed in the second trench along the vertical direction. The second transistor structure includes a second oxide semiconductor layer, a second gate dielectric layer and a second gate stacked on the first sidewall of the second trench away from the first transistor structure. The second oxide semiconductor layer is connected to the first gate. A first insulating layer is located at the bottom of the second trench, and the top surface of the first insulating layer reaches the first gate. The second oxide semiconductor layer, the second gate dielectric layer, and the second gate layer of a portion of the second transistor structure are stacked on the first insulating layer.
2. The semiconductor structure according to claim 1, characterized in that, Also includes: A second insulating layer, located in the remaining space of the second trench having the second gate, insulates and isolates the second gate from the first gate.
3. The semiconductor structure according to claim 2, characterized in that, In the second transistor structure: The second oxide semiconductor layer is located on the first sidewall of the second trench away from the first transistor structure and on the top surface covering the first insulating layer to the surface connected to the first gate. The second gate dielectric layer is located on the second oxide semiconductor layer; The second gate is located between the second gate dielectric layer and the second insulating layer.
4. The semiconductor structure according to claim 1, characterized in that, In the first transistor structure: The first oxide semiconductor layer is located on the inner wall of the first trench and on the second sidewall of the second trench near the first transistor structure; The first gate dielectric layer is located on the first oxide semiconductor layer in the first trench; The first gate is located on the first gate dielectric layer.
5. The semiconductor structure according to any one of claims 1 to 4, characterized in that, The materials of the first oxide semiconductor layer and the second oxide semiconductor layer respectively include at least one of indium gallium zinc oxide and gallium-doped zinc oxide.
6. The semiconductor structure according to any one of claims 1 to 4, characterized in that, Also includes: A third oxide semiconductor layer is located on the substrate on the side of the second trench closer to the first transistor structure, and the third oxide semiconductor layer is connected to the first oxide semiconductor layer; And / or, A fourth oxide semiconductor layer is located on the substrate on the side of the second trench near the second transistor structure, and the fourth oxide semiconductor layer is connected to the second oxide semiconductor layer.
7. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, and a first trench extending in a horizontal direction and a second trench extending in a vertical direction are formed on the substrate, wherein the opening of the first trench faces the second trench and communicates with one side of the second trench; Forming a first transistor structure extending along the horizontal direction in the first trench includes: forming a first oxide semiconductor layer, a first gate dielectric layer, and a first gate stacked from the inner wall of the first trench; Forming a second transistor structure in the second trench along the vertical direction includes: forming a stacked second oxide semiconductor layer, a second gate dielectric layer, and a second gate on a first sidewall of the second trench away from the first transistor, wherein the second oxide semiconductor layer is connected to the first gate. Before forming a second transistor structure disposed along the vertical direction in the second trench, the method further includes: forming a first insulating layer at the bottom of the second trench, and making the top surface of the first insulating layer reach the first gate. Forming a second transistor structure in the second trench along the vertical direction includes: forming a stacked second oxide semiconductor layer, a second gate dielectric layer, and a second gate layer on the first insulating layer, which partially form the second transistor structure; After forming a second transistor structure disposed in the vertical direction in the second trench, the process includes: A second insulating layer is formed in the remaining space of the second trench having the second gate, thereby insulating and isolating the second gate from the first gate.
8. The method according to claim 7, characterized in that, The first oxide semiconductor layer, the first gate dielectric layer, and the first gate electrode, stacked from the inner wall of the first trench, include: A first oxide semiconductor layer is formed on the inner wall of the first trench and on the second sidewall of the second trench near the first transistor structure; A first gate dielectric layer is formed on the first oxide semiconductor layer located in the first trench; The first gate is filled in the first trench forming the first gate dielectric layer.