Semiconductor structure and method of manufacturing the same

Abstract

This disclosure relates to a semiconductor structure and its fabrication method. The semiconductor structure includes: a substrate comprising an array region and a peripheral region; a bit line structure located on the substrate in the array region, the bit line structure including a first dielectric layer and a first conductive layer sequentially stacked along a direction away from the substrate surface; and a gate structure located on the substrate in the peripheral region, the gate structure including a gate dielectric layer, a second conductive layer, and a second dielectric layer sequentially stacked along a direction away from the substrate surface, wherein the dielectric constant of the second dielectric layer is greater than the dielectric constant of the first dielectric layer. The semiconductor structure provided by this disclosure can at least improve the reliability of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] DRAM (Dynamic Random Access Memory) is a common type of semiconductor memory, typically consisting of a core array region and a peripheral region. The array region contains bit lines, which are used for signal transmission between the array region and the transistors. The peripheral region contains gate structures, which control the conduction of the transistors in the peripheral region. During the semiconductor structure fabrication process, the bit lines and the gate structures of the peripheral region are usually fabricated based on film layers formed in the same step. Patterning processes are performed on the film layers of the peripheral region and the array region separately to form the gate structure in the peripheral region and the bit lines in the array region.

[0003] The magnitude of parasitic capacitance in the array region and leakage current in the peripheral region have a significant impact on the reliability of semiconductor structures. Currently, the reliability of semiconductor structures still needs further improvement. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and its fabrication method, which at least helps to improve the reliability of the semiconductor structure.

[0005] This disclosure provides a semiconductor structure, including: a substrate, the substrate including an array region and a peripheral region; a bit line structure located on the substrate of the array region, the bit line structure including a first dielectric layer and a first conductive layer stacked sequentially in a direction away from the substrate surface; and a gate structure located on the substrate of the peripheral region, the gate structure including a gate dielectric layer, a second conductive layer and a second dielectric layer stacked sequentially in a direction away from the substrate surface, the dielectric constant of the second dielectric layer being greater than the dielectric constant of the first dielectric layer.

[0006] In some embodiments, the material of the first dielectric layer includes titanium nitride, and the material of the second dielectric layer includes silicon-doped metal nitride.

[0007] In some embodiments, the thickness of the first dielectric layer is not less than the thickness of the second dielectric layer.

[0008] In some embodiments, the gate structure further includes a third conductive layer located on the side of the second dielectric layer away from the substrate surface.

[0009] In some embodiments, the material of the first conductive layer is the same as the material of the third conductive layer, and the thickness of the first conductive layer is equal to the thickness of the third conductive layer.

[0010] Accordingly, this disclosure also provides a method for fabricating a semiconductor structure, comprising: providing a substrate having an array region and a peripheral region; forming a bit line structure on the substrate of the array region, the bit line structure including a first dielectric layer and a first conductive layer stacked sequentially in a direction away from the substrate surface; and forming a gate structure on the substrate of the peripheral region, the gate structure including a second conductive layer and a second dielectric layer stacked sequentially in a direction away from the substrate surface, wherein the dielectric constant of the second dielectric layer is greater than the dielectric constant of the first dielectric layer.

[0011] In some embodiments, the substrate of the peripheral region includes a first active region, the first active region including a first channel region; the substrate of the array region includes a second active region, the second active region including a second channel region and second source / drain regions located on both sides of the second channel region; the method of forming the bit line structure and the gate structure includes: forming an initial first dielectric layer and an initial first conductive layer sequentially stacked in a direction away from the substrate surface on the substrate of the array region; performing a first patterning process on the initial first dielectric layer and the initial first conductive layer to form a first dielectric layer and a first conductive layer facing the first channel region; forming an initial second conductive layer and an initial second dielectric layer sequentially stacked in a direction away from the substrate surface on the substrate of the peripheral region; performing a second patterning process on the initial first gate dielectric layer, the initial second conductive layer and the initial second dielectric layer to form a second conductive layer and a second dielectric layer facing the second channel region.

[0012] In some embodiments, the step of forming the initial second dielectric layer is performed before the step of forming the initial first dielectric layer. The step of forming the initial second dielectric layer includes: forming a primary second conductive layer on the substrate surface of the peripheral region and the array region; forming a primary second dielectric layer on the surface of the primary second conductive layer; removing the primary second conductive layer and the primary second dielectric layer located in the array region, with the remaining primary second conductive layer forming the initial second conductive layer, and the remaining primary second dielectric layer forming the initial second dielectric layer.

[0013] In some embodiments, the method of forming the initial first dielectric layer includes: forming an original first dielectric layer on a substrate of the array region and on the surface of the initial second dielectric layer; forming a protective layer on the surface of the original first dielectric layer located in the array region, the protective layer exposing the original first dielectric layer located on the surface of the initial second dielectric layer; removing the original first dielectric layer located on the surface of the initial second dielectric layer using a wet etching process, the remaining original first dielectric layer located in the array region forming the initial first dielectric layer.

[0014] In some embodiments, the method of forming the first conductive layer includes: forming an initial first conductive layer on the surface of an initial first dielectric layer in the array region and an initial second dielectric layer in the peripheral region; performing a first patterning process on the initial first conductive layer located in the array region to form the first conductive layer; and performing a second patterning process on the initial first conductive layer located in the peripheral region to form a third conductive layer, wherein the third conductive layer is used to constitute the gate structure.

[0015] The technical solutions provided in this disclosure have at least the following advantages:

[0016] In the semiconductor structure provided in this embodiment, the first dielectric layer in the bit line structure acts as a diffusion barrier for the first conductive layer, and the second dielectric layer in the gate structure acts as a gate dielectric layer. The dielectric constant of the first dielectric layer is smaller than that of the second dielectric layer, meaning the dielectric constant of the first dielectric layer in the bit line structure is small, thus ensuring a small parasitic capacitance in the array region. The dielectric constant of the second dielectric layer in the peripheral region is large, which can reduce the equivalent gate oxide thickness of the gate dielectric layer in the peripheral region, thereby reducing the parasitic capacitance of the array region while simultaneously reducing the equivalent gate oxide thickness of the peripheral region. Attached Figure Description

[0017] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a cross-sectional structural diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0019] Figures 2 to 16 This is a schematic cross-sectional view of different steps in a method for fabricating a semiconductor structure according to another embodiment of this disclosure. Detailed Implementation

[0020] As the background technology shows, the reliability of current semiconductor structures needs further improvement. Analysis reveals that one reason for this is that current semiconductor structures, including the array region and the peripheral region, have their bit line structure and gate structure film layers formed in the same step. Therefore, the materials and thicknesses of the film layers in both are usually consistent, including the diffusion barrier layer. Based on the formula C = KS / d (where K is the dielectric constant of the dielectric between the plates, S is the plate area, and d is the distance between the plates), to ensure a small parasitic capacitance in the array region, the dielectric constant of the dielectric layer in the array region needs to be small. However, based on the formula EOT = (K... SiO2 / K hk )×T HK (EOT is the equivalent gate oxide thickness, K) SiO2 K is the dielectric constant of SiO2. hk T is the dielectric constant of the high-k dielectric material. HK As can be seen from the physical thickness of the high-k dielectric material, the smaller the dielectric constant of the dielectric layer, the larger the equivalent gate oxide thickness of the gate dielectric layer. Therefore, if the dielectric constant of the dielectric layer in the peripheral region is small, it will lead to an excessively large equivalent gate oxide thickness in the peripheral region, which may result in excessive gate leakage current in the gate structure of the peripheral region and reduced reliability. Thus, it is clear that current technology cannot reduce the parasitic capacitance of the array region while simultaneously reducing the equivalent gate oxide thickness of the peripheral region, resulting in lower reliability of the semiconductor structure.

[0021] This disclosure provides a semiconductor structure in which the first dielectric layer in the bit line structure has a low dielectric constant, thereby ensuring a small parasitic capacitance in the array region. The second dielectric layer in the peripheral region has a high dielectric constant, which can reduce the equivalent gate oxide thickness of the gate dielectric layer in the peripheral region. This reduces the parasitic capacitance of the array region while simultaneously lowering the equivalent gate oxide thickness in the peripheral region.

[0022] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0023] Figure 1 This is a cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure.

[0024] refer to Figure 1The semiconductor structure includes: a substrate 101, which includes an array region 1 and a peripheral region 2. The semiconductor structure also includes: a bit line structure located on the substrate of the array region 1, the bit line structure including a first dielectric layer 102 and a first conductive layer 103 stacked sequentially along a direction away from the surface of the substrate 101. The semiconductor structure further includes: a gate structure located on the substrate 101 of the peripheral region 2, the gate structure including a second conductive layer 104 and a second dielectric layer 105 stacked sequentially along a direction away from the surface of the substrate 101, the dielectric constant of the second dielectric layer 105 being greater than the dielectric constant of the first dielectric layer 102.

[0025] In some embodiments, the substrate 101 may be made of a semiconductor material. In some embodiments, the substrate 101 may be made of silicon. In some embodiments, the substrate 101 may also be made of germanium, germanium-silicon, or silicon on an insulator.

[0026] In some embodiments, the substrate 101 of the peripheral region 2 includes a first active region 10, the first active region 10 includes a first channel region, the second conductive layer 104 is electrically connected to the first channel region, the second conductive layer 104 has a first doped ion, the first channel region has a second doped ion, and the conductivity type of the first doped ion is the same as that of the second doped ion.

[0027] The second conductive layer 104 is located above the first channel region and is electrically connected to the first channel region.

[0028] In some embodiments, the first dopant ion and the second dopant ion can both be N-type dopant ions, and the N-type dopant ion can be any one of phosphorus ion, bismuth ion, antimony ion or arsenic ion.

[0029] In some embodiments, the first dopant ion and the second dopant ion can both be P-type dopant ions, and the P-type dopant ion can be any one of boron ion, aluminum ion, gallium ion or indium ion.

[0030] The second conductive layer 104 is doped with the same type of dopant ions as the first channel region, which can improve and reduce carrier accumulation in the gate structure when the first channel region is turned on, and can improve the gate depletion effect.

[0031] The second dielectric layer 105 serves as the gate dielectric layer of the gate structure. Since the second dielectric layer 105 has a high dielectric constant, directly forming it on the surface of the substrate 101 would result in poor formation quality, negatively impacting the electrical performance of the transistor in the peripheral region 2. By placing the second conductive layer 104 between the substrate 101 and the second dielectric layer 105, a good interface is provided between them, thereby improving the interface characteristics.

[0032] The equivalent gate oxide thickness is defined as the thickness of the SiO2 gate dielectric layer when the actual physical thickness of the high-k gate dielectric layer and the SiO2 gate dielectric layer achieve the same gate capacitance. The smaller the equivalent gate oxide thickness of the gate dielectric layer, the more it can achieve a much thicker actual physical thickness than the SiO2 gate dielectric layer while having the same equivalent thickness. This can improve serious problems such as excessive gate leakage current and reduced reliability caused by the SiO2 gate dielectric layer approaching its thickness limit.

[0033] In some embodiments, the material of the second conductive layer 104 may be polycrystalline silicon.

[0034] In this embodiment, the dielectric constant of the first dielectric layer 102 in the bit line structure is smaller than the dielectric constant of the second dielectric layer 105 in the gate structure of the peripheral region 2. That is, the dielectric constant of the first dielectric layer 102 in the bit line structure is small, thus ensuring a small parasitic capacitance in the array region 1. The dielectric constant of the second dielectric layer 105 in the peripheral region 2 is large, resulting in a smaller equivalent gate oxide thickness for the second dielectric layer 105 as the gate dielectric layer of the gate structure. This leads to stronger electrical performance of the transistor in the peripheral region 2, enabling it to withstand larger electric fields and faster carrier velocity, thereby reducing the gate leakage current of the gate structure in the peripheral region 2 and improving the reliability of the semiconductor structure.

[0035] In some embodiments, the equivalent gate oxide thickness of the second dielectric layer 105 is 0.2 Å to 0.8 Å. Within this range, the equivalent gate oxide thickness of the second dielectric layer 105 is relatively small, which can effectively reduce the gate leakage current of the peripheral region 2.

[0036] In some embodiments, the substrate 101 of the array region 1 includes a second active region 11, the second active region 11 includes a second channel region and second source / drain regions located on both sides of the second channel region, and the bit line structure is electrically connected to one of the second source / drain regions, wherein the second channel region has a third doped ion, and the type of the third doped ion is different from the type of the second doped ion.

[0037] The second channel region and the second source / drain regions located on both sides of the second channel region together constitute a transistor. In some embodiments, the second source / drain regions located on both sides of the second channel region include a second source region and a second drain region, wherein the second source region is used to form the source of the transistor, and the second drain region is used to form the drain of the transistor. In some embodiments, the bit line structure may be electrically connected to the second source region.

[0038] The third dopant ion type differs from the second dopant ion type, resulting in a different type of transistor formed in peripheral region 2 compared to the transistor formed in array region 1. In some embodiments, the third dopant ion can be P-type, and the transistor formed in array region 1 is an NMOS transistor. The P-type dopant ion can be any one of boron, aluminum, gallium, or indium ions. The second dopant ion type can be N-type, and the transistor formed in peripheral region 2 is an NMOS transistor. The N-type dopant ion can be any one of phosphorus, bismuth, antimony, or arsenic ions.

[0039] In some embodiments, the semiconductor structure further includes a bit line contact structure 105, which is located on the surface of the second channel region and is electrically in contact with the second channel region, and is located between the second channel region and the first dielectric layer 102.

[0040] The bit line contact structure 105 is used to electrically connect the bit line structure and the second channel region. The first dielectric layer 102 is located between the bit line contact structure 105 and the first conductive layer 103, which prevents the interdiffusion of ions in the bit line contact structure 105 and the first conductive layer 103.

[0041] In some embodiments, the bit line contact structure 105 has a fourth doped ion, the fourth doped ion having the same conductivity type as the third doped ion.

[0042] The bit line contact structure 105 and the first conductive layer 103 can be regarded as conductive plates, and the first dielectric layer 102 can be regarded as the dielectric between the plates. The first dielectric layer 102 has a relatively small dielectric constant, which makes the parasitic capacitance between the bit line contact structure 105 and the first conductive layer 103 smaller, thereby improving the response speed of the transistor in the array region 1.

[0043] In some embodiments, the bit line contact structure 105 is at least partially located within the substrate 101, with the top surface of the bit line contact structure 105 being lower than the top surface of the substrate 101, or the top surface of the bit line contact structure 105 being slightly higher than the top surface of the substrate 101.

[0044] In some embodiments, the bit line contact structure 105 has a fourth doped ion of the same type as the doped ion in the second channel region. In the actual fabrication step of the bit line contact structure 105, it is possible to avoid the formation of holes when depositing the bit line contact structure 105, thereby forming a denser bit line contact structure 105, resulting in a smaller resistance of the bit line contact structure 105 and reducing the contact resistance between the bit line contact structure 105 and the second channel region.

[0045] In some embodiments, the material of the bit line contact structure 105 may include polycrystalline silicon.

[0046] In some embodiments, the array region 1 has a plurality of second active regions 11, which are arranged at intervals. The semiconductor structure may further include an isolation structure 20, which is located between adjacent second active regions 11 and serves to isolate adjacent second active regions 11.

[0047] In some embodiments, the number of first active regions 10 in the substrate 101 of the peripheral region 2 is multiple, and the multiple first active regions 10 are arranged at intervals. Then the isolation structure 20 is also located in the substrate 101 of the peripheral region 2 and between adjacent first active regions 10, and is used to isolate adjacent first active regions 10.

[0048] In some embodiments, the material of the isolation structure 20 may be silicon oxide.

[0049] In some embodiments, the material of the first dielectric layer 102 includes titanium nitride, and the material of the second dielectric layer 105 includes silicon-doped metal nitride.

[0050] Titanium nitride has a smaller dielectric constant than silicon-doped metal nitrides, which can reduce the parasitic capacitance between the bit line structure and the substrate 101.

[0051] Silicon-doped metal nitrides are metal nitrides doped with silicon. Silicon-doped titanium nitride is an excellent dielectric material with superior electrical conductivity. Furthermore, silicon-doped metal nitrides can effectively prevent the diffusion of dopant ions in the second conductive layer 104.

[0052] Furthermore, by using silicon-doped metal nitride as the second dielectric layer 105, even if the dielectric layer is thin, the beneficial barrier properties of the second dielectric layer 105 can be utilized, thereby ensuring that the overall thickness of the gate structure is small.

[0053] It is understood that, in some embodiments, the material of the second dielectric layer 105 may also include either silicon-doped tantalum nitride or silicon-doped tungsten nitride.

[0054] In some embodiments, the thickness of the first dielectric layer 102 is not less than the thickness of the second dielectric layer 105. That is, the second dielectric layer 105 not only has a lower dielectric constant than the first dielectric layer 102, but its thickness is also less than that of the first dielectric layer 102. Here, thickness refers to physical thickness. Based on the formula EOT = (K SiO2 / K hk )×T HKIt is known that when the thickness of the second dielectric layer 105 is small, the effective gate oxide thickness is smaller, and the smaller the physical thickness of the second dielectric layer 105, the more effective gate oxide thickness can be reduced. Therefore, setting the thickness of the first dielectric layer 102 to be no less than the thickness of the second dielectric layer 105 can further reduce the effective gate oxide thickness.

[0055] In some embodiments, the physical thickness of the first dielectric layer 102 and the physical thickness of the second dielectric layer 105 can be 3:1 to 1:1. Within this range, the physical thickness of the second dielectric layer 105 is relatively small, which helps to further reduce the effective gate oxide thickness and further reduce the probability of gate leakage current in the gate structure.

[0056] In some embodiments, the gate structure further includes a third conductive layer 106, which is located on the side of the second dielectric layer 105 away from the surface of the substrate 101. The third conductive layer 106 can serve as a conductive portion in the gate structure for transmitting signals.

[0057] The second dielectric layer 105 also prevents mutual diffusion between the second conductive layer 104 and the third conductive layer 106, reducing the parasitic capacitance of the gate structure. Since the mutual diffusion problem between the second conductive layer 104 and the third conductive layer 106 is improved by setting the dielectric layer, the third conductive layer 106 can be set with a relatively small thickness, reducing the overall thickness of the gate structure.

[0058] In some embodiments, the material of the first conductive layer 103 is the same as that of the third conductive layer 106, and the thickness of the first conductive layer 103 is equal to the thickness of the third conductive layer 106. Thus, the first conductive layer 103 and the third conductive layer 106 can be formed in the same process step, greatly simplifying the manufacturing process.

[0059] In some embodiments, the thickness of the first conductive layer 103 formed in the same process step may also be approximately equal to the thickness of the third conductive layer 106.

[0060] In some embodiments, both the first conductive layer 103 and the third conductive layer 106 are made of titanium.

[0061] In some embodiments, the materials of the first conductive layer and the third conductive layer 106 may both be tungsten, copper or nickel.

[0062] In some embodiments, the bit line structure further includes a bit line capping layer 111, which is located on the surface of the first conductive layer 103 away from the substrate 101, and serves to protect the first conductive layer 103. In some embodiments, the material of the bit line capping layer 111 may be either silicon nitride or silicon oxynitride.

[0063] In some embodiments, the gate structure further includes a gate capping layer 112, which is located on the surface of the third conductive layer 106 away from the substrate 101 and serves to protect the third conductive layer 106. In some embodiments, the gate capping layer 112 may be made of either silicon nitride or silicon oxynitride.

[0064] In some embodiments, the semiconductor structure further includes a sidewall structure 120, which is located on the sidewall of the gate structure. The sidewall structure 120 provides lateral protection for the gate structure.

[0065] In some embodiments, the sidewall structure 120 may include a first sidewall layer 121, a second sidewall layer 122, and a third sidewall layer 123 arranged sequentially along the direction away from the sidewall of the gate structure. The material of the first sidewall layer 121 may be the same as that of the third sidewall layer 123, while the material of the second sidewall layer 122 may be different from that of the first sidewall layer 121. In some embodiments, the materials of the first sidewall layer 121 and the third sidewall layer 123 may both be silicon nitride, while the material of the second sidewall layer 122 may be silicon oxide. The sandwich-structured sidewall structure 120 can improve the rigidity of the sidewall structure 120, thereby enhancing the protective effect of the sidewall structure 120 on the gate structure.

[0066] In the semiconductor structure provided in the above embodiments, the first dielectric layer 102 in the bit line structure has a small dielectric constant, thereby ensuring that the parasitic capacitance of the array region 1 is small. The second dielectric layer 105 of the peripheral region 2 has a large dielectric constant, which can reduce the equivalent gate oxide thickness of the gate dielectric layer of the peripheral region 2. This reduces the parasitic capacitance of the array region 1 while simultaneously reducing the equivalent gate oxide thickness of the peripheral region 2.

[0067] Accordingly, this disclosure also provides a method for preparing a semiconductor structure, which can be used to prepare the semiconductor structure provided in the above embodiments. The semiconductor structure provided in an embodiment of this disclosure will be described in detail below with reference to the accompanying drawings.

[0068] Methods for fabricating semiconductor structures include:

[0069] refer to Figure 2 A substrate 101 is provided, which has an array region 1 and a peripheral region 2.

[0070] In some embodiments, the substrate 101 may be made of a semiconductor material. In some embodiments, the substrate 101 may be made of silicon. In some embodiments, the substrate 101 may also be made of germanium, germanium-silicon, or silicon on an insulator.

[0071] In some embodiments, a first active region 10 is formed on the substrate 101 of the peripheral region 2. The first active region 10 includes a first channel region. A first conductive layer 103 is electrically connected to the first channel region. The first conductive layer 103 has a first doped ion. The conductivity type of the first doped ion is the same as that of the doped ion in the first channel region.

[0072] In some embodiments, the substrate 101 of the peripheral region 2 further includes first source / drain regions located on both sides of the first channel region, the first channel region and the first source / drain regions forming a transistor. In some embodiments, the first source / drain region includes a first source region and a first drain region, the first source region being used to form the source of the transistor and the first drain region being used to form the drain of the transistor.

[0073] In some embodiments, the dopant ion type of the first channel region is opposite to that of the first source / drain region. For example, the dopant ion type of the first channel region can be P-type, and the dopant ion type of the first source / drain region can be N-type. Alternatively, the dopant ion type of the first channel region can be N-type, and the dopant ion type of the first source / drain region can be P-type.

[0074] In some embodiments, the substrate 101 of the array region 1 further includes a second active region 11, the second active region 11 including a second channel region and second source-drain regions located on both sides of the second channel region, the second channel region and the second source-drain regions forming a transistor. In some embodiments, the second source-drain regions include a second source region and a second drain region, the second source region being used to form the source of the transistor, and the second drain region being used to form the drain of the transistor.

[0075] In some embodiments, the dopant ion type in the second channel region is opposite to that in the second source / drain region. For example, the dopant ion type in the second channel region can be P-type, and the dopant ion type in the second source / drain region can be N-type. Alternatively, the dopant ion type in the second channel region can be N-type, and the dopant ion type in the second source / drain region can be P-type.

[0076] In some embodiments, the dopant ion type in the first channel region is different from that in the second channel region; the dopant ion type in the first channel region can be P-type, and the dopant ion type in the second channel region can be N-type. In some embodiments, the dopant ion type in the first channel region can also be N-type, and the dopant ion type in the second channel region can also be P-type.

[0077] P-type dopant ions can be any of boron ions, aluminum ions, gallium ions, or indium ions, while N-type dopant ions can be any of phosphorus ions, bismuth ions, antimony ions, or arsenic ions.

[0078] In some embodiments, the method for forming the first active region 10 and the second active region 11 includes:

[0079] An initial substrate is provided, which is an undoped and unetched substrate 101. The initial substrate includes a peripheral region 2 and an array region 1. A patterning process is performed on the surface of the initial substrate to define the positions of the first active region 10 and the second active region 11. In some embodiments, either SADP (Self-aligned Double Patterning) or SAQP (Self-Aligned Quadruple Patterning) processes can be used to pattern the surface of the initial substrate. Then, an etching process is performed on the patterned initial substrate surface to etch a portion of the initial substrate to form a plurality of spaced-apart first trenches in the substrate 101 of the peripheral region 2, and initial first active regions 10 separated by the first trenches. A portion of the initial substrate is also etched to form a plurality of spaced-apart second trenches in the substrate 101 of the array region 1, and initial second active regions 11 separated by the second trenches. The remaining portion of the initial substrate serves as substrate 101. In some embodiments, the etching process can be either a dry etching process or a wet etching process.

[0080] Next, isolation material is deposited in the first trench and the second trench to form an isolation structure 20 filling the first trench and an isolation structure 20 filling the second trench. In some embodiments, either atomic layer deposition or chemical vapor deposition can be used to form the isolation structure 20. In some embodiments, the material of the isolation structure 20 can be silicon oxide.

[0081] In some embodiments, after forming the initial first active region 10 and the initial second active region 11, a doping process is performed on the initial first active region 10 and the initial second active region 11 to implant dopant ions into the initial first active region 10 and the initial second active region 11 respectively, thereby forming the first active region 10 and the second active region 11.

[0082] In some embodiments, the initial first active region 10 includes a first region, a second region, and a third region arranged sequentially along a direction parallel to the surface of the substrate 101. The method of forming the first active region 10 may include: forming a first sacrificial layer on the surface of the initial first active region 10; the first sacrificial layer having a first opening that exposes the surface of the second region; and the first sacrificial layer covering the surfaces of the first and third regions; and performing a doping process on the second region along the first opening to implant dopant ions into the second region to form a first channel region. In some embodiments, the doping process may be an ion implantation process, and the material of the first sacrificial layer may be a photoresist.

[0083] After forming the first channel region, the first sacrificial layer is removed, and a second sacrificial layer is formed on the surface of the initial first active region 10. The second sacrificial layer has a second opening that exposes the surfaces of the first and third regions, and the second sacrificial layer also covers the second region. Doping processes are then performed along the second opening in the first and third regions, implanting dopant ions to transform them into first source / drain regions, respectively. It is noteworthy that the type of dopant ions implanted in the second region is different from the type of dopant ions implanted in the first and third regions.

[0084] In some embodiments, the method for forming the second active region 11 may refer to the above description of the method for forming the first active region 10.

[0085] refer to Figures 1 to 16 A bit line structure is formed on the substrate 101 of the array region 1. The bit line structure includes a first dielectric layer 102 and a first conductive layer 103 stacked sequentially in a direction away from the surface of the substrate 101. A gate structure is formed on the substrate 101 of the peripheral region 2. The gate structure includes a gate dielectric layer, a second conductive layer 104 and a second dielectric layer 105 stacked sequentially in a direction away from the surface of the substrate 101. The dielectric constant of the second dielectric layer 105 is greater than the dielectric constant of the first dielectric layer 102.

[0086] In the bitline structure, the first dielectric layer 102 acts as a diffusion barrier for the first conductive layer 103, while the second dielectric layer 105 in the gate structure functions as the gate dielectric layer. The dielectric constant of the first dielectric layer 102 is smaller than that of the second dielectric layer 105, meaning the dielectric constant of the first dielectric layer 102 in the bitline structure is small, thus ensuring a small parasitic capacitance in the array region 1. The dielectric constant of the second dielectric layer 105 in the peripheral region 2 is large, which reduces the equivalent gate oxide thickness of the gate dielectric layer in the peripheral region 2. This reduces both the parasitic capacitance of the array region 1 and the equivalent gate oxide thickness of the peripheral region 2.

[0087] In some embodiments, the substrate 101 of the peripheral region 2 includes a first active region 10, the first active region 10 including a first channel region; the substrate 101 of the array region 1 includes a second active region 11, the second active region 11 including a second channel region and second source / drain regions located on both sides of the second channel region 11, and the method for forming the bit line structure and the gate structure includes:

[0088] refer to Figures 8 to 16 ,as well as Figure 1 An initial first dielectric layer 1022 and an initial first conductive layer 42 are formed on the substrate 101 of the array region 1, stacked sequentially in a direction away from the surface of the substrate 101. A first patterning process is performed on the initial first dielectric layer 1022 and the initial first conductive layer 42 to form a first dielectric layer 102 and a first conductive layer 103 that are opposite to the second channel region 11.

[0089] refer to Figures 2 to 12 An initial second conductive layer 1011 and an initial second dielectric layer 1012 are formed on the substrate 101 of the peripheral region 2, stacked sequentially in a direction away from the surface of the substrate 101. A second patterning process is performed on the initial second conductive layer 1011 and the initial second dielectric layer 1012 to form a second conductive layer 104 and a second dielectric layer 105 that are opposite to the first channel region 10.

[0090] In some embodiments, a first patterning process and a second patterning process may be performed separately to form bit line structures and gate structures on the substrates 101 of the array region 1 and the peripheral region 2, respectively. In a specific example, the second patterning process may be performed before the first patterning process, that is, the gate structure is formed first, and then the bit line structure is formed.

[0091] Specifically, the steps for forming the bit line structure and gate structure are as follows:

[0092] refer to Figures 2 to 12 In some embodiments, the step of forming the initial second dielectric layer 1012 precedes the step of forming the initial first dielectric layer 1022. The step of forming the initial second dielectric layer 1012 includes:

[0093] refer to Figure 2 An original second conductive layer 31 is formed on the surface of the substrate 101 in the peripheral region 2 and the array region 1.

[0094] The original second conductive layer 31 of the peripheral region 2 is subsequently used to form the second conductive layer 104 as a gate structure, and the original second conductive layer 31 of the array region 1 needs to be removed in a subsequent step. In some embodiments, an interlayer dielectric layer may be formed on the surface of the substrate 101 of the array region 1 before the step of forming the original second conductive layer 31 on the surface of the substrate 101 of the array region 1. In some embodiments, the material of the interlayer dielectric layer may be silicon nitride.

[0095] In some embodiments, a deposition process can be used to form the original second conductive layer 31. The material of the original second conductive layer 31 can be a semiconductor material, such as any one of polycrystalline silicon, amorphous silicon, or microcrystalline silicon.

[0096] In some embodiments, the original second conductive layer 31 may also undergo a first doping process to form first doped ions in the original second conductive layer 31. The first doped ions have the same doped ion type as the first channel region, so that the doped ion type of the second conductive layer 104 formed is the same as that of the second channel region. This enables the second conductive layer 104 to improve the gate depletion effect. In some embodiments, the first doping process includes an ion implantation process.

[0097] refer to Figure 3 A primary second dielectric layer 32 is formed on the surface of the primary second conductive layer 31. In some embodiments, the material of the primary second dielectric layer 32 includes silicon-doped metal nitride. The primary second dielectric layer 32 is formed simultaneously on the surface of the primary second conductive layer 31 in the array region 1 and on the surface of the primary second conductive layer 31 in the peripheral region 2. In some embodiments, the primary second dielectric layer 32 can be formed using an atomic layer deposition method.

[0098] refer to Figure 5 After the original second dielectric layer 32 is formed, the original second dielectric layer 32 and the original second conductive layer 31 of the array region 1 are removed.

[0099] refer to Figure 4 To prevent damage to the original second dielectric layer 32 and the original second conductive layer 31 of array region 1 from the original second dielectric layer 32 of peripheral region 2, a first protective layer 17 and a second protective layer 18 can be formed on the surface of the original second dielectric layer 32 of peripheral region 2, stacked sequentially away from the surface of substrate 101. The material of the first protective layer 17 can be silicon oxide, and the material of the second protective layer 18 can be photoresist. Silicon oxide has a relatively high hardness and can provide good protection for the initial dielectric layer 142 of peripheral region 2.

[0100] In some embodiments, the first protective layer 17 formed is also located on the surface of the original second dielectric layer 32 of the array region 1.

[0101] In some embodiments, the original second dielectric layer 32 and the original second conductive layer 31 of the array region 1 can be etched using a dry etching process.

[0102] refer to Figure 5 Remove the original second conductive layer 31 and the original second dielectric layer 32 located in array region 1. The remaining original second conductive layer 31 forms the initial second conductive layer 1011, and the remaining original second dielectric layer 32 forms the initial second dielectric layer 1012.

[0103] After removing the original second conductive layer 31 and the original second dielectric layer 32 located in array region 1, the second protective layer located in peripheral region 2 is removed.

[0104] refer to Figures 6 to 7 In some embodiments, the method for fabricating the semiconductor structure further includes: after forming an initial second conductive layer 1011 and an initial second dielectric layer 1012, forming a bit line contact structure 105 in the substrate 101 of the array region 1.

[0105] In some embodiments, a second active region 11 is formed in the substrate 101 of the array region 1. The second active region 11 includes a second channel region and second source / drain regions located on both sides of the second channel region. The bit line contact structure 105 is electrically connected to one of the second source / drain regions. The original second conductive layer 31 is also formed on the surface of the substrate 101 of the array region 1. The process for forming the bit line contact structure 105 includes:

[0106] After forming the original second conductive layer 31, the interlayer dielectric layer of a portion of the array region 1 is etched to expose the surface of the substrate 101. A portion of the substrate 101 is then etched along its surface to form bit line contact holes, exposing the second source / drain regions at the bottom of the bit line contact holes. After forming the bit line contact holes, a bit line contact structure 105 is formed, filling the bit line contact holes.

[0107] In some embodiments, the method of forming a bit line contact hole includes:

[0108] refer to Figure 6 The interlayer dielectric layer of array region 1 is patterned. In some embodiments, the SAQP process can be used to pattern the interlayer dielectric layer of array region 1. The method may include:

[0109] A silicon oxide layer 22, a first mask layer 34, and a first photoresist layer 12 are sequentially formed on the surface of the interlayer dielectric layer in array region 1. In some embodiments, during the step of forming the first mask layer 34 and the first photoresist layer 12 on the surface of the interlayer dielectric layer in array region 1, the first mask layer 34 and the first photoresist layer 12 may also be formed on the surface of the first protective layer 17 in peripheral region 2. Thus, the first mask layer 34 and the first photoresist layer 12 located in peripheral region 2 can protect peripheral region 2.

[0110] In some embodiments, the first mask layer 34 may include a first hard mask layer 35, a first etch barrier layer 36, a sacrificial layer 37, a second hard mask layer 38, and a second etch barrier layer 39, stacked sequentially in a direction away from the substrate 101. In a specific example, the material of the first hard mask layer 35 may be an APF (Advanced Patterning Film) mask, the material of the first etch barrier layer 36 may be silicon oxynitride, the material of the sacrificial layer 37 may be silicon oxide, the material of the second hard mask layer 38 may be a spin-coated hard mask, and the material of the second etch barrier layer 39 may be silicon oxynitride.

[0111] A patterning process is performed on the first photoresist layer 12 of the array region 1. The pattern of the first photoresist layer 12 of the array region 1 is used to define the opening shape of the bit line contact hole. Based on the first photoresist layer 12, the first mask layer 34 is etched to pattern the original second conductive layer 31 of the array region 1. The patterned interlayer dielectric layer is etched until a portion of the top surface of the isolation structure 20 is exposed. The isolation structure 20 and the second active region 11 of a certain thickness are then etched to form the bit line contact hole.

[0112] refer to Figure 7 A bit line contact structure 105 is formed filling the bit line contact hole. In some embodiments, the method of forming the bit line contact structure 105 may include: forming the bit line contact structure 105 filling the bit line contact hole using a deposition process. In some embodiments, the bit line contact structure 105 may be formed by atomic layer deposition, and the material of the bit line contact structure 105 may be polycrystalline silicon.

[0113] In some embodiments, the bit line contact structure 105 has a fourth doped ion, the fourth doped ion having the same conductivity type as the doped ion in the second channel region; the method of forming the bit line contact structure 105 includes:

[0114] A bit line contact structure 105 is formed by a deposition process, and in the step of depositing the bit line contact structure 105, an in-situ doping process is performed on the bit line contact structure 105 to form a fourth dopant ion in the bit line contact structure 105.

[0115] After forming the bit line contact structure 105, the first mask layer 34 and the first photoresist layer 12 located in the peripheral region 2 are removed.

[0116] refer to Figures 8 to 10 After forming the bit line contact structure 105, an initial first dielectric layer 1022 is formed. In some embodiments, the method for forming the initial first dielectric layer 1022 includes:

[0117] refer to Figure 8 The original first dielectric layer 41 is formed on the substrate 101 of the array region 1 and on the surface of the initial second dielectric layer 1012. That is, there is no need to form a mask on the surface of the initial second dielectric layer 1012 to prevent the original first dielectric layer 41 from being formed on the surface of the initial second dielectric layer 1012. Subsequently, it is only necessary to remove the original first dielectric layer 41 on the surface of the initial second dielectric layer 1012, which greatly saves process steps.

[0118] In some embodiments, the original first dielectric layer 41 may be formed using a deposition process. In some embodiments, the material of the original first dielectric layer 41 may include titanium nitride. Titanium nitride has a low dielectric constant, which can reduce the parasitic capacitance of the array region 1.

[0119] refer to Figure 9 A protective layer 19 is formed on the surface of the original first dielectric layer 41 located in array region 1, exposing the original first dielectric layer 41 located on the surface of the initial second dielectric layer 1012. The protective layer 19 is used to protect the original first dielectric layer 41 of array region 1 from process damage during the step of removing the original first dielectric layer 41 of peripheral region 2. In some embodiments, the material of the protective layer 19 may be photoresist.

[0120] refer to Figure 10 The original first dielectric layer 41 located on the surface of the initial second dielectric layer 1012 is removed by a wet etching process, and the remaining original first dielectric layer 41 located in the array region 1 forms the initial first dielectric layer 1022.

[0121] In some embodiments, the etching liquid used in the wet etching process has a large selectivity for the initial second dielectric layer 1012 and the original first dielectric layer 41, thereby avoiding the problem of over-etching of the initial second dielectric layer 1012 by the etching liquid and ensuring that the initial second dielectric layer 1012 has a good morphology.

[0122] In some embodiments, the etching liquid can be an alkaline liquid. Specifically, a mixture of ammonium hydroxide solution, hydrogen peroxide solution, and aqueous solution can be used to etch the original first dielectric layer 41. In some embodiments, the ratio of ammonium hydroxide solution, hydrogen peroxide solution, and aqueous solution can be 1:1:5 to 1:2:7.

[0123] After the step of removing the original first dielectric layer 41 of the peripheral region 2, the protective layer 19 of the array region 1 is removed.

[0124] refer to Figures 11 to 16 ,as well as Figure 1 After the initial first dielectric layer 1022 is formed, the first conductive layer 103 is formed.

[0125] In some embodiments, the method of forming the first conductive layer 103 includes:

[0126] refer to Figure 11 An initial first conductive layer 42 is formed on the surface of the initial first dielectric layer 1022 of the array region 1 and the initial second dielectric layer 1012 of the peripheral region 2.

[0127] In some embodiments, an initial first conductive layer 42 is formed on the surface of the initial first dielectric layer 1022 of the array region 1 and the surface of the initial second dielectric layer 1012 of the peripheral region 2. The initial first conductive layer 42 of the array region 1 serves as the first conductive layer 103 of the bit line structure, the initial first conductive layer 42 of the peripheral region 2 serves as the third conductive layer 106 of the gate structure, and the second conductive layer 104 serves as the conductive structure of the gate structure, thus playing a role in signal transmission.

[0128] In some embodiments, an initial first conductive layer 42 may be formed using a deposition process. In some embodiments, the material of the initial first conductive layer 42 may be titanium.

[0129] It is easy to see that the first conductive layer 103 and the third conductive layer 106 are both formed from the initial first conductive layer 42 formed in the same process step, which can greatly simplify the process steps.

[0130] In some embodiments, the method for fabricating the semiconductor structure further includes: forming an initial capping layer on the surface of the initial first conductive layer 42, wherein the initial capping layer of the array region 1 is used to form a bit line capping layer 111, and the initial capping layer of the peripheral region 2 is used to form a gate capping layer 112. In some embodiments, a deposition process, such as atomic layer deposition, may be used to form the initial capping layer, and the material of the initial capping layer may be silicon nitride.

[0131] After the initial capping layer is formed, the array region 1 and the peripheral region 2 are patterned to form the bit line structure and the gate structure, respectively.

[0132] For details, please refer to the following: Figures 14 to 16 ,as well as Figure 1 The initial first conductive layer 42 located in the array region 1 is subjected to a first patterning process to form a first conductive layer 103, and the initial first conductive layer 42 located in the peripheral region 2 is subjected to a second patterning process to form a third conductive layer 106. The third conductive layer 106 is used to form a gate structure.

[0133] In some embodiments, the second patterning process may be performed prior to the first patterning process.

[0134] refer to Figures 11 to 12 The first patterning process includes:

[0135] A second mask layer 50 and a second photoresist layer 13 are sequentially formed on the surface of the initial capping layer 43. The formed second mask layer 50 and second photoresist layer 13 are located on the surface of the initial capping layer of the array region 1 and the initial capping layer of the peripheral region 2, and are used to protect the array region 1.

[0136] In some embodiments, the material of the second mask layer 50 may include a third hard mask layer 51 and a third etch barrier layer 52 stacked sequentially in a direction away from the substrate 101. The material of the third hard mask layer 51 may be a spin-coated hard mask layer, and the material of the third etch barrier layer 52 may be silicon oxynitride.

[0137] The second photoresist layer 13 of the peripheral region 2 is patterned, and the pattern of the second photoresist layer 13 is used to define the shape of the gate structure.

[0138] refer to Figure 12 Based on the pattern of the second photoresist layer 13, the second mask layer 50 is etched to expose the surface of the initial capping layer 43. The initial capping layer 43, the initial first conductive layer 42, the initial second dielectric layer 1012 and the initial second conductive layer 1011 are etched to form the second conductive layer 104, the second dielectric layer 105, the third conductive layer 106 and the gate capping layer 112 stacked sequentially in the direction away from the substrate 101. The second conductive layer 104, the second dielectric layer 105, the third conductive layer 106 and the gate capping layer 112 form the gate structure.

[0139] refer to Figure 13 In some embodiments, after forming the gate cap layer 112, the method further includes forming a sidewall structure 120 on the sidewall of the gate structure. In some embodiments, the method of forming the sidewall structure 120 may include sequentially forming a first sidewall layer 121, a second sidewall layer 122, and a third sidewall layer 123 on the sidewall of the gate structure using a deposition process, such as atomic layer deposition. In some embodiments, the first sidewall layer 121 and the third sidewall layer 123 may both be made of silicon nitride, and the second sidewall layer 122 may be made of silicon oxide.

[0140] In some embodiments, after forming the sidewall structure 120, the method further includes forming a filler layer 114 that covers the surface of the sidewall structure 120 and is flush with the top surface of the sidewall structure 120. The filler layer 114 can be used to support other structures formed on the top surface of the sidewall structure 120 in subsequent steps, for example, to provide support for a subsequently formed third mask layer.

[0141] In some embodiments, after the step of forming the gate structure, the second mask layer 50 and the second photoresist layer 13 located in the array region 1 are removed.

[0142] refer to Figure 14 , Figure 15 , Figure 16 as well as Figure 1 A first patterning process is performed on the bit line contact structure 105, the initial first dielectric layer 1022, the initial first conductive layer 42 and the initial capping layer located in the array region to form the bit line structure.

[0143] In some embodiments, the first patterning process includes:

[0144] refer to Figure 14 A sub-capping layer 44 is formed on the surface of the initial capping layer 43 in array region 1. The material of the sub-capping layer 44 is the same as that of the initial capping layer 43. The sub-capping layer 44 in array region 1 is used together with the initial capping layer 43 to form the bit line capping layer 111, so that the thickness of the bit line capping layer 111 is greater than the thickness of the gate capping layer 112. That is to say, the thickness of different film layers can be adjusted according to the different requirements of the bit line structure and the gate to achieve the optimal performance of the bit line structure and the gate structure.

[0145] In some embodiments, the formed sub-cover layer 44 is also located on the filling layer 114 of the peripheral region 2 and the top surface of the sidewall structure 120.

[0146] Continue to refer to Figure 14 After the sub-capping layer 44 is formed, a third mask layer 60 and a third photoresist layer 14 are formed on the surface of the sub-capping layer 44. In some embodiments, the third mask layer 60 and the third photoresist layer 14 are formed on the surface of the sub-capping layer 44 in the peripheral region 2 and on the surface of the sub-capping layer 44 in the array region 1.

[0147] In some embodiments, the third mask layer 60 includes a fourth hard mask layer 61, a fourth etch barrier layer 62, a fifth hard mask layer 63, and a fifth etch barrier layer 64, which are sequentially stacked along a direction away from the substrate 101. In some embodiments, the material of the fourth hard mask layer 61 may include APF, the material of the fourth etch barrier layer 62 may include silicon oxynitride, the material of the fifth hard mask layer 63 may include a spin-coated hard mask, and the material of the fifth etch barrier layer 64 may include silicon oxynitride.

[0148] refer to Figure 14 The third photoresist layer 14 of the array region 1 is patterned.

[0149] refer to Figure 15 The fifth etch barrier layer 64 and the fifth hard mask layer 63, which are not covered by the third photoresist layer 14, are etched to form the first sub-hard mask layer 132 by the fifth etch barrier layer 64 and the second sub-hard mask layer 131 by the fifth hard mask layer 63, and the third photoresist layer 14 is removed.

[0150] In some embodiments, in the step of removing the third photoresist layer 14 of the array region 1, the third photoresist layer 14 of the peripheral region 2 is removed.

[0151] After removing the third photoresist layer 14, a fourth mask layer 15 is formed, which covers the side surfaces of the first sub-hard mask layer 132, the second sub-hard mask layer 131, and the top surface of the second sub-hard mask layer 131. In some embodiments, the material of the fourth mask layer 15 may be silicon oxide. In some embodiments, the fourth mask layer 15 may be formed using a deposition process, such as atomic layer deposition.

[0152] In some embodiments, the fourth mask layer 15 is also formed on the top surface of the fifth etch barrier layer 64 in the peripheral region 2.

[0153] refer to Figure 16 After the fourth mask layer 15 is formed, the fourth mask layer 15 located on the top surface of the second sub-hard mask layer 131 is removed, and the fourth mask layer 15 located on the side of the first sub-hard mask layer 132 and the side of the second sub-hard mask layer 131 is retained as the third sub-hard mask layer 16, and the first sub-hard mask layer 132 and the second sub-hard mask layer 131 are removed.

[0154] The pattern of the third sub-hard mask layer 16 is used to define the shape of the bitline structure.

[0155] refer to Figure 1 Based on the pattern of the third sub-hard mask layer 16, the fourth etch barrier layer 62 and the fourth hard mask layer 61 of the array region 1 are etched until the top surface of the sub-capping layer 44 is exposed. The sub-capping layer 44, the initial capping layer, the initial first conductive layer 42 and the initial first dielectric layer 1022 are etched. The remaining sub-capping layer 44 and the initial capping layer form the bit line capping layer 111. The remaining initial first conductive layer 42 of the array region 1 forms the first conductive layer 103. The remaining initial first dielectric layer 1022 of the array region 1 forms the first dielectric layer 102.

[0156] In some embodiments, during the etching step of the initial first dielectric layer 1022, the top surface of the bit line contact structure 105 is exposed, and the bit line contact structure 105 is etched so that the bit line contact structure 105 has the same shape as the formed first dielectric layer 102. That is, the orthographic projection of the formed bit line contact structure 105 on the substrate 101 coincides with the orthographic projection of the first dielectric layer 102 on the substrate 101.

[0157] After forming the bit line structure, the remaining third mask layer 60 is removed, and a portion of the thickness of the sub-cap layer 44 in the peripheral region 2 is removed.

[0158] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate, the substrate including an array region and a peripheral region; Bit line structure, located on the substrate of the array region, the bit line structure includes a first dielectric layer and a first conductive layer stacked sequentially along a direction away from the substrate surface; A gate structure is located on the substrate of the peripheral region. The gate structure includes a second conductive layer and a second dielectric layer stacked sequentially along a direction away from the substrate surface. The dielectric constant of the second dielectric layer is greater than the dielectric constant of the first dielectric layer. The material of the first dielectric layer includes titanium nitride, and the material of the second dielectric layer includes silicon-doped metal nitride; The thickness of the first dielectric layer is not less than the thickness of the second dielectric layer.

2. The semiconductor structure according to claim 1, characterized in that, The gate structure further includes a third conductive layer located on the side of the second dielectric layer away from the substrate surface.

3. The semiconductor structure according to claim 2, characterized in that, The material of the first conductive layer is the same as that of the third conductive layer, and the thickness of the first conductive layer is equal to the thickness of the third conductive layer.

4. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate having an array region and a peripheral region; A bit line structure is formed on the substrate of the array region, the bit line structure comprising a first dielectric layer and a first conductive layer stacked sequentially along a direction away from the surface of the substrate; A gate structure is formed on the substrate of the peripheral region. The gate structure includes a second conductive layer and a second dielectric layer stacked sequentially along a direction away from the substrate surface. The dielectric constant of the second dielectric layer is greater than the dielectric constant of the first dielectric layer. The substrate of the peripheral region includes a first active region, the first active region including a first channel region; the substrate of the array region includes a second active region, the second active region including a second channel region and second source / drain regions located on both sides of the second channel region; the method for forming the bit line structure and the gate structure includes: An initial first dielectric layer and an initial first conductive layer are formed on the substrate of the array region, stacked sequentially in a direction away from the substrate surface. A first patterning process is performed on the initial first dielectric layer and the initial first conductive layer to form the first dielectric layer and the first conductive layer that are directly opposite the second channel region. An initial second conductive layer and an initial second dielectric layer are formed on the substrate of the peripheral region in a direction away from the substrate surface. A second patterning process is performed on the initial second conductive layer and the initial second dielectric layer to form a second conductive layer and a second dielectric layer that are directly opposite to the first channel region. The step of forming the initial second dielectric layer, prior to the step of forming the initial first dielectric layer, includes: An original second conductive layer is formed on the substrate surface of the peripheral region and the array region; An original second dielectric layer is formed on the surface of the original second conductive layer; The original second conductive layer and the original second dielectric layer located in the array region are removed, and the remaining original second conductive layer forms the initial second conductive layer, and the remaining original second dielectric layer forms the initial second dielectric layer.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, The method for forming the initial first dielectric layer includes: An original first dielectric layer is formed on the substrate of the array region and on the surface of the initial second dielectric layer; A protective layer is formed on the surface of the original first dielectric layer located in the array region, the protective layer exposing the original first dielectric layer located on the surface of the initial second dielectric layer; The original first dielectric layer located on the surface of the initial second dielectric layer is removed by a wet etching process, and the remaining original first dielectric layer located in the array region forms the initial first dielectric layer.

6. The method for preparing a semiconductor structure according to claim 4, characterized in that, The method for forming the first conductive layer includes: An initial first conductive layer is formed on the surface of the initial first dielectric layer in the array region and the initial second dielectric layer in the peripheral region; The initial first conductive layer located in the array region is subjected to the first patterning process to form the first conductive layer, and the initial first conductive layer located in the peripheral region is subjected to the second patterning process to form the third conductive layer, the third conductive layer being used to form the gate structure.

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