A method of manufacturing a semiconductor device

Abstract

A method for manufacturing a semiconductor device includes forming a magnetic tunneling junction (MTJ) on a substrate, forming a spin orbit torque (SOT) layer on the MTJ, forming an intermetal dielectric layer around the MTJ and the SOT layer, forming a first hard mask on the intermetal dielectric layer, forming a semiconductor layer on the first hard mask, and patterning the first hard mask.

Description

Technical Field

[0001] This invention relates to a method for manufacturing semiconductor devices, and more particularly to a method for manufacturing magnetoresistive random access memory (MRAM) devices. Background Technology

[0002] Magnetoresistance (MR) is the effect of a material's resistance changing with the application of a magnetic field. Its physical quantity is defined as the rate of change of resistance, calculated by dividing the resistance difference (with and without a magnetic field) by the original resistance. Currently, the magnetoresistance effect has been successfully applied in hard drive manufacturing and has significant commercial value. Furthermore, utilizing the characteristic that giant magnetoresistance materials have different resistance values ​​under different magnetization states, magnetic random access memory (MRAM) can also be fabricated, which has the advantage of retaining stored data even when no power is applied.

[0003] The aforementioned magnetoresistive effect is also applied in the field of magnetic field sensing, such as in the electronic compass components of mobile phones that integrate with the Global Positioning System (GPS) to provide users with information such as their location. Currently, various magnetic field sensing technologies are available on the market, such as anisotropic magnetoresistive (AMR) sensing elements, giant magnetoresistive (GMR) sensing elements, and magnetic tunneling junction (MTJ) sensing elements. However, these existing technologies typically have drawbacks, including larger chip area, higher manufacturing costs, higher power consumption, insufficient sensitivity, and susceptibility to temperature changes, necessitating further improvements. Summary of the Invention

[0004] One embodiment of the present invention discloses a method for fabricating a semiconductor device, which mainly involves first forming a magnetic tunneling junction (MTJ) on a substrate, then forming a spinorbit torque (SOT) layer on the MTJ, forming an intermetallic dielectric layer surrounding the MTJ and the SOT layer, forming a first hard mask on the intermetallic dielectric layer, forming a semiconductor layer on the first hard mask, and then patterning the first hard mask. Attached Figure Description

[0005] Figures 1 to 11This is a schematic diagram illustrating a method for fabricating an MRAM cell according to an embodiment of the present invention.

[0006] Explanation of main component symbols

[0007] 12: Base

[0008] 14: MRAM region

[0009] 16: Logical Area

[0010] 18: Interlayer dielectric layer

[0011] 20: Metal interconnect structure

[0012] 22: Metal interconnect structure

[0013] 24: Intermetallic dielectric layer

[0014] 26: Metal interconnects

[0015] 28: Stop Layer

[0016] 30: Intermetallic dielectric layer

[0017] 32: Metal interconnects

[0018] 34: Barrier Layer

[0019] 36: Metal layer

[0020] 38: Lower electrode

[0021] 40: MTJ stacked structure

[0022] 42: Upper electrode

[0023] 44: SOT layer

[0024] 48:MTJ

[0025] 50: Covering layer

[0026] 52: Intermetallic dielectric layer

[0027] 56: Intermetallic dielectric layer

[0028] 58: Metal interconnects

[0029] 60: Stop Layer

[0030] 62: Intermetallic dielectric layer

[0031] 64: Metal interconnects

[0032] 66: Interstitial wall

[0033] 68: Hard Mask

[0034] 70: Hard Mask

[0035] 72: Semiconductor layer

[0036] 74: Hard Mask Detailed Implementation

[0037] Please refer to Figures 1 to 11 , Figures 1 to 11 This is a schematic diagram illustrating a method for fabricating an MRAM cell according to an embodiment of the present invention. Figure 1 As shown, a substrate 12 is first provided, for example, a substrate 12 made of semiconductor material, wherein the semiconductor material may be selected from the group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc., and an MRAM region 14 and a logic region 16 are preferably defined on the substrate 12.

[0038] The substrate 12 may contain active (active) devices such as metal-oxide-semiconductor (MOS) transistors, passive (passive) devices, conductive layers, and dielectric layers such as interlayer dielectric (ILD) 18 covering it. More specifically, the substrate 12 may contain planar or non-planar (such as fin structure transistors) MOS transistor devices, wherein the MOS transistors may include gate structures (such as metal gates) and source / drain regions, spacers, epitaxial layers, contact hole etch stop layers, and other transistor elements. The interlayer dielectric layer 18 may be disposed on the substrate 12 and cover the MOS transistors, and the interlayer dielectric layer 18 may have multiple contact plugs electrically connecting the gate and / or source / drain regions of the MOS transistors. Since the fabrication processes of planar or non-planar transistors and interlayer dielectric layers are well known in the art, they will not be described in detail here.

[0039] Then, metal interconnect structures 20 and 22 are sequentially formed on the interlayer dielectric layer 18 to electrically connect the aforementioned contact plug. The metal interconnect structure 20 includes an intermetal dielectric layer 24 and a metal interconnect 26 embedded in the intermetal dielectric layer 24. The metal interconnect structure 22 includes a stop layer 28, an intermetal dielectric layer 30 and a metal interconnect 32 embedded in the stop layer 28 and the intermetal dielectric layer 30.

[0040] In this embodiment, each metal interconnect 26 in the metal interconnect structure 20 preferably includes a trench conductor, and the metal interconnect 32 in the MRAM region 14 of the metal interconnect structure 22 includes a via conductor. Furthermore, each metal interconnect 26 and 32 in the metal interconnect structures 20 and 22 can be embedded in the inter-metal dielectric layers 24 and 30 and / or the stop layer 28 and electrically connected to each other using a single damascene fabrication process or a double damascene fabrication process. For example, each metal interconnect 26 and 32 may further include a barrier layer 34 and a metal layer 36, wherein the barrier layer 34 may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and the metal layer 36 may be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since single-damascene or dual-damascene fabrication processes are well-known in the art, they will not be described in detail here. Furthermore, in this example, the metal layer 36 in the metal interconnect 26 preferably contains copper, the metal layer 36 in the metal interconnect 32 preferably contains tungsten, the intermetallic dielectric layers 24 and 30 preferably contain silicon oxide such as tetraethylorthosilicate (TEOS), and the stop layer 28 contains a nitrogen-doped carbide (NDC), silicon nitride, or silicon carbon nitride (SiCN), but is not limited thereto.

[0041] Next, a lower electrode 38, an MTJ stack structure 40, an upper electrode 42, a spinorbit torque (SOT) layer 44, and a hard mask 68 are formed on the metal interconnect structure 22. In this embodiment, the MTJ stack structure 40 can be formed by first sequentially forming a pinned layer, a barrier layer, and a free layer on the lower electrode 38. In this embodiment, the lower electrode 38 and the upper electrode 42 preferably contain conductive materials, such as, but not limited to, tantalum (Ta), tantalum nitride (TaN), platinum (Pt), copper (Cu), gold (Au), and aluminum (Al). The pinned layer may contain ferromagnetic materials such as, but not limited to, cobalt-iron-boron (CoFeB), cobalt-iron (CoFe), iron (Fe), and cobalt (Co). In addition, the fixing layer can also be made of antiferromagnetic (AFM) materials, such as iron-manganese (FeMn), platinum-manganese (PtMn), iridium-manganese (IrMn), and nickel oxide (NiO), to fix or restrict the magnetic moment direction of adjacent layers. The barrier layer can be made of insulating materials containing oxides, such as aluminum oxide (AlO). x The free layer can be made of ferromagnetic materials, such as iron, cobalt, nickel, or their alloys, such as cobalt-iron-boron (CoFeB), but is not limited to these. The magnetization direction of the free layer can be "freely" changed by an external magnetic field. In this embodiment, the SOT layer 44 is preferably used as a channel for a spin orbit torque (SOT) MRAM, therefore its material can include tantalum (Ta), tungsten (W), platinum (Pt), hafnium (Hf), bismuth selenide (Bi). x Se 1-x Alternatively, the hard mask 68 may contain conductive or metallic materials such as ruthenium (Ru), but is not limited thereto.

[0042] Subsequently, as Figure 2As shown, a patterned hard mask (not shown) is used as the mask to perform one or more etching processes to remove a portion of the hard mask 68, a portion of the SOT layer 44, a portion of the upper electrode 42, a portion of the MTJ stack structure 40, a portion of the lower electrode 38, and a portion of the intermetallic dielectric layer 30 to form at least one MTJ 48 in the MRAM region 14, and then the patterned mask is removed. It is worth noting that the etching process performed on the patterned upper electrode 42, MTJ stack structure 40, lower electrode 38, and intermetallic dielectric layer 30 in this embodiment may include reactive ion etching or ion beam etching (IBE). Due to the characteristics of the ion beam etching process, the remaining upper surface of the intermetallic dielectric layer 30 is preferably slightly lower than the upper surface of the metal interconnect 32, and the upper surface of the intermetallic dielectric layer 30 preferably presents an arc or curved surface. It should also be noted that when removing part of the intermetallic dielectric layer 30 using the ion beam etching process in this embodiment, part of the metal interconnects 32 can be removed at the same time, so that the metal interconnects 32 form an inclined sidewall near the junction of MTJ 48.

[0043] A masking layer 50 is then formed on the MTJ 48, covering the surface of the intermetallic dielectric layer 30 of the MRAM region 14 and the logic region 16. In this embodiment, the masking layer 50 preferably comprises silicon nitride, but other dielectric materials such as, but not limited to, silicon oxide, silicon oxynitride, or silicon carbide may be selected according to the fabrication process requirements.

[0044] Then as Figure 3 As shown, with or without any patterned mask, such as a patterned photoresist, an etching process is performed to remove part of the masking layer 50 to form a spacer wall 66 surrounding or disposed on the MTJ 48, the SOT layer 44, and the hard mask sidewalls, wherein the formed spacer wall 66 preferably presents an approximately L-shape at a cross-sectional angle. Then, a deposition process, such as atomic layer deposition (ALD), is performed to form an intermetallic dielectric layer 52 on the hard mask 68, the spacer wall 66, and the intermetallic dielectric layer 30. Then, a planarization process, such as chemical mechanical polishing (CMP) or an etch-back process, is performed to remove part of the intermetallic dielectric layer 52, so that the top surface of the remaining intermetallic dielectric layer 52 is approximately flush with the spacer wall 66 and the top surface of the hard mask 68. Subsequently, another hard mask 70 is formed on the intermetallic dielectric layer 52 and covers the hard mask 68 and the spacer wall 66, wherein the hard mask 70 preferably contains a metal nitride such as titanium nitride, but is not limited thereto.

[0045] like Figure 4As shown, a semiconductor layer 72 and another hard mask 74 are then sequentially formed on the hard mask 70. In this embodiment, the semiconductor layer 72 preferably contains silicon, such as polysilicon or amorphous silicon, while the hard mask 74 contains a dielectric layer such as silicon nitride, but is not limited thereto.

[0046] like Figure 5 As shown, a patterned mask (not shown) can be formed first, for example, a patterned photoresist can be applied to the hard mask 74. Then, an etching process is performed using the patterned mask to remove part of the hard mask 74 and expose the top surface of the semiconductor layer 72. Finally, the patterned mask is removed.

[0047] Then as Figure 6 As shown, a patterned semiconductor layer 72 is patterned and placed on the surface of the hard mask 70 using a dry etching process with the patterned hard mask 74 as the mask.

[0048] Then as Figure 7 As shown, a wet etching process is then performed using a hard mask 74 as a mask to remove part of the hard mask 70, exposing the top surface of the intermetallic dielectric layer 52, and aligning the sidewalls of the hard mask 74 with the sidewalls of the semiconductor layer 72 and the hard mask 70. The wet etching process performed in this stage can use an etchant composed of a standard cleaning solution SC2 to remove part of the hard mask 70, but is not limited to this.

[0049] Subsequently, as Figure 8 As shown, a wet etching process is performed to remove the top hard mask 74 and expose the top surface of the semiconductor layer 72. In this stage of the wet etching process, phosphoric acid (H3PO4) is preferably used to completely remove the hard mask 72 made of silicon nitride and expose the surface of the semiconductor layer 72.

[0050] like Figure 9 As shown, the next step is to perform another wet etching process to remove the semiconductor layer 72. In this stage, the wet etching process preferably uses tetramethyl ammonium hydroxide (TMAH) to completely remove the semiconductor layer 72 made of polysilicon and expose the top surface of the hard mask 70.

[0051] like Figure 10As shown, another intermetallic dielectric layer 56 is then formed on the hard mask 70 and the intermetallic dielectric layers 52 on both sides. The intermetallic dielectric layer 56 is preferably conformally disposed on the hard mask 70, and the intermetallic dielectric layers 52 and 56 may contain an ultra-low dielectric constant dielectric layer, such as a porous dielectric material, such as, but not limited to, silicon carbide (SiOC) or silicon carbide hydrogen (SiOCH). Next, a planarization process is performed, for example, using a chemical mechanical polishing (CMP) process or an etch-back process to remove part of the intermetallic dielectric layer 56, but the top surface of the remaining intermetallic dielectric layer 56 is still higher than the top surface of the hard mask 70.

[0052] A pattern transfer fabrication process is then performed, for example, by using a patterned mask (not shown) to remove a portion of the intermetallic dielectric layer 56, a portion of the intermetallic dielectric layer 52, a portion of the intermetallic dielectric layer 30, and a portion of the stop layer 28 between MRAM region 14 and logic region 16 to form contact holes (not shown) and expose the underlying metal interconnects 26. The contact holes are then filled with the desired metal material, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials or combinations thereof, such as tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. Next, a planarization fabrication process is performed, for example, by chemical mechanical polishing to remove a portion of the metal material to form contact plugs or metal interconnects 58 electrically connecting the metal interconnects 26 within the contact holes.

[0053] Then as Figure 11 As shown, a stop layer 60 is first formed in the MRAM region 14 and the logic region 16, covering the intermetallic dielectric layer 56 and the metal interconnects 58. An intermetallic dielectric layer 62 is then formed on the stop layer 60. One or more photolithography and etching processes are performed to remove portions of the intermetallic dielectric layer 62, the stop layer 60, and the intermetallic dielectric layer 56 in the MRAM region 14 and the logic region 16, forming contact holes (not shown). Next, conductive material is filled into each contact hole, and a planarization process such as CMP is used to form metal interconnects 64 in the MRAM region 14 and the logic region 16, electrically connecting to the underlying MTJ48 and the metal interconnects 58. Preferably, the metal interconnects 64 in the MRAM region 14 directly contact the underlying hard mask 70, while the metal interconnects 64 in the logic region 16 contact the underlying metal interconnects 58.

[0054] In this embodiment, the stop layer 60 and the stop layer 28 may contain the same or different materials, both of which can be selected from the group consisting of nitrogen-doped carbide (NDC), silicon nitride, and silicon carbon nitride (SiCN). As with the aforementioned metal interconnects, the metal interconnects 64 disposed within the intermetallic dielectric layer 62 can be embedded within the intermetallic dielectric layer 62 using a single damascene fabrication process or a double damascene fabrication process. For example, the metal interconnects 64 may further include a barrier layer and a metal layer, wherein the barrier layer can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), while the metal layer can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since single-damascene or dual-damascene fabrication processes are well-known in the art, they will not be described in detail here. This completes the fabrication of a semiconductor element according to an embodiment of the present invention.

[0055] Generally, before patterning the aforementioned titanium nitride hard mask 70, a composite hard mask composed of silicon nitride and silicon oxide is usually formed sequentially on the hard mask 70. Then, a dry etching process is performed to pattern the hard mask 70, and finally, diluted hydrofluoric acid (dHF) is used to remove the composite hard mask composed of silicon nitride and silicon oxide. However, the currently used diluted hydrofluoric acid easily causes damage to the intermetallic dielectric layer and affects the device surface. Therefore, this invention primarily forms a hard mask 72 composed of a semiconductor material such as polysilicon and a hard mask 74 composed of silicon nitride before patterning the hard mask 70, and then uses these two hard masks to perform a series of etching processes. By using hard masks composed of these two materials to pattern the titanium nitride hard mask 70, this invention can omit the etching process based on diluted hydrofluoric acid and instead use etching formulations composed of SC2 and phosphoric acid to pattern the hard mask 70. This can improve the situation where the surface of the intermetallic dielectric layer is damaged by diluted hydrofluoric acid.

[0056] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Include: A magnetic tunneling junction (MTJ) stack structure is formed on the substrate; A spin orbit torque (SOT) layer is formed on the magnetic tunneling junction stack structure; A third hard mask is formed directly on the spin-orbit torque layer; The third hard mask, the spin-orbit torque layer, and the magnetic tunneling junction stack are patterned to form a magnetic tunneling junction, wherein the sidewalls of the third hard mask, the sidewalls of the spin-orbit torque layer, and the sidewalls of the magnetic tunneling junction are aligned. Form gap walls adjacent to both sides of the third hard mask, the spin-orbit torque layer, and the magnetic tunnel junction; An intermetallic dielectric layer is formed around the magnetic tunneling junction and the spin-orbit torque layer, wherein the top surface of the intermetallic dielectric layer and the top surface of the third hard mask are coplanar. A first hard mask is formed on the intermetallic dielectric layer and the magnetic tunnel junction, wherein the bottom surface of the first hard mask is flush with the top surface of the intermetallic dielectric layer, the top surface of the spacer wall and the top surface of the third hard mask. A semiconductor layer is formed on the top surface of the first hard mask and in direct contact with the top surface of the first hard mask. The semiconductor layer overlaps with the magnetic tunneling junction and the intermetallic dielectric layer, and the bottom surface of the semiconductor layer is higher than the top surface of the intermetallic dielectric layer, the top surface of the spacer wall, and the top surface of the third hard mask. Pattern the first hard mask.

2. The method of claim 1, further comprising: The intermetallic dielectric layer is formed around the gap wall; A second hard mask is formed on the semiconductor layer; Pattern the semiconductor layer; The first hard mask is patterned using the second hard mask; Remove the second hard mask; as well as Remove the semiconductor layer.

3. The method of claim 2, further comprising performing a dry etching process to pattern the semiconductor layer.

4. The method of claim 2, further comprising performing a wet etching process to remove the first hard mask.

5. The method of claim 2, further comprising performing a wet etching process to remove the second hard mask.

6. The method of claim 2, further comprising performing a wet etching process to remove the semiconductor layer.

7. The method of claim 2, wherein the second hard mask comprises a dielectric layer.

8. The method of claim 2, wherein the first hard mask comprises a metal nitride.

9. The method of claim 2, wherein the semiconductor layer comprises polycrystalline silicon.

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