Functional safety test method, device and equipment under chip transient fault
By sorting test vectors based on functional unit contribution and coverage under transient chip fault conditions and inputting them in stages, the problem of low efficiency in chip functional safety testing is solved, and more efficient and accurate functional safety testing is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN INST OF ADVANCED TECH
- Filing Date
- 2023-04-21
- Publication Date
- 2026-07-14
AI Technical Summary
Existing technologies have low efficiency in functional safety testing of chips under transient faults, making it difficult to improve efficiency effectively.
By acquiring the set of functional units that are hit in the transient fault simulation test of the chip and their corresponding test vector sets, sorting the test vector sets based on the contribution and coverage of the functional units, controlling the irradiation source to continuously irradiate the chip, and inputting the test vectors in sequence to detect the fault detection results of the functional units, the functional test results of the chip are finally determined.
It improves the efficiency of functional safety testing of chips under transient faults, can detect transient faults that have a significant impact on safety earlier, ensures that weak functional units are tested, reduces the number of test vectors, and improves test accuracy and efficiency.
Smart Images
Figure CN116719685B_ABST
Abstract
Description
Technical Field
[0001] This specification relates to the field of functional safety testing technology for chips, and in particular to a method, apparatus and equipment for functional safety testing of chips under transient faults. Background Technology
[0002] Electromagnetic interference or crosstalk can easily cause transient failures in chips. Functional safety testing of chips under transient failures is an important means of verifying the correctness of their functional safety design and manufacturing process. However, the testing efficiency of current functional safety testing of chips under transient failures urgently needs improvement. Summary of the Invention
[0003] The purpose of the embodiments in this specification is to provide a method, apparatus, and device for functional safety testing of chips under transient faults, so as to improve the testing efficiency of functional safety testing of chips under transient faults.
[0004] To achieve the above objectives, on the one hand, embodiments of this specification provide a functional safety testing method under transient chip faults, including:
[0005] Obtain the set of functional units that are hit in the transient fault simulation test of the chip and the set of test vectors corresponding to the hit;
[0006] The test vector set is sorted into a test vector sequence based on its contribution and coverage to the functional unit set;
[0007] The irradiation source is controlled to continuously irradiate the chip;
[0008] Each test vector in the test vector sequence is input into the chip sequentially, and the fault detection result of each functional unit is detected each time it is input.
[0009] Based on the fault detection results of each functional unit under each input, the functional test result of the chip under each input is determined.
[0010] In the functional safety testing method for chip transient faults in the embodiments of this specification, the step of sorting the test vector set into a test vector sequence based on the contribution and coverage of the functional unit set includes:
[0011] Determine the contribution of each test vector in the test vector set to the set of functional units;
[0012] Arrange the test vector set into an initial sequence according to their contribution.
[0013] The coverage of the functional unit set by the subsequence formed by the largest contributor and each of the remaining test vectors in the initial sequence is determined.
[0014] The coverage of the functional unit set is determined by the subsequence with the largest coverage and the subsequence formed by each of the remaining test vectors in the initial sequence.
[0015] The process is repeated until the length of the subsequence with the largest coverage obtained so far meets the preset condition.
[0016] Use the subsequence with the highest coverage obtained so far as the test vector sequence.
[0017] In the functional safety testing method for chip transient faults in the embodiments of this specification, the preset conditions include:
[0018] The subsequence with the highest coverage obtained so far achieves full coverage.
[0019] In the functional safety testing method for chip transient faults in the embodiments of this specification, determining the contribution of each test vector in the test vector set to the functional unit set includes:
[0020] According to the formula Calculate the contribution of each test vector in the test vector set to the functional unit set;
[0021] Among them, C i N represents the contribution of the i-th test vector in the test vector set to the set of functional units. ik M represents the probability that the i-th test vector hits the k-th functional unit in the set of functional units, where M is the size of the set of functional units.
[0022] In the functional safety testing method for chip transient faults in the embodiments of this specification, each test vector in the test vector sequence is input into the chip sequentially, and the fault detection result of each functional unit under each input is detected, including:
[0023] From the sequence of test vectors, select one unselected test vector as the target test vector;
[0024] The target test vector is input into the chip;
[0025] The fault detection results of each of the functional units are detected under the target test vector input;
[0026] Repeat the above steps when the conditions for continuing the test are met, until all test vectors in the test vector sequence have been selected.
[0027] In the functional safety testing method for chip transient faults in the embodiments of this specification, the functional test result of the chip under each input is determined based on the fault detection results of each functional unit under each input, including:
[0028] The number of functional units that have been detected as faulty in the set of functional units under the current input is accumulated;
[0029] Determine whether the accumulated value has reached the preset threshold;
[0030] When the accumulated value reaches the threshold, the accumulated value is output.
[0031] The functional safety testing method for chip transient faults in the embodiments of this specification, which determines the functional test result of the chip under each input based on the fault detection results of each functional unit under each input, further includes:
[0032] When the accumulated value does not reach the threshold, it is determined whether there are any unselected test vectors among the target test vectors;
[0033] If there are unselected test vectors among the target test vectors, the test continues.
[0034] In the functional safety testing method for chip transient failures in the embodiments of this specification, the chip includes an automotive-grade chip.
[0035] On the other hand, embodiments of this specification also provide a functional safety testing apparatus for chip transient faults, including:
[0036] The acquisition module is used to acquire the set of functional units that are hit by the chip under transient fault simulation test and the set of test vectors corresponding to the hit.
[0037] The sorting module is used to sort the test vector set into a test vector sequence based on the contribution and coverage of the functional unit set.
[0038] An irradiation module is used to control the irradiation source to continuously irradiate the chip;
[0039] The detection module is used to input each test vector in the test vector sequence into the chip in sequence, and to detect the fault detection results of each functional unit under each input.
[0040] The determination module is used to determine the functional test result of the chip under each input based on the fault detection results of each functional unit under each input.
[0041] On the other hand, embodiments of this specification also provide a computer device, including a memory, a processor, and a computer program stored in the memory, wherein the computer program, when run by the processor, executes instructions for the above-described method.
[0042] On the other hand, embodiments of this specification also provide a computer storage medium storing a computer program thereon, which, when run by the processor of a computer device, executes instructions for the above-described method.
[0043] On the other hand, embodiments of this specification also provide a computer program product, which includes a computer program that, when run by the processor of a computer device, executes instructions for the above-described method.
[0044] As can be seen from the technical solutions provided in the embodiments of this specification above, the embodiments of this specification can perform transient fault simulation tests on the chip in advance to obtain each functional unit hit under the transient fault simulation test and each test vector used when hit, and these are correspondingly used as a functional unit set and a test vector set. This allows for the selection of functional units with weak security as test objects and simplifies the number of test vectors used, thereby improving the efficiency of functional safety testing of the chip under transient faults. Furthermore, by sorting the test vector set into a test vector sequence based on its contribution and coverage to the functional unit set, and testing in stages according to the order of the test vector sequence, it is beneficial to hit transient faults that have a significant impact on the expected safety target earlier, thereby further improving the efficiency of functional safety testing of the chip under transient faults. Attached Figure Description
[0045] To more clearly illustrate the technical solutions in the embodiments or prior art of this specification, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:
[0046] Figure 1 This specification shows schematic diagrams illustrating application scenarios of the functional safety testing apparatus in some embodiments;
[0047] Figure 2 This specification shows flowcharts of functional safety testing methods under transient chip failures in some embodiments;
[0048] Figure 3 It shows Figure 2 The flowchart shown illustrates the sorting process of the test vector set in the method described.
[0049] Figure 4 It shows Figure 2 The flowchart shown illustrates the method of performing tests in stages according to the order of the test vector sequence.
[0050] Figure 5 It shows Figure 2The flowchart shown illustrates the method for determining the corresponding functional test result based on the fault detection result under each input.
[0051] Figure 6 This specification illustrates a functional safety test diagram under transient chip failure in an exemplary embodiment.
[0052] Figure 7 A schematic diagram of a functional unit (see the cross mark in the figure) detected under a single input in an exemplary embodiment of this specification is shown;
[0053] Figure 8 This specification shows a structural block diagram of a functional safety test apparatus for chip transient faults in some embodiments;
[0054] Figure 9 A structural block diagram of a computer device in some embodiments of this specification is shown.
[0055] [Explanation of Labels in the Attached Image]
[0056] 11. Irradiation source;
[0057] 12. Functional safety testing equipment;
[0058] 81. Acquisition Module
[0059] 82. Sorting module;
[0060] 83. Irradiation module;
[0061] 84. Detection module;
[0062] 85. Determine the module;
[0063] 902. Computer equipment;
[0064] 904, Processor;
[0065] 906. Memory;
[0066] 908. Drive mechanism;
[0067] 910. Input / output interfaces;
[0068] 912. Input devices;
[0069] 914. Output devices;
[0070] 916. Presentation equipment;
[0071] 918. Graphical User Interface;
[0072] 920. Network interface;
[0073] 922. Communication link;
[0074] 924. Communication bus. Detailed Implementation
[0075] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this specification.
[0076] The embodiments in this specification relate to transient fault safety testing techniques for chips, which can be applied to transient fault safety testing of automotive-grade chips as well as non-automotive-grade chips. Automotive-grade chips can be, for example, automotive-grade safety MCU chips, automotive-grade gateway control MCU chips, engine powertrain control chips, etc.
[0077] Figure 1 The document illustrates application scenarios of the functional safety testing apparatus in some embodiments. In these scenarios, the irradiation source 11, also known as a radiation source, refers to a device that emits electromagnetic radiation such as lasers or heavy ions to irradiate the chip, facilitating functional safety testing under electromagnetic interference simulation. In an exemplary embodiment, the irradiation source 11 can be a laser, a radiation generator, etc. The functional safety testing apparatus 12 is an integrated circuit testing device used to detect the integrity of integrated circuit functions. Specifically, the functional safety testing apparatus 12 can acquire the set of functional units hit by the chip under transient fault simulation testing and the set of test vectors corresponding to the hits; sort the test vector set into a test vector sequence based on the contribution and coverage of the functional unit set; control the irradiation source 11 to continuously irradiate the chip; sequentially input each test vector in the test vector sequence into the chip, and detect the fault detection results of each functional unit under each input; then, based on the fault detection results of each functional unit under each input, determine the functional test result of the chip under each input.
[0078] In an exemplary embodiment, the functional safety testing apparatus may be, for example, a combination of a test bench and a host computer, or a test bench that integrates the data analysis and processing functions of a host computer.
[0079] This specification provides a functional safety testing method for chip transient faults, which can be applied to the aforementioned functional safety testing device. (Refer to...) Figure 2As shown, in some embodiments, the functional safety testing apparatus may include the following steps:
[0080] Step 201: Obtain the set of functional units that are hit under transient fault simulation test of the chip and the set of test vectors corresponding to the hit.
[0081] Step 202: Sort the test vector set into a test vector sequence based on the contribution and coverage of the functional unit set.
[0082] Step 203: Control the irradiation source to continuously irradiate the chip.
[0083] Step 204: Input each test vector in the test vector sequence into the chip in sequence, and detect the fault detection results of each functional unit under each input.
[0084] Step 205: Determine the functional test result of the chip under each input based on the fault detection results of each functional unit under each input.
[0085] In the embodiments of this specification, transient fault simulation tests can be performed on the chip in advance to obtain the functional units that are hit under the transient fault simulation test and the test vectors used when they are hit. These are then used as a set of functional units and a set of test vectors, thereby selecting functional units with weak security as test objects and reducing the number of test vectors used. This improves the efficiency of functional safety testing of the chip under transient faults. Furthermore, by sorting the test vector set into a test vector sequence based on its contribution to and coverage of the functional unit set, and testing in stages according to the order of the test vector sequence, it is beneficial to hit transient faults that have a significant impact on the expected safety objectives earlier, thereby further improving the efficiency of functional safety testing of the chip under transient faults.
[0086] Transient fault simulation testing refers to injecting transient faults into each functional unit of a chip through a programmed simulation of an integrated circuit test environment (e.g., using simulation tools such as VCS) to perform fault simulation. The simulation test is performed sequentially using each test vector from the full set of test vectors, and the functional units that are hit and the test vectors used when they are hit are statistically analyzed. A hit functional unit refers to a functional unit identified as having a transient fault or having a high probability of having a transient fault during the transient fault simulation test. For example, in an exemplary embodiment, if functional unit A of the chip detects a fault after inputting test vector R, then functional unit A is one of the hit functional units, and test vector R is the test vector corresponding to when functional unit A is hit.
[0087] In this way, by conducting transient fault simulation tests in advance to screen functional units and test vectors, it can be ensured that functional units with weak functional safety in the chip can participate in actual functional tests, which helps to ensure the accuracy of functional safety tests of the chip under transient faults.
[0088] It should be noted that a test pattern is a test input signal. In functional safety testing scenarios under transient chip failures, test patterns can be used to detect the functional safety of the chip. In some embodiments, test pattern generation tools (such as TetraMax) can be used to generate test patterns.
[0089] In the embodiments of this specification, a functional unit refers to the various modules or units within a chip that are divided according to their functions, and each module or unit can perform a specific function. For example, taking a CPU chip as an example, a CPU chip may include an arithmetic logic unit (ALU), a control unit, registers, etc. The ALU, control unit, and registers can all be considered as functional units. In practical application scenarios, the granularity of the functional units in a chip can be adjusted according to actual needs (for example, it can be divided into more finely).
[0090] refer to Figure 3 As shown, in some embodiments, sorting the test vector set into a test vector sequence based on its contribution to and coverage of the functional unit set may include the following steps:
[0091] Step 301: Determine the contribution of each test vector in the test vector set to the functional unit set.
[0092] The contribution of a test vector to the set of functional units refers to the degree to which a single test vector hits a functional unit during transient fault simulation testing. The more functional units a single test vector hits, the greater its contribution. A greater contribution indicates that the test vector is more important in functional safety testing.
[0093] In some embodiments, it can be based on the formula Calculate the contribution of each test vector in the test vector set to the functional unit set. Where, C i N represents the contribution of the i-th test vector in the test vector set to the set of functional units. ik M represents the probability that the i-th test vector hits the k-th functional unit in the set of functional units, where M is the size of the set of functional units (i.e., the number of elements in the set of functional units).
[0094] Step 302: Arrange the set of test vectors into an initial sequence according to their contribution.
[0095] Arranging the test vector set into an initial sequence according to contribution means arranging the test vector set into an initial sequence in descending order of contribution.
[0096] Step 303: Determine the coverage of the functional unit set by the subsequence formed by the largest contributor and each of the remaining test vectors in the initial sequence.
[0097] Coverage refers to the percentage of functional units hit by a single test vector subsequence relative to the entire set of test vectors during transient fault simulation testing. A higher coverage indicates greater importance of the test vectors in functional safety testing.
[0098] For example, in an exemplary embodiment, it is assumed that the contribution ranking of each test vector is C1 > C2 > K > C i >K>C n The corresponding initial test vector sequence (i.e., the initial sequence) is {V1, V2, K, V}. i ,K,V n Since C1 is the largest contributor, the test vector V1 corresponding to C1 is the one with the largest contribution. Therefore, in V1, V2, K, V... i ,K,V n The remaining test vectors include {V2,K,V}. i ,K,V n If the test vector V1 can be used with {V2, K, V}, then the test vector V1 can be used with {V2, K, V}. i ,K,V n Each test vector in {} forms a subsequence; for example, {V1,V2}, {V1,V3}, ..., {V1,V2}. i}、…、{V1,V n}
[0099] Based on transient fault simulation testing of the chip, the coverage of each subsequence can be statistically determined. For example, in the exemplary embodiment described above, it is assumed that the chip has 10 functional units F1 to F2. 10 If the functional units hit by V1, V2, and V3 are respectively:
[0100] V1: F1, F2, F5, F8, F 10 ;
[0101] V2: F1, F2, F6, F8;
[0102] V3: F1, F4, F7;
[0103] The total number of functional units hit by the subsequence {V1,V2} are: F1, F2, F5, F6, F8, F 10 ;
[0104] The total number of functional units hit by the subsequence {V1,V3} are: F1, F2, F4, F5, F7, F8, F 10 ;
[0105] Therefore, the coverage of subsequence {V1,V3} is greater than that of subsequence {V1,V2}.
[0106] Step 304: Determine the coverage of the functional unit set by the subsequence with the largest coverage and the subsequence formed by each of the remaining test vectors in the initial sequence.
[0107] Taking the exemplary embodiment in step 303 as an example, if the subsequence {V1,V3} is {V1,V2}, {V1,V3}, ..., {V1,V2}, ..., {V1,V3}, ... i}、…、{V1,V n The subsequence with the largest coverage in {V1,V2,K,V}; then at this time, the subsequence with the largest coverage in {V1,V2,K,V}. i ,K,V n In the remaining test vectors, {V2,V4,K,V}, the remaining test vectors include {V2,V4,K,V}. i ,K,V n If the subsequence {V1,V3} can be combined with {V2,V4,K,V}, then the subsequence {V1,V3} can be combined with {V2,V4,K,V}. i ,K,V n Each test vector in {V1,V3,V2} forms a new subsequence; for example, {V1,V3,V4}, ..., {V1,V3,V4}. i}、…、{V1,V3,V n}, and based on this, calculate the coverage of each new subsequence to the set of functional units;
[0108] If the subsequence {V1,V3,V2} is {V1,V3,V2}, {V1,V3,V4}, ..., {V1,V3,V2}, then... i}、…、{V1,V3,V n The subsequence with the largest coverage in {V1,V2,K,V} is then in {V1,V2,K,V}. i ,K,V n In the remaining test vectors, {V4,K,V}, the remaining test vectors include {V4,K,V}. i ,K,V n If the subsequence {V1,V3,V2} can be combined with {V4,K,V}, then the subsequence {V1,V3,V2} can be combined with {V4,K,V}. i ,K,V n Each test vector in {V1,V3,V2,V5} forms a new subsequence; for example, {V1,V3,V2,V6}, ..., {V1,V3,V2,V6}. i}、…、{V1,V3,V2,V n}, and on this basis, calculate the coverage of each new subsequence to the set of functional units, and so on.
[0109] Step 305: Determine whether the length of the subsequence with the largest coverage currently obtained meets the preset condition. If it does, proceed to step 306; otherwise, proceed to step 304 to continue sorting.
[0110] The preset conditions can be customized as needed. For example, in some embodiments, the preset condition can be to achieve full coverage of the currently obtained subsequence with the largest coverage (i.e., coverage is 100%). This is beneficial for further simplifying test vectors, thereby improving testing efficiency. If full coverage is not achieved when the length of the currently obtained subsequence with the largest coverage is R = S-1 (R is the length of the currently obtained subsequence with the largest coverage, and S is the length of the initial sequence), then the last remaining test vector in the initial sequence needs to participate in the test to ensure test accuracy.
[0111] Step 306: Use the subsequence with the highest coverage obtained so far as the test vector sequence.
[0112] For example, taking the exemplary embodiments in steps 303 and 304 as examples, if the currently obtained subsequence with the largest coverage {V1,V3,V2,V5,K,V... i ,K,V n-1 If the length of} is n-1, then the remaining test vector V in the initial sequence can be... n Add to {V1,V3,V2,V5,K,V i ,K,V n-1 The end of} forms the test vector sequence {V1,V3,V2,V5,K,V}. i ,K,V n-1 V n}
[0113] Therefore, when the test vector set is sorted into a test vector sequence based on the contribution and coverage of the functional unit set, and the test is performed in batches according to the order of the test vector sequence, not only can transient faults that have a significant impact on chip safety be hit earlier, thus ending the test in advance and achieving the purpose of saving test time and improving test efficiency, but it can also avoid missing functional units with weak safety performance, thereby ensuring test accuracy.
[0114] refer to Figure 4 As shown, in some embodiments, inputting each test vector in the test vector sequence into the chip sequentially and detecting the fault detection results of each functional unit under each input may include the following steps:
[0115] Step 401: Select an unselected test vector from the test vector sequence as the target test vector.
[0116] For example, in an exemplary embodiment, if the test vector sequence {V1,V2,K,V} i ,K,V n If none of the test vectors in the sequence {V1, V2, K, V} have been selected before, then test vector V1 can be selected this time; if the test vector sequence {V1, V2, K, V} has not been selected before, then test vector V1 can be selected this time. i ,K,V n If none of the test vectors in the sequence {V1, V2, K, V} have been selected before, then test vector V2 can be selected this time; if the test vector sequence {V1, V2, K, V} has not been selected before, then test vector V2 can be selected this time. i ,K,V n In the given list, since none of the test vectors V1 and V2 have been selected before, test vector V3 can be selected this time; and so on.
[0117] Step 402: Input the target test vector into the chip.
[0118] Obviously, the input of the target test vector into the chip is performed under the background or premise that the irradiation source is continuously irradiating the chip.
[0119] Step 403: Detect the fault detection results of each functional unit under the target test vector input.
[0120] The functional safety testing equipment is equipped with a fault detection device that can detect whether the output of each functional unit of the chip is the expected output after the target test vector is input. If the output of a functional unit is the expected output, it means that the functional unit is not faulty under the target test vector input; otherwise, it means that the functional unit is faulty under the target test vector input, and the faulty functional unit can be marked (e.g., Figure 6 or Figure 7 (The faulty functional units are marked with a cross in the text).
[0121] Step 404: Determine if the conditions for continuing the test are met. If met, proceed to step 401 to continue the test; otherwise, end the test.
[0122] The conditions for continuing test execution can be customized. For example, in one embodiment, the conditions for continuing test execution can be: the total number of functional units with detected faults under the current target test vector is lower than a set threshold, and there are unselected target test vectors in the test vector sequence. If the total number of functional units with detected faults under the current target test vector is lower than the set threshold, it indicates that the expected safety target of the chip will not be affected in this scenario, and the test can continue.
[0123] refer to Figure 5 As shown, in some embodiments, determining the functional test result of the chip under each input based on the fault detection results of each functional unit under each input may include the following steps:
[0124] Step 501: Accumulate the number of functional units that have been detected as faulty in the functional unit set under the current input.
[0125] Step 502: Determine whether the accumulated value has reached a preset threshold. If the accumulated value has reached the preset threshold, proceed to step 503; otherwise, proceed to step 504.
[0126] Step 503: Output the accumulated value.
[0127] By outputting the accumulated value, the severity of the chip malfunction can be quantitatively alerted to relevant personnel, enabling them to respond and handle the situation.
[0128] Step 504: Determine whether there are any unselected test vectors among the target test vectors. If there are unselected test vectors among the target test vectors, proceed to step 505; otherwise, end the test.
[0129] Step 505: Continue with the test.
[0130] Corresponding to the functional safety testing methods under transient chip faults described above, refer to Figure 8 As shown, in some embodiments, the functional safety testing apparatus of this specification may include:
[0131] The acquisition module 81 is used to acquire the set of functional units that are hit by the chip under transient fault simulation test and the set of test vectors corresponding to the hit.
[0132] The sorting module 82 is used to sort the test vector set into a test vector sequence based on the contribution and coverage of the functional unit set.
[0133] Irradiation module 83 is used to control the irradiation source to continuously irradiate the chip;
[0134] The detection module 84 is used to input each test vector in the test vector sequence into the chip in sequence, and to detect the fault detection results of each functional unit under each input.
[0135] The determination module 85 is used to determine the functional test result of the chip under each input based on the fault detection results of each functional unit under each input.
[0136] For ease of description, the above devices are described in terms of function, divided into various units. Of course, in implementing this specification, the functions of each unit can be implemented in one or more software and / or hardware components.
[0137] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in the embodiments of this specification are all information and data authorized and agreed upon by the user and fully authorized by all parties.
[0138] Embodiments of this specification also provide a computer device. For example... Figure 9 As shown, in some embodiments of this specification, the computer device 902 may include one or more processors 904, such as one or more central processing units (CPUs) or graphics processing units (GPUs), each of which may implement one or more hardware threads. The computer device 902 may also include any memory 906 for storing information of any kind, such as code, settings, data, etc. In one specific embodiment, a computer program is stored on the memory 906 and can run on the processor 904. When the computer program is run by the processor 904, it can execute instructions of the functional safety testing method under chip transient failures described in any of the above embodiments. Without limitation, for example, the memory 906 may include any type of RAM, any type of ROM, flash memory, hard disk, optical disk, etc. More generally, any memory can use any technology to store information. Furthermore, any memory can provide volatile or non-volatile retention of information. Furthermore, any memory may represent a fixed or removable component of the computer device 902. In one scenario, when processor 904 executes associated instructions stored in any memory or combination of memories, computer device 902 can perform any operation of the associated instructions. Computer device 902 also includes one or more drive mechanisms 908 for interacting with any memory, such as hard disk drive mechanisms, optical disk drive mechanisms, etc.
[0139] Computer device 902 may also include an input / output interface 910 (I / O) for receiving various inputs (via input device 912) and providing various outputs (via output device 914). A specific output mechanism may include a presentation device 916 and an associated graphical user interface 918 (GUI). In other embodiments, the input / output interface 910 (I / O), input device 912, and output device 914 may be omitted, and the device may function solely as a computer device within a network. Computer device 902 may also include one or more network interfaces 920 for exchanging data with other devices via one or more communication links 922. One or more communication buses 924 couple the components described above together.
[0140] Communication link 922 can be implemented in any way, such as via a local area network, a wide area network (e.g., the Internet), a point-to-point connection, or any combination thereof. Communication link 922 may include any combination of hardwired links, wireless links, routers, gateway functions, name servers, etc., governed by any protocol or combination of protocols.
[0141] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), computer-readable storage media, and computer program products according to some embodiments of this specification. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processor to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processor, create a mechanism for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0142] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processor to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0143] These computer program instructions may also be loaded onto a computer or other programmable data processor, causing a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable device for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0144] In a typical configuration, a computer device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.
[0145] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.
[0146] Computer-readable media, including both permanent and non-permanent, removable and non-removable media, can store information using any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by computer equipment. As defined in this specification, computer-readable media does not include transient media, such as modulated data signals and carrier waves.
[0147] Those skilled in the art will understand that the embodiments of this specification can be provided as methods, systems, or computer program products. Therefore, the embodiments of this specification can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, the embodiments of this specification can take the form of computer program products implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0148] The embodiments described in this specification can be described in the general context of computer-executable instructions, such as program modules, that are executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. The embodiments of this specification can also be practiced in distributed computing environments where tasks are performed by remote processors connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.
[0149] It should also be understood that, in the embodiments of this specification, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.
[0150] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.
[0151] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments of this specification. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0152] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.
Claims
1. A functional safety testing method for chips under transient faults, characterized in that, include: Obtain the set of functional units that are hit in the transient fault simulation test of the chip and the set of test vectors corresponding to the hit; The test vector set is sorted into a test vector sequence based on its contribution and coverage to the functional unit set. This includes determining the contribution of each test vector in the test vector set to the functional unit set; arranging the test vector set into an initial sequence according to its contribution; determining the coverage of the functional unit set by the subsequence formed by the test vector with the largest contribution and each of the remaining test vectors in the initial sequence; and determining the coverage of the functional unit set by the subsequence formed by the subsequence with the largest coverage and each of the remaining test vectors in the initial sequence. The process is repeated until the length of the subsequence with the highest coverage currently obtained meets a preset condition; the subsequence with the highest coverage currently obtained is taken as the test vector sequence; wherein, determining the contribution of each test vector in the test vector set to the functional unit set includes: according to the formula Calculate the contribution of each test vector in the test vector set to the functional unit set; where, For the test vector set, the first The contribution of each test vector to the set of functional units. For the first The test vector hits the first functional unit in the set of said test vectors. The probability of each functional unit, The size of the set of functional units; The irradiation source is controlled to continuously irradiate the chip; Each test vector in the test vector sequence is input into the chip sequentially, and the fault detection result of each functional unit is detected each time it is input. Based on the fault detection results of each functional unit under each input, the functional test result of the chip under each input is determined.
2. The functional safety testing method for chip transient faults as described in claim 1, characterized in that, The preset conditions include: The subsequence with the highest coverage obtained so far achieves full coverage.
3. The functional safety testing method for chip transient faults as described in claim 1, characterized in that, The test vectors in the test vector sequence are input into the chip sequentially, and the fault detection results of each functional unit under each input are detected, including: From the sequence of test vectors, select one unselected test vector as the target test vector; The target test vector is input into the chip; The fault detection results of each of the functional units are detected under the target test vector input; Repeat the above steps when the conditions for continuing the test are met, until all test vectors in the test vector sequence have been selected.
4. The functional safety testing method for chip transient faults as described in claim 3, characterized in that, Based on the fault detection results of each functional unit under each input, the functional test results of the chip under each input are determined, including: The number of functional units that have been detected as faulty in the set of functional units under the current input is accumulated; Determine whether the accumulated value has reached the preset threshold; When the accumulated value reaches the threshold, the accumulated value is output.
5. The functional safety testing method for chip transient faults as described in claim 4, characterized in that, Based on the fault detection results of each functional unit under each input, the functional test result of the chip under each input is determined, which also includes: When the accumulated value does not reach the threshold, it is determined whether there are any unselected test vectors among the target test vectors; If there are unselected test vectors among the target test vectors, the test continues.
6. The functional safety testing method for chip transient faults as described in claim 1, characterized in that, The chip includes automotive-grade chips.
7. A functional safety testing device for chip transient faults, characterized in that, include: The acquisition module is used to acquire the set of functional units that are hit by the chip under transient fault simulation test and the set of test vectors corresponding to the hit. A sorting module is used to sort the test vector set into a test vector sequence based on the contribution and coverage of the functional unit set. This includes determining the contribution of each test vector in the test vector set to the functional unit set; arranging the test vector set into an initial sequence according to the contribution; determining the coverage of the functional unit set by the subsequence formed by the test vector with the largest contribution and each of the remaining test vectors in the initial sequence; and determining the coverage of the functional unit set by the subsequence formed by the subsequence with the largest coverage and each of the remaining test vectors in the initial sequence. The process is repeated until the length of the subsequence with the highest coverage currently obtained meets a preset condition; the subsequence with the highest coverage currently obtained is taken as the test vector sequence; wherein, determining the contribution of each test vector in the test vector set to the functional unit set includes: according to the formula Calculate the contribution of each test vector in the test vector set to the functional unit set; where, For the test vector set, the first The contribution of each test vector to the set of functional units. For the first The test vector hits the first functional unit in the set of said test vectors. The probability of each functional unit, The size of the set of functional units; An irradiation module is used to control the irradiation source to continuously irradiate the chip; The detection module is used to input each test vector in the test vector sequence into the chip in sequence, and to detect the fault detection results of each functional unit under each input. The determination module is used to determine the functional test result of the chip under each input based on the fault detection results of each functional unit under each input.
8. A computer device comprising a memory, a processor, and a computer program stored in the memory, characterized in that, When the computer program is run by the processor, it executes the instructions of the method according to any one of claims 1-6.
9. A computer storage medium having a computer program stored thereon, characterized in that, When the computer program is run by the processor of the computer device, it executes the instructions of the method according to any one of claims 1-6.
10. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, performs instructions according to any one of claims 1-6.