Integrated circuit design method and integrated circuit simulation system

Abstract

The application provides an integrated circuit design method and an integrated circuit simulation system, and relates to the technical field of circuit design, wherein the integrated circuit design method comprises the following steps: generating an initial architecture of an integrated circuit based on selected components according to obtained application information, and performing system-level architecture performance simulation on the initial architecture to obtain architecture performance parameters; in the case that the architecture performance parameters meet a set performance condition, determining pin interconnection information between the components according to pin information of the components; performing pin connection and layout on the components in the initial architecture based on the pin interconnection information and a set process constraint to obtain a target architecture of the integrated circuit; performing integrity simulation on the target architecture to obtain integrity parameters, and in the case that the integrity parameters meet a set integrity condition, outputting the target architecture, which is used for designing the integrated circuit. The architecture simulation process can be simplified, the simulation and verification efficiency of the integrated circuit is improved, and the hardware design cycle is shortened.

Description

Technical Field

[0001] This invention relates to the fields of circuit design technology and architecture simulation, and in particular to an integrated circuit design method and an integrated circuit simulation system. Background Technology

[0002] With the continuous development of science and technology, System on Wafer (SoW) has emerged. SoW is a new integrated circuit design paradigm that brings synergistic gains through system architecture and process innovation.

[0003] Due to the long iterative design cycle of hardware, simulation verification of the design scheme is usually performed in the early stages of chip design. Currently, there are various open-source simulators available, which can be used independently or flexibly combined to build various architectures. Simulation results can provide a preliminary assessment of the architecture's functional correctness, execution time, throughput, and other architectural performance parameters. However, architecture-level simulation results still differ from the performance of real hardware and cannot simulate the chip's power supply and signal performance. Therefore, an effective solution is urgently needed to address these issues. Summary of the Invention

[0004] To address the problems existing in the prior art, embodiments of the present invention provide an integrated circuit design method and an integrated circuit simulation system.

[0005] This invention provides an integrated circuit design method, comprising:

[0006] Based on the obtained application information, at least one component is selected, and an initial architecture of an integrated circuit is generated based on each component. System-level architecture performance simulation is then performed on the initial architecture to obtain architecture performance parameters.

[0007] When the architecture performance parameters meet the set performance conditions, the pin interconnection information between the components is determined based on the pin information of each component.

[0008] Based on the pin interconnection information and the set process constraints, the pin connections and layouts of each component in the initial architecture are performed to obtain the target architecture of the integrated circuit.

[0009] Integrity simulation is performed on the target architecture to obtain integrity parameters. If the integrity parameters meet the set integrity conditions, the target architecture is output. The target architecture is used to design the integrated circuit. The integrity simulation includes signal integrity simulation and / or power integrity simulation.

[0010] According to an integrated circuit design method provided by the present invention, the step of determining the pin interconnection information between the components based on the pin information of each component, when the architecture performance parameters meet the set performance conditions, includes:

[0011] When the architecture performance parameters meet the set performance conditions, the pin information of each component is read from the acquired component specifications.

[0012] Based on the pin information, determine the pin port mapping;

[0013] Based on the pin port mapping and the component interconnection relationship of each component in the initial architecture, the pin interconnection information between each component is determined.

[0014] According to an integrated circuit design method provided by the present invention, the step of performing pin interconnection and placement of each component in the initial architecture based on the pin interconnection information and set process constraints to obtain the target architecture of the integrated circuit includes:

[0015] Based on the pin interconnection information, the pins of each component in the initial architecture are connected to obtain the alternative architecture of the integrated circuit;

[0016] Based on the set process constraints, the components in the backup architecture are laid out to obtain the target architecture of the integrated circuit.

[0017] According to an integrated circuit design method provided by the present invention, the step of laying out each of the components in the alternative architecture according to the set process constraints to obtain the target architecture of the integrated circuit includes:

[0018] The backup architecture is displayed via a display device to receive user instructions for adjusting the backup architecture;

[0019] Based on the adjustment instructions and the set process constraints, the components in the backup architecture are laid out to obtain the target architecture of the integrated circuit; or

[0020] According to the adjustment instructions and the set process constraints, the components in the backup architecture are laid out and the pin connections between the components are adjusted to obtain the target architecture of the integrated circuit.

[0021] According to an integrated circuit design method provided by the present invention, the step of selecting at least one component based on acquired application information and generating an initial architecture of the integrated circuit based on each component includes:

[0022] The acquired application information is parsed;

[0023] Based on the analysis results and the set performance constraints, the simulation parameters are determined. The simulation parameters include the types of components, the number of components, and the interconnection information of the components in the design of the integrated circuit.

[0024] Select at least one component based on the type and quantity of the components;

[0025] Based on the interconnection information of the components, the components are connected to generate the initial architecture of the integrated circuit.

[0026] According to an integrated circuit design method provided by the present invention, the step of performing system-level architecture performance simulation on the initial architecture to obtain architecture performance parameters includes:

[0027] Based on the simulation parameters, a system-level architecture performance simulation is performed on the initial architecture to obtain the architecture performance parameters;

[0028] After performing system-level architecture performance simulation on the initial architecture to obtain the architecture performance parameters, the process further includes:

[0029] If the architecture performance parameters do not meet the set performance conditions, the step of selecting at least one component and generating an initial architecture of the integrated circuit based on each component is executed according to the application information and the architecture performance parameters.

[0030] After performing integrity simulation on the target architecture to obtain integrity parameters, the process further includes:

[0031] If the integrity parameters do not meet the set integrity conditions, the target architecture of the integrated circuit is reconstructed according to the integrity parameters.

[0032] According to an integrated circuit design method provided by the present invention, the integrity parameters include signal integrity parameters and power integrity parameters;

[0033] Accordingly, when the integrity parameters do not meet the set integrity conditions, reconstructing the target architecture of the integrated circuit based on the integrity parameters includes:

[0034] If the power integrity parameters do not meet the set integrity conditions, the step of selecting at least one component and generating an initial architecture of the integrated circuit based on each component is performed according to the application information and the power integrity parameters.

[0035] If the power integrity parameter satisfies the set integrity condition, but the signal integrity parameter does not satisfy the set integrity condition, based on the signal integrity parameter, the pin interconnection information, and the set process constraints, the step of connecting and laying out the pins of each of the components in the initial architecture to obtain the target architecture of the integrated circuit is performed.

[0036] The present invention also provides an integrated circuit simulation system, comprising:

[0037] An architecture design generation module is used to select at least one component based on the acquired application information and generate an initial architecture of an integrated circuit based on each component.

[0038] The system-level simulation module is used to perform system-level architecture performance simulation on the initial architecture to obtain architecture performance parameters.

[0039] A visualization layout module is used to determine the pin interconnection information between the components based on the pin information of each component when the architecture performance parameters meet the set performance conditions; and to perform pin connection and layout of each component in the initial architecture based on the pin interconnection information and set process constraints to obtain the target architecture of the integrated circuit.

[0040] The integrity simulation module is used to perform integrity simulation on the target architecture, obtain integrity parameters, and output the target architecture when the integrity parameters meet the set integrity conditions. The target architecture is used to design the integrated circuit. The integrity simulation includes signal integrity simulation and / or power integrity simulation.

[0041] According to an integrated circuit simulation system provided by the present invention, the system-level simulation module is further used for:

[0042] If the architecture performance parameters meet the set performance conditions, generate the initial architecture's class schematic file;

[0043] Extract the component types, component quantities, and component interconnection information from the aforementioned schematic file to the first data exchange file;

[0044] The first data exchange file is passed to the visualization layout module;

[0045] The visualization layout module is also used for:

[0046] The received first data exchange file is parsed to obtain the initial architecture;

[0047] The initial architecture is displayed on a display device, and the user inputs process constraints based on the initial architecture.

[0048] According to an integrated circuit simulation system provided by the present invention, the visualization layout module is further used for:

[0049] Based on the pin interconnection information, the pins of each component in the initial architecture are connected to obtain the alternative architecture of the integrated circuit;

[0050] The initial architecture is displayed through a display device, and when a user triggers a magnification operation on a specified component in the initial architecture, the specified component in the alternative architecture is displayed through the display device.

[0051] Receive the user's adjustment instructions for the backup architecture;

[0052] Based on the adjustment instructions and the set process constraints, the components in the backup architecture are laid out to obtain the target architecture of the integrated circuit; or

[0053] According to the adjustment instructions and the set process constraints, the components in the backup architecture are laid out and the pin connections between the components are adjusted to obtain the target architecture of the integrated circuit.

[0054] According to an integrated circuit simulation system provided by the present invention, the visualization layout module is further used for:

[0055] Based on the target architecture, generate a second data exchange file;

[0056] The second data exchange file is sent to the integrity simulation module;

[0057] The integrity simulation module is also used for:

[0058] The second data exchange file is converted to a new format to obtain the target simulation file specified by the simulation software.

[0059] The specified simulation software is invoked to perform integrity simulation on the target architecture based on the target simulation file, thereby obtaining integrity parameters, which include signal integrity parameters and power integrity parameters.

[0060] The integrity simulation module is also used for:

[0061] If the power integrity parameters do not meet the set integrity conditions, the power integrity parameters are sent to the architecture design generation module.

[0062] If the power integrity parameter meets the set integrity condition, but the signal integrity parameter does not meet the set integrity condition, the power integrity parameter is sent to the visualization layout module.

[0063] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the integrated circuit design method described above.

[0064] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the integrated circuit design method as described above.

[0065] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements an integrated circuit design method as described above.

[0066] The integrated circuit design method and simulation system provided by this invention select at least one component based on acquired application information, generate an initial architecture of the integrated circuit based on each component, and perform system-level architecture performance simulation on the initial architecture to obtain architecture performance parameters. If the architecture performance parameters meet set performance conditions, determine the pin interconnection information between the components based on their pin information. Based on the pin interconnection information and set process constraints, perform pin wiring and layout on each component in the initial architecture to obtain the target architecture of the integrated circuit. Perform integrity simulation on the target architecture to obtain integrity parameters, and output the target architecture if the integrity parameters meet set integrity conditions. The target architecture is used to design the integrated circuit. The integrity simulation includes signal integrity simulation and / or power integrity simulation. By integrating integrated circuit architecture design technology and simulation tools, the system automatically generates the architecture from coarse-grained integrated circuit architecture to fine-grained pin interconnections, solving the problems of high barriers to entry and fragmented tools. It also simplifies the integrated circuit architecture simulation process, improves the efficiency of integrated circuit architecture design simulation verification, shortens the hardware design cycle, and improves the efficiency of architecture optimization iteration. Simultaneously, it provides multi-level analysis data for integrated circuit design iteration optimization. Attached Figure Description

[0067] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0068] Figure 1 This is one of the flowcharts illustrating the integrated circuit design method provided by the present invention;

[0069] Figure 2 This is the second flowchart illustrating the integrated circuit design method provided by the present invention;

[0070] Figure 3 This is a schematic diagram of the integrated circuit simulation system provided by the present invention;

[0071] Figure 4 This is a schematic diagram of the processing flow of the integrated circuit design system provided by the present invention;

[0072] Figure 5 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0073] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0074] To facilitate a clearer understanding of the various embodiments of the present invention, some relevant background knowledge will be introduced as follows.

[0075] With the continuous development of science and technology, System-on-Wafer (SoW) has emerged. Compared with traditional systems based on Printed Circuit Board (PCB) designs or microsystems built on advanced packaging, SoW features extremely large integration scale, extremely complex interconnections, ultra-high density heterogeneous integration, and ultra-high density power supply and heat dissipation. It belongs to a new integrated circuit design paradigm that brings synergistic gains through system architecture innovation and process innovation. SoW directly uses a complete wafer substrate as the interconnect base for the various modules within the system, realizing a complete system on a wafer densely packed with various chips. This reduces performance losses between layer connections.

[0076] Due to the long iterative design cycle of hardware, simulation verification of the design scheme is usually required in the early stages of chip design. Currently, there are various open-source simulators available, such as Gem5 (a system-level multi-core CPU simulator), GPGPU-sim (a graphics processing unit (GPU) simulator), DRAMsim (a memory simulator), and the Structural Simulation Toolkit (SST). These simulators can be used individually or flexibly combined to build various architectures. Simulation results can provide a preliminary assessment of the architecture's functional correctness, execution time, throughput, and other architectural performance parameters. However, architecture-level simulation results still differ from the performance of real hardware and cannot simulate the chip's power supply, signal performance, and other aspects. Furthermore, most open-source simulation platforms rely on configuration scripts to drive simulation and lack a visual interface to display the simulated architecture.

[0077] To more accurately simulate the performance of on-chip architectures, mature commercial Electronic Design Automation (EDA) tools such as Cadence and Synopsys are typically used to verify the power and signal integrity of the architecture. These commercial EDA tools are relatively complex to operate, requiring a learning curve to become proficient. Furthermore, the process from system-level simulation to EDA verification of power and signal integrity necessitates manual modification of the architecture design to meet the input specifications of the EDA tools. Wafer-level system (system-on-chip) architectures are large-scale, with complex chip pins and interconnections, making modifications time-consuming.

[0078] The architecture design and simulation process for on-chip systems requires the use of multiple tools. This tool fragmentation forces designers to frequently switch work environments and modify design schemes, preventing hardware developers from focusing on architecture design. The online computer-aided design (CAD) tool Chipuller addresses this fragmentation issue to some extent, providing a one-stop service for chip design and improving chip design efficiency. However, Chipuller is based on silicon substrates and lacks simulation verification. During chip construction, all connections between chip pins and the silicon substrate must be manually created, making it unsuitable for ultra-high integration density wafer-level chip design scenarios.

[0079] The architecture design of on-chip systems must meet performance and process constraints, balancing performance with chip area. A single simulator cannot simultaneously meet the simulation requirements of on-chip system architecture design. For simulation scenarios involving ultra-large-scale integration of on-chip systems, collaborative simulation using multiple simulators faces the problem of cumbersome cross-simulator input conversion.

[0080] Therefore, this invention provides an integrated circuit design method and an integrated circuit simulation system. Based on acquired application information, at least one component is selected, and an initial architecture of the integrated circuit is generated based on each component. System-level architecture performance simulation is performed on the initial architecture to obtain architecture performance parameters. If the architecture performance parameters meet set performance conditions, pin interconnection information between the components is determined based on their pin information. Based on the pin interconnection information and set process constraints, pin connections and layouts are performed on the components in the initial architecture to obtain the target architecture of the integrated circuit. Integrity simulation is performed on the target architecture to obtain integrity parameters. If the integrity parameters meet set integrity conditions, the target architecture is output. The target architecture is used to design the integrated circuit. The integrity simulation includes signal integrity simulation and / or power integrity simulation. By integrating integrated circuit architecture design technology and simulation tools, the system automatically generates information from coarse-grained integrated circuit architecture to fine-grained pin interconnections, solving the problems of high barriers to entry and fragmented tools. It also simplifies the integrated circuit architecture simulation process, improves the efficiency of integrated circuit architecture design simulation verification, shortens the hardware design cycle, and improves the efficiency of architecture optimization iteration. Simultaneously, it provides multi-level analysis data for integrated circuit design iteration optimization.

[0081] The following is combined Figures 1-4 The present invention describes the integrated circuit design method and integrated circuit simulation system.

[0082] Figure 1 This is one of the flowcharts illustrating the integrated circuit design method provided by this invention. See also... Figure 1 As shown, steps 101-104 are included, wherein:

[0083] Step 101: Based on the obtained application information, select at least one component, generate an initial architecture of the integrated circuit based on each component, and perform system-level architecture performance simulation on the initial architecture to obtain architecture performance parameters.

[0084] First, it should be noted that the subject of this invention can be any electronic device that designs integrated circuits, such as any desktop computer, laptop computer, etc.

[0085] Specifically, application information can be application source code or application features. Integrated circuits can be any type of circuit; preferably, they are highly integrated circuits, such as system-on-a-chip (SoC). Components, also known as prefabricated parts. Initial architecture refers to the integrated circuit obtained by connecting multiple components at the component level, such as connecting semiconductor A and capacitor B, without involving pin-level connections. System-level architecture performance, also known as architecture performance, refers to the performance of the initial architecture at the system level, including at least one of the following: runtime, power consumption, throughput, memory, and bandwidth. Architecture performance parameters refer to the parameters corresponding to the simulated system-level architecture performance.

[0086] In practical applications, users upload or input application source code or application characteristics, and the executing entity obtains the application information accordingly; or users trigger integrated circuit design instructions or application information retrieval instructions, and the executing entity retrieves the application information from the storage area corresponding to the instruction.

[0087] Furthermore, the architecture design algorithm is invoked to apply the information and automatically construct an architecture adapted to the application, i.e., the initial architecture of the integrated circuit: the architecture design algorithm selects the required components from a preset component library based on the application information, and connects the components to generate the initial architecture of the integrated circuit. Then, a system-level simulator is invoked to perform system-level architecture performance simulation on the initial architecture, evaluate its performance, and obtain the architecture performance parameters.

[0088] Step 102: If the architecture performance parameters meet the set performance conditions, determine the pin interconnection information between the components based on the pin information of each component.

[0089] Specifically, architecture performance includes at least one of the following: runtime, power consumption, throughput, memory, and bandwidth. Performance setting conditions refer to the conditions set for runtime, power consumption, throughput, memory, and bandwidth, such as runtime not exceeding a set duration or power consumption being lower than a set threshold. Pin information includes the number of pins and their functions. Pin interconnection information refers to the connection relationships between pins.

[0090] In practical applications, after obtaining the architecture performance parameters, it is determined whether the architecture performance parameters meet the set performance conditions. If not, the initial architecture is unqualified and needs to be reconstructed. This involves selecting at least one new component, generating an initial architecture of the integrated circuit based on each component, and iteratively optimizing it until an initial architecture whose performance parameters meet the set performance conditions is obtained. If the conditions are met, the initial architecture is qualified, and the pin information of each component in the initial architecture can be obtained: the pin information of each component is extracted according to the set component datasheet or hardware specification. Furthermore, based on the pin information of each component and the connection relationships between the components in the initial architecture, the pin interconnection information between the components is determined.

[0091] Step 103: Based on the pin interconnection information and the set process constraints, perform pin connection and layout for each component in the initial architecture to obtain the target architecture of the integrated circuit.

[0092] Specifically, setting process constraints, also known as process constraint conditions, includes the size of the integrated circuit, the spacing and arrangement of components, etc., such as wafer area, single die area, and die pitch. Process constraints can be user-inputted, or they can be obtained by the executing entity from the memory area or site pointed to by the user-triggered process constraint fetch command. The target architecture refers to the integrated circuit obtained after optimizing the pin-level connections and layout of multiple components.

[0093] In practical applications, after determining the pin interconnection information, the pin-dimensional connections of each component in the initial architecture are made according to the pin interconnection information and the set process constraints, and the layout between each component is adjusted to obtain the target architecture of the integrated circuit.

[0094] Step 104: Perform integrity simulation on the target architecture to obtain integrity parameters, and output the target architecture when the integrity parameters meet the set integrity conditions. The target architecture is used to design the integrated circuit. The integrity simulation includes signal integrity simulation and / or power integrity simulation.

[0095] Specifically, integrity includes power integrity (SI) and / or signal integrity (PI). Integrity simulation can include at least one of power integrity simulation and signal integrity simulation. Setting integrity conditions, corresponding to integrity simulation, refers to the requirements or conditions set for power integrity and / or signal integrity; these can be provided by the execution entity or input by the user.

[0096] In practical applications, an integrity emulator is called, that is, simulation software such as Cadence 3DIC is set to perform integrity simulation on the target architecture to obtain integrity parameters. Further, it is judged whether the integrity parameters meet the set integrity conditions. If they meet, it means that the target architecture is qualified and the integrated circuit design is successful. Then the target architecture is output for the user to fabricate an integrated circuit according to the target architecture.

[0097] The integrated circuit design method provided by the present invention selects at least one component according to the obtained application information, generates an initial architecture of the integrated circuit based on each of the components, and performs system-level architecture performance simulation on the initial architecture to obtain architecture performance parameters; when the architecture performance parameters meet the set performance conditions, according to the pin information of each of the components, determine the pin interconnection information between each of the components; based on the pin interconnection information and the set process constraints, perform pin wiring and layout on each of the components in the initial architecture to obtain the target architecture of the integrated circuit; perform integrity simulation on the target architecture to obtain integrity parameters, and when the integrity parameters meet the set integrity conditions, output the target architecture, and the target architecture is used to design the integrated circuit, and the integrity simulation includes signal integrity simulation and / or power integrity simulation. By integrating the architecture design technology and simulation tools of the integrated circuit, automatic generation from the coarse-grained architecture of the integrated circuit to the fine-grained pin interconnection is realized, solving the problems of high usage threshold of design tools and tool fragmentation; it can also simplify the architecture simulation process of the integrated circuit, improve the efficiency of architecture design simulation verification of the integrated circuit, shorten the hardware design cycle, and improve the efficiency of architecture optimization iteration. At the same time, it provides multi-level analysis data for the design iteration optimization of the integrated circuit.

[0098] In one or more optional embodiments of the present invention, the process of determining the pin interconnection information between each of the components according to the pin information of each of the components when the architecture performance parameters meet the set performance conditions may be specifically implemented as follows:

[0099] When the architecture performance parameters meet the set performance conditions, read the pin information of each of the components from the obtained component specifications;

[0100] Determine the pin port mapping according to the pin information;

[0101] Determine the pin interconnection information between each of the components according to the pin port mapping and the component interconnection relationship of each of the components in the initial architecture.

[0102] Specifically, component specifications refer to component instruction manuals and / or hardware specifications, used to describe each component. These specifications can be uploaded by the user or retrieved based on a user-triggered component specification retrieval command. Port mapping maps a port of one component to a port of another component, providing corresponding functions or services. Component interconnection refers to the connection relationships between components.

[0103] In practical applications, if the architecture performance parameters meet the set performance conditions, the pin information of each component is read according to the component specifications. Based on this pin information, the mapping and connection rules for the ports on the components are defined, i.e., pin-port mapping. Furthermore, based on the interconnection relationships and pin-port relationships of each component, the pin interconnection information between each component is determined. This improves the reliability and accuracy of the pin interconnection information, thereby improving the accuracy of integrated circuit design.

[0104] In one or more optional embodiments of the present invention, the specific implementation process of connecting and laying out the pins of each of the components in the initial architecture based on the pin interconnection information and setting process constraints to obtain the target architecture of the integrated circuit can be as follows:

[0105] Based on the pin interconnection information, the pins of each component in the initial architecture are connected to obtain the alternative architecture of the integrated circuit;

[0106] Based on the set process constraints, the components in the backup architecture are laid out to obtain the target architecture of the integrated circuit.

[0107] Specifically, a backup architecture refers to an integrated circuit in which multiple components are connected at the pin level but the layout has not been optimized.

[0108] In practical applications, after determining the pin interconnection information, the pins of each component in the initial architecture are connected according to this information to obtain a backup architecture for the integrated circuit. Then, based on the set process constraints, the arrangement of each component in the backup architecture is adjusted and optimized, i.e., placement is performed, to obtain the target architecture of the integrated circuit. Thus, first connecting the pins based on the pin interconnection information, and then placing them based on the set process constraints, can improve the efficiency of generating the target architecture, as well as the accuracy and aesthetics of the target architecture.

[0109] Optionally, during the layout process, the executing entity can invoke intelligent optimization algorithms based on set process constraints to automatically optimize the layout of each component in the backup architecture, thereby avoiding manual layout and improving layout efficiency.

[0110] Optionally, the step of laying out each of the components in the alternative architecture according to the set process constraints to obtain the target architecture of the integrated circuit includes:

[0111] The backup architecture is displayed via a display device to receive adjustment instructions from the user regarding the backup architecture;

[0112] Based on the adjustment instructions and the set process constraints, the components in the backup architecture are laid out to obtain the target architecture of the integrated circuit; or

[0113] According to the adjustment instructions and the set process constraints, the components in the backup architecture are laid out and the pin connections between the components are adjusted to obtain the target architecture of the integrated circuit.

[0114] Specifically, the display device can be a display window, a monitor, an interactive interface, and so on.

[0115] In practical applications, the backup architecture is displayed on a display device, allowing users to manually arrange the components within it. Correspondingly, the execution unit receives adjustment instructions and, based on these instructions and established process constraints, arranges the components accordingly. Alternatively, users can manually arrange the components in the backup architecture and adjust pin connections. Again, the execution unit receives adjustment instructions and, based on these instructions and established process constraints, arranges the components and adjusts the pin connections. This allows users to visually adjust the architecture according to their personal preferences, promoting human-computer interaction and increasing user satisfaction with the target architecture, making the process more user-friendly.

[0116] Furthermore, the initial and backup architectures can be displayed to the user in a hierarchical manner: for example, the initial architecture can be displayed on the display device, and when the user moves the mouse pointer over a component in the initial architecture, the backup architecture can be displayed for that component; or, the initial architecture can be displayed on the display device, and when the user adjusts the zoom level of the display interface to a set zoom value, the backup architecture can be displayed to the user, that is, the backup architecture is displayed after the display interface is enlarged. This enhances the efficiency of the display process.

[0117] Optionally, the step of laying out each of the components in the backup architecture according to the set process constraints to obtain the target architecture of the integrated circuit includes: displaying the initial architecture through a display device to receive the set process constraints.

[0118] In one or more optional embodiments of the present invention, the step of selecting at least one component based on the acquired application information and generating an initial architecture of the integrated circuit based on each component can be specifically implemented as follows:

[0119] The acquired application information is parsed;

[0120] Based on the analysis results and the set performance constraints, the simulation parameters are determined. The simulation parameters include the types of components, the number of components, and the interconnection information of the components in the design of the integrated circuit.

[0121] Select at least one component based on the type and quantity of the components;

[0122] Based on the interconnection information of the components, the components are connected to generate the initial architecture of the integrated circuit.

[0123] In practical applications, the architecture design algorithm is invoked to parse the application information to obtain the parsed structure. Then, based on the parsing results and performance constraints, the required components (component types), the number of each type of component (component quantity), and the connection between the components (component interconnection information) are determined, thus determining the simulation parameters.

[0124] Furthermore, based on the type and quantity of components, the required components are selected from a pre-defined component library. Then, according to the component interconnection information, all selected components are connected to obtain the initial architecture of the integrated circuit. This can improve the performance of the initial architecture to a certain extent, thereby improving the efficiency of integrated circuit design.

[0125] It should be noted that, given the initial architecture, to improve the efficiency of system-level architecture performance simulation, the initial architecture can be simulated based on its simulation parameters. That is, performing system-level architecture performance simulation on the initial architecture to obtain architecture performance parameters includes: performing system-level architecture performance simulation on the initial architecture based on the simulation parameters to obtain the architecture performance parameters. Thus, performing system-level architecture performance simulation based on simulation parameters eliminates the need to analyze the initial architecture during system-level architecture performance simulation to obtain the simulation parameters, thereby improving the efficiency of system-level architecture performance simulation and consequently improving the design efficiency of integrated circuits.

[0126] In one or more optional embodiments of the present invention, after performing system-level architectural performance simulation on the initial architecture to obtain architectural performance parameters, the method further includes:

[0127] If the architecture performance parameters do not meet the set performance conditions, the step of selecting at least one component and generating an initial architecture of the integrated circuit based on each component is performed according to the application information and the architecture performance parameters.

[0128] In practical applications, after obtaining the architecture performance parameters, it is determined whether these parameters meet the set performance conditions. If not, the initial architecture is unqualified and needs to be reconstructed. This involves selecting at least one new component, generating an initial architecture of integrated circuits based on these components, and iteratively optimizing it until an initial architecture whose performance parameters meet the set performance conditions is obtained. In this way, the initial architecture can be guaranteed to meet the set performance conditions during its formation, thus improving its performance.

[0129] In one or more optional embodiments of the present invention, the integrity simulation includes signal integrity simulation and power integrity simulation; the integrity parameters include signal integrity parameters and power integrity parameters; correspondingly, the specific implementation process of performing integrity simulation on the target architecture to obtain integrity parameters can be as follows:

[0130] Signal integrity simulation and power integrity simulation are performed on the target architecture to obtain the signal integrity parameters and the power integrity parameters.

[0131] Specifically, signal integrity refers to the quality of signals in a circuit system. Power integrity refers to verifying whether the voltage and current at the power source and destination meet the requirements.

[0132] In practical applications, to improve the reliability and rationality of integrated circuits, signal and power simulation software, such as Cadence 3DIC, can be used to simulate the signal integrity and power integrity of the target structure when performing integrity simulation of the target architecture.

[0133] In one or more optional embodiments of the present invention, after performing integrity simulation on the target architecture to obtain integrity parameters, the method further includes:

[0134] If the integrity parameters do not meet the set integrity conditions, the target architecture of the integrated circuit is reconstructed according to the integrity parameters.

[0135] In practical applications, if the simulation results do not meet the set integrity conditions, i.e., the integrity parameters do not meet the set integrity conditions, it means that the target architecture cannot meet the requirements of the designed integrated circuit. It is necessary to rebuild the target architecture that meets the requirements to ensure that the final target architecture meets the set integrity conditions in terms of integrity, thereby improving the reliability of the target architecture and improving the usability of the final designed integrated circuit.

[0136] Optionally, the integrity parameters include signal integrity parameters and power integrity parameters; correspondingly, the step of reconstructing the target architecture of the integrated circuit based on the integrity parameters when the integrity parameters do not meet the set integrity conditions can be implemented as follows:

[0137] If the power integrity parameters do not meet the set integrity conditions, the step of selecting at least one component and generating an initial architecture of the integrated circuit based on each component is performed according to the application information and the power integrity parameters.

[0138] If the power integrity parameter satisfies the set integrity condition, but the signal integrity parameter does not satisfy the set integrity condition, based on the signal integrity parameter, the pin interconnection information, and the set process constraints, the step of connecting and laying out the pins of each of the components in the initial architecture to obtain the target architecture of the integrated circuit is performed.

[0139] In practical applications, based on the simulation of power integrity and signal integrity, if the power integrity and signal integrity do not meet the set integrity conditions, design optimization is performed according to the performance type: if the power integrity parameters do not meet the set integrity conditions, it indicates that the target architecture design is unreasonable, and the on-chip architecture optimization algorithm is returned for iterative optimization, that is, the step of selecting at least one component and generating the initial architecture of the integrated circuit based on each component is returned; if the signal integrity parameters do not meet the set integrity conditions, it indicates that the layout design of the target architecture is unreasonable, and the layout optimization related to process constraints is returned, that is, the step of pin connection and layout of each component in the initial architecture is returned to obtain the target architecture of the integrated circuit.

[0140] In this way, by judging power integrity and signal integrity, different steps are executed according to the corresponding integrity type, avoiding the same steps for different integrity types. To a certain extent, this can reduce the design process and improve design efficiency.

[0141] Optionally, the integrity parameters include signal integrity parameters and power integrity parameters; correspondingly, the step of reconstructing the target architecture of the integrated circuit based on the integrity parameters when the integrity parameters do not meet the set integrity conditions includes: when the power integrity parameters and / or signal integrity do not meet the set integrity conditions, performing the step of selecting at least one component and generating an initial architecture of the integrated circuit based on each component according to the application information.

[0142] The following is combined Figure 2 The integrated circuit design method provided by the present invention will be further described below. Figure 2 This is a second flowchart illustrating the integrated circuit design method provided by the present invention, including:

[0143] Step 1: Enter the application source code.

[0144] Step 2: Call the architecture design optimization algorithm of the on-chip system, select components from the component library based on the application source code and performance constraints, and generate the initial architecture and simulation parameters of the on-chip system.

[0145] Step 3: Use a system-level simulator to evaluate the performance of the initial architecture, i.e., perform system-level architecture performance simulation to obtain architecture performance parameters. If the architecture performance parameters meet the requirements, i.e., performance conditions are set, the initial architecture's class schematic diagram is output; otherwise, return to Step 2 to continue iterative optimization. The system-level simulator also outputs a JSON file describing the class schematic diagram, and a script program automatically extracts the component types, component quantities, and component interconnection information into XML.

[0146] Step 4: Based on the hardware prefabrication manual or hardware specifications, i.e. component specifications, extract the component pin information, define port mapping rules and interconnection rules, automatically generate port mapping and pin interconnection information on the wafer substrate according to the mapping rules and interconnection rules, generate a backup architecture, and save it to an XML file.

[0147] Step 5: Parse the XML to obtain the design information of the alternative architecture. Display the target architecture through the software interface and receive input process constraints (set process constraints). Based on the design information and process constraints, perform a visual architecture layout. The layout and pin connections can be manually adjusted, or the layout can be automatically optimized using intelligent optimization algorithms. The optimization results are saved to an XML file.

[0148] Step 6: Convert the layout-optimized XML file into the file format required by the signal and power supply simulation software, and perform signal integrity simulation and power supply integrity simulation.

[0149] Step 7: If the power integrity parameters and signal integrity parameters meet the set integrity conditions, output the target architecture-like schematic diagram, complete the on-chip system architecture simulation process, and manufacture the integrated circuit based on the schematic diagram. If the power integrity parameters do not meet the set integrity conditions, it indicates that the target architecture design is unreasonable. Return to the on-chip architecture optimization algorithm for iterative optimization, i.e., return to the step of selecting each component to generate the initial architecture of the integrated circuit. If the signal integrity parameters do not meet the set integrity conditions, it indicates that the target architecture layout design is unreasonable. Return to the process constraint-related layout optimization, i.e., return to the step of pin connection and layout of each component in the initial architecture to obtain the target architecture of the integrated circuit.

[0150] The integrated circuit simulation system provided by the present invention is described below. The integrated circuit simulation system described below can be referred to in correspondence with the integrated circuit design method described above.

[0151] Figure 3 This is a schematic diagram of the integrated circuit simulation system provided by the present invention, as shown below. Figure 3 As shown, the integrated circuit simulation system 300 includes: an architecture design generation module 301, a system-level simulation module 302, a visualization layout module 303, and an integrity simulation module 304, wherein:

[0152] Architecture design generation module 301 is used to select at least one component based on the acquired application information and generate an initial architecture of the integrated circuit based on each component.

[0153] The system-level simulation module 302 is used to perform system-level architecture performance simulation on the initial architecture to obtain architecture performance parameters.

[0154] The visualization layout module 303 is used to determine the pin interconnection information between the components based on the pin information of each component when the architecture performance parameters meet the set performance conditions; and to perform pin connection and layout of each component in the initial architecture based on the pin interconnection information and set process constraints to obtain the target architecture of the integrated circuit.

[0155] The integrity simulation module 304 is used to perform integrity simulation on the target architecture, obtain integrity parameters, and output the target architecture when the integrity parameters meet the set integrity conditions. The target architecture is used to design the integrated circuit. The integrity simulation includes signal integrity simulation and / or power integrity simulation.

[0156] The integrated circuit simulation system provided by this invention selects at least one component based on acquired application information, generates an initial architecture of the integrated circuit based on each component, and performs system-level architecture performance simulation on the initial architecture to obtain architecture performance parameters. When the architecture performance parameters meet set performance conditions, the system determines the pin interconnection information between the components based on their pin information. Based on the pin interconnection information and set process constraints, the system performs pin wiring and layout for each component in the initial architecture to obtain the target architecture of the integrated circuit. The system performs integrity simulation on the target architecture to obtain integrity parameters, and outputs the target architecture when the integrity parameters meet set integrity conditions. The target architecture is used to design the integrated circuit. The integrity simulation includes signal integrity simulation and / or power integrity simulation. By integrating integrated circuit architecture design technology and simulation tools, an integrated circuit simulation system is formed, automatically generating information from coarse-grained integrated circuit architecture to fine-grained pin interconnections, solving the problems of high barriers to entry and fragmented tools. It also simplifies the integrated circuit architecture simulation process, improves the efficiency of integrated circuit architecture design simulation verification, shortens the hardware design cycle, and improves the efficiency of architecture optimization iteration. Simultaneously, it provides multi-level analysis data for integrated circuit design iteration optimization.

[0157] Optionally, the system-level simulation module 302 is further configured to:

[0158] If the architecture performance parameters meet the set performance conditions, generate the initial architecture's class schematic file;

[0159] Extract the component types, component quantities, and component interconnection information from the aforementioned schematic file to the first data exchange file;

[0160] The first data exchange file is passed to the visualization layout module.

[0161] Specifically, a class schematic file refers to a file that describes a class schematic, such as a class schematic or a JSON file containing a class schematic. A data exchange file refers to a standardized file used by an integrated circuit simulation system for interaction between modules, serving as an interface between different simulation tools and visualization layout tools, such as XML files or Word files.

[0162] In practical applications, when the system-level simulation module meets the set performance conditions for the architecture performance parameters, it outputs a schematic-like file, such as a JSON file describing the schematic-like structure. A script then converts this schematic-like file into a unified data exchange file: automatically parsing the schematic-like file and extracting the types, quantities, and interconnection information of prefabricated components into a first data exchange file, such as a first XML file. This first data exchange file is then passed to the visualization layout module. This improves the processing efficiency of the visualization layout module and facilitates interaction between different modules.

[0163] Optionally, the visualization layout module 303 is further configured to:

[0164] The received first data exchange file is parsed to obtain the initial architecture;

[0165] The initial architecture is displayed on a display device, and the user inputs process constraints based on the initial architecture.

[0166] In practical applications, the visualization layout module parses the first data exchange file transmitted by the system-level simulation module to obtain the initial architecture, which is then displayed to the user. This initial architecture is shown on a display device, and the user, based on it, outputs process constraints. The visualization layout module receives these process constraints. Thus, by displaying the initial architecture and receiving the process constraints, not only is human-computer interaction improved, but integrated circuit design can also be performed based on the user-input process constraints, thereby increasing user satisfaction.

[0167] Optionally, the visualization layout module 303 is further configured to:

[0168] Based on the pin interconnection information, the pins of each component in the initial architecture are connected to obtain the alternative architecture of the integrated circuit;

[0169] The initial architecture is displayed through a display device, and when a user triggers a magnification operation on a specified component in the initial architecture, the specified component in the alternative architecture is displayed through the display device.

[0170] Receive the user's adjustment instructions for the backup architecture;

[0171] Based on the adjustment instructions and the set process constraints, the components in the backup architecture are laid out to obtain the target architecture of the integrated circuit; or

[0172] According to the adjustment instructions and the set process constraints, the components in the backup architecture are laid out and the pin connections between the components are adjusted to obtain the target architecture of the integrated circuit.

[0173] In practical applications, the visualization layout module can connect the pins of each component in the initial architecture based on the pin interconnection information to obtain the backup architecture. Furthermore, the visualization layout module displays the initial architecture to the user, and when it detects that the user has triggered a zoom operation on a specific component in the initial architecture, it displays that specific component in the backup architecture. The specified component can be any single component. In addition, the initial and backup architectures can be displayed to the user in a hierarchical manner: for example, the initial architecture can be displayed first, and when the user moves the mouse pointer to a component in the initial architecture, the backup architecture is displayed for that component; or, the initial architecture can be displayed first, and when the user adjusts the zoom level of the display interface to a set zoom value, the backup architecture is displayed, essentially zooming in on the display interface to show the backup architecture.

[0174] Users can adjust the layout of specified components. Correspondingly, the visual layout module receives the user's adjustment instructions for the backup architecture, and then, based on the adjustment instructions and set process constraints, lays out each component in the backup architecture to obtain the target integrated circuit architecture. Alternatively, users can adjust the pin connections and layout of specified components. The visual layout module, based on the adjustment instructions and set process constraints, lays out each component in the backup architecture and adjusts the pin connections between them to obtain the target architecture. This allows for diverse layout adjustments, enabling both manual and automatic adjustments.

[0175] Optionally, the visualization layout module 303 is further configured to:

[0176] Based on the target architecture, generate a second data exchange file;

[0177] The second data exchange file is sent to the integrity simulation module.

[0178] In practical applications, after generating the target architecture, it is converted into a second data exchange file, which is then transmitted to the integrity simulation module for integrity simulation. This improves the speed of integrity simulation.

[0179] Optionally, the integrity simulation module 304 is further configured to:

[0180] The second data exchange file is converted to a new format to obtain the target simulation file specified by the simulation software.

[0181] The specified simulation software is invoked to perform integrity simulation on the target architecture based on the target simulation file, thereby obtaining integrity parameters.

[0182] In practical applications, the integrity simulation module, upon obtaining the second data exchange file, converts it to the specified file format according to the simulation software to obtain the target simulation file. This target simulation file is then input into the simulation software to perform integrity simulation on the target architecture, yielding integrity parameters. This ensures the smooth and efficient execution of the integrity simulation.

[0183] Optionally, the integrity parameters include signal integrity parameters and power integrity parameters; the integrity simulation module 304 is further configured to:

[0184] If the power integrity parameters do not meet the set integrity conditions, the power integrity parameters are sent to the architecture design generation module 301.

[0185] If the power integrity parameter meets the set integrity condition, but the signal integrity parameter does not meet the set integrity condition, the power integrity parameter is sent to the visualization layout module 303.

[0186] In practical applications, based on the simulation of power integrity and signal integrity, if the power integrity and signal integrity do not meet the set integrity conditions, design optimization is required according to the performance type: If the power integrity parameters do not meet the set integrity conditions, it indicates that the target architecture design is unreasonable. In this case, the integrity simulation module sends the power integrity parameters to the architecture design generation module. The architecture design generation module then selects at least one component based on the power integrity parameters and application information, and generates an initial architecture of the integrated circuit based on each component until a target architecture that meets the integrity conditions is obtained. If the signal integrity parameters do not meet the set integrity conditions, it indicates that the layout design of the target architecture is unreasonable. In this case, the integrity simulation module sends the power integrity parameters to the visualization layout module. The visualization layout module then re-connects and lays out the pins of each component in the initial architecture to obtain the target architecture of the integrated circuit.

[0187] In this way, by judging power integrity and signal integrity, different steps are executed according to the corresponding integrity type, avoiding the same steps for different integrity types. To a certain extent, this can reduce the design process and improve design efficiency.

[0188] The following is combined Figure 4 The integrated circuit design system provided by the present invention will be further described below. Figure 4 This is a schematic diagram of the processing flow of the integrated circuit design system provided by the present invention, including:

[0189] Architecture design generation module: Analyzes the input application source code using on-chip architecture design algorithm, automatically builds an architecture design adapted to the application in combination with performance constraints, obtains the initial architecture and simulation parameters of the initial architecture, and passes them to the system-level simulation module.

[0190] System-level simulation module: This module uses an open-source simulator to perform system-level simulations, simulating the performance of the generated initial architecture based on simulation parameters. Based on the performance metrics (architectural performance parameters) output by the simulation, iteratively optimizes and outputs a schematic diagram (containing only the types and quantities of components and their interconnections) of the initial architecture that meets the set performance conditions. The simulation platform uses a standardized data exchange file as an interface for different simulation tools and visualization layout tools. The schematic diagram of the initial architecture is converted into a first data exchange file (e.g., XML) and passed to the visualization layout module.

[0191] Visual Layout Module: After adding pin interconnection information to the first data exchange file, this module visualizes the layout of components on the wafer substrate. It automatically optimizes the layout using a layout optimization algorithm to meet set process constraints, resulting in the target architecture. The second data exchange file corresponding to the optimized target architecture is then passed to the integrity simulation module.

[0192] Integrity Simulation Module: After layout optimization, the target architecture design undergoes further power integrity and signal integrity simulations. Based on the simulation results (integrity parameters), if the integrity parameters meet the set integrity conditions, downstream design processes such as placement and routing, and schematic design can proceed according to the target architecture's schematic-like diagram. If the integrity parameters do not meet the set integrity conditions, the process returns to the architecture design generation module or the visual layout module to continue iteratively optimizing the design scheme.

[0193] Figure 5 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 5 As shown, the electronic device may include a processor 510, a communications interface 520, a memory 530, and a communication bus 540. The processor 510, communications interface 520, and memory 530 communicate with each other via the communication bus 540. The processor 510 can call logic instructions from the memory 530 to execute integrated circuit design methods.

[0194] Furthermore, the logical instructions in the aforementioned memory 530 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0195] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer is able to execute the integrated circuit design methods provided by the above methods.

[0196] In another aspect, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to perform the integrated circuit design methods provided by the methods described above.

[0197] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0198] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0199] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An integrated circuit design method, characterized by, include: Based on the obtained application information, at least one component is selected, and an initial architecture of an integrated circuit is generated based on each component. System-level architecture performance simulation is performed on the initial architecture to obtain architecture performance parameters. The integrated circuit is a system-on-a-chip. When the architecture performance parameters meet the set performance conditions, the pin interconnection information between the components is determined based on the pin information of each component. Based on the pin interconnection information and the set process constraints, the pin connections and layouts of each component in the initial architecture are performed to obtain the target architecture of the integrated circuit. Integrity simulation is performed on the target architecture to obtain integrity parameters. If the integrity parameters meet the set integrity conditions, the target architecture is output. The target architecture is used to design the integrated circuit. The integrity simulation includes signal integrity simulation and / or power integrity simulation. The step of selecting at least one component based on the acquired application information and generating an initial architecture of an integrated circuit based on each component includes: The architecture design algorithm is invoked to parse the acquired application information; Based on the analysis results and the set performance constraints, the simulation parameters are determined. The simulation parameters include the types of components, the number of components, and the interconnection information of the components in the design of the integrated circuit. Select at least one component based on the type and quantity of the components; Based on the interconnection information of the components, the components are connected to generate the initial architecture of the integrated circuit.

2. The integrated circuit design method of claim 1, wherein, When the architecture performance parameters meet the set performance conditions, determining the pin interconnection information between the components based on the pin information of each component includes: When the architecture performance parameters meet the set performance conditions, the pin information of each component is read from the acquired component specifications. Based on the pin information, determine the pin port mapping; Based on the pin port mapping and the component interconnection relationship of each component in the initial architecture, the pin interconnection information between each component is determined.

3. The integrated circuit design method of claim 1, wherein, The step of connecting and laying out the pins of each component in the initial architecture based on the pin interconnection information and setting process constraints to obtain the target architecture of the integrated circuit includes: Based on the pin interconnection information, the pins of each component in the initial architecture are connected to obtain the alternative architecture of the integrated circuit; Based on the set process constraints, the components in the backup architecture are laid out to obtain the target architecture of the integrated circuit.

4. The integrated circuit design method of claim 3, wherein, The step of laying out each of the components in the backup architecture according to the set process constraints to obtain the target architecture of the integrated circuit includes: The backup architecture is displayed via a display device to receive user instructions for adjusting the backup architecture; Based on the adjustment instructions and the set process constraints, the components in the backup architecture are laid out to obtain the target architecture of the integrated circuit; or According to the adjustment instructions and the set process constraints, the components in the backup architecture are laid out and the pin connections between the components are adjusted to obtain the target architecture of the integrated circuit.

5. The integrated circuit design method according to claim 1, characterized in that, The system-level architecture performance simulation of the initial architecture is performed to obtain architecture performance parameters, including: Based on the simulation parameters, a system-level architecture performance simulation is performed on the initial architecture to obtain the architecture performance parameters; After performing system-level architecture performance simulation on the initial architecture to obtain the architecture performance parameters, the process further includes: If the architecture performance parameters do not meet the set performance conditions, the step of selecting at least one component and generating an initial architecture of the integrated circuit based on each component is executed according to the application information and the architecture performance parameters. After performing integrity simulation on the target architecture to obtain integrity parameters, the process further includes: If the integrity parameters do not meet the set integrity conditions, the target architecture of the integrated circuit is reconstructed according to the integrity parameters.

6. The integrated circuit design method according to claim 5, characterized in that, The integrity parameters include signal integrity parameters and power integrity parameters; Accordingly, when the integrity parameters do not meet the set integrity conditions, reconstructing the target architecture of the integrated circuit based on the integrity parameters includes: If the power integrity parameters do not meet the set integrity conditions, the step of selecting at least one component and generating an initial architecture of the integrated circuit based on each component is performed according to the application information and the power integrity parameters. If the power integrity parameter satisfies the set integrity condition, but the signal integrity parameter does not satisfy the set integrity condition, based on the signal integrity parameter, the pin interconnection information, and the set process constraints, the step of connecting and laying out the pins of each of the components in the initial architecture to obtain the target architecture of the integrated circuit is performed.

7. An integrated circuit simulation system, characterized in that, include: An architecture design generation module is used to select at least one component based on the acquired application information, and generate an initial architecture of an integrated circuit based on each component, wherein the integrated circuit is a system-on-a-chip. The system-level simulation module is used to perform system-level architecture performance simulation on the initial architecture to obtain architecture performance parameters. A visualization layout module is used to determine the pin interconnection information between the components based on the pin information of each component when the architecture performance parameters meet the set performance conditions; and to perform pin connection and layout of each component in the initial architecture based on the pin interconnection information and set process constraints to obtain the target architecture of the integrated circuit. The integrity simulation module is used to perform integrity simulation on the target architecture, obtain integrity parameters, and output the target architecture when the integrity parameters meet the set integrity conditions. The target architecture is used to design the integrated circuit. The integrity simulation includes signal integrity simulation and / or power integrity simulation. The architecture design generation module is specifically used to call the architecture design algorithm to parse the obtained application information; determine the simulation parameters based on the parsing results and set performance constraints, the simulation parameters including the types, quantities, and interconnection information of the components used in designing the integrated circuit; select at least one component based on the types and quantities of the components; and connect the components according to the interconnection information to generate the initial architecture of the integrated circuit.

8. An integrated circuit simulation system according to claim 7, characterized in that, The system-level simulation module is also used for: If the architecture performance parameters meet the set performance conditions, generate the initial architecture's class schematic file; Extract the component types, component quantities, and component interconnection information from the aforementioned schematic file to the first data exchange file; The first data exchange file is passed to the visualization layout module; The visualization layout module is also used for: The received first data exchange file is parsed to obtain the initial architecture; The initial architecture is displayed on a display device, and the user inputs process constraints based on the initial architecture.

9. An integrated circuit simulation system according to claim 7, characterized in that, The visualization layout module is also used for: Based on the pin interconnection information, the pins of each component in the initial architecture are connected to obtain the alternative architecture of the integrated circuit; The initial architecture is displayed through a display device, and when a user triggers a magnification operation on a specified component in the initial architecture, the specified component in the alternative architecture is displayed through the display device. Receive the user's adjustment instructions for the backup architecture; Based on the adjustment instructions and the set process constraints, the components in the backup architecture are laid out to obtain the target architecture of the integrated circuit. or According to the adjustment instructions and the set process constraints, the components in the backup architecture are laid out and the pin connections between the components are adjusted to obtain the target architecture of the integrated circuit.

10. An integrated circuit simulation system according to claim 7, characterized in that, The visualization layout module is also used for: Based on the target architecture, generate a second data exchange file; The second data exchange file is sent to the integrity simulation module; The integrity simulation module is also used for: The second data exchange file is converted to a new format to obtain the target simulation file specified by the simulation software. The specified simulation software is invoked to perform integrity simulation on the target architecture based on the target simulation file, thereby obtaining integrity parameters, which include signal integrity parameters and power integrity parameters. The integrity simulation module is also used for: If the power integrity parameters do not meet the set integrity conditions, the power integrity parameters are sent to the architecture design generation module. If the power integrity parameter meets the set integrity condition, but the signal integrity parameter does not meet the set integrity condition, the power integrity parameter is sent to the visualization layout module.

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