Package structure and packaging method of package structure

Abstract

The embodiment of the present disclosure provides a packaging structure and a packaging method of the packaging structure. The packaging structure comprises: a substrate, the substrate has opposite first and second surfaces, and the first surface has a first pad; a laminated structure, located on the first surface, the laminated structure comprises a plurality of chips stacked and spaced apart in a direction away from the substrate, the chip has opposite third and fourth surfaces, the third surface faces away from the substrate, the third surface has a second pad, and the edge region of the chip has a notch, the notch extends from the plane where the third surface is to the chip; a protective film, the protective film is located in the notch; and a wire, one end of the wire is in contact with the second pad, the other end of the wire is in contact with the first pad, and the part of the wire adjacent to the chip is also in fixed contact with the protective film. The embodiment of the present disclosure at least has the advantages of reducing the possibility of leakage or short circuit of the packaging structure.

Description

Technical Field

[0001] This disclosure relates to the field of packaging, and in particular to a packaging structure and a packaging method for the packaging structure. Background Technology

[0002] As electronic devices become increasingly integrated, the semiconductor packaging field has developed technologies such as Package on Package (PoP) and Stacked Die Package. These packages involve overlapping multiple packages or bare chips in the height direction to reduce the package's footprint. Current chip stacking methods include wire bonding (WB), which uses fine metal wires and leverages heat, pressure, and ultrasonic energy to tightly bond the metal wires to chip pads and substrate pads, enabling electrical interconnection between the chip and substrate and information exchange between chips. However, as the number of stacked chips increases, and the total package thickness cannot increase proportionally, the space reserved for wire bonding is compressed, potentially leading to problems such as leakage or short circuits.

[0003] Therefore, there is an urgent need to improve semiconductor packaging technology. Summary of the Invention

[0004] This disclosure provides a packaging structure and a packaging method for the packaging structure, which at least helps to reduce the possibility of leakage or short circuit in the packaging structure.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a packaging structure, including: a substrate having opposing first and second surfaces, the first surface having a first pad; a stacked structure located on the first surface, the stacked structure including a plurality of chips stacked and spaced apart in a direction away from the substrate, the chips having opposing third and fourth surfaces, the third surface facing away from the substrate, the third surface having a second pad, the edge region of the chip having a notch extending from the plane of the third surface into the chip; a protective film located in the notch; and a conductive wire, one end of the conductive wire contacting the second pad, the other end of the conductive wire contacting the first pad, and the portion of the conductive wire adjacent to the chip also being in fixed contact with the protective film.

[0006] In some embodiments, the portion of the conductor adjacent to the chip is located within the protective film.

[0007] In some embodiments, the top surface of the protective film is not higher than the third surface.

[0008] In some embodiments, the protective film further covers the third surface, and the thickness of the protective film on the third surface is less than the thickness of the protective film in the notch.

[0009] In some embodiments, the inner wall surface of the notch is a beveled surface, or the inner wall surface of the notch is composed of a side surface connected to the third surface and a bottom surface connected to the side surface, wherein the angle between the side surface and the bottom surface is greater than or equal to 90°.

[0010] According to some embodiments of this disclosure, another aspect of this disclosure provides a packaging method for a packaging structure, comprising: providing a wafer, the wafer including a plurality of chip regions and a scribe line region located between adjacent chip regions, the scribe line region extending along a predetermined direction, the wafer having opposing third and fourth surfaces, the third surface having a second pad formed thereon; performing a first grooving along the scribe line region to form a first trench, the depth of the first trench being less than the thickness of the wafer, the sidewall of the first trench being connected to the third surface; performing a second grooving along the scribe line region to form a second trench communicating with the first trench, and dividing the wafer. The plurality of chip regions are multiple chips, and the edge regions of the chips have notches formed by the first trench and the second trench, the notches connecting to the third surface; a protective film is filled in the notches to form a wire, one end of the wire is fixed to the second pad, and the portion of the wire adjacent to the chip is in fixed contact with the protective film; a substrate is provided, the substrate having opposing first and second surfaces, the first surface having a first pad; the plurality of chips are stacked on the first surface, with the fourth surface of the chips facing the substrate, the plurality of chips are spaced apart and form a stacked structure; a wire bonding process is performed to fix the other end of the wire to the first pad.

[0011] In some embodiments, the step of filling the gap with the protective film and forming the conductor includes: first forming the conductor and fixing one end of the conductor to the second pad; and then forming the protective film after forming the conductor.

[0012] In some embodiments, the step of forming the protective film includes: forming an initial protective film before forming the second trench, the initial protective film filling the first trench and covering the wafer surface connected to the sidewall of the first trench; pre-curing the initial protective film; and in the step of forming the second trench, removing the initial protective film at the position directly opposite the second trench, and using the remaining initial protective film located within the notch as the protective film.

[0013] In some embodiments, prior to forming the initial protective film, the method further includes forming a protective layer that covers the second pad.

[0014] In some embodiments, during the wire bonding process, the protective film is further subjected to a re-curing treatment to ensure that the portion of the wire adjacent to the chip is located within the protective film and to improve the curing rate of the protective film.

[0015] The technical solutions provided in this disclosure have at least the following advantages:

[0016] The packaging structure provided in this embodiment has a notch in the edge region of the chip, and a protective film is filled in the notch. The protective film is in fixed contact with the part of the wire adjacent to the chip, which can reduce the possibility of the wire contacting the adjacent chip, thereby reducing the possibility of leakage or short circuit caused by the wire contacting the adjacent chip. In addition, the protective film can fix the direction of the wire, thereby improving the consistency of the position, shape and direction of each wire, thereby improving the overall impact resistance of the wire during the plastic encapsulation process, so as to resist the impact of the fluid plastic encapsulation material used in the plastic encapsulation process, and improve the reliability of the packaging structure. Attached Figure Description

[0017] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a packaging structure provided in an embodiment of the present disclosure;

[0019] Figure 2 This is a schematic diagram of another packaging structure provided in an embodiment of the present disclosure;

[0020] Figure 3 A schematic diagram of another packaging structure provided in an embodiment of this disclosure.

[0021] Figure 4 A flowchart corresponding to a packaging method for a packaging structure provided in another embodiment of this disclosure;

[0022] Figure 5 A top view of a wafer provided for another embodiment of this disclosure;

[0023] Figures 6 to 15 This is a schematic diagram of the steps of a packaging method for a packaging structure provided in another embodiment of the present disclosure. Detailed Implementation

[0024] As can be seen from the background technology, the current packaging technology for semiconductor structures needs to be improved.

[0025] This disclosure provides a packaging structure in which a notch is provided in the edge region of the chip, the notch is filled with protective adhesive, one end of a wire is fixedly contacted with a second pad on the chip, and the other end of the wire is fixedly contacted with a first pad on the substrate, so as to realize electrical connection and information communication between the chip and the substrate through the wire. The protective film is fixedly contacted with the portion of the wire adjacent to the chip, which can reduce the possibility of the wire contacting the adjacent chip, thereby reducing the possibility of leakage or short circuit caused by the wire contacting the adjacent chip. The protective film can also fix the direction of the wire, thereby improving the consistency of the position, shape and direction of each wire, thereby improving the overall impact resistance of the wire during the plastic encapsulation process, so as to resist the impact of the fluid plastic encapsulation material used in the plastic encapsulation process, and improve the reliability of the packaging structure.

[0026] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0027] Figure 1 This is a schematic diagram of a packaging structure provided in one embodiment of the present disclosure. Figure 2 This is a schematic diagram of another packaging structure provided in an embodiment of the present disclosure. Figure 3 This is a schematic diagram of another packaging structure provided in an embodiment of the present disclosure.

[0028] refer to Figure 1The packaging structure includes: a substrate 100 having opposing first surfaces 10 and second surfaces 20, with a first pad 101 on the first surface 10; a stacked structure located on the first surface 10, the stacked structure including a plurality of chips 102 stacked and spaced apart in a direction away from the substrate 100, the chips 102 having opposing third surfaces 30 and fourth surfaces 40, the third surface 30 being away from the substrate 100, the third surface 30 having a second pad 103, the edge region of the chip 102 having a notch 104 extending from the plane of the third surface 30 into the chip 102; a protective film 105 located in the notch 104; and a conductive wire 106, one end of the conductive wire 106 contacting the second pad 103, the other end of the conductive wire 106 contacting the first pad 101, and the portion of the conductive wire 106 adjacent to the chip 102 also in fixed contact with the protective film 105.

[0029] By fixing the protective film 105 to the portion of the wire 106 adjacent to the chip 102, the possibility of the wire 106 contacting the adjacent chip 102 can be reduced, thereby reducing leakage or short circuit problems caused by the contact between the wire 106 and the adjacent chip 102. In addition, the protective film 105 can fix the direction of the wire 106, thereby improving the consistency of the position, shape and direction of each wire 106, thereby improving the overall impact resistance of the wire 106 when the packaging structure is plastic encapsulated, so as to resist the impact of the fluid plastic encapsulation material used in the plastic encapsulation process, and improve the reliability of the packaging structure.

[0030] The substrate 100 may be a printed circuit board (PCB), which may be a rigid PCB or a flexible PCB. The material of the substrate 100 may include one or more combinations of bismaleimide triazine (BT) resin, FR-4 (a composite material composed of fiberglass woven fabric and flame-retardant epoxy resin adhesive), ceramic, glass, plastic, tape, film, or other support materials. In some embodiments, the surface area of ​​the substrate 100 is larger than the surface area of ​​other components in the package structure. Therefore, the overall size of the package structure depends on the size of the substrate 100, with the length of the package structure being greater than or equal to the length of the substrate 100, and the width of the package structure being greater than or equal to the width of the substrate 100.

[0031] The material of the first pad 101 can be tungsten (W), cobalt (Co), copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), nickel, silicides (e.g., WSix, CoSix, NiSix, AlSix, etc.), metal alloys, or any combination thereof. The first pad 101 is located outside the orthogonal projection of the chip 102 onto the substrate 100.

[0032] Chip 102 can be a logic chip. For example, a logic chip can be a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip. In some embodiments, chip 102 can also be a memory chip, including volatile memory semiconductor chips, which can be dynamic random access memory (DRAM) or static random access memory (SRAM), and non-volatile memory semiconductor chips can be phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), or resistive random access memory (RRAM). In some embodiments, chip 102 can also be flash memory, such as NAND (Not AND) flash memory. The stacked structure includes multiple chips 102, which can all be logic chips, memory chips, or flash memory chips. Alternatively, some of the chips can be logic chips and some can be memory chips.

[0033] Chip 102 may include a substrate (not shown) and a functional layer (not shown) located on the substrate. The functional layer may be composed of alternating conductive and dielectric layers. The top surface of the functional layer is the third surface 30 of chip 103. The functional layer is used to form a semiconductor element. In some embodiments, along the thickness direction of chip 102, the maximum height of notch 104 (the maximum height of notch 104 is the distance between the point in notch 104 furthest from the third surface 30 of the chip where the notch is located and the third surface 30) may not be greater than the thickness of the functional layer. This facilitates the setting of a chip seal ring, which may be set above the notch, thereby protecting the chip area and reducing the overall stress of the chip. Along the thickness direction of chip 102, the maximum height of notch 104 may not be greater than 10 μm. For example, the height may be 10 μm, 9.7 μm, 8.3 μm, 7.1 μm, or 5.2 μm. The material of the second pad 103 can be tungsten, cobalt, copper, titanium, tantalum, aluminum, titanium nitride, tantalum nitride, nickel, silicide, metal alloy or any combination thereof.

[0034] The orthographic projection of chip 102 onto substrate 100 can be a polygon. For example, the orthographic projection of chip 102 onto substrate 100 can be, but is not limited to, a quadrilateral, a pentagon, or a hexagon. Alternatively, the orthographic projection of chip 102 onto substrate 100 can also be a circle or an ellipse, etc. Taking the orthographic projection of chip 102 on substrate 100 as a rectangle as an example, chip 102 may include a first side, a second side, a third side, and a fourth side connected in sequence, and notch 104 may be provided near at least one side of chip 102; for example, notch 102 may be provided near one side, two sides, three sides, or four sides, wherein notch 102 may extend from the chip edge region where one side is located to the chip edge region where the adjacent side is located, and the protective film 105 in notch 102 may also extend from the chip edge region where one side is located to the chip edge region where the adjacent side is located, or there may be multiple notches 102, and each chip edge region where each side is located has at least one notch 102, and each edge region where each side is located has at least one protective film 105; for another example, notch 104 may also be provided around the circumference of chip 102, and the protective film 105 in notch 104 may also be provided around the circumference of chip 102.

[0035] refer to Figure 3 In some embodiments, the inner wall surface of the notch 104 can be a beveled surface. (See reference...) Figure 1 and Figure 2 In some embodiments, the inner wall surface of the notch 104 may be composed of a side surface connected to the third surface 30 and a bottom surface connected to the side surface, wherein the angle between the side surface and the bottom surface may be greater than or equal to 90°. In some embodiments, the inner wall surface of the notch 104 may also be composed of a side surface connected to the third surface 30, a bottom surface connected to the side surface, and another side surface connected to the bottom surface. The embodiments disclosed herein do not constitute a limitation on the shape of the notch 104.

[0036] The protective film 105 is made of an insulating material to isolate the wire 106 and the edge region of the chip 102 bonded to the wire 106. In some embodiments, the material of the protective film 105 can be a UV-curable material or a thermosetting material. UV-curable or thermosetting materials have better insulation properties and can isolate the wire 106 and the edge region of the chip 102 bonded to the wire 106. For example, the material of the protective film 105 can be PI (polyimide), PDMS (polydimethylsiloxane), phenolic resin, urea-formaldehyde resin, melamine resin, unsaturated polyester resin, epoxy resin, silicone resin, or polyurethane. Furthermore, the method for forming a protective film 105 made of UV-curable material or thermosetting material includes: filling the gap 104 with the protective film 105, pre-curing the protective film 105 so that the protective film 105 has a certain adhesiveness and can adhere to the wire 106, thereby fixing the direction of the wire 106, and reducing the flow properties of the protective film 105 through pre-curing so that the protective film 105 can be fixed in the gap 104.

[0037] The side surface of the protective film 105 may be flush with the side surface of the chip 102. In some embodiments, the top surface of the protective film 105 may not be higher than the third surface 30 to avoid excessive thickness of the protective film 105, which would increase the height between chips 102. In some embodiments, the top surface of the protective film 105 may also be higher than the third surface 30, and the thickness of the portion of the protective film 105 above the third surface 30 may provide better protection, adhesion, or fixation of metal leads, or even support for the chip 102 above it.

[0038] In some embodiments, the ratio of the thickness of the protective film 105 in the notch 104 to the thickness of the chip 102 can be 1 / 2 to 2 / 3, for example, the ratio can be 0.5, 0.52, 0.63 or 0.66. Within this thickness ratio range, the thickness of the protective film 105 can be avoided from being too small, so as to avoid poor isolation effect of the protective film 105; and the thickness of the protective film 105 can be avoided from being too large, so as to avoid the protective film 105 compressing the space of the wire 106, thereby avoiding contact between the wire 106 and the chip 102 above the wire 106, and reducing the impact of the protective film 105 on the volume of the packaging structure.

[0039] refer to Figure 2In some embodiments, the protective film 105 may also cover the third surface 30, and the thickness of the protective film 105 on the third surface 30 is less than the thickness of the protective film 105 in the notch 104. That is, during the formation of the protective film 105, the protective film 105 can fill the notch 104 and cover the surface of the third surface 30 to ensure that the notch 104 is filled by the protective film 105. Thus, after the pre-cured protective film 105, the thickness of the protective film 105 in the notch 104 will not be too small, so as to avoid poor isolation effect due to the thinness of the protective film 105 in the notch 104. This ensures the isolation effect of the protective film 105 and the good contact performance between the protective film 105 and the wire 106. The protective film 105 on the third surface 30 can also be used to adhere adjacent chips 102.

[0040] In some embodiments, a protective film 105 may be provided corresponding to at least one wire 106, that is, at least one wire 106 may span over the protective film 105 in a notch 104, and the protective film 105 may isolate at least one wire 102 spanning over the protective film 105.

[0041] In some embodiments, the portion of the wire 106 adjacent to the chip 102 may be located within the protective film 105 in the notch to enhance the strength of the contact between the protective film 105 and the wire 106. Specifically, one end of the wire 106 may be bonded to the second pad 103 first, and then the protective film 105 may be formed in the notch 104, with the portion of the wire 106 adjacent to the chip 102 disposed within the protective film 105 along a predetermined path of the wire 106. In some embodiments, the portion of the wire 106 adjacent to the chip 102 may also contact the surface of the protective film 105 in the notch 105 away from the third surface 30.

[0042] In the direction perpendicular to the third surface 30, the distance between the highest point of the conductor 106 and the third surface 30 of the adjacent conductor 106 can be 10um to 100um. That is, in the direction perpendicular to the third surface 30, the distance between the highest point of the conductor 106 and the third surface 30 to which the conductor 106 is bonded can be 10um to 100um. For example, the distance can be 10um, 20um, 47um, 65um, 84um or 100um. The distance between the highest point of the conductor 106 and the third surface 30 of the adjacent conductor 106 can be adjusted by adjusting the thickness of the protective film 105. Within this distance range, the possibility of the conductor 106 contacting the adjacent third surface 30 and fourth surface 40 is reduced.

[0043] The wire 106 is formed of a conductive material, such as tungsten, copper, aluminum, silver, gold, or other metals. Wire bonding can be used to bond the wire 106 to the chip 102 and the substrate 100.

[0044] refer to Figure 1 In some embodiments, the packaging structure may further include an adhesive layer 107, which is disposed between adjacent chips 102 and between the substrate 100 and the chip 102 of the adjacent substrate 100, for adhering to adjacent chips 102 and the chip 102 of the substrate 100 and the adjacent substrate 100. The adhesive layer can prevent collisions or wear between adjacent chips 101 or chips 102 and the substrate 100, thereby protecting the chips.

[0045] In some embodiments, a protective film 105 is coated on the third surface 30 of the chip and the first surface 10 of the substrate 100, and an adhesive layer 107 is located between the protective film 105 and the fourth surface 40 and between the substrate 100 and the chip 102 adjacent to the substrate 100.

[0046] refer to Figure 2 In some embodiments, the adjacent chip 102 can be directly adhered with the protective film 105, and an adhesive layer 107 is provided between the substrate 100 and the chip 102 adjacent to the substrate 100 to protect the chip 102.

[0047] The encapsulation structure may also include a molding compound (not shown), which is located on the substrate and encapsulates the stacked structure and the wires 106. The material of the molding compound may include resin (e.g., epoxy molding compound) or silicon dioxide. The step of molding the entire encapsulation structure with a molding compound includes: injecting molten molding compound into the encapsulation structure; heating the molding compound to harden it and form the molding compound. Because the protective film 105 can fix the routing of the wires 106, ensuring the consistency of routing, position, and shape among the wires 106, the overall impact resistance of the wires during the molding process of the encapsulation structure is improved, resisting the impact of the molten molding compound and improving the reliability of the encapsulation structure.

[0048] The packaging structure provided in the above-disclosed embodiments, by filling the gap 104 in the edge region of the chip 102 with a protective film 105, and fixing the protective film 105 in contact with the portion of the wire 106 adjacent to the chip 102, can reduce the possibility of the wire 106 contacting the adjacent chip 102, thereby avoiding leakage or short circuit problems caused by the contact between the wire and the adjacent chip. In addition, the protective film 105 can fix the direction of the wire 106, thereby improving the consistency of the position, shape and direction of each wire 106, thereby improving the overall impact resistance of the wire 106 when the packaging structure is plastic encapsulated, so as to resist the impact of the plastic encapsulation material after melting during the plastic encapsulation process, and improve the reliability of the packaging structure.

[0049] Accordingly, another embodiment of this disclosure also provides a packaging method for a packaging structure. The packaging method for the packaging structure provided in this other embodiment can be used to manufacture the packaging structure provided in the foregoing embodiment. The packaging method for the packaging structure provided in this other embodiment will be described in detail below with reference to the accompanying drawings. For parts that are the same as or corresponding to the previous embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be described in detail below. Figure 4 A flowchart corresponding to a packaging method for a packaging structure provided in another embodiment of this disclosure is shown. Figure 5 This is a top view of a wafer provided in another embodiment of the present disclosure. Figures 6 to 15 This is a schematic diagram of the structure corresponding to each step of a packaging method for a packaging structure provided in another embodiment of this disclosure, wherein, Figures 6 to 15 For along Figure 5 A sectional view of section AA1.

[0050] refer to Figures 4 to 6 In step S100, a wafer 200 is provided. The wafer 200 includes a plurality of chip regions 201 and a scribe line region 202 located between adjacent chip regions 201. The scribe line region 202 extends along a preset direction. The wafer has a third surface 30 and a fourth surface 40. A second pad 103 is formed on the third surface.

[0051] Chip region 201 is used to form a chip. The chip can be a logic chip. For example, a logic chip can be a central processing unit chip, a graphics processing unit chip, or an application processor chip. In some embodiments, the chip can also be a memory chip, including a volatile memory semiconductor chip, which can be dynamic random access memory or static random access memory, and a non-volatile memory semiconductor chip can be phase-change random access memory, magnetoresistive random access memory, ferroelectric random access memory, or resistive random access memory. In some embodiments, the chip can also be flash memory, such as NAND flash memory. The chip region has opposing third surfaces 30 and fourth surfaces 40. A second pad 103 is provided on the third surface 30. Chip region 201 can include a substrate (not shown) and a functional layer (not shown) located on the substrate. The functional layer can be composed of alternating conductive layers and dielectric layers. The top surface of the functional layer is the third surface 30, and the bottom surface of the substrate away from the functional layer is the fourth surface 40. The functional layer is used to form a semiconductor element. The material of the second pad 103 can be tungsten, cobalt, copper, titanium, tantalum, aluminum, titanium nitride, tantalum nitride, nickel, silicide, metal alloy or any combination thereof.

[0052] The scribe line region 202 can be arranged around the chip region 201, and subsequent steps can divide the wafer 200 into multiple chips along the scribe line region 202. In some embodiments, electronic components can be provided on the scribe line region 202, such as test structures, protection structures, etc.

[0053] refer to Figure 4 and Figure 7 In step S101, the wafer 200 is first grooved along the dicing area 202 to form a first trench 203. The depth of the first trench 203 is less than the thickness of the wafer 200, and the sidewall of the first trench 203 is connected to the third surface 30.

[0054] The width of the first trench 203 may not exceed the width of the scribe line region 202 between adjacent chip regions 201. The sidewall of the first trench 203 is connected to the top surface of the functional layer of the chip region 201. In the first grooving step, the trench is grouted from the top surface of the chip region 201 toward the substrate. The maximum depth of the first trench 203 may not exceed the thickness of the functional layer, which is beneficial for the subsequent setting of the chip seal ring. The seal ring can be subsequently set above the notch filled with the protective film, while protecting the chip region and reducing the overall stress of the chip. Along the thickness direction of the chip region 201, the maximum height of the first trench 203 may not exceed 10µm, for example, the height may be 10µm, 9.7µm, 8.3µm, 7.1µm, or 5.2µm. The process used for the first grooving may be mechanical wafer dicing, laser dicing, or etching.

[0055] In some embodiments, the first trench 203 may be disposed around the chip region 201, and the subsequently formed notches may also be disposed around the chip region 201. In some embodiments, the surface of the chip region 201 perpendicular to the thickness direction of the wafer 200 may include, but is not limited to, quadrilaterals, pentagons, hexagons, circles, or ellipses; taking a rectangular surface of the chip region 201 perpendicular to the thickness direction of the wafer 200 as an example, the chip region may include a first side, a second side, a third side, and a fourth side connected in sequence, and the first trench 203 may be disposed near at least one side of the chip region; for example, the first trench 203 may be disposed near one, two, three, or four sides, wherein the first trench 203 may be disposed around two adjacent sides, or at least one first trench 203 may be disposed on each side. The position of the first trench 203 is related to the position of the subsequently formed wires, and the embodiments disclosed herein do not constitute a limitation on the position of the first trench 203.

[0056] Along the thickness direction of wafer 200, the cross-sectional shape of the first trench 203 can be triangular, rectangular or trapezoidal.

[0057] refer to Figure 4 , Figures 12 to 13In step S102, the wafer 200 is grooved a second time along the dicing area 202 to form a second trench 204 that is connected to the first trench 203, and the wafer 200 is divided into multiple chip areas 201 into multiple chips 102. The edge area of ​​the chip 102 has a notch 104 formed by the first trench 203 and the second trench 204, and the notch 104 connects to the third surface 30.

[0058] The second grooving process can be mechanical wafer dicing, laser dicing, or etching. After the second grooving, the chip region 201 of wafer 200 is divided into multiple chips 102. The third surface 30 of wafer 200 serves as the third surface of chip 102, and the fourth surface 40 of wafer 200 serves as the fourth surface of chip 102. The functional layer and substrate of each chip region 201 constitute the functional layer and substrate of the corresponding chip 102. The third surface 30 is the top surface of the functional layer, and the fourth surface 40 is the bottom surface of the substrate away from the functional layer.

[0059] Along the thickness direction of wafer 200, the cross-sectional shape of the second trench 203 can be triangular, rectangular, or trapezoidal. The shape of the formed notch 104 is related to the shapes of the first trench 203 and the second trench 204. In some embodiments, the inner wall surface of the notch 104 can be a beveled surface. In some embodiments, the inner wall surface of the correspondingly formed notch 104 can be composed of a side surface connected to the third surface 30 and a bottom surface connected to the side surface, and the angle between the side surface and the bottom surface can be greater than or equal to 90°.

[0060] Subsequent steps include filling the gap with a protective film and forming a conductive line, one end of which is fixed to the second pad 103; Reference Figures 8 to 9 Before forming the second trench 204, an initial protective film 205 can be formed. This initial protective film fills the first trench 203 and covers the wafer surface connected to the sidewalls of the first trench 203, i.e., the third surface 30 of the chip 102. By forming the initial protective film 205 on the third surface 30, damage to the wafer caused by the second trenching is reduced. The initial protective film 205 undergoes a pre-curing treatment to reduce its flow properties, improve the adhesion between the initial protective film 205 and the first trench, and give the initial protective film 205 a certain degree of adhesion. The protective film made from the initial protective film 205 has a certain degree of adhesion and can adhere to the wires. After the initial protective film is pre-cured, the surface part of the initial protective film is cured, while the internal curing degree of the initial protective film is lower, and it has a certain shape retention strength, which facilitates the wires to enter the colloid. In the step of forming the second trench 204, the initial protective film 205 at the position directly opposite the second trench 204 is removed, and the remaining initial protective film 205 located in the notch serves as a protective film. The initial protective film 205 located on the surface of the wafer 200 can be used to adhere the chips in the adjacent layers in the subsequent step of forming the stacked structure.

[0061] The initial protective film 205 can be made of a UV-curable or thermosetting material. UV-curable or thermosetting materials have good insulation properties and can isolate the subsequently formed wires from the edge areas of the chip to which they are bonded. For example, the initial protective film 205 can be made of PI material, PDMS, phenolic resin, urea-formaldehyde resin, melamine resin, unsaturated polyester resin, epoxy resin, silicone resin, or polyurethane.

[0062] In the step of forming the initial protective film 205, the initial protective film 205 on the third surface 30 covers the second pad 103. Before forming the initial protective film 205, the process may further include: forming a protective layer (not shown) that covers the second pad 103 to prevent the second pad 103 from being adhered to by the initial protective film 205. In the subsequent step of forming the conductive lines, the protective layer and the initial protective film on the second pad 103 need to be etched away to expose the second pad 103, facilitating bonding between the conductive lines and the second pad in subsequent steps. After the conductive lines are bonded to the second pad, a protective film material can be filled into the bonding area between the conductive lines and the second pad to protect the bonding between the conductive lines and the second pad. The material of the protective layer can be at least one of silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, in the step of forming the initial protective film 205, the top surface of the initial protective film 205 on the third surface 30 is lower than the top surface of the second pad, facilitating bonding between the conductive lines and the second pad in subsequent steps.

[0063] In some embodiments, the initial protective film 205 may only fill the first trench 204; wherein, since the volume of the initial protective film 205 will shrink after the initial protective film 205 is pre-cured, the thickness of the initial protective film 205 along the thickness direction of the wafer 200 can be set to be greater than or equal to the depth of the first trench 204, so as to avoid the initial protective film 205 after pre-curing being too thin to adhere to the wire.

[0064] refer to Figure 4 , Figure 10 and Figure 14 In step S103, a protective film 105 is filled into the notch 104 to form a wire 106. One end of the wire 106 is fixed to the second pad 103, and the portion of the wire 106 adjacent to the chip 102 is in fixed contact with the protective film 105.

[0065] In this process, one end of the wire 106 is fixed to the second pad 103 using a wire bonding process. The material of the wire 106 can be metals such as tungsten, copper, aluminum, silver, or gold. The step of forming the protective film 105 may include: forming the protective film 105 and pre-curing the protective film 105 to reduce the flow properties of the protective film 105, improve the firmness of the contact between the protective film 105 and the notch, and give the protective film 105 a certain degree of adhesion so that the protective film 105 can adhere to the wire. After pre-curing the protective film, the surface part of the protective film is cured, while the interior of the protective film has a lower degree of curing and a certain degree of conformal strength, which facilitates the adjustment of the wire routing so that the part of the wire adjacent to the chip can be located within the protective film. The curing rate of the protective film can be adjusted by adjusting the pre-curing time. The curing rate of the pre-cured protective film 105 can be 50% to 70%, for example, 50%, 54.5%, 61%, 66% or 70%. Within this range, the pre-cured protective film 105 can be guaranteed to have a certain degree of adhesion, and the protective film 105 and the notch 104 can be in good contact.

[0066] The protective film 105 can be made of a UV-curable material or a thermosetting material. UV-curable or thermosetting materials have good insulation properties and can isolate the edge area of ​​the chip to which the subsequently formed wires are bonded. For example, the material of the protective film 105 can be PI material, PDMS, phenolic resin, urea-formaldehyde resin, melamine resin, unsaturated polyester resin, epoxy resin, silicone resin, or polyurethane.

[0067] In some embodiments, the step of filling the notch 104 with a protective film 105 and forming a conductive line 106 may include: first forming the conductive line 106 and fixing one end of the conductive line 106 to the second pad 103; after forming the conductive line 106, forming a protective film 105, so that in the step of forming the protective film 105, along the predetermined direction of the conductive line 106, the portion of the conductive line 106 adjacent to the chip 102 is disposed within the protective film 105, so as to enhance the firmness of the contact between the protective film 105 and the conductive line 106.

[0068] In some embodiments, a protective film 105 may be formed first; after the protective film 105 is formed, a wire 106 is formed, and one end of the wire 106 is fixed to the second pad 103.

[0069] refer to Figure 4 , Figure 11 and Figure 15 In step S104, a substrate 100 is provided, the substrate 100 having a first surface 10 and a second surface 20 opposite to each other, and a first pad 101 is provided on the first surface 10.

[0070] The substrate 100 may be a printed circuit board (PCB), which may be a rigid PCB or a flexible PCB. The material of the substrate 100 may include one or more combinations of bismaleimide triazine (BT) resin, FR-4 (a composite material composed of fiberglass woven fabric and flame-retardant epoxy resin adhesive), ceramic, glass, plastic, tape, film, or other support materials. In some embodiments, the surface area of ​​the substrate 100 is larger than the surface area of ​​other components in the package structure. Therefore, the overall size of the package structure depends on the size of the substrate 100, with the length of the package structure being greater than or equal to the length of the substrate 100, and the width of the package structure being greater than or equal to the width of the substrate 100.

[0071] The material of the first pad 101 can be tungsten, cobalt, copper, titanium, tantalum, aluminum, titanium nitride, tantalum nitride, nickel, silicide, metal alloy or any combination thereof.

[0072] refer to Figure 4 , Figure 11 and Figure 15 In step S105, multiple chips 102 are stacked on the first surface 10, with the fourth surface 40 of the chips 102 facing the substrate 100. The multiple chips 102 are spaced apart and form a stacked structure.

[0073] In this embodiment, adjacent chips 102 can be bonded together by an adhesive layer 107, which is also located between the substrate 100 and the chips adjacent to the substrate 100 to adhere the substrate 100 and the chips 102, preventing collisions or wear between adjacent chips 101 or 102 and the substrate 100, thereby protecting the chips. In some embodiments, the aforementioned steps also include providing a protective film 105 on the third surface 30. Adhesive layers 107 may not be provided between adjacent chips 102; instead, the protective film 105 on the third surface can be used to adhere the adjacent chips 102. The protective film 105 is also applied to the substrate 100 and the chips 102 adjacent to the substrate 100 to protect the chips 102.

[0074] refer to Figure 4 , Figure 11 and Figure 15 In step S106, a wire bonding process is performed to fix the other end of the wire 106 onto the first pad 101.

[0075] During the wire bonding process, the temperature provided by the wire bonding process can also be used to re-cur the protective film 105, so that the portion of the wire 106 adjacent to the chip 102 is located within the protective film 105 and the curing rate of the protective film 105 is improved.

[0076] In some embodiments, the aforementioned steps may first form a protective film 105, and after forming the protective film 105, form a conductor 106 and fix one end of the conductor 106 to the second pad 103; wherein, the step of fixing one end of the conductor 106 to the second pad 103 can be performed simultaneously with fixing the other end of the conductor 106 to the first pad 101, which is beneficial to reduce process complexity and process cost.

[0077] Subsequent steps may include forming a molding compound (not shown), which is located on the substrate and encapsulates the stacked structure and the wires 106. Specific steps for molding the entire package structure using a molding compound may include: injecting molten molding material into the package structure; heating the molding compound material to harden and form the molding compound. Since the protective film 105 can fix the routing of the wires 106, ensuring consistency in routing, position, and shape among the wires 106, the overall impact resistance of the wires during the molding process of the package structure is improved, resisting the impact from the molten molding material and improving the reliability of the formed package structure. The material of the molding compound may include resin (e.g., epoxy molding compound) or silicon dioxide.

[0078] The packaging method of the above-disclosed embodiment can form a conductive line 106 before forming the protective film 105 within the notch 104, and fix one end of the conductive line 106 to the second pad 103. In the step of forming the protective film 105, along the predetermined direction of the conductive line 106, the portion of the conductive line 106 adjacent to the chip 102 is disposed within the protective film 105, thereby strengthening the contact between the protective film 105 and the conductive line 106. Furthermore, in the step of fixing the other end of the conductive line 106 to the first pad 101, the protective film 105 can be further cured, strengthening the connection between the protective film 105 and the conductive line 102. The contact strength between 06; or, after forming the protective film 105, the wire 106 can be formed, and in the same wire bonding process step, one end of the wire 106 can be fixed to the second pad 103, and the other end of the wire 106 can be fixed to the first pad 101. The wire 106 is in contact with the protective film 106, which helps to reduce process complexity and process cost. In addition, in the step of fixing both ends of the wire 106 to the first pad 101 and the second pad 103 using the wire bonding process, the protective film 105 can be further solidified, strengthening the contact strength between the protective film 105 and the wire 106. The packaging method of the packaging structure provided in this embodiment of the present disclosure, by fixing the wire 106 with the protective film 105, can reduce the possibility of the wire 106 contacting the adjacent chip 102, thereby avoiding leakage or short circuit problems caused by the wire contacting the adjacent chip.

[0079] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make various alterations and modifications without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A packaging method for a packaging structure, characterized in that, include: A wafer is provided, the wafer including a plurality of chip regions and a scribe line region located between adjacent chip regions, the scribe line region extending along a predetermined direction, the wafer having opposing third and fourth surfaces, and a second pad formed on the third surface; The wafer is first slotted along the dicing area to form a first trench, the depth of which is less than the thickness of the wafer, and the sidewall of the first trench is connected to the third surface. The wafer is slotted a second time along the dicing area to form a second trench that communicates with the first trench, and the wafer is divided into multiple chip areas into multiple chips. The edge area of ​​the chip has a notch formed by the first trench and the second trench, and the notch connects to the third surface. A protective film is filled into the gap to form a conductive line, one end of which is fixed to the second pad, and the portion of the conductive line adjacent to the chip is in fixed contact with the protective film. A substrate is provided, the substrate having opposing first and second surfaces, the first surface having a first pad; Multiple chips are stacked on the first surface, with the fourth surface of each chip facing the substrate, and the multiple chips are spaced apart to form a stacked structure; A wire bonding process is performed to fix the other end of the wire to the first pad.

2. The packaging method of the packaging structure according to claim 1, characterized in that, The steps of filling the gap with the protective film and forming the conductor include: first forming the conductor and fixing one end of the conductor to the second pad; and after forming the conductor, forming the protective film.

3. The packaging method of the packaging structure according to claim 1, characterized in that, The step of forming the protective film includes: forming an initial protective film before forming the second trench, the initial protective film filling the first trench and covering the wafer surface connected to the sidewall of the first trench; and pre-curing the initial protective film. In the step of forming the second trench, the initial protective film at the position directly opposite the second trench is removed, and the remaining initial protective film located within the notch serves as the protective film.

4. The packaging method of the packaging structure according to claim 3, characterized in that, Before forming the initial protective film, the method further includes forming a protective layer that covers the second pad.

5. The packaging method of the packaging structure according to claim 1, characterized in that, In the wire bonding process, the protective film is further subjected to a re-curing treatment to ensure that the portion of the wire adjacent to the chip is located within the protective film and to improve the curing rate of the protective film.

6. A packaging structure obtained by the method according to any one of claims 1 to 5, characterized in that, include: A substrate having opposing first and second surfaces, the first surface having a first pad; A stacked structure is located on the first surface. The stacked structure includes a plurality of chips stacked and spaced apart in a direction away from the substrate. The chips have opposing third and fourth surfaces. The third surface is away from the substrate and has a second pad. The edge region of the chip has a notch that extends from the plane of the third surface into the chip. A protective film is located within the notch; A wire, one end of which is in contact with the second pad, and the other end of which is in contact with the first pad. The portion of the wire adjacent to the chip is also in fixed contact with the protective film.

7. The packaging structure according to claim 6, characterized in that, The portion of the conductor adjacent to the chip is located within the protective film.

8. The packaging structure according to claim 6, characterized in that, The top surface of the protective film is not higher than the third surface.

9. The packaging structure according to claim 6, characterized in that, The protective film also covers the third surface, and the thickness of the protective film on the third surface is less than the thickness of the protective film in the notch.

10. The packaging structure according to claim 6, characterized in that, The inner wall of the notch is a beveled surface, or the inner wall of the notch is composed of a side surface connected to the third surface and a bottom surface connected to the side surface, wherein the angle between the side surface and the bottom surface is greater than or equal to 90°.

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