Semiconductor device structure, image sensor and method of manufacturing the same, electronic device

Abstract

The application provides a semiconductor device structure, an image sensor and a preparation method, and an electronic device, and the semiconductor device structure is suitable for the image sensor and comprises a semiconductor substrate, the semiconductor substrate comprises a plurality of chip regions and a cutting region located at the periphery of the chip regions; the cutting region comprises an interface blocking cutting area, and the chip region comprises an auxiliary cutting area; wherein the auxiliary cutting area is arranged adjacent to the cutting region, and a cutting outer edge corresponds to the interface blocking cutting area and has a spacing between the auxiliary cutting area. Through the above design of the application, the influence of the cutting process on the core area of the chip during the process of cutting to obtain the chip can be effectively alleviated.

Description

Technical Field

[0001] This invention belongs to the field of image acquisition technology, and in particular relates to a semiconductor device structure, an image sensor and its preparation method, and an electronic device. Background Technology

[0002] Image sensors are a crucial component of digital cameras. Based on their components, they can be broadly categorized into CCD (Charge-Coupled Device) and CMOS (Metal-Oxide-Semiconductor) sensors. With the continuous development of CMOS integrated circuit manufacturing processes, especially the design and manufacturing processes of CMOS image sensors (CIS), CMOS image sensors have gradually replaced CCD image sensors as the mainstream. Compared to CCD sensors, CMOS image sensors offer advantages such as higher industrial integration and lower power consumption.

[0003] Existing image sensors often experience imaging interference or chipping during chip dicing, resulting in varying degrees of damage to the core chip area and directly affecting the sensor's performance and imaging quality. Therefore, improving the chip dicing process is a pressing issue.

[0004] Therefore, it is necessary to provide a semiconductor device structure, an image sensor and its fabrication method, and an electronic device to solve the above-mentioned problems in the prior art.

[0005] It should be noted that the above description of the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and for the convenience of those skilled in the art to understand them. It should not be assumed that the above technical solutions are known to those skilled in the art simply because they have been described in the background section. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a semiconductor device structure, an image sensor and its fabrication method, as well as a corresponding electronic device, to solve the problems of the impact on the core area of ​​the chip during the chip segmentation process of the image sensor in the prior art.

[0007] To achieve the above and other related objectives, the present invention provides a semiconductor device structure suitable for image sensors, the semiconductor device structure comprising:

[0008] A semiconductor substrate, comprising several chip regions and a diced region located around the chip regions;

[0009] The cutting area includes an interface barrier cutting area, and the chip area includes an auxiliary cutting area;

[0010] The auxiliary cutting area is adjacent to the cutting area, and the outer edge of the cutting area corresponds to the interface barrier cutting area and has a gap between it and the auxiliary cutting area.

[0011] Optionally, the cutting area further includes a peripheral functional area, and the interface barrier cutting area is located between the peripheral functional area and the chip area. The peripheral functional area includes a first material structure and a second material structure with different materials. The interface barrier cutting area and / or the auxiliary cutting area include a crack mitigation material layer located in the same structural layer as the interface between the two.

[0012] Optionally, the peripheral functional area includes multiple chip detection structures, and a first buffer zone is provided between the chip detection structure and the interface barrier cutting area on the adjacent side;

[0013] Optionally, a second buffer zone is provided between adjacent chip detection structures along the direction in which the chip region and the cutting region are arranged.

[0014] Optionally, the first material structure is a metal, the second material structure is an interlayer dielectric, and the crack mitigation material layer is an interlayer dielectric.

[0015] Optionally, the plurality of chip detection structures form at least one detection structure band, and the first buffer is located between the detection structure band and the adjacent interface barrier cutting area; when the number of detection structure bands is at least two, the second buffer is located between adjacent detection structure bands, and different sides of the cutting outer edge correspond to the interface barrier cutting area or correspond to the interface barrier cutting area and the second buffer respectively.

[0016] Optionally, the semiconductor substrate includes a stacked semiconductor substrate and an interconnect structure layer, the chip region includes a chip body region, the auxiliary dicing region is located between the chip body region and the dicing region, and the interconnect structure layer includes a first clearance region corresponding to the interface barrier dicing region and / or a second clearance region corresponding to the auxiliary dicing region.

[0017] Optionally, the interconnect structure layer further includes a virtual wiring area corresponding to the auxiliary cutting area, the second clearance area is adjacent to the cutting area and the virtual wiring area, the virtual wiring area includes at least one of a wiring buffer structure area and a protection ring structure area, and when both exist, the wiring buffer structure area is located close to the second clearance area.

[0018] Optionally, the protection ring structure region includes multiple protection ring structures, which are arranged in a ring around the periphery of the chip body region.

[0019] Optionally, the wiring buffer structure area includes multiple wiring buffer structures, which form several buffer structure rows and / or buffer structure columns around the chip body area.

[0020] Optionally, the width of the first clearance zone is greater than or equal to 4 μm.

[0021] Optionally, the width of the second clearance zone is greater than or equal to 3 μm.

[0022] Optionally, the sum of the widths of the wiring buffer structure area and the second clearance area is greater than or equal to 18 μm.

[0023] Optionally, the distance between the outer edge of the cut and the protective ring structure area on the adjacent side is greater than or equal to 20 μm.

[0024] Optionally, the semiconductor substrate includes a virtual active region corresponding to the auxiliary dicing region, the virtual active region being located between the dicing region and the chip body region, and the virtual active region at least corresponding to the second clearance region.

[0025] Optionally, the virtual active area includes a clearance release area and an evaluation buffer area. The clearance release area is adjacent to the cutting area and is correspondingly disposed to the second clearance area. The evaluation buffer area is adjacent to the chip body area.

[0026] Optionally, a virtual device transition area is further provided between the clearance release area and the evaluation buffer area. When there are adjacent second clearance areas and virtual wiring areas, the virtual device transition area covers the boundary between them; and / or, the evaluation buffer area is provided with an evaluation buffer slot, and there is an interval structure layer between the bottom and the wiring buffer structure area.

[0027] Optionally, the virtual device transition area is provided with a trench isolation structure, including multiple sub-isolation structures arranged in an array or a single trench isolation structure with a cutout; and / or, the spacing structure layer includes a single spacing structure or multiple spacing blocks arranged in an array, and the bottom of the evaluation buffer groove exposes the spacing structure or the spacing blocks.

[0028] Optionally, the angle between the row center line and the cutting line of the wiring buffer structure in each row is set to an acute angle, and the angle between the column center line and the cutting line of the wiring buffer structure in each column is set to an acute angle.

[0029] Optionally, the angle between the row center line and the cutting line of the trench isolation structure in each row is set to an acute angle, and the angle between the column center line and the cutting line of the trench isolation structure in each column is set to an acute angle.

[0030] Optionally, the wiring buffer structure is arranged in at least two vertical layers, with a gap between the centers of the wiring buffer structures at corresponding positions in adjacent layers.

[0031] Optionally, the semiconductor device structure further includes at least one stacked substrate disposed on top of the semiconductor substrate, wherein each region of the stacked substrate is disposed vertically corresponding to each region of the semiconductor substrate.

[0032] Optionally, the peripheral functional area of ​​the semiconductor substrate and the peripheral functional area of ​​the stacked substrate are electrically connected through an interlayer interconnect structure, and the same structural layer of the interlayer interconnect structure corresponds to the auxiliary dicing area and the interface barrier dicing area.

[0033] The present invention also provides an image sensor, including a chip region, said chip region being cut along said cutting region based on a semiconductor device structure as described in any of the above embodiments.

[0034] The present invention also provides an electronic device including an image sensor as described in any of the above embodiments.

[0035] The present invention also provides a method for fabricating an image sensor as described in any of the above embodiments, comprising:

[0036] Provide the semiconductor device structure;

[0037] A first cut is made along the outer edge of the cut to obtain an intermediate cut structure;

[0038] Corresponding to the cutting area, the intermediate cutting structure is cut a second time to obtain the separated chip areas. The width of the cutting blade for the second cut is smaller than the width of the cutting blade for the first cut.

[0039] Optionally, along the cutting direction, the bottom of the first cut extends beyond the depth of the peripheral functional area of ​​the semiconductor device structure.

[0040] As described above, the semiconductor device structure, image sensor and fabrication method, and electronic device of the present invention can effectively mitigate the impact on the chip area during the dicing process based on the configuration design of each region on the semiconductor device structure. This helps prevent the generation of chipping cracks during dicing and also helps prevent interface cracks and direct tearing of the substrate. Furthermore, the size of the dicing tool can be flexibly configured, and the combined configuration of the dicing tools can further mitigate the impact of the dicing process on the chip, thereby improving imaging quality. Attached Figure Description

[0041] Figure 1 The diagram shows the basic structure of an image sensor system.

[0042] Figure 2 The diagram shows a pixel circuit made of an image sensor.

[0043] Figure 3 The diagram shown is a top view of a semiconductor structure provided in one embodiment of this application.

[0044] Figure 4 Displayed as Figure 3 The diagram shows a cross-sectional view of the semiconductor device structure along position I-II.

[0045] Figure 5 Displayed as Figure 4 The dashed box corresponds to a cross-sectional schematic diagram of a structural example.

[0046] Figure 6 Displayed as Figure 5 A top view of a corresponding structural example.

[0047] Figure 7 Displayed as Figure 5 A top view of another corresponding structural example.

[0048] Figure 8 Displayed as Figure 4 A cross-sectional schematic diagram of another structural example corresponding to the dashed box.

[0049] Figure 9 Displayed as Figure 8 A top view of a corresponding structural example.

[0050] Figure 10 The diagram shows a partial distribution of the interconnect structure layer of a semiconductor device structure in one embodiment of this application.

[0051] Figure 11 The diagram shows a partial distribution of the semiconductor substrate in a semiconductor device structure according to an embodiment of this application.

[0052] Figure 12 The diagram shown is a schematic representation of the wiring buffer structure in one embodiment of this application.

[0053] Figure 13 The diagram shown is a schematic representation of the arrangement of the trench isolation structure in one embodiment of this application.

[0054] Figure 14 The diagram shown is a flowchart illustrating the fabrication process of an image sensor according to an embodiment of this application.

[0055] Figure 15 The diagram shown is a schematic of the intermediate cutting structure in the fabrication of an image sensor according to an embodiment of this application.

[0056] Component designation explanation

[0057] Detailed Implementation

[0058] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0059] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0060] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0061] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0062] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0063] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0064] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0065] The following detailed description of the invention is provided in conjunction with the accompanying drawings.

[0066] Figure 1 The diagram shows a basic structural block diagram of an image sensor system. The image sensor includes a readout circuit and a control circuit connected to a pixel array. A functional logic unit is connected to the readout circuit, and the readout circuit and control circuit are connected to a status register to control the reading of the pixel array. The pixel array includes multiple pixels (P1, P2, P3) arranged in rows (R1, R2, R3…Ry) and columns (C1, C2, C3…Cx). The pixel signals output by the pixel array are output to the readout circuit via column lines. In one embodiment, after each pixel acquires image data, the image data is read out using the readout mode specified by the status register and then transmitted to the functional logic unit. In specific applications, the readout circuit may include an analog-to-digital converter (ADC) circuit and others.

[0067] In some applications, the status register may contain a programmed selection system to determine whether the readout system reads out in rolling shutter or global shutter mode. The functional logic unit may store only image data or image data applied or processed with image effects. In specific applications, the readout circuitry may read out one row of image data at a time along the readout column lines, or it may use various other methods to read out image data. The operation of the control circuitry can be determined by the current setting of the status register. For example, the control circuitry generates a shutter signal to control image acquisition. In some applications, this shutter signal may be a global shutter signal, causing all pixels in the pixel array to acquire their image data simultaneously through a single acquisition window. In other applications, this shutter signal may be a rolling shutter signal, causing pixels in each pixel row of the pixel array to be read out continuously through the acquisition window.

[0068] Figure 2 This is a schematic diagram showing the connection of a pixel circuit in an image sensor. (Example) Figure 2As shown, each pixel circuit includes a photoelectric conversion element (e.g., a photodiode) and pixel circuitry (as shown by the transistor within the dashed box in the figure). The photodiode can be a buried photodiode (PPD) used in current image sensors. In one application example, the pixel circuitry includes a reset transistor (RST), a source follower transistor (SF), and a pixel select transistor (RS), connected to a transfer transistor (TX) and the photodiode as shown in the figure. In another stacked structure application example, not shown in the figure, the pixel circuitry includes a reset transistor, a source follower transistor, and a pixel select transistor disposed on a circuit chip, connected to a photodiode in another chip based on the transfer transistor. During operation, the photoelectric conversion element generates photocharge in response to incident light during exposure. The transfer transistor is connected to a transfer signal that controls the transfer transistor to transfer the charge accumulated in the photoelectric conversion element to the floating diffusion region (FD). In one embodiment, the transfer transistor can be a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), the reset transistor is connected between VDD and the floating diffusion region, and in response to a reset signal, resets the sensor pixel circuitry (e.g., discharges or charges the floating diffusion region and photodiode to the current voltage), the floating diffusion region is connected to the gate of the source follower transistor, the source follower transistor is connected between VDD and the pixel select transistor, and in response to the potential of the floating diffusion region, outputs it, and the pixel select transistor is connected to the source follower transistor and the pixel circuit bit line, and in response to a pixel select control signal, performs pixel select readout and outputs it to the readout column.

[0069] With advancements in semiconductor process nodes, wafer packaging technology is also rapidly progressing. This is especially true for CMOS image sensors used in cameras of consumer electronics such as smartphones and tablets, where the requirements for packaging technology are becoming increasingly stringent. Currently, mainstream CMOS image sensors used in cameras of smartphones and tablets generally employ blade-cutting technology. Previously, the mainstream laser cutting method is increasingly lagging behind technological iterations. Laser cutting involves high temperatures, which easily generate molten silicon. This molten material is prone to peeling off during the product's lifespan or during drops, and it has a high probability of landing on the imaging area of ​​the CMOS image sensor, interfering with the normal operation of the CMOS image sensor chip. Moreover, this problem is visible to the end customer and is extremely likely to cause customer complaints.

[0070] However, pure blade dicing avoids the generation of molten silicon at the cutting location, thus preventing such problems. Pure blade dicing is prone to silicon wafer peeling, and without special design for the dicing path, it can also result in unacceptable yield losses. Existing image sensor chips suffer damage during dicing, a problem that is difficult to effectively solve. The semiconductor device structure of this application can effectively solve the above problems.

[0071] Example 1:

[0072] Please see Figure 3 and Figure 4 As shown, this embodiment provides a semiconductor device structure 100 suitable for image sensors, including: a semiconductor substrate W1, the semiconductor substrate W1 including a plurality of chip regions 101a, 101b, 101c, 101d and diced regions 102a, 102b located around the chip regions; the semiconductor device structure 100 of this embodiment will be described below using chip region 101b and diced region 102a as examples:

[0073] In this embodiment, the cutting region 102a includes interface barrier cutting regions 1022 and 1023. The following description uses interface barrier cutting region 1022 as an example. It can be understood that an interface barrier cutting region 1023 also exists between the cutting region 102a and the adjacent chip region 100a on the other side. Additionally, the chip region 101b includes an auxiliary cutting region 1012; wherein the auxiliary cutting region 1012 is adjacent to the cutting region 102a, and the outer edge of the cut corresponds to the interface barrier cutting region 1022 and has a gap between it and the auxiliary cutting region 1012. In this embodiment, the outer edge of the cut can be as follows: Figure 4 The edge of the first cutting tool 201 shown, such as the edge of a cutting blade, corresponds to the interface barrier cutting area 1022 on the right side of the outer edge during the cutting process, and there is a gap between the right side of the outer edge ... As those skilled in the art will understand, other necessary or inevitable material layers in the fabrication of existing image sensors may also exist in the corresponding region. It is not strictly speaking just one material, as long as it can solve the problem of mitigating crack formation and stress propagation in the peripheral function proposed in this application.

[0074] Please see Figure 4 and Figure 10 , Figure 11As shown, in one embodiment, the cutting region 102a further includes a peripheral functional region 1021, and an interface barrier cutting region 1022 is located between the peripheral functional region 1021 and the chip region 101b. The peripheral functional region 1021 includes a first material structure and a second material structure with different materials, and an interface is formed between the two material structures. For example, the first material structure can be a metal material structure, such as Gu, W, etc., and the second material structure can be an insulating dielectric material structure, such as silicon oxide, etc.

[0075] In this embodiment, the interface barrier cutting area 1022 can be designed to include a crack mitigation material layer, or the auxiliary cutting area 1012 can be designed to include a crack mitigation material layer, or both can be designed to include a crack mitigation material layer. The material of the crack mitigation material layer includes, but is not limited to, silicon oxide. Furthermore, this crack mitigation material layer is located in the same structural layer as the interface between the first and second material structures, meaning they are located in the same depth range. From a side view, the crack mitigation material layer covers the interface. Based on this design, during the cutting process, the cutting edge falls into the crack mitigation material layer area, thereby avoiding cutting into the interface of different material structures. This prevents easily torn interfaces from tearing, further preventing stress from extending to the chip area during tearing, which helps prevent crack propagation and is beneficial for protecting the chip core area within the chip region. The crack mitigation material layer can be a single material structure layer, or it can be a structure layer including multiple materials. Interfaces formed by multiple material structure layers are less prone to crack formation or have relatively weaker stress.

[0076] See also Figure 4 and Figure 10 , Figure 11 As shown, the peripheral functional area 1021 includes multiple chip detection structures 301a and 301b. A first buffer zone 302 is provided between the chip detection structure 301b and the adjacent interface barrier cutting area 1022. It is understood that a first buffer zone 303 may also be provided on the other side. Alternatively, a second buffer zone 304 is provided between adjacent chip detection structures 301a and 301b along the direction of arrangement of the chip area 101b and the cutting area 102a. Alternatively, both the peripheral functional area 1021 may have first and second buffer zones. The configuration of each buffer zone is beneficial for further achieving cutting stress buffering. In this example, the multiple chip detection structures 301a and 301b can be understood as the first material structure in the above example, while the surrounding insulating dielectric material layer can be understood as the corresponding second material structure. The crack mitigation material layer utilizes the surrounding insulating dielectric material layer and does not contain metallic materials to mitigate crack formation and propagation.

[0077] In a further example, multiple chip detection structures form at least one detection structure band 305, 306, and multiple chip detection structures form a chip detection structure region 300. A first buffer zone 302 is located between the detection structure band 306 and the adjacent interface barrier cutting region 1022. When the number of detection structure bands is at least two, such as detection structure bands 305, 306, a second buffer zone 304 is located between adjacent detection structure bands 305, 306. In this embodiment, different sides of the cutting outer edge can all correspond to interface barrier cutting regions 1022, 1023, or different sides of the cutting outer edge can correspond to interface barrier cutting region 1022 and the second buffer zone 304 respectively. In this case, the second buffer zone 304 acts as the interface barrier cutting region 1022, meaning that cutting can be performed based on the second buffer zone 304, and the cutting outer edge can fall on the second buffer zone 304. During the cutting process, no interface of different material structures is cut, or the stress is weak, thereby achieving the same effect as relieving stress during cutting as in the aforementioned example. Of course, in other embodiments, when there are two second buffer zones 304, the edges of the cutting blade can also fall within the area of ​​the second buffer zone 304. Based on the above design, the size of the cutting tool can be configured accordingly, and when there are an odd number of detection structural bands, the middle band can be cut.

[0078] Specifically, chip test structures 301a and 301b can be test structures (test keys) arranged in the dicing area for chip testing. Alternatively, they can be other process monitoring structures such as marks, pads for process measurement and electrical connections, etc. The first buffer zones 302 and 303, and the second buffer zone 304 can all be areas formed by dielectric materials (such as silicon oxide) commonly used in the fabrication of existing image sensor wiring structures. In this embodiment, the cutting edge of the dicing tool either falls on the interface barrier cutting areas 1022 and 1023, or on the second buffer zone 304, ensuring that the edge of the dicing tool does not contact the interface formed by different materials. Cutting within a single material layer helps mitigate the phenomenon of cracking when the dicing tool edge falls on the interface of different materials. Through the design of this embodiment, not only can the impact of the cutting process on the chip area be mitigated, but the size of the dicing tool can also be flexibly configured while meeting the above requirements.

[0079] Please see Figure 4 As shown, in one embodiment, the semiconductor substrate W1 includes a stacked semiconductor substrate A and an interconnect structure layer M, the chip region 101b includes a chip body region 1011, the auxiliary dicing region 1012 is located between the chip body region 1011 and the dicing region 102a, and the interconnect structure layer M includes a first clearance region K1 corresponding to the interface barrier dicing region 1022 and / or a second clearance region K2 corresponding to the auxiliary dicing region 1012.

[0080] Specifically, the semiconductor device structure 100 can be a structure fabricated on a wafer during the image sensor fabrication process, or it can be a structure that has been fabricated but not yet cut. The semiconductor substrate A can be any structure used in the field of image sensors to fabricate various functional areas of the image sensor. In addition, the interconnect structure layer M can be an interconnect structure layer of the device fabricated on the semiconductor substrate A, and can include metal interconnect structures and insulating dielectric material layers to realize electrical connections between devices of the image sensor.

[0081] For example, photosensitive elements, control transistors, and wiring of CMOS image sensors can be fabricated based on semiconductor substrates. The semiconductor substrate can be a single-layer material structure, including but not limited to silicon substrates, where the components in each region are fabricated within the silicon substrate. This silicon substrate can be made of monocrystalline silicon, monocrystalline germanium, polycrystalline silicon, amorphous silicon, or silicon-germanium compounds. Alternatively, the semiconductor substrate can be a stacked structure consisting of two or more material layers, with each region fabricated within any desired layer. For example, the semiconductor substrate may include a silicon substrate and an epitaxial layer (EPI) formed on the silicon substrate. Photoelectric conversion elements and transistor components (such as charge transport elements) are fabricated within the epitaxial layer, allowing for the fabrication of back-illuminated image sensors. Furthermore, the semiconductor substrate can also be silicon-on-insulator (SOI). Additionally, the semiconductor substrate can contain N-type or P-type doped regions to meet the functional requirements of the device.

[0082] In this embodiment, the interconnect structure layer M includes a first clearance area K1 corresponding to the interface barrier cutting region 1022, or the interconnect structure layer M includes a second clearance area K2 corresponding to the auxiliary cutting region 1012, or both the interconnect structure layer M and the first clearance area K1 and the second clearance area K2 are included. It is understood that the first clearance area K1 and the second clearance area K2 can be part of the interconnect structure layer M, such as being composed of its dielectric layer, forming a crack mitigation material layer to mitigate the generation and propagation of cutting cracks. The first clearance area K1 and the second clearance area K2 can prevent the propagation of cracks in the horizontally corresponding structural layers. Furthermore, it should be noted that for the interconnect structure layer M, where the interface barrier cutting region 1022 corresponds to the first clearance area K1, this layer can also include corresponding first buffer zones and second buffer zones, which can be composed of its dielectric layer.

[0083] See also Figure 4As shown, the interconnect structure layer M also includes a virtual wiring area 1014 corresponding to the auxiliary cutting area 1012. A second clearance area 1013 is adjacent to the cutting area 102a and the virtual wiring area 1014. The virtual wiring area 1014 includes at least one of a wiring buffer structure area 1015 and a protective ring structure area 1016. When both exist, the wiring buffer structure area 1015 is positioned close to the second clearance area 1013. Based on the above design, the second clearance area K2 can further mitigate cutting cracks and facilitate the blocking of crack propagation through the wiring buffer structure area 1015 and the protective ring structure area 1016.

[0084] Specifically, referring to the description of the above embodiments, for the interconnect structure layer M, the corresponding auxiliary cutting area 1012 may sequentially include a corresponding second clearance area 1013 (the area indicated by K2 in this layer), a wiring buffer structure area 1015, and a guard ring structure area 1016. The second clearance area 1013 may be composed of the dielectric layer of the interconnect structure layer M, the wiring buffer structure area 1015 may be a virtual metal structure, and the guard ring structure area 1016 may be a guard ring (sealing ring) made of metal structure.

[0085] As an example, the width K1 of the first clearance area is greater than or equal to 4μm, for example, it can be 5μm or 6μm; the width K2 of the second clearance area 1013 is greater than or equal to 3μm, for example, it can be 3.5μm or 4.5μm; as an example, the sum of the widths of the wiring buffer structure area 1015 and the second clearance area 1013 is greater than or equal to 15μm, for example, it can be 18μm, 20μm, or 22μm. As an example, the distance between the outer edge of the cut closest to the chip body area 1011 and the adjacent protective ring structure area 1016 is greater than or equal to 20μm. For example, it can be 21μm, 22μm, or 25μm. The above dimensions can be set according to the actual chip size and requirements.

[0086] See also Figure 4 As shown, in one embodiment, the protection ring structure region 1016 includes multiple protection ring structures, which are arranged in a ring around the periphery of the chip body region 1011. The periphery of the chip body region 1011 can have one or multiple ring-shaped protection ring structures. Figure 4 The diagram shows a structure of three rings. In addition, a single protective ring structure can be a closed ring structure or a ring structure formed by multiple spaced-apart protective rings.

[0087] In one embodiment, the wiring buffer structure region 1015 includes multiple wiring buffer structures, which form several buffer structure rows and / or buffer structure columns around the chip body region 1011. The wiring buffer structures can be metal blocks, and multiple metal blocks are arranged in an array according to rows and columns.

[0088] See also Figure 4 As shown, the semiconductor substrate A includes a virtual active region 1017 corresponding to the auxiliary dicing region 1012. The virtual active region 1017 is located between the dicing region 102a and the chip body region 1011, and the virtual active region 1017 corresponds at least to the second clearance region 1013. It is understood that the virtual active region 1017 is located in the semiconductor substrate, and the core imaging devices of the actual image sensor are not fabricated in this region. For example, pixel circuit devices of the image sensor, such as photoelectric conversion elements, charge transport elements, floating diffusion active regions, and signal output transistors, are fabricated in the semiconductor substrate at the same horizontal layer as this region and at the position corresponding to the chip body region 1011. The active region corresponding to the virtual active region 1017 may not contain these devices.

[0089] See also Figure 4 As shown, in one embodiment, the virtual active region 1017 includes a clearance release region 1018 and an evaluation buffer trench region 1020. The clearance release region 1018 is adjacent to the dicing region 102a and correspondingly disposed with respect to the second clearance region 1013. The evaluation buffer trench region 1020 is adjacent to the chip body region 1011. The clearance release region 1018 can be an active region belonging to that layer in the semiconductor substrate, i.e., it can be a P-type silicon substrate. The clearance release region 1018 of the virtual active region AA can facilitate the definition of the chip die edge. The evaluation buffer trench region 1020 can be a trench structure fabricated by the backside process of the semiconductor substrate.

[0090] In a further example, a virtual device transition region 1019 is provided between the clearance release region 1018 and the evaluation buffer region 1020. When there are adjacent second clearance regions 1013 and virtual wiring regions 1014, the virtual device transition region 1019 covers the boundary between them. The virtual device transition region 1019 can be based on the active region belonging to this layer in the semiconductor substrate, and can be fabricated with an isolation structure 105. In other examples, virtual devices 106, etc., can also be fabricated.

[0091] Please see Figure 4 and Figure 5-9As shown, in one embodiment, the evaluation buffer trench area 1020 is provided with an evaluation buffer trench 1021, and a spacer structure layer is provided between the bottom of the evaluation buffer trench 1021 and the wiring buffer structure area 1015. The evaluation buffer trench 1021 can be a trench structure fabricated by a back-side process of the semiconductor substrate. In other embodiments, the evaluation buffer trench 1021 can be filled with other materials, including but not limited to silicon oxide, to relieve stress. The spacer structure layer includes, but is not limited to, a silicon oxide layer. The evaluation buffer trench 1021 can be used to stop silicon peeling. Furthermore, this ring of evaluation buffer trench 1021 can also be used to evaluate whether silicon peeling will cause failure. The degree of silicon peeling varies from slight to severe; generally, silicon peeling not exceeding this ring of trenches is considered a good product, while peeling exceeding this ring of trenches is considered a failed product.

[0092] As an example, please refer to Figure 5-7 As shown, the spacer structure layer is a single spacer structure 103, and the bottom of the evaluation buffer groove 1021 exposes the single spacer structure 103. For another example, please refer to... Figure 8 and Figure 9 As shown, the spacer structure layer consists of multiple spacer blocks 104 arranged in an array, with the spacer blocks 104 exposed at the bottom of the evaluation buffer trench 1021. Individual spacer structures 103 and spacer blocks 104 can be fabricated simultaneously with the chip body region 1011 during the fabrication of the device isolation structure. For example, they can be fabricated using a shallow trench isolation (STI) process based on an image sensor, with materials including but not limited to silicon oxide, which simplifies the process. The formation of the spacer structure layer also facilitates compatibility between the evaluation buffer trench 1021 and the pad fabrication opening process of the device. The evaluation buffer trench 1021 and pad openings can be formed simultaneously using the same process. The pad openings can be TSV vias that expose a metal layer (such as the first metal layer), preventing over-etching of the pad area.

[0093] Continue reading Figure 4 and Figure 5-9 As shown, in one embodiment, the virtual device transition region 1019 is provided with a trench isolation structure 105, which includes a plurality of sub-isolation structures arranged in an array, such as... Figure 7 and Figure 9 As shown, or, having a single, hollowed-out groove isolation structure, such as Figure 6 As shown, in this embodiment, the preferred design is a single trench isolation structure with a hollowed-out area, where the hollowed-out empty area is a square active area AA. The single trench isolation structure with hollowed-out area and the multiple sub-isolation structures can be fabricated together with the chip body area 1011 during the fabrication of the device isolation structure. For example, it can be fabricated using the shallow trench isolation structure (STI) process based on an image sensor, with materials including but not limited to silicon oxide, which simplifies the process.

[0094] Please see Figure 4 , Figure 10 and Figure 12 As shown, the center line of the row wiring buffer structure 1015a in each row forms an acute angle with the cutting line, and the center line of the column wiring buffer structure in each column forms an acute angle with the cutting line. The wiring buffer structure 1015a is inclined along the cutting line, which helps to buffer the cutting stress. It should be noted that the acute angle here can be a regular acute angle, or it can be an acute angle formed by a non-strict ray, with the aim of alleviating the stress of cutting through this design. In addition, the cutting line here refers to the line corresponding to the mark left by the horizontal stroke of the cutting blade.

[0095] Please see Figure 4 , Figure 11 and Figure 13 As shown, the angle between the row centerline of the trench isolation structure and the cutting line in each row tends to be an acute angle, and the angle between the column centerline of the trench isolation structure and the cutting line in each column tends to be an acute angle. The trench isolation structure is inclined along the cutting line, which helps to buffer the cutting stress. It should be noted that the row centerline of the trench isolation structure here can be understood as the centerline formed by the center of each sub-isolation structure when the trench isolation structure includes multiple sub-isolation structures arranged in an array. In this case, virtual active area structures and virtual devices (such as virtual polysilicon structures) can be formed between each sub-isolation structure. In addition, when the trench isolation structure 105 is a single trench isolation structure with a cutout, the row centerline of the trench isolation structure can be understood as the centerline formed by the center of each array of cutouts. In this case, virtual active area structures and virtual devices can be formed in each cutout area. Of course, no other devices can be formed, and only the active area material based on the semiconductor substrate can be formed.

[0096] For further information, please refer to [link / reference]. Figure 4 and Figure 10-13 As shown, the wiring buffer structure is arranged in at least two vertical layers, with a gap between the centers of the wiring buffer structures at corresponding positions in adjacent layers. In this example, the upper and lower centers of the two corresponding structural layers do not correspond. For example, in the second wiring buffer structure, the center of a certain wiring buffer structure (such as a metal block) does not coincide with the center of the wiring buffer structure in its vertical direction when projected onto the first and third wiring buffer structure layers. For example, the projection may fall within the space enclosed by adjacent wiring buffer structures (such as those made of insulating dielectric material).

[0097] Please see Figure 4As shown, in one embodiment, the semiconductor device structure further includes at least one stacked substrate W2 stacked with the semiconductor substrate W1, with each region of the stacked substrate W2 corresponding vertically to each region of the semiconductor substrate W1. It should be noted that this embodiment provides a stacked structure for an image sensor, wherein at least a photosensitive element is fabricated on the first wafer (semiconductor substrate W1), and at least peripheral circuitry, such as an analog-to-digital converter (ADC), is fabricated on the second wafer (stacked substrate W2). Of course, the specific device distribution in the image sensor can be selected according to actual needs. In other embodiments, three or more wafers may be included to complete the image sensor fabrication through stacking.

[0098] Please continue reading. Figure 4 As shown, in one embodiment, the peripheral functional region 1021 of the semiconductor substrate W1 and the peripheral functional region of the stacked substrate W2 are electrically connected through an interlayer interconnect structure, and the same structural layer of the interlayer interconnect structure corresponds to an auxiliary cutting region 1012 and an interface barrier cutting region 1022. In this embodiment, the auxiliary cutting region 1012 and the interface barrier cutting region 1022 extend in the two substrates. For example, it can be understood that at the interface where the two substrates are joined, the materials of the upper and lower substrates in that region are the same, so that the interface formed by different material structures in the interlayer interconnect structure can be covered laterally based on the same material layer, which can further alleviate the crack propagation formed at the interface between the two substrates during the cutting process.

[0099] Example 2:

[0100] The present invention also provides an image sensor including a chip region. The chip region of this embodiment is obtained by cutting along a cutting region 102a based on a semiconductor device structure as described in any of the above embodiments. That is, the chip region of this embodiment includes a chip body region 1011.

[0101] The present invention also provides an electronic device including an image sensor as described in any of the above embodiments. The image sensor may be a CMOS image sensor, and the electronic device may be a security monitoring device, an automotive electronics device, a mobile phone camera, a machine vision device, etc. The image sensor based on the present invention can acquire high-quality image information.

[0102] Example 3:

[0103] Please see Figure 3 , Figure 4 and Figure 14 and Figure 15 As shown, this embodiment also provides a method for fabricating an image sensor as described in any of the above solutions, comprising:

[0104] S1: Provides semiconductor device structures, such as Figure 4 As shown;

[0105] S2: A first cut is made along the outer edge of the cut to obtain the intermediate cut structure, such as... Figure 13 As shown;

[0106] S3: For the corresponding cutting area 102a, the intermediate cutting structure is cut a second time to obtain the separated chip areas 101b. The width of the cutting blade 202 for the second cut is smaller than the width of the cutting blade 201 for the first cut.

[0107] Specifically, in this embodiment, a two-stage cutting method is used to obtain the chip area. The use of a narrower second cutting blade further reduces the formation of cutting cracks and their impact on the chip. Of course, in other embodiments, since this application embodiment has already effectively improved the semiconductor device structure, a single-stage cutting method can also effectively mitigate the formation and impact of cutting cracks.

[0108] See also Figure 15 As shown, along the cutting direction, the bottom of the first cut extends beyond the depth of the peripheral functional area of ​​the semiconductor device structure.

[0109] Specifically, in this embodiment, during the first cutting process, the cutting depth of the cutting blade exceeds the depth of the peripheral functional area. For example, the cutting depth of the cutting blade may exceed the interconnect structure layer M located below. In addition, in a structure with a stacked substrate W2 and a semiconductor substrate W1, the cutting depth of the cutting blade extends from the semiconductor substrate W1 to the stacked substrate W2, and further exceeds the interconnect structure layer of the stacked substrate W2. The problem of cutting cracks can be solved based on the configuration of the semiconductor devices in this application.

[0110] In one embodiment, the width D of the cutting regions 102a and 102b can be set between 100μm and 200μm, for example, it can be 120μm, 150μm, or 180μm. In addition, the width of the first cutting tool 201 is between 105μm and 120μm, such as 110μm or 115μm; and the width of the second cutting tool 202 is between 80μm and 100μm, such as 85μm or 90μm.

[0111] In summary, the semiconductor device structure, image sensor and fabrication method, and electronic device of the present invention can effectively mitigate the impact on the chip area during the dicing process based on the configuration design of each region on the semiconductor device structure. This helps prevent chipping during dicing and also helps prevent interface cracks and direct tearing of the substrate. Furthermore, the size of the dicing tool can be flexibly configured, and the combined configuration of the dicing tools can further mitigate the impact of the dicing process on the chip, improving imaging quality. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0112] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A semiconductor device structure suitable for image sensors, characterized in that, include: A semiconductor substrate, comprising several chip regions and a diced region located around the chip regions; The cutting area includes an interface barrier cutting area, and the chip area includes an auxiliary cutting area; The auxiliary cutting area is adjacent to the cutting area, and the outer edge of the cutting area corresponds to the interface barrier cutting area and has a gap between it and the auxiliary cutting area. The semiconductor substrate includes stacked semiconductor substrates and interconnect structure layers, the chip region includes a chip body region, and the auxiliary dicing region is located between the chip body region and the dicing region; The interconnect structure layer includes a second clearance area corresponding to the auxiliary cutting area and a virtual wiring area corresponding to the auxiliary cutting area. The second clearance area is adjacent to the cutting area and the virtual wiring area. The virtual wiring area includes a wiring buffer structure area and a protection ring structure area. The wiring buffer structure area is located close to the second clearance area. The second clearance area is composed of the dielectric layer of the interconnect structure layer, which serves as a crack mitigation material layer to mitigate the generation and propagation of cutting cracks. The crack mitigation material layer is a single material structure layer.

2. The semiconductor device structure as described in claim 1, characterized in that, The cutting area also includes a peripheral functional area. The interface barrier cutting area is located between the peripheral functional area and the chip area. The peripheral functional area includes a first material structure and a second material structure with different materials. The interface barrier cutting area and / or auxiliary cutting area include a crack mitigation material layer located in the same structural layer as the interface of the two.

3. The semiconductor device structure as described in claim 2, characterized in that, The peripheral functional area includes multiple chip detection structures, and a first buffer zone is provided between the chip detection structure and the interface barrier cutting area on the adjacent side; and / or, a second buffer zone is provided between adjacent chip detection structures along the direction in which the chip area and the cutting area are arranged; and / or, the first material structure is metal, the second material structure is an interlayer dielectric, and the crack mitigation material layer is an interlayer dielectric.

4. The semiconductor device structure as described in claim 3, characterized in that, The plurality of chip detection structures form at least one detection structure band, and the first buffer is located between the detection structure band and the adjacent interface barrier cutting area; when the number of detection structure bands is at least two, the second buffer is located between adjacent detection structure bands, and different sides of the cutting outer edge correspond to the interface barrier cutting area or correspond to the interface barrier cutting area and the second buffer respectively.

5. The semiconductor device structure as described in claim 1, characterized in that, The interconnect structure layer also includes a first clearance area corresponding to the interface barrier cutting area.

6. The semiconductor device structure as described in claim 5, characterized in that, The protection ring structure area includes multiple protection ring structures arranged in a ring around the periphery of the chip body area; and / or, the wiring buffer structure area includes multiple wiring buffer structures forming several buffer structure rows and / or buffer structure columns around the periphery of the chip body area; and / or, the width of the first clearance area is greater than or equal to 4 μm; the width of the second clearance area is greater than or equal to 3 μm; the sum of the widths of the wiring buffer structure area and the second clearance area is greater than or equal to 18 μm; the distance between the cutting outer edge and the nearby protection ring structure area is greater than or equal to 20 μm.

7. The semiconductor device structure as described in claim 5, characterized in that, The semiconductor substrate includes a virtual active region corresponding to the auxiliary dicing region. The virtual active region is located between the dicing region and the chip body region, and the virtual active region corresponds at least to the second clearance region.

8. The semiconductor device structure as described in claim 7, characterized in that, The virtual active area includes a clearance release area and an evaluation buffer area. The clearance release area is adjacent to the cutting area and is correspondingly set to the second clearance area. The evaluation buffer area is adjacent to the chip body area.

9. The semiconductor device structure as described in claim 8, characterized in that, A virtual device transition area is also provided between the clearance release area and the evaluation buffer area. When there are adjacent second clearance areas and virtual wiring areas, the virtual device transition area covers the boundary between them; and / or, the evaluation buffer area is provided with an evaluation buffer slot, and there is an interval structure layer between the bottom of the evaluation buffer slot and the wiring buffer structure area.

10. The semiconductor device structure as described in claim 9, characterized in that, The virtual device transition area is provided with a trench isolation structure, including multiple sub-isolation structures arranged in an array or a single trench isolation structure with a cutout; and / or, the spacing structure layer includes a single spacing structure or multiple spacing blocks arranged in an array, and the bottom of the evaluation buffer groove exposes the spacing structure or the spacing blocks.

11. The semiconductor device structure as described in claim 10, characterized in that, The wiring buffer structure area includes multiple wiring buffer structures, wherein the center line of each row of the wiring buffer structure forms an acute angle with the cutting line, and the center line of each column of the wiring buffer structure forms an acute angle with the cutting line; and / or, the center line of each row of the trench isolation structure forms an acute angle with the cutting line, and the center line of each column of the trench isolation structure forms an acute angle with the cutting line; and / or, the wiring buffer structure area includes multiple wiring buffer structures, which are arranged vertically in at least two layers, with a gap between the centers of the wiring buffer structures at corresponding positions in adjacent layers.

12. The semiconductor device structure according to any one of claims 1-11, characterized in that, The semiconductor device structure further includes at least one stacked substrate stacked with the semiconductor substrate, wherein each region of the stacked substrate is arranged vertically corresponding to each region of the semiconductor substrate.

13. The semiconductor device structure as described in claim 12, characterized in that, The peripheral functional area of ​​the semiconductor substrate and the peripheral functional area of ​​the stacked substrate are electrically connected through an interlayer interconnect structure, and the same structural layer of the interlayer interconnect structure corresponds to the auxiliary dicing area and the interface barrier dicing area.

14. An image sensor, characterized in that, Includes a chip region, which is obtained by cutting along the cutting region based on the semiconductor device structure as described in any one of claims 1-13.

15. An electronic device, characterized in that, Including the image sensor as described in claim 14.

16. A method for fabricating an image sensor as described in claim 14, characterized in that, include: Provide the semiconductor device structure; The semiconductor device structure includes: A semiconductor substrate, the semiconductor substrate comprising stacked semiconductor substrates and interconnect structure layers, and including a plurality of chip regions and dicing regions located around the chip regions, the chip regions including a chip body region and an auxiliary dicing region located between the chip body region and the dicing regions; The cutting area includes an interface barrier cutting area, and the auxiliary cutting area is disposed adjacent to the cutting area, with the outer edge of the cutting area corresponding to the interface barrier cutting area and having a gap between it and the auxiliary cutting area. The interconnect structure layer includes a second clearance area corresponding to the auxiliary cutting area and a virtual wiring area corresponding to the auxiliary cutting area. The second clearance area is adjacent to the cutting area and the virtual wiring area. The virtual wiring area includes a wiring buffer structure area and a protection ring structure area. The wiring buffer structure area is located close to the second clearance area. The second clearance area is composed of a dielectric layer of the interconnect structure layer and serves as a crack mitigation material layer to mitigate the generation and propagation of cutting cracks. The crack mitigation material layer is a single material structure layer. A first cut is made along the outer edge of the cut to obtain an intermediate cut structure; Corresponding to the cutting area, the intermediate cutting structure is cut a second time to obtain the separated chip areas. The width of the cutting blade for the second cut is smaller than the width of the cutting blade for the first cut.

17. The method for fabricating an image sensor as described in claim 16, characterized in that, Along the cutting direction, the bottom of the first cut extends beyond the depth of the peripheral functional area of ​​the semiconductor device structure.

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