Semiconductor structure and method of manufacturing a semiconductor structure

Abstract

The embodiment of the present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises: a substrate with opposite first and second surfaces, the substrate has a groove extending from the first surface to the second surface, the groove comprises a first groove and a second groove connected in communication, and the second groove is located between the first groove and the second surface; a first gate and a second gate which are separated from each other, the first gate is located in the first groove, and the second gate is located in the first groove and extends into the second groove; a first semiconductor layer which extends from the first surface to the inner wall of the first groove and is located on the side of the first gate facing the inner wall of the first groove, and further extends to electrically contact the second gate; and a second semiconductor layer which extends from the first surface to the inner wall of the first groove, the side wall of the second groove and the bottom surface of the second groove in sequence, and is located on the side of the second gate facing the inner wall of the first groove and the inner wall of the second groove. The embodiment of the present disclosure is at least beneficial to improve the performance of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the semiconductor structure. Background Technology

[0002] Common Dynamic Random Access Memory (DRAM) is of the 1T1C type, meaning that a single transistor's source or drain is electrically connected to a capacitor to form a memory cell structure. This structure uses capacitors to store data, but because reading data consumes the capacitor's charge, and the capacitor itself can leak current, the charge in the capacitor needs to be constantly refreshed. This results in high power consumption and unstable electrical performance for DRAM. Furthermore, the large area required for capacitor manufacturing makes miniaturization a significant challenge.

[0003] To overcome the problems caused by capacitors, a 2T0C type memory cell structure was applied, in which the source or drain of one transistor is electrically connected to the gate of another transistor to form a memory cell structure. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and a method for manufacturing the semiconductor structure, which at least helps to improve the performance of the semiconductor structure.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, including: a substrate having opposing first and second surfaces, and a trench extending from the first surface to the second surface within the substrate, the trench including a first trench and a second trench that are connected, the sidewall of the first trench being connected to the first surface, and the second trench being located between the first trench and the second surface; a first gate and a second gate that are mutually discrete, the first gate being located in the first trench, and the second gate being located in the first trench and extending into the second trench; a first semiconductor layer extending from the first surface to the inner wall of the first trench, and located on the side of the first gate facing the inner wall of the first trench, and also extending to the second gate electrical contact; a second semiconductor layer extending sequentially from the first surface to the inner wall of the first trench, the sidewall of the second trench, and the bottom surface of the second trench, the second semiconductor layer being located on the side of the second gate facing the inner wall of the first trench and the inner wall of the second trench; wherein, the first gate and the first semiconductor layer are used to form a first transistor, and the second gate and the second semiconductor layer are used to form a second transistor.

[0006] In some embodiments, the first trench includes a first sidewall and a second sidewall opposite to each other along a first direction, the first semiconductor layer is located at least on the first sidewall and extends to contact the second gate, and the second semiconductor layer is located at least on the second sidewall and also extends to the inner wall of the second trench.

[0007] In some embodiments, the orthographic projection of the first gate on the second surface is a rectangle, and the orthographic projection of the second gate on the second surface is a rectangle; or, the orthographic projection of the first gate on the second surface is a U-shape, and the orthographic projection of the second gate on the second surface is a U-shape.

[0008] In some embodiments, the cross-sectional shape of the first groove perpendicular to the first surface includes a trapezoid, a rectangle, or a bowl shape; the cross-sectional shape of the second groove perpendicular to the first surface includes a triangle, a trapezoid, a rectangle, or a bowl shape.

[0009] In some embodiments, the substrate further includes a via that communicates with the second trench, the via being located between the second trench and the second surface; the second semiconductor layer further fills the via.

[0010] In some embodiments, the semiconductor structure further includes a third gate located within the substrate, on the side of the second semiconductor layer away from the second gate, and at least partially opposite the second gate.

[0011] In some embodiments, the semiconductor structure further includes: an isolation layer located within the second trench, wherein the first semiconductor layer extends to the top surface of the isolation layer to make electrical contact with the second gate, the isolation layer covering the second gate located within the second trench; and a low-k dielectric layer located within the first trench and between the first gate and the second gate.

[0012] According to some embodiments of this disclosure, another aspect of this disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a substrate having opposing first and second surfaces, and having a trench extending from the first surface to the second surface within the substrate, the trench including a first trench and a second trench that are interconnected, the sidewall of the first trench being connected to the first surface, and the second trench being located between the first trench and the second surface; forming a first sub-semiconductor layer and a second semiconductor layer that are mutually discrete, the first sub-semiconductor layer extending from the first surface to the inner wall of the first trench, and the second semiconductor layer extending from the first surface sequentially to the inner wall of the first trench, the sidewall of the second trench, and the bottom surface of the second trench; forming a first gate and a second gate, the first gate being located on the side of the first sub-semiconductor layer opposite to the inner wall of the trench, and the second gate being located on the side of the second semiconductor layer opposite to the inner wall of the trench; forming a second sub-semiconductor layer covering the bottom surface of the second trench, and the second sub-semiconductor layer contacting the first sub-semiconductor layer and constituting the first semiconductor layer, the second sub-semiconductor layer further extending to contact the second gate; wherein the first gate and the first semiconductor layer are used to constitute a first transistor, and the second gate and the second semiconductor layer are used to constitute a second transistor.

[0013] In some embodiments, the first trench includes a first sidewall and a second sidewall opposite to each other along a first direction, and a third sidewall and a fourth sidewall opposite to each other along a second direction. The third sidewall and the fourth sidewall are both connected to the first sidewall and to the second sidewall, and the second direction intersects the first direction. The step of forming the first sub-semiconductor layer and the second semiconductor layer includes: forming an initial semiconductor layer extending from the first surface to the entire inner wall of the trench; removing at least a portion of the initial semiconductor layer on the third sidewall and the fourth sidewall, and further removing material from the second trench adjacent to the third sidewall and the fourth sidewall. The initial semiconductor layer on the sidewall of the fourth sidewall, the second trench sidewall adjacent to the first sidewall, and the bottom surface, and the remaining initial semiconductor layer in the trench are two separate parts; wherein, the first sub-semiconductor layer includes the remaining initial semiconductor layer on the surface of the first sidewall, the third sidewall, and the fourth sidewall adjacent to the first sidewall, and the second semiconductor layer includes the remaining initial semiconductor layer on the second sidewall, the initial semiconductor layer on the surface of the third sidewall and the fourth sidewall adjacent to the second sidewall, and the initial semiconductor layer in the second trench.

[0014] In some embodiments, the first trench includes a first sidewall and a second sidewall opposite to each other along a first direction; the step of forming the first sub-semiconductor layer, the second semiconductor layer, the first gate, and the second gate includes: forming an initial semiconductor layer, the initial semiconductor layer extending at least from the first surface to the first sidewall and the second sidewall, and continuing to extend sequentially to the inner wall of the second trench; forming an initial gate, the initial gate being formed on the side of the first sub-semiconductor layer and the second semiconductor layer opposite to the inner wall of the trench; in the same etching process step, removing the initial semiconductor layer and the initial gate on the inner wall of the second trench adjacent to the first sidewall, and retaining at least the remaining initial semiconductor layer and the initial gate located on the first sidewall, so as to respectively form the first sub-semiconductor layer and the first gate, and retaining the remaining initial semiconductor layer and the initial gate located on the second sidewall and connected to the second sidewall on the inner wall of the second trench, so as to respectively form the second semiconductor layer and the second gate.

[0015] In some embodiments, a via is further formed in the substrate, communicating with the second trench, and the via is located between the second trench and the second surface; in the step of forming the second semiconductor layer, the second semiconductor layer further fills the via.

[0016] The technical solutions provided in this disclosure have at least the following advantages:

[0017] The semiconductor structure provided in this disclosure includes a first gate and a second gate disposed separately in a trench. The first gate is located in the first trench, and the second gate extends from the first trench to the second trench. A first semiconductor layer extends from a first surface to the side of the first gate facing the inner wall of the first trench, and the first semiconductor layer is also in electrical contact with the second gate. By providing a trench, the problem of semiconductor structure miniaturization is solved. While ensuring that the semiconductor structure occupies a small layout space, the lengths of the first semiconductor layer, the second semiconductor layer, the first gate, and the second gate can be increased. This reduces the possibility of short-channel effects caused by the short channel length in the first and second semiconductor layers, and also helps to increase the facing area between the first gate and the first semiconductor layer, as well as the facing area between the second semiconductor layer and the second semiconductor layer, thereby improving the control capability of the first gate over the first semiconductor layer and the control capability of the second gate over the second semiconductor layer, and improving the electrical performance of the semiconductor structure. In addition, by placing the first gate and the second gate in the trench, the distance between the first gate and the second gate can be increased by adjusting the trench size, reducing the coupling effect between the first gate and the second gate. Attached Figure Description

[0018] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 A cross-sectional view of a first semiconductor structure provided in an embodiment of this disclosure, perpendicular to the first surface direction;

[0020] Figure 2 A cross-sectional view of a second semiconductor structure provided in an embodiment of this disclosure, perpendicular to the first surface.

[0021] Figure 3 A cross-sectional view of a third semiconductor structure provided in an embodiment of this disclosure, perpendicular to the first surface.

[0022] Figure 4 A cross-sectional view of a first trench parallel to a first surface in a semiconductor structure provided in an embodiment of this disclosure;

[0023] Figure 5 A cross-sectional view of a first trench parallel to a first surface in another semiconductor structure provided in an embodiment of this disclosure;

[0024] Figure 6 A cross-sectional view of a fourth semiconductor structure provided in an embodiment of this disclosure, perpendicular to the first surface.

[0025] Figure 7 A cross-sectional view of a fifth semiconductor structure provided in an embodiment of this disclosure, perpendicular to the first surface.

[0026] Figure 8 This is a simplified circuit diagram corresponding to a semiconductor structure provided in one embodiment of the present disclosure;

[0027] Figure 9 A simplified circuit diagram corresponding to another semiconductor structure provided in one embodiment of this disclosure;

[0028] Figures 10 to 14 This is a schematic diagram of the steps in a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure. Detailed Implementation

[0029] As can be seen from the background technology, the performance of current semiconductor structures needs to be improved.

[0030] The semiconductor structure provided in this disclosure, by forming trenches in a substrate, includes a first trench and a second trench that are interconnected. A first gate and a second gate, which are mutually independent, are disposed within the trenches. The first gate is located in the first trench, and the second gate extends from the first trench to the second trench. A first semiconductor layer extends from a first surface to the side of the first gate facing the inner wall of the first trench, and the first semiconductor layer is also in electrical contact with the second gate. A second semiconductor layer extends from the first surface to the side of the second gate facing the inner wall of the trench. The first gate and the first semiconductor layer are used to form a first transistor, and the second gate and the second semiconductor layer are used to form a second transistor. This trench configuration addresses the issue of semiconductor structure miniaturization, ensuring a small footprint for the semiconductor structure. While improving the layout space, increasing the lengths of the first semiconductor layer, the second semiconductor layer, the first gate, and the second gate can reduce the possibility of short-channel effects caused by excessively short channel lengths in the first and second semiconductor layers. It also helps to increase the facing area between the first gate and the first semiconductor layer, and between the second semiconductor layer, thereby improving the control capability of the first gate over the first semiconductor layer and the control capability of the second gate over the second semiconductor layer, thus improving the electrical performance of the semiconductor structure. Furthermore, placing the first and second gates in a trench allows for increasing the distance between them by adjusting the trench size, reducing the coupling effect between the first and second gates. The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0031] Figure 1 A cross-sectional view of a first semiconductor structure provided in an embodiment of this disclosure, perpendicular to the first surface direction; Figure 2 A cross-sectional view of a second semiconductor structure provided in an embodiment of this disclosure, perpendicular to the first surface. Figure 3 A cross-sectional view of a third semiconductor structure provided in an embodiment of this disclosure, perpendicular to the first surface. Figure 4 A cross-sectional view of a first trench parallel to a first surface in a semiconductor structure provided in an embodiment of this disclosure; Figure 5 A cross-sectional view of a first trench parallel to a first surface in another semiconductor structure provided in an embodiment of this disclosure; Figure 6 A cross-sectional view of a fourth semiconductor structure provided in an embodiment of this disclosure, perpendicular to the first surface. Figure 7 This is a cross-sectional view of a fifth semiconductor structure provided in an embodiment of the present disclosure, perpendicular to the first surface.

[0032] refer to Figure 1 The semiconductor structure includes: a substrate 100 having opposing first surfaces 10 and second surfaces 20, and a trench 101 extending from the first surface 10 to the second surface 20 within the substrate 100. The trench includes a first trench 102 and a second trench 103 that are connected to each other. The sidewall of the first trench 102 is connected to the first surface 10, and the second trench 103 is located between the first trench 102 and the second surface 20. The semiconductor structure includes a first gate 104 and a second gate 105 that are mutually discrete. The first gate 104 is located in the first trench 102, and the second gate 105 is located in the first trench 102 and extends into the second trench 103. The semiconductor structure includes a first semiconductor layer 106 that extends from the first surface 10 to the inner wall of the first trench 102, and is located on the side of the first gate 104 facing the inner wall of the first trench 102, and also extends to make an electrical contact with the second gate 105. The semiconductor structure includes a second semiconductor layer 107, which extends sequentially from the first surface 10 to the inner wall of the first trench 102, the sidewall of the second trench 103, and the bottom surface of the second trench 103. The second semiconductor layer 107 is located on the side of the second gate 105 facing the inner wall of the first trench 102 and the inner wall of the second trench 103.

[0033] The first gate 104 and the first semiconductor layer 106 are used to form the first transistor, and the second gate 105 and the second semiconductor layer 107 are used to form the second transistor.

[0034] By placing the first gate 104 and the second gate 105 within the trench 101, the lengths of the first gate 104 and the second gate 105 can be increased while maintaining a smaller layout space for the semiconductor structure. Furthermore, the distance between the first gate 104 and the second gate 105 can be increased by adjusting the trench size, reducing the coupling effect between them. The first semiconductor layer 106 and the second semiconductor layer 107 extend from the first surface 10 into the trench 101, increasing their lengths and simultaneously increasing the facing area of ​​the first gate 104 and the first semiconductor layer 106, as well as the facing area of ​​the second gate 105 and the second semiconductor layer 107. This enhances the control capability of the first gate 104 over the first semiconductor layer 106 and the second gate 105 over the second semiconductor layer 107, thereby improving the electrical performance of the semiconductor structure. In this way, the problem of semiconductor structure miniaturization can be solved, and the electrical performance of the semiconductor structure can be improved.

[0035] The length of the second semiconductor layer 107 refers to the length of the second semiconductor layer along its extension direction. The extension direction refers to the direction from the first surface to the inner wall of the first trench and then to the inner wall of the second trench.

[0036] The substrate 100 may be a single film layer, and the material of the substrate 100 may be a semiconductor material, including silicon, germanium, gallium nitride (GaN), gallium arsenide (GaAs), and indium phosphide (InP). In some embodiments, the substrate 100 may also be composed of multiple film layers. For example, the substrate 100 may include a substrate and a dielectric layer, wherein the surface of the dielectric layer away from the substrate is a first surface 10, the surface of the substrate away from the dielectric layer is a second surface 20, a trench 101 is located in the dielectric layer, the substrate is made of a semiconductor material, and the dielectric layer is made of a dielectric material such as silicon nitride, silicon oxide, silicon carbide, or silicon oxynitride.

[0037] The first semiconductor layer 106 may include a first source / drain region 16, a first channel region 26, and a second source / drain region 36 connected in sequence. The first semiconductor layer 106 on the first surface 10 serves as the first source / drain region 16. The first semiconductor layer 106 in the first trench 102 that is directly opposite the first gate 104 serves as the first channel region 26. The first semiconductor layer 106 in the first trench 102 other than the first channel region 26 serves as the second source / drain region 36. That is, the first semiconductor layer 106 that extends from the first channel region 26 to contact the second gate 105 serves as the second source / drain region 36.

[0038] The material of the first semiconductor layer 106 can be IGZO (Indium Gallium Zinc Oxide). The carrier mobility of IGZO is 20 to 50 times that of polycrystalline silicon, which is beneficial for improving the carrier mobility in the channel region of the first semiconductor layer 106 and also for increasing the charge and discharge rate of the semiconductor structure. This helps to reduce the leakage current of the first transistor during operation and improve the energy efficiency of the first transistor. In some embodiments, the material of the first semiconductor layer 106 can also be at least one of IWO (Indium Tungsten Oxide) or ITO (Indium Tin Oxide).

[0039] The first semiconductor layer 106 may also be doped with N-type ions or P-type ions. The first source / drain region 16 and the second source / drain region 36 have the same type of doped ions. N-type ions may include nitrogen ions, phosphorus ions, etc., and P-type ions may include boron ions, aluminum ions, etc. In some embodiments, the first transistor is a junction transistor, where the junction refers to a PN junction. The type of doped ions in the first source / drain region 16 is opposite to the type of doped ions in the first channel region 26. For example, the first source / drain region 16 and the second source / drain region 36 may be doped with N-type ions, and the first channel region 26 may be doped with P-type ions. In some embodiments, the first transistor is a junctionless transistor. The type of doped ions in the first source / drain region 16 is the same as the type of doped ions in the first channel region 26. For example, the first source / drain region 16, the second source / drain region 36, and the first channel region 26 may all be doped with P-type ions.

[0040] The second semiconductor layer 107 may include a third source / drain region 17, a second channel region 27, and a fourth source / drain region 37 connected in sequence. The second semiconductor layer 107 on the first surface 10 serves as the third source / drain region 17. The second semiconductor layer 107 in the first trench 102 and the second trench 103 that is directly opposite to the second gate 105 serves as the second channel region 27. The second semiconductor layer 107 in the second trench 103 other than the second channel region 27 serves as the fourth source / drain region 37.

[0041] The material of the second semiconductor layer 107 can be IGZO. IGZO material is beneficial for improving the carrier mobility in the channel region of the second semiconductor layer 107, and can also improve the charge and discharge rate of the semiconductor structure, thereby helping to reduce the leakage current during the operation of the second transistor and improve the energy efficiency of the second transistor. In some embodiments, the material of the second semiconductor layer 107 can also be at least one of IWO or ITO.

[0042] The second semiconductor layer 107 may also be doped with N-type or P-type ions. The third source / drain region 17 and the fourth source / drain region 37 have the same type of doped ions; N-type ions may include nitrogen ions, phosphorus ions, etc., and P-type ions may include boron ions, aluminum ions, etc. In some embodiments, the second transistor is a junction transistor, where the junction refers to a PN junction. The type of doped ions in the third source / drain region 17 is opposite to the type of doped ions in the second channel region 27. For example, the third source / drain region 17 and the fourth source / drain region 37 may be doped with N-type ions, and the second channel region 27 may be doped with P-type ions. In some embodiments, the second transistor is a junctionless transistor, and the type of doped ions in the third source / drain region 17 is the same as the type of doped ions in the second channel region 27. For example, the third source / drain region 17, the fourth source / drain region 37, and the second channel region 27 may all be doped with P-type ions.

[0043] The first gate 104 and the second gate 105 are both made of conductive materials, which may include polysilicon, tungsten, aluminum, molybdenum, ruthenium, titanium nitride or tantalum.

[0044] In some embodiments, a first gate dielectric layer 110 may be disposed on the surface of the first gate 104 facing the first semiconductor layer 106; and a second gate dielectric layer 111 may be disposed on the surface of the second gate 105 facing the second semiconductor layer 107. The materials of the first gate dielectric layer 110 and the second gate dielectric layer 111 are both dielectric materials, which may include hafnium dioxide, silicon oxide, silicon nitride, or silicon nitride.

[0045] refer to Figure 2 The semiconductor structure may further include a third gate 112, which is located within the substrate 100, on the side of the second semiconductor layer 107 away from the second gate 105, and at least partially opposite to the second gate 105. That is, the second transistor is a dual-gate transistor, and the threshold voltage of the second transistor is jointly controlled by the first gate 104 and the second gate 105, which facilitates flexible control of the second transistor's on / off state to improve the electrical performance of the semiconductor structure. The second gate dielectric layer 111 may also be disposed between the third gate and the second semiconductor layer 107. The material of the third gate 112 may be at least one of polysilicon, tungsten, aluminum, molybdenum, ruthenium, titanium nitride, or tantalum.

[0046] Continue to refer to Figure 2 The semiconductor structure may further include a low-k dielectric layer 116, which is located within the first trench 102 and between the first gate 104 and the second gate 105. The low-k dielectric layer 116 has a dielectric constant < 3.9 to reduce the parasitic capacitance between the first gate 104 and the second gate 105, thereby improving the electrical performance of the semiconductor structure. The material of the low-k dielectric layer 116 may be at least one of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide.

[0047] The dimensions and shapes of the first and second grooves are described in detail below.

[0048] refer to Figure 1 as well as Figure 2The cross-sectional shape of the first trench 102 perpendicular to the first surface 10 can be rectangular; the cross-sectional shape of the second trench 103 perpendicular to the first surface 10 can also be rectangular. The extension direction of the sidewall of the first trench 102 may not coincide with the extension direction of the corresponding sidewall of the second trench 103. The distance between the opposite sidewalls of the first trench 102 can be greater than the distance between the corresponding opposite sidewalls of the second trench 103. This increases the distance between the first gate and the second gate by increasing the size of the cross-section of the first trench 102 perpendicular to the first surface 10, reducing the coupling capacitance between the first gate and the second gate, and thus improving the electrical performance of the semiconductor structure. In some embodiments, the sidewall of the first trench 102 may also coincide with the extension direction of the corresponding sidewall of the second trench 103, that is, the cross-sectional shape of the trench perpendicular to the first surface 10 is rectangular.

[0049] refer to Figure 3 The cross-sectional shape of the first groove 102 perpendicular to the first surface 10 can be trapezoidal; the cross-sectional shape of the second groove 103 perpendicular to the first surface 10 can be triangular. The extension direction of the sidewall of the first groove 102 can coincide with the extension direction of the corresponding sidewall of the second groove 103, that is, the cross-sectional shape of the groove perpendicular to the first surface 10 is triangular. In some embodiments, the extension direction of the sidewall of the first trench 102 may not coincide with the extension direction of the corresponding sidewall of the second trench 103. The angle between the sidewall of the first trench 102 perpendicular to the first surface 10 and the first surface (here, "angle" refers to the acute angle formed by the sidewall of the first trench and the first surface) may be smaller than the angle between the corresponding sidewall of the second trench 103 and the first surface 10 (here, "angle" refers to the acute angle formed by the sidewall of the second trench and the first surface). This is to increase the distance between the first gate and the second gate by increasing the size of the cross-section of the first trench 102 in the direction perpendicular to the first surface 10, thereby reducing the coupling capacitance generated between the first gate and the second gate and improving the electrical performance of the semiconductor structure.

[0050] In some embodiments, the cross-sectional shape of the first groove 102 along the direction of the first surface 10 may be bowl-shaped. In some embodiments, the cross-sectional shape of the second groove 103 along the direction of the first surface 10 may be bowl-shaped.

[0051] It should be noted that the shape of the first groove 102 is not related to the shape of the second groove 103. It is only necessary that the first groove 102 and the second groove 103 are connected. The embodiments disclosed herein do not limit the shape of the first groove 102 and the second groove 103.

[0052] In some embodiments, the orthographic projection of the second groove 103 on the second surface 20 is located within the orthographic projection of the first groove 102 on the second surface 20. That is, the distance between at least one pair of sidewalls of the first groove 102 is greater than the distance between the corresponding pair of sidewalls in the second groove 103, and the distance between the remaining opposite sidewalls of the first groove 102 is not less than the distance between the corresponding opposite sidewalls in the second groove 103.

[0053] It should be noted that if the sidewall extending direction of the first groove 102 coincides with the extending direction of the second groove 103, then the sidewalls of the first groove 102 and the corresponding sidewalls of the second groove 103 are connected, so that the first groove 102 and the second groove 103 are connected, and the inner wall of the first groove 102 is the sidewall of the first groove 102; if the sidewall extending direction of the first groove 102 does not coincide with the sidewall extending direction of the second groove 103, and the orthographic projection of the second groove 103 on the second surface 20 is located within the orthographic projection of the first groove 102 on the second surface 20, then the first groove 102 also has a bottom surface, and the inner wall of the first groove 102 is the sidewall and the bottom surface of the first groove 102. The inner wall of the second groove 103 is the sidewall and the bottom surface of the second groove 103.

[0054] refer to Figure 4 In some embodiments, the first trench includes a first sidewall 108 and a second sidewall 109 opposite each other along a first direction X, a first semiconductor layer 106 is located at least on the first sidewall 108 and extends to contact the first gate 104, and a second semiconductor layer 107 is located at least on the second sidewall 109 and also extends to the inner wall of the second trench 103.

[0055] For example, the first semiconductor layer 106 may be located on the first sidewall and not in contact with the sidewall connected to the first sidewall 108, and the second semiconductor layer 107 may be located on the second sidewall 109 and not in contact with the sidewall connected to the second sidewall 109. Alternatively, the first semiconductor layer 107 may be located on the first sidewall 108 and also on the sidewall connected to the first sidewall 108, and the second semiconductor layer 107 may be located on the second sidewall 109 and also on the sidewall connected to the second sidewall 109, thereby increasing the surface area of ​​the first semiconductor layer 106 by utilizing the multiple sidewalls of the first trench, thus improving the performance of the semiconductor structure.

[0056] refer to Figure 4 In some embodiments, the orthographic projection of the first gate 104 onto the second surface 20 can be rectangular, and the orthographic projection of the second gate 105 onto the second surface 20 can also be rectangular. For example, in the first trench 102, the first gate 104 extends only on the surface of the first semiconductor layer on the first sidewall, and the second gate 105 extends only on the surface of the second semiconductor layer on the second sidewall and the bottom surface connected to the second sidewall. (See reference...) Figure 5In some embodiments, the orthographic projection of the first gate 104 on the second surface 20 can be U-shaped, and the orthographic projection of the second gate 105 on the second surface 20 can be U-shaped. This is beneficial to increase the facing area between the first gate 104 and the first semiconductor layer 106, thereby improving the control capability of the first gate 104 over the first semiconductor layer 106, and thus improving the electrical performance of the semiconductor structure.

[0057] refer to Figure 6 The substrate 100 may also have a via 113 communicating with the second trench 103, the via 113 being located between the second trench 103 and the second surface 20; the second semiconductor layer 107 further fills the via 113 to increase the length of the second semiconductor layer 107 by providing the via. The second semiconductor layer 107 on the first surface 10 serves as the third source / drain region 17, the second semiconductor layer 107 in the first trench 102 and the second trench 103 serves as the second channel region 27, and the second semiconductor layer 107 in the via 113 serves as the fourth source / drain region 37.

[0058] In some embodiments, the semiconductor structure may further include an isolation layer 114 located within the second trench 103, and the first semiconductor layer 106 extending to the top surface of the isolation layer 114 to make electrical contact with the second gate 105. The isolation layer 114 covers the second gate 105 located within the second trench 103. By providing the isolation layer 114, the bottom surface of the first trench 102 extends to the first semiconductor layer 106 that contacts the second gate 105, preventing the first semiconductor layer 106 from collapsing and improving the reliability of the semiconductor structure.

[0059] In some embodiments, the second semiconductor layer 107 further extends between the isolation layer 114 and the bottom surface of the second trench 103, the second gate 105 is directly opposite the sidewall of the isolation layer 114, the second semiconductor layer 107 between the isolation layer 114 and the second trench 103 serves as the fourth source / drain region 37 of the second transistor, and the remaining second semiconductor layer 107 located in the second trench 103 and the first trench 102 serves as the second channel region 27.

[0060] The isolation layer 114 is made of a dielectric material to reduce the possibility of leakage while supporting the first semiconductor layer 106. For example, the isolation layer 114 can be made of silicon nitride. Silicon nitride is relatively dense and can provide good support. In addition, the semiconductor layer made of IGZO material is sensitive to oxygen and hydrogen elements in the external environment. The silicon nitride covering the bottom surface of the second source / drain region 36 can prevent oxygen and hydrogen elements in the external environment from penetrating the second source / drain region 36 from the bottom surface, thus ensuring the performance of the second source / drain region 36 and improving the performance of the semiconductor structure.

[0061] The top surface of the isolation layer 114 is flush with the top of the second trench to ensure good contact between the second source / drain area 36 and the first channel area 26.

[0062] It is understood that in some embodiments, the space below the second source / drain region 36 that is not filled by the second gate, the second semiconductor layer and the second gate dielectric layer is small, and the isolation layer 114 may not be provided.

[0063] In some embodiments, a raised portion 115 may be provided between the isolation layer 114 and the bottom surface of the second trench 103. The surface of the raised portion 115 facing the isolation layer 114 is flush with the top surface of the second semiconductor layer 107 on the bottom surface of the second trench 103. By providing the raised portion 115, the possibility of unevenness of the top surface of the deposited isolation layer during the step of forming the isolation layer 114 is reduced, thereby reducing the unevenness of the first semiconductor layer 106 on the top surface of the isolation layer 114, and reducing the possibility that the unevenness of this part of the first semiconductor layer 106 will cause poor contact between the first semiconductor layer 106 and the second gate 105.

[0064] Figure 8 This is a simplified circuit diagram corresponding to a semiconductor structure provided in one embodiment of the present disclosure.

[0065] refer to Figure 8 as well as Figure 1 In the semiconductor structure provided in this embodiment, the first transistor 1 is a write transistor, and the second transistor 2 is a read transistor. The first transistor 1 and the second transistor 2 constitute a single-gate 2TOC type memory cell. In the second transistor 2, the second gate 105, which is electrically connected to the second source / drain region 36, can be used as a charge storage electrode layer (i.e., a capacitor electrode layer), and the second gate dielectric layer can be used as a charge storage dielectric layer (i.e., a capacitor dielectric layer) for storing signal information. The electrically connected second source / drain region 36 and the second gate 105 constitute a memory node SN. The memory cell structure composed of the read transistor and the write transistor is a 2TOC type memory cell structure, which eliminates the need for capacitors, thereby reducing the size of the semiconductor structure and increasing the integration density of the semiconductor structure.

[0066] The semiconductor structure also includes a write word line (WWL), a write bit line (WBL), a read word line (RWL), and a read bit line (RBL). The first gate 104 of the first transistor, which serves as the write transistor, is electrically connected to the write word line (WWL). The first source / drain region 16 of the first transistor is electrically connected to the write bit line (WBL). The third source / drain region 17 and the fourth source / drain region 37 of the second transistor are electrically connected to the read word line (RWL) and the read bit line (RBL), respectively.

[0067] The steps for performing a write operation on the semiconductor structure provided in this embodiment may include: applying a voltage to the write word line WWL to turn on the write transistor, and applying a voltage to the write bit line WBL to charge the memory node SN, so that the memory node SN presents a high voltage or a low voltage, representing data 1 and 0 respectively; during the write operation on the memory node SN, no voltage is applied to the read word line RWL so as not to provide a voltage signal to the gate of the read transistor that is electrically connected to the read word line RWL.

[0068] The steps for performing a read operation on the semiconductor structure provided in this embodiment may include: when reading "1", applying a voltage to the read word line RWL to provide a voltage signal to the gate electrically connected to the read word line RWL. Since there is a certain charge in the memory structure, current flows between the read line RBL and the read word line RWL. The memory node SN is read by detecting the magnitude of the current in the read bit line RBL; when reading "0", applying a read voltage to the read word line RWL in the read transistor. Since there is no charge in the memory node, no current flows or a small current flows between the read bit line RBL and the read word line RWL. No current is read on the read bit line RBL, thus completing the reading process of data 0.

[0069] Figure 9 This is another simplified circuit diagram corresponding to another semiconductor structure provided in an embodiment of the present disclosure.

[0070] refer to Figure 9 In some embodiments, the first transistor 1 is a write transistor, and the second transistor 2 is a read transistor. The second transistor also has a third gate 112. The first transistor 1 and the second transistor 2 constitute a dual-gate 2TOC type memory cell. The write word line WWL is electrically connected to the first gate 104, the first source-drain region 16 is electrically connected to the bit line BL, the second source-drain region 36 is electrically connected to the second gate 105, one of the third source-drain region 17 and the fourth source-drain region 37 is electrically connected to the bit line BL, and the third gate 112 is electrically connected to the read word line RWL.

[0071] In the second transistor 2, the second gate 105, electrically connected to the second source / drain region 36, can be used as a charge storage electrode layer (i.e., a capacitor electrode layer), and the second gate dielectric layer can be used as a charge storage dielectric layer (i.e., a capacitor dielectric layer) for storing signal information. The electrically connected second source / drain region 36 and second gate 105 constitute a storage node SN. The storage cell structure, composed of read and write transistors, is a 2TOC type storage cell structure, eliminating the need for capacitors. This reduces the size of the storage cell structure itself, thereby increasing its integration density.

[0072] The method of using the two gates of the read transistor to perform data storage and read / write operation control is explained in detail.

[0073] The steps for performing a write operation on the semiconductor structure provided in this embodiment may include: applying a voltage to the write word line WWL to turn on the write transistor, and applying a voltage to the bit line BL to charge the memory node SN, so that the memory node SN presents a high voltage or a low voltage, representing data 1 and 0 respectively; during the write operation of the memory node SN, no voltage is applied to the read word line RWL so as not to provide a voltage signal to the gate of the read transistor that is electrically connected to the read word line RWL.

[0074] The steps for performing a read operation on the semiconductor structure provided in this embodiment may include: applying a voltage to the read word line RWL to provide a voltage signal to the gate electrically connected to the read word line RWL, and applying a voltage to the source-drain region of the read transistor that is not electrically connected to the bit line BL; determining the potential level at the memory structure SN by detecting the magnitude of the current in the bit line BL, so as to perform a read operation on the memory node SN; and not providing a voltage signal to the third gate during the read operation on the memory node SN.

[0075] The read transistor 201 provided in the aforementioned embodiment is a dual-gate transistor. Compared with a single-gate transistor, the dual-gate read transistor uses the read word line RWL to perform read operations on the gate of the read transistor that is electrically connected to the read word line RWL. This is beneficial to use the two gates of the first transistor 1 to complete data storage and read / write operation control respectively. Based on the advantage of gate-controlled read / write operations, the read / write operation of the constructed 2TOC type memory cell structure is more flexible.

[0076] Furthermore, the storage cell structure is controlled by two word lines (the first word line WWL and the second word line RWL) and one bit line BL, which reduces the number of bit lines required for the storage cell structure. This helps to further reduce the overall size of the storage cell structure and the wiring complexity in the storage array structure, thereby helping to further improve the integration density of the storage array structure.

[0077] Furthermore, since the second word line RWL in the memory array structure is electrically connected to one of the first gate and the second gate in the read transistor, the current flowing through the second word line RWL is very small and can be considered as 0. Therefore, the current flowing through the second word line RWL will not affect the number of first transistors 1 electrically connected to the same second word line RWL, which is beneficial to improving the storage density of the memory array structure.

[0078] Accordingly, another embodiment of this disclosure also provides a method for manufacturing a semiconductor structure. The semiconductor structure provided in the foregoing embodiments can be manufactured using this method. The semiconductor structure provided in another embodiment of this disclosure will be described in detail below with reference to the accompanying drawings. For parts that are the same as or corresponding to the previous embodiment, please refer to the corresponding descriptions in the foregoing embodiments; detailed descriptions will not be repeated hereafter. Figures 10 to 14 This is a schematic diagram of the steps in a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure.

[0079] refer to Figure 10 A substrate 100 is provided, the substrate having a first surface 10 and a second surface 20 opposite to each other, and a groove 101 extending from the first surface 10 to the second surface 20 is provided in the substrate. The groove 101 includes a first groove 102 and a second groove 103 that are connected to each other. The sidewall of the first groove 102 is connected to the first surface 10, and the second groove 103 is located between the first groove 102 and the second surface 20.

[0080] The substrate 100 may be a single film layer, and the material of the substrate 100 may be a semiconductor material, including silicon, germanium, gallium nitride (GaN), gallium arsenide (GaAs), and indium phosphide (InP). In some embodiments, the substrate 100 may also be composed of multiple film layers. For example, the substrate 100 may include a substrate and a dielectric layer, wherein the surface of the dielectric layer away from the substrate is a first surface 10, the surface of the substrate away from the dielectric layer is a second surface 20, a trench 101 is located in the dielectric layer, the substrate is made of a semiconductor material, and the dielectric layer is made of a dielectric material such as silicon nitride, silicon oxide, silicon carbide, or silicon oxynitride.

[0081] In some embodiments, the orthographic projection of the second trench 103 on the second surface 20 lies within the orthographic projection of the first trench 102 on the second surface 20. In some embodiments, the orthographic projection of the second trench 103 on the second surface 20 and the orthographic projection of the first trench 102 on the second surface 20 both lie within each other. That is, the dimension of the cross-section of the first trench perpendicular to the first surface is greater than the dimension of the cross-section of the second trench perpendicular to the first surface. For example, the distance between at least one pair of sidewalls of the first trench can be greater than the distance between corresponding opposite sidewalls in the second trench 103, and the distance between the remaining opposite sidewalls of the first trench 102 is not less than the distance between corresponding opposite sidewalls in the second trench 103. By setting the cross-sectional dimension of the first trench 102 perpendicular to the first surface 10 to be larger, it is beneficial to increase the distance between the first gate and the second gate subsequently formed in the first trench 102, reduce the coupling capacitance generated between the first gate and the second gate, and improve the electrical performance of the formed semiconductor structure. This embodiment does not limit the size of the formed second trench 103 and first trench 102, as long as the first trench 102 and the second trench 103 are connected.

[0082] In some embodiments, a via 113 communicating with the second trench may also be formed within the substrate 100. The via 113 is located between the second trench 103 and the second surface 20, and is used to accommodate a second semiconductor layer formed in subsequent steps to increase the length of the second semiconductor layer along the extension direction. The via 113 and the trench can be formed using a double damascene process. For example, the via 113 and the initial trench are formed using a double damascene process, and then conventional processes such as etching are used to increase the size of the region adjacent to the first surface 10 of the initial trench to form the first trench 102 and the second trench 103.

[0083] refer to Figure 13 A first sub-semiconductor layer 206 and a second semiconductor layer 107 are formed, which are mutually independent. The first sub-semiconductor layer 206 extends from the first surface to the inner wall of the first trench 102, and the second semiconductor layer 107 extends from the first surface 10 to the inner wall of the first trench 102, the side wall of the second trench 103 and the bottom surface of the second trench 103 in sequence.

[0084] The material of the first sub-semiconductor layer 206 may include IGZO. The carrier mobility of IGZO is 20 to 50 times that of polycrystalline silicon, which is beneficial for improving the carrier mobility of the first channel region 26 in the first semiconductor layer 106, and also for increasing the charge and discharge rate of the semiconductor structure. This helps to reduce the leakage current of the transistor constructed from this semiconductor structure during operation and improves the transistor's energy efficiency. In some embodiments, the material of the first sub-semiconductor layer 206 may also be at least one of IWO or ITO.

[0085] The material of the second semiconductor layer 107 can be IGZO. IGZO material is beneficial for improving the carrier mobility in the channel region of the second semiconductor layer 107, and can also improve the charge and discharge rate of the semiconductor structure, thereby helping to reduce the leakage current during the operation of the second transistor and improve the energy efficiency of the second transistor. In some embodiments, the material of the second semiconductor layer 107 can also be at least one of IWO or ITO.

[0086] The processes for fabricating the first sub-semiconductor layer 206 and the second semiconductor layer 107 can be chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0087] In some embodiments, a first sub-semiconductor layer 206 and a second semiconductor layer 107 may be formed in the same process step, wherein the material of the first sub-semiconductor layer 206 and the material of the second semiconductor layer 107 are the same.

[0088] Taking the first groove 102 and the second groove 103 as examples, where the inner cavity is a cuboid structure. In some embodiments, the first groove 102 may include a first sidewall and a second sidewall opposite to each other along the first direction X, and a third sidewall and a fourth sidewall opposite to each other along the second direction Y. The third sidewall and the fourth sidewall are both connected to the first sidewall and to the second sidewall, and the second direction intersects the first direction.

[0089] The steps of forming the first sub-semiconductor layer 206 and the second semiconductor layer 107 may include: forming an initial semiconductor layer that extends from the first surface to the entire inner wall of the trench 101; removing at least a portion of the initial semiconductor layer on the third and fourth sidewalls, and also removing the initial semiconductor layer on the sidewalls of the second trench adjacent to the third and fourth sidewalls, and the sidewalls and bottom surface of the second trench adjacent to the first sidewall, with the remaining initial semiconductor layer in the trench being two separate parts; wherein, the first sub-semiconductor layer 206 includes the remaining initial semiconductor layer on the surface of the first, third, and fourth sidewalls adjacent to the first sidewall, and the second semiconductor layer includes the remaining initial semiconductor layer on the second sidewall, the initial semiconductor layer on the surface of the third and fourth sidewalls adjacent to the second sidewall, and the initial semiconductor layer in the second trench.

[0090] That is, the orthographic projection of the first sub-semiconductor layer 206 on the second surface 20 of the first trench sidewall is U-shaped, and the orthographic projection of the second semiconductor layer 107 on the second surface 20 of the first trench sidewall is U-shaped. The surface areas of the first sub-semiconductor layer and the second sub-semiconductor layer opposite to the corresponding trench sidewalls are large. In subsequent steps, a first gate covering the first sub-semiconductor layer and a second gate covering the second semiconductor layer are formed in the trench. Thus, the orthographic projection of the first gate on the second surface is also U-shaped, and the orthographic projection of the second gate at two points on the second surface is also U-shaped. The facing area of ​​the first gate and the first sub-semiconductor layer is large, and the facing area of ​​the second gate and the second semiconductor layer is also large, which is beneficial to improving the gate control capability and improving the performance of the formed semiconductor structure.

[0091] It is understandable that the first sub-semiconductor layer 206 and the second semiconductor layer 107 can also be formed in different process steps.

[0092] The first sub-semiconductor layer 206 includes a first source / drain region 16 and a first channel region 26 connected together. The first sub-semiconductor layer 206 on the first surface 10 serves as the first source / drain region 16, the first sub-semiconductor layer 206 in the first trench 102 serves as the first channel region 26, and the second sub-semiconductor layer formed subsequently serves as the second source / drain region.

[0093] The second semiconductor layer 107 may include a third source / drain region 17, a second channel region 27, and a fourth source / drain region 37 connected in sequence. The second semiconductor layer 107 on the first surface 10 serves as the third source / drain region 17. The second semiconductor layer in the first trench 102, the second semiconductor layer on the sidewall of the second trench 103, and the second semiconductor layer on the bottom surface adjacent to the sidewall serve as the second channel region 27. The second semiconductor layer in the second trench 103, excluding the second channel region 27 and located on the bottom surface of the second trench 103, serves as the fourth source / drain region 37. In some embodiments, a via 113 communicating with the second trench 103 is also formed in the substrate 100. The via 113 is located between the second trench 103 and the second surface 20. In the step of forming the second semiconductor layer 107, the second semiconductor layer further fills the via 113. The second semiconductor layer 107 in the first trench 102 and the second trench 103 can be used as the second channel region, and the second semiconductor layer in the via 113 can be used as the fourth source / drain region.

[0094] In some embodiments, N-type ions or P-type ions can be doped into the first sub-semiconductor layer 206 and the second semiconductor layer 107 through processes such as diffusion or ion implantation. N-type ions may include nitrogen ions, phosphorus ions, etc., and P-type ions may include boron ions, aluminum ions, etc. The doped ion types of the first source / drain region 16 and the first channel region 26 may be the same or different; the doped ion types of the third source / drain region 17 and the fourth source / drain region 37 are the same, while the doped ion types of the second channel region 27 and the fourth source / drain region 37 may be the same or different.

[0095] refer to Figure 13 A first gate 104 and a second gate 105 are formed. The first gate 104 is located on the side of the first sub-semiconductor 206 layer away from the inner wall of the trench 101, and the second gate 105 is located on the side of the second semiconductor layer 107 away from the inner wall of the trench 101.

[0096] The material of the first gate 104 can be at least one of polysilicon, tungsten, aluminum, molybdenum, ruthenium, titanium nitride, or tantalum. The material of the second gate 105 can be at least one of polysilicon, tungsten, aluminum, molybdenum, ruthenium, titanium nitride, or tantalum. The materials of the first gate 104 and the second gate 105 can be the same, and the first gate 104 and the second gate 105, which are made of the same material, can be made from the same original gate. Alternatively, the materials of the first gate 104 and the second gate 105 can be different, and the first gate 104 and the second gate 105 can be made in different process steps. The processes for forming the first gate 104 and the second gate 105 can both include chemical vapor deposition, electroplating, atomic layer deposition, or physical vapor deposition.

[0097] Before forming the first gate 104 and the second gate 105, a first gate dielectric layer 110 and a second gate dielectric layer 111 are also formed in the trench 101. The first gate dielectric layer 110 is located on the surface of the first sub-semiconductor layer away from the trench 101. The first gate 104 is formed on the surface of the first gate dielectric layer 110 away from the first sub-semiconductor layer. The first gate dielectric layer 110 is used to isolate the first sub-semiconductor layer 206 and the first gate 104. The second gate dielectric layer 111 is located on the surface of the second semiconductor layer 107 away from the trench 101. The second gate 105 is formed on the surface of the second gate dielectric layer 111 away from the second semiconductor layer 107. The second gate 105 is used to isolate the second gate 105 from the second semiconductor layer 107.

[0098] Figures 11 to 13 This is a schematic diagram of the structure corresponding to each step of a method for forming a first sub-semiconductor layer, a second semiconductor layer, a first gate, and a second gate, provided in an embodiment of this disclosure.

[0099] refer to Figures 11 to 13 The first trench 102 includes a first sidewall 108 and a second sidewall 109 opposite each other along a first direction; the steps of forming a first sub-semiconductor layer 206, a second semiconductor layer 107, a first gate 104, and a second gate 105 include: forming an initial semiconductor layer 201, the initial semiconductor layer 201 extending at least from the first surface 10 to the first sidewall 108 and the second sidewall 109, and continuing to extend sequentially to the inner wall of the second trench 103; forming an initial gate 202, the initial gate 202 being formed on the back of the first sub-semiconductor layer 206 and the second semiconductor layer 107. On the side away from the inner wall of trench 101; in the same etching process step, the initial semiconductor layer and initial gate on the inner wall of the second trench 103 adjacent to the first sidewall 108 are removed, while at least the remaining initial semiconductor layer and initial gate on the first sidewall 108 are retained to form the first sub-semiconductor layer 206 and the first gate 104, respectively. The remaining initial semiconductor layer and initial gate on the inner wall of the second trench 103 connected to the second sidewall 109 are retained to form the second semiconductor layer 107 and the second gate 105, respectively. Thus, patterning the initial semiconductor layer and initial gate in the same process step helps reduce process complexity.

[0100] Before forming the initial gate, an initial gate dielectric layer 203 is formed on the initial semiconductor layer. In the same etching process step, in the step of removing the initial semiconductor layer and the initial gate on the inner wall of the second trench 103 adjacent to the first sidewall 108, the initial gate dielectric layer 203 on the inner wall adjacent to the first sidewall 108 is also removed. The remaining initial gate dielectric layer 203 located between the first sub-semiconductor layer and the first gate is used as the first gate dielectric layer 110, and the remaining initial gate dielectric layer located between the second semiconductor layer and the second gate is used as the second gate dielectric layer 111.

[0101] In some embodiments, a third gate (not shown) may be formed before the formation of the second semiconductor layer 107. The third gate is located within the substrate 100, and the third gate and the subsequently formed second gate are located on opposite sides of the second semiconductor layer 107. The third gate is located on the side of the second semiconductor layer away from the first semiconductor layer 106, and the third gate and the second gate 105 are at least partially opposite each other. A second gate dielectric layer may also be formed between the third gate and the second semiconductor layer 107. The second gate and the third gate are subsequently used to form a dual-gate transistor. By jointly controlling the threshold voltage of the transistor through the second gate and the third gate, it is beneficial to flexibly control the conduction or turn-off of the transistor, thereby improving the electrical performance of the semiconductor structure.

[0102] refer to Figure 14 A second sub-semiconductor layer 306 is formed, which covers the bottom surface of the second trench 103 and contacts the first sub-semiconductor layer 206 to form the first semiconductor layer 106. The second sub-semiconductor layer 306 also extends to contact the second gate 105.

[0103] The second sub-semiconductor layer 306 serves as the second source / drain region 36. The material of the second sub-semiconductor layer 306 can be IGZO, IWO, or ITO. The material of the second sub-semiconductor layer 306 can be the same as that of the first sub-semiconductor layer 206 to ensure good interfacial contact between them. In some embodiments, the material of the second sub-semiconductor layer 306 can be different from that of the first sub-semiconductor layer 206. The second sub-semiconductor layer 306 may also be doped with N-type or P-type ions.

[0104] Before forming the second sub-semiconductor layer 306, an isolation layer 114 can be formed in the second trench 103. The isolation layer 114 covers the sidewalls not covered by the second gate and the second semiconductor layer, and also contacts the surface of the second gate 105 facing the first semiconductor layer. The top surface of the isolation layer 114 can be flush with the top of the second trench 103. By providing the isolation layer 114, the bottom surface of the first trench 102 extends to the first semiconductor layer 106 in contact with the second gate 105, preventing the first semiconductor layer 106 from collapsing and improving the reliability of the semiconductor structure. The isolation layer 114 is made of a dielectric material to reduce the possibility of leakage while supporting the first semiconductor layer 106. For example, the material of the isolation layer 114 can be silicon nitride. Silicon nitride is relatively dense and can provide good support. In addition, the semiconductor layer made of IGZO material is sensitive to oxygen and hydrogen elements in the external environment. The silicon nitride covering the bottom surface of the first semiconductor layer that contacts the second gate can prevent oxygen and hydrogen elements in the external environment from penetrating into this part of the first semiconductor layer from the bottom surface of the second source / drain region 36, ensuring the performance of the first semiconductor layer and improving the performance of the formed semiconductor structure. It can be understood that after the second gate, the second semiconductor layer, and the second gate dielectric layer are formed, the remaining space in the second trench 103 is small, and the isolation layer 114 to support the second source / drain region 36 may not be provided.

[0105] In some embodiments, a raised portion 115 may be formed between the isolation layer 114 and the bottom surface of the second trench 103. The surface of the raised portion 115 facing the isolation layer 114 is flush with the top surface of the second semiconductor layer 107 at the bottom surface of the second trench 103. By providing the raised portion 115, the possibility of unevenness of the top surface of the deposited isolation layer during the step of forming the isolation layer 114 is reduced, thereby reducing the unevenness of the first semiconductor layer 106 on the top surface of the isolation layer 114, and reducing the possibility that the unevenness of this part of the first semiconductor layer 106 will cause poor contact between the first semiconductor layer 106 and the second gate 105.

[0106] In some embodiments, after forming the first gate and the second gate, a low-k dielectric layer 116 is also formed in the first trench 102, located between the first gate 104 and the second gate 105 in the first trench 102. The low-k dielectric layer 116 is a dielectric layer with a dielectric constant < 3.9, to reduce the parasitic capacitance generated between the first gate 104 and the second gate 105, which is beneficial to improving the electrical performance of the semiconductor structure. The material of the low-k dielectric layer 116 can be at least one of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide.

[0107] In the semiconductor structure formed in this embodiment, a first gate 104 and a first semiconductor layer 106 are used to form a first transistor, and a second gate 105 and a second semiconductor layer 107 are used to form a second transistor. The first transistor is a write transistor, and the second transistor can be a read transistor. The first transistor and the second transistor constitute a single-gate 2TOC type memory cell. In the second transistor, the second gate 105, which is electrically connected to the second source-drain region 36, can be used as a charge storage electrode layer (i.e., a capacitor electrode layer), and the second gate dielectric layer can be used as a charge storage dielectric layer (i.e., a capacitor dielectric layer) for storing signal information. The electrically connected second source-drain region 36 and the second gate 105 constitute a memory node SN. The memory cell structure formed by the read transistor and the write transistor is a 2TOC type memory cell structure, which does not require capacitors, which is beneficial to reduce the size of the semiconductor structure itself and improve the integration density of the semiconductor structure. In some embodiments, a third gate 112 is also formed. The second transistor, including the third gate 112, the second gate 105, and the second semiconductor layer 107, is a dual-gate transistor. The first transistor and the second transistor constitute a dual-gate 2TOC type memory cell. On the one hand, the memory cell structure, consisting of read and write transistors, is a 2TOC type memory cell structure, eliminating the need for capacitors. This helps reduce the size of the memory cell structure itself, thereby increasing its integration density. On the other hand, compared to a single-gate 2TOC type memory cell, it reduces the number of bit lines required in the semiconductor structure, which further helps reduce the overall size of the semiconductor structure and the wiring complexity, thus further improving the integration density of the semiconductor structure.

[0108] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make various alterations and modifications without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate having opposing first and second surfaces, and having a groove extending from the first surface to the second surface within the substrate, the groove including a first groove and a second groove that are connected, the sidewall of the first groove being connected to the first surface, and the second groove being located between the first groove and the second surface; A first gate and a second gate are mutually independent, the first gate being located in the first trench and the second gate being located in the first trench and extending into the second trench; A first semiconductor layer extends from the first surface to the inner wall of the first trench and is located on the side of the first gate facing the inner wall of the first trench, and also extends to the second gate electrical contact. The second semiconductor layer extends sequentially from the first surface to the inner wall of the first trench, the side wall of the second trench, and the bottom surface of the second trench. The second semiconductor layer is located on the side of the second gate facing the inner wall of the first trench and the inner wall of the second trench. Wherein, the first gate and the first semiconductor layer are used to form a first transistor, and the second gate and the second semiconductor layer are used to form a second transistor.

2. The semiconductor structure according to claim 1, characterized in that, The first trench includes a first sidewall and a second sidewall opposite to each other along a first direction, the first semiconductor layer is located at least on the first sidewall and extends to contact the second gate, the second semiconductor layer is located at least on the second sidewall and also extends to the inner wall of the second trench; wherein the first direction is perpendicular to the first surface.

3. The semiconductor structure according to claim 2, characterized in that, The orthographic projection of the first gate on the second surface is a rectangle, and the orthographic projection of the second gate on the second surface is a rectangle; or, the orthographic projection of the first gate on the second surface is a U-shape, and the orthographic projection of the second gate on the second surface is a U-shape.

4. The semiconductor structure according to any one of claims 1-3, characterized in that, The cross-sectional shape of the first groove perpendicular to the first surface includes a trapezoid, a rectangle, or a bowl shape; the cross-sectional shape of the second groove perpendicular to the first surface includes a triangle, a trapezoid, a rectangle, or a bowl shape.

5. The semiconductor structure according to claim 1, characterized in that, The substrate also has a through-hole communicating with the second trench, the through-hole being located between the second trench and the second surface; the second semiconductor layer further fills the through-hole.

6. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a third gate located within the substrate, on the side of the second semiconductor layer away from the second gate, and at least partially opposite the second gate.

7. The semiconductor structure according to claim 1, characterized in that, Semiconductor structures also include: An isolation layer is located within the second trench, and the first semiconductor layer extends to the top surface of the isolation layer to make electrical contact with the second gate, the isolation layer covering the second gate located within the second trench; a low-k dielectric layer is located within the first trench and between the first gate and the second gate.

8. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided having opposing first and second surfaces, and a groove extending from the first surface to the second surface within the substrate, the groove including a first groove and a second groove that are connected, the sidewall of the first groove being connected to the first surface, and the second groove being located between the first groove and the second surface. A first sub-semiconductor layer and a second semiconductor layer are formed, which are mutually independent. The first sub-semiconductor layer extends from the first surface to the inner wall of the first trench, and the second semiconductor layer extends from the first surface to the inner wall of the first trench, the side wall of the second trench, and the bottom surface of the second trench in sequence. A first gate and a second gate are formed, wherein the first gate is located on the side of the first sub-semiconductor layer opposite to the inner wall of the trench, and the second gate is located on the side of the second semiconductor layer opposite to the inner wall of the trench; A second sub-semiconductor layer is formed, which covers the bottom surface of the second trench and contacts the first sub-semiconductor layer to form the first semiconductor layer. The second sub-semiconductor layer also extends to contact the second gate. Wherein, the first gate and the first semiconductor layer are used to form a first transistor, and the second gate and the second semiconductor layer are used to form a second transistor.

9. The method for manufacturing a semiconductor structure according to claim 8, characterized in that, The first trench includes a first sidewall and a second sidewall opposite to each other along a first direction, and a third sidewall and a fourth sidewall opposite to each other along a second direction. The third sidewall and the fourth sidewall are both connected to the first sidewall and to the second sidewall. The second direction intersects the first direction. The steps of forming the first sub-semiconductor layer and the second semiconductor layer include: An initial semiconductor layer is formed, the initial semiconductor layer extending from the first surface to the entire inner wall of the trench; At least a portion of the initial semiconductor layer on the third sidewall and the fourth sidewall is removed, and the initial semiconductor layer on the sidewall of the second trench adjacent to the third sidewall and the fourth sidewall, as well as on the sidewall and bottom surface of the second trench adjacent to the first sidewall, is also removed. The remaining initial semiconductor layer in the trench consists of two separate parts. The first sub-semiconductor layer includes the initial semiconductor layer remaining on the surface of the first sidewall, the third sidewall, and the fourth sidewall adjacent to the first sidewall. The second semiconductor layer includes the initial semiconductor layer remaining on the second sidewall, the initial semiconductor layer on the surface of the third sidewall and the fourth sidewall adjacent to the second sidewall, and the initial semiconductor layer in the second trench.

10. The method for manufacturing a semiconductor structure according to claim 8, characterized in that, The first trench includes a first sidewall and a second sidewall that are opposite each other along a first direction; The steps of forming the first sub-semiconductor layer, the second semiconductor layer, the first gate, and the second gate include: An initial semiconductor layer is formed, the initial semiconductor layer extending at least from the first surface to the first sidewall and the second sidewall, and continuing to extend sequentially to the inner wall of the second trench; An initial gate is formed on the side of the first sub-semiconductor layer and the second semiconductor layer opposite to the inner wall of the trench; In the same etching process step, the initial semiconductor layer and the initial gate on the inner wall of the second trench adjacent to the first sidewall are removed, and at least the remaining initial semiconductor layer and the initial gate on the first sidewall are retained to form the first sub-semiconductor layer and the first gate, respectively. The remaining initial semiconductor layer and the initial gate on the inner wall of the second trench connected to the second sidewall are retained to form the second semiconductor layer and the second gate, respectively.

11. The method for manufacturing a semiconductor structure according to claim 8, characterized in that, A through-hole communicating with the second trench is also formed in the substrate, and the through-hole is located between the second trench and the second surface; in the step of forming the second semiconductor layer, the second semiconductor layer also fills the through-hole.

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