Semiconductor structure, memory cell structure, and method of manufacturing a semiconductor structure

Abstract

This disclosure provides a semiconductor structure, a memory cell structure, and a method for manufacturing the semiconductor structure. The semiconductor structure includes: a substrate having a first surface and a second surface opposite to each other, and having interconnected trenches and vias within the substrate. The trenches extend from the first surface towards the second surface, and the vias are located between the trenches and the second surface; a first gate and a second gate, located within the trenches and discretely separated from each other, with the first gate and the second gate located on opposite sides of the vias; a first gate dielectric layer, located at least on the surface of the first gate facing the trench, and also on the surface of the second gate facing the trench; and a first semiconductor layer, extending from the first surface to the inner wall of the trench, and also filling the vias. The first semiconductor layer located within the trench is located on the surface of the first gate dielectric layer away from the first gate and on the surface of the first gate dielectric layer away from the second gate. This disclosure provides at least the advantage of improving the performance of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure, a memory cell structure, and a method for manufacturing the semiconductor structure. Background Technology

[0002] Common Dynamic Random Access Memory (DRAM) is of the 1T1C type, meaning that a single transistor's source or drain is electrically connected to a capacitor to form a memory cell structure. This structure uses capacitors to store data, but because reading data consumes the capacitor's charge, and the capacitor itself can leak current, the charge in the capacitor needs to be constantly refreshed. This results in high power consumption and unstable electrical performance for DRAM. Furthermore, the large area required for capacitor manufacturing makes miniaturization a significant challenge.

[0003] To overcome the problems caused by capacitors, a 2T0C type memory cell structure was applied, in which the source or drain of one transistor is electrically connected to the gate of another transistor to form a memory cell structure. Summary of the Invention

[0004] This disclosure provides a semiconductor structure, a memory cell structure, and a method for manufacturing the semiconductor structure, which at least helps to improve the performance of the semiconductor structure.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, including: a substrate having a first surface and a second surface opposite to each other, and having a trench and a via connected therein, the trench extending from the first surface towards the second surface, and the via located between the trench and the second surface; a first gate and a second gate located within the trench and mutually discrete, the first gate and the second gate respectively located on opposite sides of the via; a first gate dielectric layer, the first gate dielectric layer being at least located on the surface of the first gate facing the trench, and also located on the surface of the second gate facing the trench; a first semiconductor layer, the first semiconductor layer extending from the first surface to the inner wall of the trench, and also filling the via, wherein the first semiconductor layer located within the trench is located on the surface of the first gate dielectric layer away from the first gate, and on the surface of the first gate dielectric layer away from the second gate; wherein the first semiconductor layer located within the via serves as a first source / drain region, the first semiconductor layer located on the first surface serves as a second source / drain region, and the first semiconductor layer located in the trench serves as a first channel region.

[0006] In some embodiments, the cross-sectional shape of the groove along the direction perpendicular to the first surface includes a triangle, a rectangle, or a bowl shape.

[0007] In some embodiments, the trench includes a first trench and a second trench disposed and connected along the direction from the first surface toward the second surface, the second trench being connected to the via, and the width of the first trench being greater than the width of the second trench along the direction from the first gate toward the second gate; the first semiconductor layer extends from the inner wall of the first trench to the inner wall of the second trench, and both the first gate and the second gate extend from the first trench into the second trench.

[0008] In some embodiments, the first gate and the second gate are symmetrically arranged with respect to the via extension direction.

[0009] In some embodiments, the material of the first semiconductor layer includes IGZO.

[0010] In some embodiments, the orthographic projection of the first semiconductor layer on the first surface onto the first surface is a closed ring.

[0011] In some embodiments, the semiconductor structure further includes: a low-k dielectric layer located within the trench and also located between the first gate and the second gate.

[0012] According to some embodiments of this disclosure, another aspect of this disclosure also provides a memory cell structure, including: a read transistor, the read transistor being the semiconductor structure described in the foregoing embodiments; and a write transistor, the write transistor including a first terminal, a second terminal, and a control terminal, the first terminal being electrically connected to one of the first gate and the second gate, and the second terminal being electrically connected to one of the first source-drain region and the second source-drain region.

[0013] According to some embodiments of this disclosure, another aspect of this disclosure also provides a method for manufacturing a semiconductor structure, comprising: providing a substrate having a first surface and a second surface opposite to each other, the substrate further having a trench and a via connected thereto, the trench extending from the first surface toward the second surface, the via being located between the trench and the second surface; forming a first semiconductor layer, the first semiconductor layer extending from the first surface to the inner wall of the trench and filling the via, the first semiconductor layer located in the via serving as a first source / drain region, the first semiconductor layer located on the first surface serving as a second source / drain region, and the first semiconductor layer located in the trench serving as a first channel region; forming a first gate dielectric layer and a first gate and a second gate that are mutually discrete within the trench, the first gate and the second gate being located on opposite sides of the via, the first gate dielectric layer being at least located on the surface of the first gate facing the trench, and the first gate dielectric layer also being located on the surface of the second gate facing the trench.

[0014] In some embodiments, a method for forming the first semiconductor layer, the first gate dielectric layer, the first gate, and the second gate includes: forming the first semiconductor layer in the first surface, the inner wall of the trench, and the via in the same process step; forming a first gate dielectric layer covering the first semiconductor layer in the trench; forming an initial gate located on the initial first gate dielectric layer and filling the trench; and patterning the initial gate to form the first gate and the second gate, which are discrete from each other.

[0015] The technical solutions provided in this disclosure have at least the following advantages:

[0016] The semiconductor structure provided in this disclosure involves a connected trench and vias within a substrate. A first gate and a second gate are disposed within the trench, and a first semiconductor layer extends from a first surface to the inner wall of the trench. The first semiconductor layer also fills the vias. The first semiconductor layer within the vias serves as a first source / drain region, and the first semiconductor layer on the first surface serves as a second source / drain region. The first semiconductor layer in the trench constitutes a first channel region, which is connected to both the first and second source / drain regions. By providing the trenches and extending the first semiconductor layer along the inner wall of the trenches, the length of the first channel region in the first semiconductor layer can be increased while ensuring that the semiconductor structure occupies a small layout space. This reduces the likelihood of short-channel effects caused by an excessively short first channel region and increases the facing area between the first gate and the first channel region, as well as the facing area between the second gate and the first channel region. This enhances the control capability of the first and second gates over the first semiconductor layer, thereby improving the electrical performance of the semiconductor structure. Attached Figure Description

[0017] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A cross-sectional view of a first semiconductor structure provided in an embodiment of this disclosure along a direction perpendicular to the first surface;

[0019] Figure 2 for Figure 1 Top view of the semiconductor structure shown;

[0020] Figure 3 A cross-sectional view of a second semiconductor structure provided in an embodiment of this disclosure along a direction perpendicular to the first surface;

[0021] Figure 4 A cross-sectional view of a third semiconductor structure provided in an embodiment of this disclosure along a direction perpendicular to the first surface;

[0022] Figure 5 A cross-sectional view of a fourth semiconductor structure provided in an embodiment of this disclosure along a direction perpendicular to the first surface;

[0023] Figure 6 A cross-sectional view of a fifth semiconductor structure provided in an embodiment of this disclosure along a direction perpendicular to the first surface;

[0024] Figure 7 A simplified circuit diagram corresponding to a memory cell structure provided in another embodiment of this disclosure;

[0025] Figure 8 This is a schematic diagram of a storage cell structure provided in another embodiment of the present disclosure;

[0026] Figures 9 to 12 This is a schematic diagram of the steps in a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure. Detailed Implementation

[0027] As can be seen from the background technology, the electrical performance of semiconductor structures needs to be improved.

[0028] This disclosure provides a semiconductor structure in which interconnected trenches and vias are formed in a substrate. A first gate and a second gate, mutually independent, are formed within the trench, located on opposite sides of the via. A first semiconductor layer extends from a first surface of the substrate to the inner wall of the trench and fills the via. The first semiconductor layer within the via serves as a first source / drain region, and the first semiconductor layer on the first surface serves as a second source / drain region. The first semiconductor layer in the trench constitutes a first channel region, which is connected to both the first and second source / drain regions. By forming trenches and extending the first channel region along the inner wall of the trench, the length of the first channel region can be increased while maintaining a small footprint. This reduces the likelihood of short-channel effects caused by an excessively short first channel region and increases the facing area between the first gate and the first channel region, as well as the facing area between the second gate and the first channel region. This enhances the control capability of the first and second gates over the first semiconductor layer, thereby improving the electrical performance of the semiconductor structure.

[0029] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0030] Figure 1 A cross-sectional view of a first semiconductor structure provided in an embodiment of this disclosure along a direction perpendicular to the first surface; Figure 2 for Figure 1 Top view of the semiconductor structure shown; Figure 3 A cross-sectional view of a second semiconductor structure provided in an embodiment of this disclosure along a direction perpendicular to the first surface; Figure 4 A cross-sectional view of a third semiconductor structure provided in an embodiment of this disclosure along a direction perpendicular to the first surface; Figure 5 A cross-sectional view of a fourth semiconductor structure provided in an embodiment of this disclosure along a direction perpendicular to the first surface; Figure 6 A cross-sectional view of a fifth semiconductor structure provided in an embodiment of this disclosure along a direction perpendicular to the first surface;

[0031] refer to Figure 1 and Figure 2The semiconductor structure includes a substrate 100 having opposing first surfaces 10 and second surfaces 20. The substrate 100 has a connected trench 101 and a via 102. The trench 101 extends from the first surface 10 towards the second surface 20, and the via 102 is located between the trench 101 and the second surface 20. The semiconductor structure includes a first gate 103 and a second gate 104 located within the trench 101 and separated from each other. The first gate 103 and the second gate 104 are located on opposite sides of the via 102. The semiconductor structure includes a first gate dielectric layer 105, which is located at least on the surface of the first gate 103 facing the trench 101 and also on the surface of the second gate 104 facing the trench 101. The semiconductor structure includes a first semiconductor layer 106, which extends from the first surface 10 to the inner wall of the trench 101 and also fills the via 102. The first semiconductor layer 106 located in the trench 101 is located on the surface of the first gate dielectric layer 105 away from the first gate 103 and on the surface of the first gate dielectric layer 105 away from the second gate 104. The first semiconductor layer 106 located in the via 102 serves as a first source / drain region 16, the first semiconductor layer 106 located on the first surface 10 serves as a second source / drain region 26, and the first semiconductor layer 106 located in the trench 101 serves as a first channel region 36.

[0032] By providing a trench 101, the first channel region 36 extends along the inner wall of the trench 101 (the inner wall of the trench refers to the sidewall and bottom surface of the trench). This allows the length of the first channel region 36 to be increased by using the trench 101 while ensuring that the semiconductor structure occupies a small layout space. This reduces the possibility of short-channel effect caused by the short length of the first channel region 36. It also helps to increase the facing area between the first gate 103 and the first channel region 36, as well as the facing area between the second gate 104 and the first channel region 36. This improves the control capability of the first gate 103 and the second gate 104 over the first semiconductor layer 106, thereby improving the electrical performance of the semiconductor structure.

[0033] The substrate 100 may be a single film layer, and the material of the substrate 100 may be a semiconductor material, including silicon, germanium, gallium nitride (GaN), gallium arsenide (GaAs), and indium phosphide (InP). In some embodiments, the substrate 100 may also be composed of multiple film layers. For example, the substrate 100 may include a substrate and a dielectric layer, wherein the surface of the dielectric layer away from the substrate is a first surface 10, the surface of the substrate away from the dielectric layer is a second surface 20, trenches 101 and vias 102 are located in the dielectric layer, the substrate is made of a semiconductor material, and the dielectric layer is made of a dielectric material such as silicon nitride, silicon oxide, silicon carbide, or silicon oxynitride.

[0034] refer to Figure 1In some embodiments, in a direction perpendicular to the first surface 10, the first surface 10 may be located above the second surface 20, then the trench 101 is located above the via 102, and the first gate 103 and the second gate 104 in the trench 101 are located above the first source / drain region 16. (See reference...) Figure 3 In some embodiments, in a direction perpendicular to the first surface 10, the second surface 20 may be located above the first surface 10, in which case the trench 101 is located below the via 102, and the first gate 103 and the second gate 104 in the trench 101 are located below the first source / drain region 16. This disclosure does not limit the spatial relationship between the first gate 103 and the second gate 104 and the first source / drain region 16.

[0035] In some embodiments, the material of the first semiconductor layer 106 may include IGZO (indium gallium zinc oxide). The carrier mobility of IGZO is 20 to 50 times that of polycrystalline silicon, which is beneficial for improving the carrier mobility of the first channel region 36 in the first semiconductor layer 106, and also for improving the charge and discharge rate of the semiconductor structure. This helps to reduce the leakage current of the transistor constructed from this semiconductor structure during operation and improves the transistor's energy efficiency. In some embodiments, the material of the first semiconductor layer 106 may also be at least one of IWO (indium tungsten oxide) or ITO (indium tin oxide).

[0036] The first semiconductor layer 106 may also be doped with N-type ions or P-type ions. The first source / drain region 16 and the second source / drain region 26 have the same type of doped ions. N-type ions may include nitrogen ions, phosphorus ions, etc., and P-type ions may include boron ions, aluminum ions, etc. In some embodiments, the transistor formed by the semiconductor structure provided in this disclosure is a junction transistor, where the junction refers to a PN junction. The type of doped ions in the first source / drain region 16 is opposite to the type of doped ions in the first channel region 36. For example, the first source / drain region 16 and the second source / drain region 26 may be doped with N-type ions, and the first channel region 36 may be doped with P-type ions. In some embodiments, the transistor formed by the semiconductor structure provided in this disclosure is a junctionless transistor. The type of doped ions in the first source / drain region 16 is the same as the type of doped ions in the first channel region 36. For example, the first source / drain region 16, the second source / drain region 26, and the first channel region 36 may all be doped with P-type ions.

[0037] refer to Figure 2In some embodiments, the orthographic projection of the first semiconductor layer 106 on the first surface 10 can be a closed loop. The orthographic projection area of ​​the first semiconductor layer 106 on the first surface 10 is large and the pattern is relatively regular, providing a larger window for measuring the overlay error in the step of fabricating the first semiconductor layer 106 with the desired shape. This is beneficial for improving the alignment accuracy during the fabrication of the first semiconductor layer 106 with the desired shape and reducing the possibility of transistor failure due to low alignment accuracy. In some embodiments, the orthographic projection of the first semiconductor layer 106 on the first surface 10 can be a closed loop, and the first semiconductor layer 106 extending from the first surface 10 into the trench 101 covers the entire inner wall of the trench 101. This increases the contact area between the first semiconductor layer 106 and the first gate 103, as well as the contact area with the second gate 104, thereby improving the control capability of the first gate 103 and the second gate 104 over the first semiconductor layer 106, and thus improving the electrical performance of the semiconductor structure. In some embodiments, the orthographic projection of the first semiconductor layer 106 on the first surface 10 may not be a closed pattern, and the first semiconductor layer 106 extending from the first surface 10 into the trench 101 may cover part of the inner wall of the trench 101.

[0038] refer to Figure 1 The cross-sectional shape of the groove 101 along the direction perpendicular to the first surface 10 can be rectangular. (Reference) Figure 4 The cross-sectional shape of the groove 101 along the direction perpendicular to the first surface 10 can be triangular. (See reference) Figure 5 In some embodiments, the cross-sectional shape of the groove 101 along the direction perpendicular to the first surface 10 can be bowl-shaped.

[0039] In some embodiments, the trench 101 may be composed of a plurality of sub-trenches that are sequentially connected along the direction from the first surface 10 toward the second surface. For example, refer to Figure 6 In some embodiments, the trench 101 may include a first trench 107 and a second trench 108 disposed and connected along the direction from the first surface 10 toward the second surface 20. The second trench 108 communicates with a via. In the direction from the first gate 103 toward the second gate 104, the width of the first trench 107 is greater than the width of the second trench 108. By setting the width of the first trench 107 to be greater than the width of the second trench 108, it is beneficial to reduce the difficulty of forming the trench 101. The first semiconductor layer 106 extends from the inner wall of the first trench 107 to the inner wall of the second trench 108. The first gate 103 and the second gate 104 both extend from the first trench 107 into the second trench 108. The shape of the first trench 107 may be triangular, rectangular, or bowl-shaped, and the shape of the second trench 108 may be triangular, rectangular, or bowl-shaped.

[0040] By providing multiple trenches 101, the inner surface area of ​​the trenches 101 can be increased while ensuring that the semiconductor structure occupies a small layout space. This increases the area of ​​the first channel region 36 and the first gate 103 facing each other, as well as the area of ​​the first channel region 36 and the second gate 104 facing each other, thereby improving the control capability of the first gate 103 and the second gate 104 over the first semiconductor layer 106 and thus improving the electrical performance of the semiconductor structure.

[0041] The material of the first gate 103 can be at least one of polysilicon, tungsten, aluminum, molybdenum, ruthenium, titanium nitride, or tantalum. The material of the second gate 104 can be at least one of polysilicon, tungsten, aluminum, molybdenum, ruthenium, titanium nitride, or tantalum. The materials of the first gate 103 and the second gate 104 can be the same, and the first gate 103 and the second gate 104 made of the same material can be made from the same original gate, or the materials of the first gate 103 and the second gate 104 can be different. In some embodiments, the first gate 103 and the second gate 104 are symmetrically arranged with respect to the extension direction of the via 102, that is, the first gate 103 and the second gate 104 have the same dimensions, for example, in the direction along the first surface, the first gate 103 and the second gate 104 have the same width and length. In some embodiments, the first gate 103 and the second gate 104 may also not be symmetrically arranged with respect to the extension direction of the via 102. The embodiments disclosed herein do not limit the dimensions and relative positions of the first gate 103 and the second gate 104.

[0042] refer to Figure 2 In some embodiments, the semiconductor structure may further include a low-k dielectric layer 109, which is located within the trench 101 and between the first gate 103 and the second gate 104. The low-k dielectric layer 109 is a dielectric layer with a dielectric constant < 3.9, to reduce the parasitic capacitance generated between the first gate 103 and the second gate 104, thereby improving the electrical performance of the semiconductor structure. The material of the low-k dielectric layer 109 may be at least one of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide.

[0043] The semiconductor structure provided in the above embodiments has a discrete first gate 103 and a second gate 104. That is, the transistor formed by the semiconductor structure is a dual-gate transistor. The threshold voltage of the transistor is jointly controlled by the first gate 103 and the second gate 104, which is beneficial for flexibly controlling the transistor's turn-on or turn-off.

[0044] Furthermore, the semiconductor structure provided in this embodiment has a trench 101 and a via 102. A first gate 103 and a second gate 104 are disposed in the trench 101, and a first semiconductor layer 106 extends from the first surface 10 to the inner wall of the trench 101. The first semiconductor layer 106 also fills the via 102. The first channel region 36 of the first semiconductor layer 106 is located in the trench 101. This can increase the length of the first channel region 36 in the first semiconductor layer 106 while ensuring that the semiconductor structure occupies a small layout space. This can reduce the possibility of short-channel effect caused by the short length of the first channel region 36. It is also beneficial to increase the facing area of ​​the first gate 103 and the first channel region 36 and the facing area of ​​the second gate 104 and the first channel region 36, so as to improve the control capability of the first gate 103 and the second gate 104 over the first semiconductor layer 106, thereby improving the electrical performance of the semiconductor structure.

[0045] Furthermore, the orthographic projection of the first semiconductor layer 106 on the first surface can be a closed ring, which provides a larger window for measuring the overlay error in the step of preparing the first semiconductor layer 106 with the desired shape. This is beneficial to improving the alignment accuracy in the process of preparing the first semiconductor layer 106 with the desired shape and reducing the possibility of transistor failure due to low alignment accuracy.

[0046] Accordingly, another embodiment of this disclosure also provides a memory cell structure, which includes the semiconductor structure provided in the foregoing embodiments. The memory cell structure provided in another embodiment of this disclosure will be described in detail below with reference to the accompanying drawings. For parts that are the same as or corresponding to the previous embodiment, please refer to the corresponding descriptions in the foregoing embodiments; detailed descriptions will not be repeated below. Figure 7 This is a simplified circuit diagram corresponding to a memory cell structure provided in another embodiment of this disclosure. Figure 8 This is a schematic diagram of a storage unit structure provided in another embodiment of the present disclosure.

[0047] refer to Figures 7 to 8 The memory cell structure includes a read transistor 201, which is a semiconductor structure provided in the aforementioned embodiment. The memory cell structure also includes a write transistor 202, which includes a first terminal, a second terminal, and a control terminal. The first terminal is electrically connected to one of the first gate 103 and the second gate 104, and the control terminal is used to control the conduction and cutoff between the first terminal and the second terminal.

[0048] In the read transistor 201, the first gate 103 or the second gate 104 electrically connected to the first terminal can be used as a charge storage electrode layer (i.e., a capacitor electrode layer), and the first gate dielectric layer 105 facing the surface of the trench 101, also electrically connected to the first terminal, can be used as a charge storage dielectric layer (i.e., a capacitor dielectric layer) for storing signal information. The electrically connected first terminal and the first gate 103 or the second gate 104 constitute a memory node SN. The memory cell structure, composed of the read transistor and the write transistor, is a 2TOC type memory cell structure, eliminating the need for capacitors and thus reducing the size of the memory cell structure itself, thereby increasing the integration density of the memory cell structure.

[0049] The write transistor 202 may include a second semiconductor layer 203, a third gate 204, and a second gate dielectric layer 205 located between the second semiconductor layer 203 and the third gate. The second semiconductor layer 203 includes a third source / drain region, a second channel region, and a fourth source / drain region connected in sequence. The third gate 204 faces the second channel region, and the second gate dielectric layer 205 may surround the second channel region. The third gate 204 surrounds the second gate dielectric layer to improve the gate control capability of the third gate 204. One of the third or fourth source / drain regions has a first end, and the other has a second end. The write transistor 202 may also include a first dielectric layer 206, which covers the second semiconductor layer 203, the third gate 204, the second gate dielectric layer 205, and the first semiconductor layer 106 on the first surface, providing isolation. The material of the first dielectric layer 206 may be at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. The specific configuration of the write transistor provided in this embodiment is merely an example and does not constitute a limitation on the specific structure of the write transistor.

[0050] refer to Figure 7 The memory cell structure also includes a write word line WWL, a read word line RWL, and a bit line BL. The write word line WWL is electrically connected to the third gate 204 of the write transistor 202. One of the third source-drain region and the fourth source-drain region is electrically connected to the bit line BL. One of the first source-drain region and the second source-drain region is electrically connected to the bit line BL. The one of the first gate 103 and the second gate 104 that is not electrically connected to the first terminal is electrically connected to the read word line RWL.

[0051] The method of using the two gates of the read transistor to perform data storage and read / write operation control is explained in detail.

[0052] The steps for performing a write operation on the memory cell provided in this embodiment may include: applying a voltage to the write word line WWL to turn on the write transistor, and applying a voltage to the bit line BL to charge the memory node SN, so that the memory node SN presents a high voltage or a low voltage, representing data 1 and 0 respectively; during the write operation on the memory node SN, no voltage is applied to the read word line RWL so as not to provide a voltage signal to the gate of the read transistor that is electrically connected to the read word line RWL.

[0053] The steps for performing a read operation on the memory cell provided in this embodiment may include: applying a voltage to the read word line RWL to provide a voltage signal to the gate electrically connected to the read word line RWL, and applying a voltage to the source-drain region of the read transistor that is not electrically connected to the bit line BL; determining the potential level at the memory structure SN by detecting the magnitude of the current in the bit line BL, so as to perform a read operation on the memory node SN; and not providing a voltage signal to the third gate during the read operation on the memory node SN.

[0054] The read transistor 201 provided in the aforementioned embodiment is a dual-gate transistor. Compared with a single-gate transistor, the dual-gate read transistor uses the read word line RWL to perform read operations on the gate of the read transistor that is electrically connected to the read word line RWL. This is beneficial to use the two gates of the read transistor to complete data storage and read / write operation control respectively. Based on the advantage of gate-controlled read / write operations, the read / write operation of the constructed 2TOC type memory cell structure is more flexible.

[0055] Furthermore, the storage cell structure is controlled by two word lines (Write Word Line WWL and Read Word Line RWL) and one bit line BL, which reduces the number of bit lines required for the storage cell structure. This helps to further reduce the overall size of the storage cell structure and the wiring complexity in the storage array structure, thereby helping to further improve the integration density of the storage array structure.

[0056] Furthermore, if the read word line RWL in the memory array structure is electrically connected to one of the first gate and the second gate of the read transistor, the current flowing through the read word line RWL is very small and can be considered as zero. Therefore, the current flowing through the read word line RWL will not affect the number of read transistors electrically connected to the same read word line RWL, which is beneficial to improving the storage density of the memory array structure.

[0057] Accordingly, another embodiment of this disclosure also provides a method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure provided in this other embodiment can be used to manufacture the semiconductor structure or readout transistor provided in the foregoing embodiments. The method for manufacturing a semiconductor structure provided in another embodiment of this disclosure will be described in detail below with reference to the accompanying drawings. For parts that are the same as or corresponding to those in the foregoing embodiments, please refer to the corresponding descriptions in the foregoing embodiments; detailed descriptions will not be repeated below. Figures 9 to 12 This is a schematic diagram of the steps in a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure.

[0058] refer to Figure 9 A substrate 100 is provided, the substrate 100 having a first surface 10 and a second surface 20 opposite to each other, and the substrate 100 also having a connected groove 101 and a through hole 102, the groove 101 extending from the first surface 10 to the second surface 20, and the through hole 102 located between the groove 101 and the second surface 20.

[0059] The substrate 100 can be a single film layer, and the material of the substrate 100 can be a semiconductor material, including silicon, germanium, gallium nitride (GaN), gallium arsenide (GaAs), and indium phosphide (InP). In some embodiments, the substrate 100 can also be composed of multiple film layers. For example, the substrate 100 can include a substrate and a dielectric layer, wherein the surface of the dielectric layer away from the substrate is a first surface 10, the surface of the substrate away from the dielectric layer is a second surface 20, trenches 101 and vias 102 are located in the dielectric layer, the substrate is a semiconductor material, and the dielectric layer is a dielectric material such as silicon nitride, silicon oxide, silicon carbide, or silicon oxynitride. In some embodiments, in a direction perpendicular to the first surface 10, the first surface 10 can be located above the second surface 20, and the trench 101 is located above the via 102. In some embodiments, in a direction perpendicular to the first surface 10, the second surface 20 can be located above the first surface 10, and the trench 101 is located below the via 102. The embodiments disclosed herein do not limit the spatial relationship between the vias and trenches.

[0060] In some embodiments, the cross-sectional shape of the trench 101 along the direction perpendicular to the first surface 10 can be triangular, rectangular, or bowl-shaped. In some embodiments, the trench 101 can be composed of a plurality of sub-grooves that are sequentially connected along the direction from the first surface 10 toward the second surface 20.

[0061] refer to Figure 10 A first semiconductor layer 106 is formed, which extends from the first surface 10 to the inner wall of the trench 101 and fills the via 102. The first semiconductor layer 106 located in the via 102 serves as the first source / drain region 16, and the first semiconductor layer 106 located on the first surface 10 serves as the second source / drain region 26.

[0062] The material of the first semiconductor layer 106 may include IGZO. The carrier mobility of IGZO is 20 to 50 times that of polycrystalline silicon, which is beneficial for improving the carrier mobility of the first channel region 36 in the first semiconductor layer 106, and also for increasing the charge and discharge rate of the semiconductor structure. This helps to reduce the leakage current of the transistor constructed from this semiconductor structure during operation and improves the transistor's energy efficiency. In some embodiments, the material of the first semiconductor layer 106 may also be at least one of IWO or ITO.

[0063] In some embodiments, a first semiconductor layer 106 can be formed in the first surface 10, the inner wall of the trench 101, and the via 102 in the same process step; that is, the first semiconductor layer 106 is a continuous film layer. The process for forming the first semiconductor layer 106 can be chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0064] The first semiconductor layer can also be treated by ion implantation or diffusion processes to dope the first semiconductor layer 106 with N-type or P-type ions. The first source / drain region 16 and the second source / drain region 26 have the same doping ion type; N-type ions can include nitrogen ions, phosphorus ions, etc., and P-type ions can include boron ions, aluminum ions, etc. In some embodiments, the transistor formed by the semiconductor structure provided in this disclosure is a junction transistor, where the junction refers to a PN junction. The doping ion type of the first source / drain region 16 is opposite to that of the first channel region 36. For example, the first source / drain region 16 and the second source / drain region 26 can be doped with N-type ions, and the first channel region 36 is doped with P-type ions. In some embodiments, the transistor formed by the semiconductor structure provided in this disclosure is a junctionless transistor. The doping ion type of the first source / drain region 16 is the same as that of the first channel region 36. For example, the first source / drain region 16, the second source / drain region 26, and the first channel region 36 can all be doped with P-type ions.

[0065] In some embodiments, the orthographic projection of the first semiconductor layer 106 formed on the first surface 10 on the first surface 10 can be a closed ring. The orthographic projection area of ​​the first semiconductor layer 106 on the first surface 10 is large and the pattern is relatively regular, which provides a larger window for measuring the overlay error in the step of preparing the first semiconductor layer 106 with the desired shape. This is beneficial to improving the alignment accuracy in the process of preparing the first semiconductor layer 106 with the desired shape and reducing the possibility of transistor failure due to low alignment accuracy.

[0066] refer to Figure 12 A first gate dielectric layer 105 and a first gate 103 and a second gate 104, which are mutually independent, are formed in the trench 101. The first gate 103 and the second gate 104 are respectively located on opposite sides of the via 102. The first gate dielectric layer 105 is at least located on the surface of the first gate 103 facing the trench 101, and the first gate dielectric layer 105 is also located on the surface of the second gate 104 facing the trench 101.

[0067] The semiconductor structure formed in this embodiment has a discrete first gate 103 and a second gate 104. That is, the transistor formed by this semiconductor structure is a dual-gate transistor. The threshold voltage of the transistor is jointly controlled by the first gate 103 and the second gate 104, which is beneficial for flexibly controlling the transistor's on or off state. The first gate 103 and the second gate are located in a trench 101. The first semiconductor layer 106 extends from the first surface 10 to the inner wall of the trench 101, and the first semiconductor layer 106 also fills the via 102. The first channel of the first semiconductor layer 106... Region 36 is located in trench 101. While ensuring that the semiconductor structure occupies a small layout space, it can increase the length of the first channel region 36 in the first semiconductor layer 106. This can reduce the possibility of short channel effect caused by the short length of the first channel region 36. It is also beneficial to increase the facing area between the first gate 103 and the first channel region 36 and the facing area between the second gate 104 and the first channel region 36, so as to improve the control capability of the first gate 103 and the second gate 104 over the first semiconductor layer 106, thereby improving the electrical performance of the semiconductor structure.

[0068] The material of the first gate 103 can be at least one of polysilicon, tungsten, aluminum, molybdenum, ruthenium, titanium nitride, or tantalum. The material of the second gate 104 can be at least one of polysilicon, tungsten, aluminum, molybdenum, ruthenium, titanium nitride, or tantalum. The materials of the first gate 103 and the second gate 104 can be the same, and the first gate 103 and the second gate 104, which are made of the same material, can be made from the same original gate. Alternatively, the materials of the first gate 103 and the second gate 104 can be different, and the first gate 103 and the second gate 104 can be made in different process steps.

[0069] refer to Figures 11 to 12 In some embodiments, the method of forming the first gate dielectric layer 105, the first gate 103, and the second gate 104 may include: forming the first gate dielectric layer 105, the first gate dielectric layer 105 covering the first semiconductor layer 106 in the trench 101; forming an initial gate 110, the initial gate 110 being located on the first gate dielectric layer 105 and filling the trench 101; and patterning the initial gate 110 to form the mutually discrete first gate 103 and second gate 104.

[0070] In the step of patterning the initial gate 110, the first gate dielectric layer 105 may also be patterned, and the first gate dielectric layer 105 located on the first gate 103 facing the surface of the trench 101 and the first gate dielectric layer 105 located on the second gate 104 facing the surface of the trench 101 may also be retained.

[0071] In some embodiments, a first gate dielectric layer 105, a first gate 103, and a second gate 104 having desired dimensions and shapes may be formed sequentially through different steps.

[0072] refer to Figure 12 After forming the first gate 103 and the second gate 104, a low-k dielectric layer 109 can be formed. This low-k dielectric layer fills the gap between the first gate 103 and the second gate 104, as well as the gap between adjacent first gate dielectric layers 105. The low-k dielectric layer 109 is a dielectric layer with a dielectric constant < 3.9, to reduce the parasitic capacitance generated between the first gate 103 and the second gate 104, which is beneficial for improving the electrical performance of the formed semiconductor structure. The material of the low-k dielectric layer 109 can be at least one of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide.

[0073] The semiconductor structure manufacturing method provided in the above embodiments forms a discrete first gate 103 and a second gate 104 in the trench 101. Thus, the transistor formed by the semiconductor structure is a dual-gate transistor. The threshold voltage of the transistor is jointly controlled by the first gate 103 and the second gate 104, which is beneficial for flexibly controlling the transistor's conduction or turn-off. Furthermore, by accommodating the first semiconductor layer 106 through the trench 101 and the via 102, the length of the first channel region 36 in the first semiconductor layer 106 can be increased while ensuring that the semiconductor structure occupies a small layout space. This reduces the possibility of short-channel effect caused by the short length of the first channel region 36. It also helps to increase the facing area of ​​the first gate 103 and the first channel region 36, as well as the facing area of ​​the second gate 104 and the first channel region 36, thereby improving the control capability of the first gate 103 and the second gate 104 over the first semiconductor layer 106.

[0074] Furthermore, a first semiconductor layer 106 can be formed in the first surface 10, the inner wall of the trench 101, and the via 102 in the same process step to obtain a continuous first semiconductor layer 106. After forming the first semiconductor layer 106, a first gate dielectric layer 105 and an initial gate 110 are sequentially formed on the first semiconductor layer 106 in the trench 101, and the first gate dielectric layer 105 and the initial gate 110 are patterned in the same process step to obtain a first gate 103 and a second gate in the same process step, thus simplifying the process steps.

[0075] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make various alterations and modifications without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, include: A substrate having opposing first and second surfaces, and having interconnected grooves and through holes within the substrate, the grooves extending from the first surface toward the second surface, and the through holes located between the grooves and the second surface; A first gate and a second gate are located within the trench and are separate from each other, with the first gate and the second gate located on opposite sides of the through hole, respectively. A first gate dielectric layer, the first gate dielectric layer being at least located on the surface of the first gate facing the trench, and also located on the surface of the second gate facing the trench; A first semiconductor layer extends from the first surface to the inner wall of the trench and also fills the via, wherein the first semiconductor layer located in the trench is located on the surface of the first gate dielectric layer away from the first gate and on the surface of the first gate dielectric layer away from the second gate. The first semiconductor layer located within the via is designated as the first source / drain region, the first semiconductor layer located on the first surface is designated as the second source / drain region, and the first semiconductor layer located in the trench is designated as the first channel region.

2. The semiconductor structure of claim 1, wherein, The cross-sectional shape of the groove along the direction perpendicular to the first surface includes a triangle, a rectangle, or a bowl shape.

3. The semiconductor structure of claim 1, wherein, The trench includes a first trench and a second trench disposed and connected along the direction from the first surface toward the second surface. The second trench is connected to the through hole. In the direction from the first gate toward the second gate, the width of the first trench is greater than the width of the second trench. The first semiconductor layer extends from the inner wall of the first trench to the inner wall of the second trench. Both the first gate and the second gate extend from the first trench into the second trench.

4. The semiconductor structure according to claim 1, characterized in that, The first gate and the second gate are symmetrically arranged with respect to the through-hole extension direction.

5. The semiconductor structure according to claim 1, characterized in that, The material of the first semiconductor layer includes IGZO.

6. The semiconductor structure according to claim 1, characterized in that, The first semiconductor layer located on the first surface has a closed ring shape when projected onto the first surface.

7. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a low-k dielectric layer, which is located within the trench and between the first gate and the second gate.

8. A storage cell structure, characterized in that, include: A read transistor, wherein the read transistor is a semiconductor structure according to any one of claims 1-7; A write transistor, the write transistor including a first terminal, a second terminal and a control terminal, the first terminal being electrically connected to one of the first gate and the second gate, and the second terminal being electrically connected to one of the first source-drain region and the second source-drain region.

9. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided, the substrate having opposing first and second surfaces, and the substrate further having communicating grooves and through holes, the grooves extending from the first surface toward the second surface, and the through holes located between the grooves and the second surface; A first semiconductor layer is formed, which extends from the first surface to the inner wall of the trench and fills the via. The first semiconductor layer located in the via serves as a first source / drain region, the first semiconductor layer located on the first surface serves as a second source / drain region, and the first semiconductor layer located in the trench serves as a first channel region. A first gate dielectric layer and a first gate and a second gate, which are mutually independent, are formed in the trench. The first gate and the second gate are respectively located on opposite sides of the via. The first gate dielectric layer is located at least on the surface of the first gate facing the trench, and the first gate dielectric layer is also located on the surface of the second gate facing the trench.

10. The method for manufacturing a semiconductor structure according to claim 9, characterized in that, The method of forming the first semiconductor layer, the first gate dielectric layer, the first gate, and the second gate includes: In the same process step, the first semiconductor layer is formed on the first surface, the inner wall of the trench, and the through hole; A first gate dielectric layer is formed, which covers the first semiconductor layer in the trench; An initial gate is formed, the initial gate being located on the first gate dielectric layer and filling the trench; The initial gate is graphically represented to form a first gate and a second gate that are discrete from each other.

Images