An enhanced GaN-based HEMT device structure and its fabrication method

Abstract

This invention discloses an enhanced GaN-based HEMT device structure and its fabrication method, comprising: an AlN nucleation layer and a GaN buffer layer sequentially located on a SiC substrate; N + The GaN region is located within the GaN buffer layer; the GaN bump is located on the GaN buffer layer and is immediately adjacent to the N-type region. + GaN region; source and drain electrodes, located on the surfaces at both ends of the GaN buffer layer; AlGaN barrier layer, located between the source and drain electrodes, consisting of the GaN buffer layer, GaN bumps, and N2O. + On the GaN region; a SiN passivation layer, located on the AlGaN barrier layer between the source and drain electrodes; a gate electrode, penetrating the SiN passivation layer and located on the AlGaN barrier layer, directly opposite the GaN protrusion; wherein, N + The GaN region is located in the GaN buffer layer between the drain and gate electrodes. This invention is a novel enhancement-mode GaN-based HEMT device structure with high device performance.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to an enhanced GaN-based HEMT device structure and its fabrication method. Background Technology

[0002] High-frequency, high-power, and high-efficiency semiconductor electronic devices have always been important development goals in the semiconductor field, with significant application value in mobile communications, rail transportation, the energy internet, next-generation general-purpose power supplies, and national defense. Since the 1960s, electronic device development has progressed from first-generation Si-based devices to second-generation GaAs-based and InP-based devices, greatly promoting the development of information technology and industry. However, since the beginning of the new century, with the rapid development of information technology and increasingly demanding operating environments, the performance requirements for electronic devices have been continuously increasing. Although Si-based devices remain the most commonly used devices in power electronic equipment, their performance has essentially reached its limit after decades of research and development. Improvements in device structure and innovations in manufacturing processes have made it difficult to further enhance overall performance. Therefore, to enable next-generation power electronic equipment to meet requirements such as high frequency, high efficiency, high temperature resistance, high voltage resistance, and high power density, third-generation semiconductor materials with superior performance are needed. GaN, as a third-generation wide-bandgap semiconductor material, has a much wider bandgap, higher electron migration speed, lower breakdown electric field, and higher operating temperature than Si and GaAs, giving it inherent advantages for power electronic devices and radio frequency devices. In recent years, GaN-based HEMT devices have shown great application potential in power, microwave RF devices and other fields due to their excellent performance such as high frequency, high power and fast switching speed. They have gradually become a popular research object in the fields of high frequency, high temperature, high efficiency and radiation resistance. Their good performance makes them very promising for applications in consumer electronics, rail transportation, industrial equipment and communication base stations.

[0003] For GaN-based HEMT devices, due to piezoelectric polarization and spontaneous polarization effects at the AlGaN / GaN heterojunction interface, a large amount of two-dimensional electron gas (2DEG) is generated in the channel. This results in a natural conductive channel remaining in the GaN-based HEMT device even without bias, keeping the device in a conducting state at zero bias. Therefore, conventional GaN-based HEMT devices are depletion-mode (D-type). However, to reduce off-state losses and simplify driver circuitry, these devices typically need to remain in a normally off state in high-frequency, high-power applications. Meanwhile, as device integration density increases, the energy-saving and design simplicity advantages of enhancement-mode devices become increasingly prominent. However, current methods for implementing enhancement-mode devices introduce a series of reliability issues, such as decreased gate control capability, increased on-resistance, decreased output current, and severe performance degradation under extreme conditions. These problems seriously hinder the practical application of enhancement-mode devices. Therefore, further research is needed on enhancement-mode implementations of GaN-based HMET devices. While ensuring a positive threshold voltage, it is essential to design new device structures to maximize output current, power density, and gate control capability, and to suppress characteristic degradation under high-temperature and high-field environments. Specifically:

[0004] The literature “Uemoto Y, Hikita M, Ueno H, et al. Gate injection transistor (GIT) — A normally-off AlGaN / GaN power transistor using conductivity modulation [J]. IEEE Transactions on Electron Devices, 2007, 54(12): 3393-3399” first realized an enhancement-mode GaN-based HEMT device through a P-GaN cap structure. Specifically, the cap structure mainly involves depositing a Mg-doped P-GaN cap layer above the AlGaN barrier layer, and then evaporating the gate metal on the cap layer. Under zero bias, the P-GaN cap layer can raise the conduction band energy at the heterojunction interface to above the Fermi level, depleting the 2DEG under the gate, resulting in the pinch-off of the effective channel under the gate, thus realizing an enhancement-mode device. The literature “Hamady S. New concepts for normally-off powergallium nitride (GaN) high electron mobility transistor (HEMT) [D]. Universite Toulouse III Paul In Sabatier, 2014, enhancement-mode devices were first realized using a thin barrier structure. Specifically, the thin barrier structure reduces the polarization charge density of the AlGaN barrier layer by decreasing its thickness. When the density drops to a certain value, the channel scattering mechanism of the device causes the two-dimensional electron gas to disappear. From the perspective of the band structure, the conduction band energy of the barrier layer drops significantly, causing the conduction band at the AlGaN / GaN heterojunction to rise above the Fermi level, causing the previously existing two-dimensional quantum well to disappear, thereby depleting the 2DEG under the gate and realizing the enhancement-mode device. The literature "Cai Y, Zhou Y, Chen KJ, et al. High-performance enhancement-mode AlGaN / GaN HEMTs using fluoride-based plasma treatment[J].IEEE Electron Device" is relevant. Letters, 2005, 26(7):435-437. This paper first realized an enhancement-mode device through F ion implantation. Specifically, F ion implantation technology usually involves implanting a certain amount of F ions into the AlGaN barrier layer under the gate before the gate metal evaporates. Since F ions are negatively charged, the F ions entering the AlGaN barrier layer will form a fixed negative charge, which will then deplete the channel electrons under the gate and form an enhancement-mode device.

[0005] However, the method proposed above has the following problems:

[0006] (1) The P-GaN cap structure requires a high level of Mg ion doping technology to achieve precise control of ion doping concentration and depth, and the process is relatively complex. On the other hand, this structure increases the distance between the gate metal and the channel, weakens the electric field strength between the gate and the channel, and affects the gate control capability of the device. At the same time, the parasitic capacitance will also affect the frequency characteristics of the device, and this problem has not yet been effectively solved.

[0007] (2) Traditional thin barrier structure devices face problems such as low channel electron density and high on-resistance, which lead to serious degradation of the output characteristics of the device. Furthermore, due to the shallow AlGaN / GaN interface quantum well of the thin barrier structure, the leakage current of the device increases and the reliability of the device decreases, which limits the widespread application of the thin barrier structure.

[0008] (3) Enhanced GaN-based HEMT devices formed by F ion implantation can achieve high threshold voltage. However, ion implantation will form a large number of interface states, resulting in a large amount of lattice damage and causing a significant decrease in channel electron mobility. At the same time, F ions are prone to form stable complexes, which leads to a decrease in the stability of device characteristics and the reliability of the device still needs to be further improved. Summary of the Invention

[0009] To address the aforementioned problems in the prior art, this invention provides an enhanced GaN-based HEMT device structure and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0010] In a first aspect, embodiments of the present invention provide an enhanced GaN-based HEMT device structure, comprising:

[0011] SiC substrate; and an AlN nucleation layer and a GaN buffer layer sequentially located on the SiC substrate;

[0012] N + The GaN region is located in the GaN buffer layer, and its upper surface is flush with the upper surface of the GaN buffer layer.

[0013] GaN bumps are located on the GaN buffer layer and are immediately adjacent to the N-type bumps. + GaN region;

[0014] The source electrode and the drain electrode are located on the surfaces at both ends of the GaN buffer layer, respectively.

[0015] AlGaN barrier layer, GaN buffer layer, GaN bumps and N-type ... +On the GaN region;

[0016] A SiN passivation layer is located on the AlGaN barrier layer between the source electrode and the drain electrode;

[0017] The gate electrode penetrates the SiN passivation layer, is located on the AlGaN barrier layer, and is directly opposite the GaN protrusion;

[0018] Wherein, the N + The GaN region is located in the GaN buffer layer between the drain electrode and the gate electrode.

[0019] In one embodiment of the present invention, the N + The doping concentration of the GaN region is 1×10⁻⁶. 15 cm -3 ~1×10 19 cm -3 The doping depth is 0.1μm to 0.8μm.

[0020] In one embodiment of the present invention, the thickness of the GaN bump is 0.002 μm to 0.008 μm.

[0021] In one embodiment of the present invention, the thickness of the AlGaN barrier layer is 0.01 μm to 0.03 μm.

[0022] In one embodiment of the present invention, the spacing between the gate electrode and the source electrode is 0.5 μm to 1.5 μm.

[0023] In one embodiment of the present invention, the spacing between the gate electrode and the drain electrode is 3.5 μm to 4.5 μm.

[0024] In one embodiment of the present invention, the on-resistance of the device structure is 3.57Ω, the maximum output current reaches 1.26A, and the maximum transconductance reaches 0.672S.

[0025] Secondly, embodiments of the present invention provide a method for fabricating an enhanced GaN-based HEMT device structure, comprising:

[0026] An AlN nucleation layer and a GaN buffer layer are sequentially grown on a SiC substrate.

[0027] N-type doping is performed on a portion of the GaN buffer layer surface to form N-type doping in the GaN buffer layer. + GaN region;

[0028] A thin GaN layer is grown on the undoped GaN buffer layer, and GaN bumps are etched to form them.

[0029] The GaN buffer layer, the GaN boss and the N + An AlGaN barrier layer is grown on the GaN region, and the AlGaN barrier layer on the GaN protrusion is thinned to make it planar.

[0030] The AlGaN barrier layer in the source and drain electrode regions is etched away, and source and drain metals are deposited in the source and drain electrode regions to form source and drain electrodes.

[0031] A SiN passivation layer is grown on the AlGaN barrier layer between the source electrode and the drain electrode;

[0032] The SiN passivation layer in the gate electrode region opposite to the GaN protrusion is removed by etching, and gate metal is deposited in the gate electrode region to form a gate electrode;

[0033] Wherein, the N + The GaN region is formed by N-type doping of the GaN buffer layer between the drain electrode and the gate electrode.

[0034] In one embodiment of the present invention, N-type doping is performed on a portion of the GaN buffer layer surface to form N-type doping in the GaN buffer layer. + The GaN region includes:

[0035] The surface of a portion of the GaN buffer layer is doped with a concentration of 1×10⁻⁶. 15 cm -3 ~1×10 19 cm -3 N-type doping with a doping depth of 0.1 μm to 0.8 μm is used to form N-type doping in the GaN buffer layer. + GaN region.

[0036] In one embodiment of the present invention, a thin GaN layer is grown on the undoped GaN buffer layer, comprising:

[0037] A thin GaN layer with a thickness of 0.002 μm to 0.008 μm is grown on the GaN buffer layer that has not been N-type doped.

[0038] The beneficial effects of this invention are:

[0039] The enhanced GaN-based HEMT device structure proposed in this invention is a novel enhanced GaN-based HEMT device structure. Specifically, the device structure includes a SiC substrate layer; and an AlN nucleation layer and a GaN buffer layer sequentially located on the SiC substrate layer; N + The GaN region is located within the GaN buffer layer, and its upper surface is flush with the upper surface of the GaN buffer layer; the GaN bump is located on the GaN buffer layer, and it is immediately adjacent to the N-type region. +GaN region; source and drain electrodes, located on the surfaces at both ends of the GaN buffer layer; AlGaN barrier layer, located between the source and drain electrodes, consisting of the GaN buffer layer, GaN bumps, and N2O. + On the GaN region; a SiN passivation layer, located on the AlGaN barrier layer between the source and drain electrodes; a gate electrode, penetrating the SiN passivation layer and located on the AlGaN barrier layer, directly opposite the GaN protrusion; wherein, N + The GaN region is located in the GaN buffer layer between the drain electrode and the gate electrode.

[0040] As can be seen, this invention introduces GaN bumps into the AlGaN barrier layer. These GaN bumps effectively reduce the thickness of the AlGaN barrier layer, thereby weakening the polarization effect in the AlGaN / GaN heterojunction below the gate electrode, depleting channel electrons below the gate electrode, and achieving an enhancement-mode device. Simultaneously, the distance between the gate electrode and the two-dimensional electron gas in the channel is significantly shortened, effectively enhancing the device's gate electrode control capability, reducing the device's on-resistance, improving the transconductance characteristics and on / off ratio, and reducing the device's off-state loss. Furthermore, this GaN bump design effectively increases the discontinuity of channel electrons, ensuring a stable threshold voltage for the enhancement-mode device and improving its reliability under extreme environments such as high temperature and high field. By changing the thickness of the GaN bumps and the N... + The doping concentration of the GaN region allows for controllable threshold voltage and output current parameters, facilitating the control of device switching, frequency, and output characteristics, and making the device more flexible in application areas and environments. This invention designs N-type doping in the GaN buffer layer below the gate and drain electrodes. + The GaN region can effectively avoid problems such as decreased output current and increased on-resistance caused by low electron density in the gate electrode channel. + GaN region design can increase the free electron concentration in GaN buffer layer, compensate for the two-dimensional electron gas in channel, increase the output current of device, and avoid the problem of output current density decrease due to the weakening of polarization effect below gate electrode.

[0041] Compared with P-GaN cap layer structures and thin AlGaN barrier structures, this invention effectively avoids the problems of decreased gate control capability and increased parasitic capacitance caused by P-GaN cap layer, thus improving the electrical reliability of the device. On the other hand, this invention only thins the AlGaN barrier layer below the gate electrode, which avoids the problems of decreased output current and increased on-resistance caused by weak polarization effect in thin barrier structure devices, ensuring that the output current characteristics of the device are not significantly affected. Compared with F ion implantation structure, this invention does not introduce F ions or other impurities that affect the carrier mobility or stability of the device, retaining the advantages of high carrier mobility, strong stability under high field and high temperature environment of GaN-based HEMT devices, and can effectively improve the gate control capability of the device.

[0042] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of an enhanced GaN-based HEMT device structure provided in an embodiment of the present invention;

[0044] Figure 2 This is a schematic diagram of the output current and transconductance as a function of gate voltage for a conventional depletion-type GaN-based HEMT device.

[0045] Figure 3 This is a schematic diagram of the output current and transconductance of the enhanced GaN-based HEMT device as a function of gate voltage, provided in an embodiment of the present invention.

[0046] Figure 4 This is a schematic diagram of the output current versus drain voltage curve of a conventional depletion-type GaN-based HEMT device.

[0047] Figure 5 This is a schematic diagram of the output current versus drain voltage curve of the enhanced GaN-based HEMT device provided in this embodiment of the invention.

[0048] Figure 6 This is a schematic diagram of a fabrication method for an enhanced GaN-based HEMT device structure provided in an embodiment of the present invention;

[0049] Figure 7 (a)~ Figure 7 (l) is a schematic diagram of the fabrication process of the enhanced GaN-based HEMT device structure provided in the embodiment of the present invention.

[0050] 1-SiC substrate; 2-AlN nucleation layer; 3-GaN buffer layer; 4-N +GaN region; 5-GaN bump; 6-AlGaN barrier layer; 7-SiN passivation layer; 8-source electrode; 9-drain electrode; 10-gate electrode. Detailed Implementation

[0051] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0052] To address the shortcomings of existing technologies in the fabrication and structure of enhancement-mode devices, and considering the actual process and technological capabilities, this invention presents a novel enhancement-mode GaN-based HEMT device structure to solve the aforementioned problems. Please refer to... Figure 1 This invention provides an enhanced GaN-based HEMT device structure, comprising:

[0053] SiC substrate 1; and AlN nucleation layer 2 and GaN buffer layer 3 sequentially located on SiC substrate 1;

[0054] N + GaN region 4 is located in GaN buffer layer 3, and its upper surface is flush with the upper surface of GaN buffer layer 3.

[0055] GaN protrusion 5 is located on GaN buffer layer 3 and is immediately adjacent to N. + GaN region 4;

[0056] The source electrode 8 and the drain electrode 9 are located on the surfaces at both ends of the GaN buffer layer 3, respectively;

[0057] AlGaN barrier layer 6, GaN buffer layer 3, GaN protrusions 5 and N-type electrodes located between source electrode 8 and drain electrode 9. + GaN region 4 on top;

[0058] SiN passivation layer 7 is located on AlGaN barrier layer 6 between source electrode 8 and drain electrode 9;

[0059] The gate electrode 10 penetrates the SiN passivation layer 7 and is located on the AlGaN barrier layer 6, and is directly opposite the GaN protrusion 5;

[0060] Where, N + GaN region 4 is located in GaN buffer layer 3 between drain electrode 9 and gate electrode 10.

[0061] Preferably, the thickness of the SiC substrate layer 1 is 0.3 μm.

[0062] Preferably, the thickness of the AlN nucleation layer 2 is 0.05 μm to 0.15 μm; more preferably, the thickness of the AlN nucleation layer 2 is 0.1 μm.

[0063] Preferably, the thickness of the GaN buffer layer 3 is 0.5 μm to 2 μm; more preferably, the thickness of the GaN buffer layer 3 is 1.3 μm.

[0064] Preferably, N + The doping concentration of GaN region 4 is 1×10⁻⁶. 15 cm -3 Up to 1×10 19 cm -3 The doping depth is 0.1 μm to 0.8 μm; more preferably, N + The doping concentration of GaN region 4 is 1×10⁻⁶. 18 cm -3 The doping depth is 0.4 μm.

[0065] Preferably, the thickness of the GaN protrusion 5 is 0.002 μm to 0.008 μm; more preferably, the thickness of the GaN protrusion 5 is 0.006 μm.

[0066] Preferably, the thickness of the AlGaN barrier layer 6 is 0.01 μm to 0.03 μm; more preferably, the thickness of the AlGaN barrier layer 6 is 0.02 μm.

[0067] Preferably, the source electrode 8 and the drain electrode 9 are made of Ti / Al / Ni / Au multilayer metal; the width of the source electrode 8 and the drain electrode 9 is 0.5μm to 1.5μm.

[0068] Preferably, the gate electrode 10 is made of Ni / Au multilayer metal; the gate electrode 10 has a thickness of 0.05μm / 0.23μm and a width of 0.5μm to 1.5μm.

[0069] Preferably, the thickness of the SiN passivation layer 7 is the same as the thickness of the gate electrode 10; the thickness of the source electrode 8 and the drain electrode 9 is the sum of the thickness of the gate electrode 10 and the thickness of the AlGaN barrier layer 6.

[0070] Preferably, the spacing between the gate electrode 10 and the source electrode 8 is 0.5 μm to 1.5 μm, and the spacing between the gate electrode 10 and the drain electrode 9 is 3.5 μm to 4.5 μm. More preferably, the spacing between the gate electrode 10 and the source electrode 8 is 1 μm, and the spacing between the gate electrode 10 and the drain electrode 9 is 4 μm.

[0071] The key optimal parameters of the device were obtained by using SILVACO TCAD simulation software for reasonable optimization. The enhanced GaN-based HEMT device proposed in this embodiment was then simulated using SILVACO TCAD software. The output current and transconductance of the conventional depletion-mode device and the new structure device of this invention as a function of gate voltage are shown below when the voltage at drain electrode 9 is 5V. Figure 2 , Figure 3 As shown, simulation results reveal the threshold voltage V of this novel GaN device. th The voltage is 0.635V, and the enhancement mode has been achieved. The maximum output current I of the new structure device proposed in this embodiment of the invention is... dmax It is 1.26A, an increase of 28.92%; maximum transconductance G mmax The current-to-drain voltage (DCV) ratio is 0.672s, representing an improvement of 101.52%. The output current versus drain voltage curves for conventional depletion-type devices and the novel device of this invention are shown below. Figure 4 , Figure 5 As shown, simulation results indicate that the on-resistance of the new structure device is 3.57Ω, a reduction of 29.43%. It can be seen that the new structure device proposed in this embodiment can achieve a positive threshold voltage while improving the device's output current, gate control capability, and output power density.

[0072] In summary, the enhanced GaN-based HEMT device structure proposed in this embodiment is a novel enhanced GaN-based HEMT device structure. Specifically, the device structure includes a SiC substrate layer 1; and an AlN nucleation layer 2 and a GaN buffer layer 3 sequentially located on the SiC substrate layer 1; N + GaN region 4 is located within GaN buffer layer 3, and its upper surface is flush with the upper surface of GaN buffer layer 3; GaN bump 5 is located on GaN buffer layer 3, and it is immediately adjacent to N. + GaN region 4; source electrode 8 and drain electrode 9, located on the surfaces at both ends of GaN buffer layer 3, respectively; AlGaN barrier layer 6, located between source electrode 8 and drain electrode 9, GaN buffer layer 3, GaN protrusion 5 and N + GaN region 4; SiN passivation layer 7, located on AlGaN barrier layer 6 between source electrode 8 and drain electrode 9; gate electrode 10, penetrating SiN passivation layer 7, located on AlGaN barrier layer 6, and directly opposite GaN protrusion 5; wherein, N + GaN region 4 is located in GaN buffer layer 3 between drain electrode 9 and gate electrode 10.

[0073] As can be seen, in this embodiment of the invention, GaN bumps 5 are introduced into the AlGaN barrier layer 6. The GaN bumps 5 effectively reduce the thickness of the AlGaN barrier layer 6, thereby weakening the polarization effect in the AlGaN / GaN heterojunction below the gate electrode 10, depleting the channel electrons below the gate electrode 10, and realizing an enhancement-mode device. Simultaneously, the distance between the gate electrode 10 and the two-dimensional electron gas in the channel is significantly shortened, effectively enhancing the control capability of the gate electrode 10, reducing the on-resistance, improving the transconductance characteristics and on / off ratio, and reducing the off-state loss. Furthermore, this GaN bump 5 design effectively increases the discontinuity of channel electrons, ensuring a stable threshold voltage for the enhancement-mode device and improving the reliability of the device under extreme environments such as high temperature and high field. By changing the thickness of the GaN bumps 5 and N... + The doping concentration of GaN region 4 allows for controllable threshold voltage and output current parameters, facilitating the control of device switching, frequency, and output characteristics, and making the device more flexible in application fields and environments. In this embodiment of the invention, an N-type doping concentration is designed in the GaN buffer layer 3 below the gate electrode 10 and drain electrode 9. + GaN region 4 can effectively avoid problems such as decreased output current and increased on-resistance caused by the low electron density in the gate electrode 10 channel. + The GaN region 4 design can increase the free electron concentration in GaN buffer layer 3, compensate for the two-dimensional electron gas in the channel, increase the output current of the device, and avoid the problem of output current density decrease due to the weakening of polarization effect below gate electrode 10.

[0074] Compared with P-GaN cap structure and thin AlGaN barrier structure, the embodiments of the present invention can effectively avoid the problems of decreased gate control capability and increased parasitic capacitance caused by P-GaN cap structure, thus improving the electrical reliability of the device. On the other hand, the embodiments of the present invention only thin the AlGaN barrier layer 6 below the gate electrode 10, which can avoid the problems of decreased output current and increased on-resistance caused by weak polarization effect in thin barrier structure devices, ensuring that the output current characteristics of the device are not greatly affected. Compared with F ion implantation structure, the embodiments of the present invention do not introduce F ions or other impurities that affect the carrier mobility or stability of the device, retaining the advantages of high carrier mobility, high field and high temperature stability of GaN-based HEMT devices, and can effectively improve the gate control capability of the device.

[0075] Secondly, please see Figure 6 This invention provides a method for fabricating an enhanced GaN-based HEMT device structure, comprising:

[0076] S10. An AlN nucleation layer 2 and a GaN buffer layer 3 are sequentially grown on a SiC substrate layer 1.

[0077] like Figure 7 As shown in (a), in this embodiment of the invention, an AlN nucleation layer 2 with a thickness of 0.05 μm to 0.15 μm is epitaxially grown on the surface of a SiC substrate layer 1 with a thickness of 0.3 μm using metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) technology. More preferably, an AlN nucleation layer 2 with a thickness of 0.1 μm is grown.

[0078] like Figure 7 As shown in (b), in this embodiment of the invention, a GaN buffer layer 3 with a thickness of 0.5 μm to 2 μm is grown on the surface of the AlN nucleation layer 2 using MOCVD or MBE technology. More preferably, a GaN buffer layer 3 with a thickness of 1.3 μm is grown.

[0079] S20. Perform N-type doping on a portion of the GaN buffer layer 3 surface to form N in the GaN buffer layer 3. + GaN region 4.

[0080] like Figure 7 As shown in (c), in this embodiment of the invention, N-type doping is performed on a portion of the GaN buffer layer 3 surface using an ion implantation process, with a doping concentration of 1×10⁻⁶. 15 cm -3 ~1×10 19 cm -3 The doping depth is 0.1 μm to 0.8 μm, more preferably, the doping concentration is 1 × 10⁻⁶. 18 cm -3 The doping depth is 0.4 μm to form the N-type doping of the GaN buffer layer 3 in the gate and drain regions, i.e., N + GaN region 4.

[0081] S30. A thin GaN layer is grown on the undoped GaN buffer layer 3, and GaN bumps 5 are etched to form them.

[0082] like Figure 7 As shown in (d), in this embodiment of the invention, a thin GaN layer with a thickness of 0.002 μm to 0.008 μm is grown on the surface of the GaN buffer layer 3 using MOCVD or MBE technology. More preferably, a thin GaN layer with a thickness of 0.006 μm is grown.

[0083] Then, as Figure 7As shown in (e), GaN bumps 5 are formed after the thin GaN layers in the gate source and gate drain regions are removed using an inductively coupled plasma (ICP) etching process.

[0084] S40, in GaN buffer layer 3, GaN protrusion 5 and N + An AlGaN barrier layer 6 is grown on GaN region 4, and the AlGaN barrier layer 6 on GaN protrusion 5 is thinned to make it planar.

[0085] like Figure 7 As shown in (f), in this embodiment of the invention, the GaN buffer layer 3, GaN protrusion 5, and N + On the surface of GaN region 4, an AlGaN barrier layer 6 with a thickness of 0.01 μm to 0.03 μm is grown using MOCVD or MBE technology, more preferably, an AlGaN barrier layer 6 with a thickness of 0.02 μm is grown.

[0086] Next, as Figure 7 As shown in (g), part of the AlGaN barrier layer 6 on the GaN protrusion 5 is removed by ICP etching process to make it planar.

[0087] S50, etch away the AlGaN barrier layer 6 in the source and drain electrode regions, and deposit source and drain metals in the source and drain electrode regions to form source electrode 8 and drain electrode 9.

[0088] like Figure 7 As shown in (h), in this embodiment of the invention, the AlGaN barrier layer 6 in the source and drain electrode region is removed by ICP etching process.

[0089] Next, as Figure 7 As shown in (i), source electrode 8 and drain electrode 9 are formed by depositing a layer of source and drain metals such as Ti / Al / Ni / Au in the source and drain electrode regions using a metal evaporation process. The thicknesses are 0.02μm / 0.18μm / 0.055μm / 0.045μm and the widths are 0.5μm to 1.5μm.

[0090] S60. A SiN passivation layer 7 is grown on the AlGaN barrier layer 6 between the source electrode 8 and the drain electrode 9.

[0091] like Figure 7 As shown in (j), in this embodiment of the invention, a SiN material with a thickness of 0.28 μm is grown on the surface of the AlGaN barrier layer 6 between the source electrode 8 and the drain electrode 9 using plasma-enhanced chemical vapor deposition (PECVD) and then subjected to high-temperature annealing to form a SiN passivation layer 7.

[0092] S70. Etch away the SiN passivation layer 7 in the gate electrode region opposite to the GaN protrusion 5, and deposit gate metal in the gate electrode region to form the gate electrode 10.

[0093] like Figure 7 As shown in (k), in this embodiment of the invention, the SiN passivation layer 7 in the gate electrode region directly opposite the GaN protrusion 5 is etched away using an ICP etching process to form a gate trench. The spacing between the gate trench and the source electrode 8 is 0.5 μm to 1.5 μm, and the spacing between the gate trench and the drain electrode 9 is 3.5 μm to 4.5 μm. More preferably, the spacing between the gate trench and the source electrode 8 is 1 μm, and the spacing between the gate trench and the drain electrode 9 is 4 μm.

[0094] Next, as Figure 7 As shown in (l), a gate metal, such as a Ni / Au multilayer metal, is deposited in the gate trench where the gate electrode region is located using a metal evaporation process to form a gate electrode 10 with a thickness of 0.05 μm / 0.23 μm and a width of 0.5 μm to 1.5 μm. More preferably, a gate electrode 10 with a thickness of 0.05 μm / 0.23 μm and a width of 1 μm is formed. That is, the spacing between the gate electrode 10 and the source electrode 8 is 0.5 μm to 1.5 μm, the spacing between the gate electrode 10 and the drain electrode 9 is 3.5 μm to 4.5 μm, and more preferably, the spacing between the gate electrode 10 and the source electrode 8 is 1 μm, and the spacing between the gate electrode 10 and the drain electrode 9 is 4 μm.

[0095] Here, N is formed for S20. + GaN region 4 will be further explained in embodiment N of the present invention. + GaN region 4 is formed by N-type doping of GaN buffer layer 3 between drain electrode 9 and gate electrode 10.

[0096] This invention proposes a method for fabricating an enhanced GaN-based HEMT device structure, addressing the first aspect. A GaN bump 5 is formed at the AlGaN / GaN heterojunction interface below the gate electrode 10 using a deposition process. Then, an AlGaN barrier layer 6 is grown to form a thin barrier layer structure under the gate. Compared to P-GaN cap layer devices, the GaN bump 5 in the device fabricated according to this invention effectively shortens the distance between the gate and the channel, improving the gate control capability of the device and avoiding parasitic capacitance, further enhancing the DC and AC characteristics of the device. In terms of process technology, the growth of the GaN bump 5 is achieved using a deposition process, which is mature and stable and does not affect device reliability. Compared to devices with a thin AlGaN barrier layer 6 structure, this invention is equivalent to thinning only the barrier layer region under the gate, suppressing the problems of low channel electron density and high on-resistance in the thin AlGaN barrier layer 6 structure. Furthermore, this invention incorporates N-type doping in the GaN buffer layer 3 below the gate-drain region to form N... + In GaN region 4, while ensuring a positive threshold voltage, the output current and power density of the device can be effectively improved. Therefore, the embodiments of the present invention achieve enhancement mode only by changing the device geometry and performing regional doping, effectively preserving the device's excellent characteristics such as high output current density, high temperature resistance, large breakdown voltage, and high electron mobility, while avoiding the impact on device reliability caused by F-ion implantation and improving the device's stability under extreme environments.

[0097] As for the preparation method embodiment of the second aspect, since it is basically similar to the structural embodiment of the first aspect, the description is relatively simple. For relevant details, please refer to the description of the structural embodiment of the first aspect.

[0098] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0099] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the specification and accompanying drawings, will understand and implement other variations of the disclosed embodiments in carrying out the claimed invention. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. While certain measures are described in different embodiments, this does not mean that these measures cannot be combined to produce good results.

[0100] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. An enhanced GaN-based HEMT device structure, characterized by, include: SiC substrate layer; And an AlN nucleation layer and a GaN buffer layer are sequentially located on the SiC substrate; N + a GaN region located in the GaN buffer layer and having an upper surface flush with the upper surface of the GaN buffer layer; GaN bumps are located on the GaN buffer layer and are immediately adjacent to the N-type bumps. + GaN region; The source electrode and the drain electrode are located on the surfaces at both ends of the GaN buffer layer, respectively. an AlGaN barrier layer on the GaN buffer layer, the GaN mesa, and the N + on the GaN region; A SiN passivation layer is located on the AlGaN barrier layer between the source electrode and the drain electrode; The gate electrode penetrates the SiN passivation layer, is located on the AlGaN barrier layer, and is directly opposite the GaN protrusion; wherein the N + a GaN region in the GaN buffer layer between the drain electrode and the gate electrode.

2. The enhanced GaN-based HEMT device structure of claim 1, wherein, The N + The doping concentration of the GaN region is 1 x 1018 15 cm -3 ~ 1 x 1018 19 cm -3 , and the doping depth is 0.1 μm ~ 0.8 μm.

3. The enhanced GaN-based HEMT device structure of claim 1, wherein, The thickness of the GaN protrusion is 0.002 μm to 0.008 μm.

4. The enhanced GaN-based HEMT device structure of claim 1, wherein, The thickness of the AlGaN barrier layer is 0.01 μm to 0.03 μm.

5. The enhanced GaN-based HEMT device structure of claim 1, wherein, The spacing between the gate electrode and the source electrode is 0.5 μm to 1.5 μm.

6. The enhanced GaN-based HEMT device structure of claim 1, wherein, The spacing between the gate electrode and the drain electrode is 3.5 μm to 4.5 μm.

7. The enhanced GaN-based HEMT device structure of claim 1, wherein, The device structure has an on-resistance of 3.57Ω, a maximum output current of 1.26A, and a maximum transconductance of 0.672S.

8. A method of fabricating an enhanced GaN-based HEMT device structure, characterized by, include: An AlN nucleation layer and a GaN buffer layer are sequentially grown on a SiC substrate. N-type doping is performed on part of the surface of the GaN buffer layer to form N + GaN region; A thin GaN layer is grown on the undoped GaN buffer layer, and GaN bumps are etched to form them. GaN buffer layer, the GaN bump and the N + Growth of an AlGaN barrier layer on the GaN region and thinning of the AlGaN barrier layer on the GaN bump to planarize it; The AlGaN barrier layer in the source and drain electrode regions is etched away, and source and drain metals are deposited in the source and drain electrode regions to form source and drain electrodes. A SiN passivation layer is grown on the AlGaN barrier layer between the source electrode and the drain electrode; The SiN passivation layer in the gate electrode region opposite to the GaN protrusion is removed by etching, and gate metal is deposited in the gate electrode region to form a gate electrode; Wherein, the N + The GaN region is formed by N-type doping to the GaN buffer layer between the drain electrode and the gate electrode.

9. The method of fabricating a reinforced GaN-based HEMT device structure according to claim 8, wherein, N-type doping is performed on part of the surface of the GaN buffer layer to form an N + a GaN region comprising: The surface of a portion of the GaN buffer layer is doped with a concentration of 1×10⁻⁶. 15 cm -3 ~1×10 19 cm -3 N-type doping with a doping depth of 0.1 μm to 0.8 μm is used to form N-type doping in the GaN buffer layer. + GaN region.

10. The method of fabricating an enhanced GaN-based HEMT device structure of claim 8, wherein, A thin GaN layer is grown on the undoped GaN buffer layer, comprising: A thin GaN layer with a thickness of 0.002 μm to 0.008 μm is grown on the GaN buffer layer that has not been N-type doped.

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