A method and circuit for reducing system clock generation based on power supply ripple

Abstract

The application discloses a method and circuit for reducing power supply ripple to generate system clock, which comprises the following steps: S1, separating voltage from ripple and performing signal amplification; S2, rectifying the amplified ripple signal and performing frequency point detection; and S3, generating clock circuit according to the frequency point to reduce power supply ripple. The circuit comprises a power supply part and a clock output part, wherein a ripple extraction part and a filter part are arranged between the power supply part and the clock output part, a signal amplification part is arranged between the ripple extraction part and the filter part, and a frequency conversion part is arranged between the filter part and the clock output part. The power supply ripple generated by the power supply is processed and frequency-converted to generate a clock signal as a switching signal to control the circuit to reduce the power supply ripple, thereby improving the stability of the circuit, reducing the clock oscillation circuit part, and simplifying the circuit structure.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and in particular to a method and circuit for generating a system clock based on reducing power supply ripple. Background Technology

[0002] Power supply ripple is the high-frequency AC component of the power supply output, and it can negatively impact the normal operation and performance of electronic devices. Therefore, reducing power supply ripple is an important issue in electronic device design.

[0003] A clock is based on a stable reference signal and a counter. The counter counts the reference signal to achieve signal transmission and measurement. Therefore, clock generation is fundamental to the normal operation of a circuit. However, existing circuits for reducing power supply ripple all require a new clock circuit as a switching control signal, making the circuit more complex. Therefore, a new method and circuit for reducing power supply ripple is urgently needed to solve this problem.

[0004] Chinese patent document CN106160464A discloses a "power supply system for reducing output ripple". It includes a BUCK converter with an energy storage element, a working circuit that switches between charging and discharging modes under the action of a pulse width modulation signal to output a first voltage; a control circuit that generates the pulse width modulation signal under the action of a clock pulse signal generated by a clock unit, a voltage feedback signal sampled from the first voltage, and a current detection signal; a charge pump circuit, including a voltage regulating circuit with an energy storage capacitor, used to convert the first voltage into a negative voltage, the voltage regulating circuit achieving voltage conversion by switching between charging and discharging modes under the action of a set of switching control signals; and a charge pump control circuit connected to the clock unit for generating the switching control signals; under the action of the clock unit, both the working circuit and the voltage regulating circuit are in charging mode, or both are in discharging mode. In the power supply system for reducing output ripple of the present invention, the voltage regulating circuit includes an input voltage terminal connected to the first voltage; and an output voltage terminal for outputting the negative voltage. However, this invention still requires an external clock circuit as a switch control signal to control the circuit and reduce power ripple. Summary of the Invention

[0005] This invention primarily addresses the technical problem of existing circuits that cannot combine power supply ripple reduction circuits with clock circuits. It provides a method and circuit for generating a system clock based on power supply ripple reduction. This invention utilizes a circuit to acquire the voltage ripple in the power supply, amplifies and filters out noise to generate a square wave. After frequency testing, the square wave signal is used to generate a clock signal. The generated clock signal controls the circuit to accurately process the voltage ripple in the power supply. Since the frequency of the voltage ripple is relatively fixed, the clock signal generated from the voltage ripple can precisely control the circuit to reduce voltage ripple, while eliminating the need for a separate clock oscillation circuit as a switching signal to control the power supply ripple reduction circuit, thus simplifying the circuit.

[0006] The above-mentioned technical problems of the present invention are mainly solved by the following technical solution: the steps of the present invention include S1 separating the voltage ripple and amplifying the signal; S2 rectifies the amplified ripple signal and performs frequency detection; S3 generates a clock circuit based on the frequency point to reduce power supply ripple.

[0007] To reduce voltage ripple in a power supply, existing circuits typically require an additional clock oscillator circuit as a switching signal to control the entire circuit and reduce power supply ripple. Adding an extra clock oscillator circuit complicates the overall circuit structure. In voltage conversion, PWM control generates voltage ripple, and the frequency of this ripple is fixed. Utilizing this characteristic, this invention acquires the power supply voltage ripple, processes it to generate a square wave, detects the frequency of the square wave, and converts the square wave to form a clock signal. This clock signal is then used as the switching signal for the circuit to reduce power supply ripple. Because the frequency of the power supply ripple is relatively fixed, using the generated clock signal as the trigger signal for reducing power supply ripple is closer to the generation frequency of the power supply ripple, thus helping the circuit to more accurately reduce the voltage ripple generated by the power supply and improve the stability of the circuit and the system it belongs to. Simultaneously, eliminating the need for an external clock oscillator circuit simplifies the overall circuit structure.

[0008] Preferably, in step S2, the filtering section of the circuit filters out the power supply noise attached to the voltage ripple, and the frequency conversion section of the circuit confirms the frequency of the filtered voltage ripple. Then, the voltage ripple after confirming the frequency is frequency-converted. The power supply ripple generated by the power supply contains noise, which affects the subsequent frequency detection of the voltage ripple, causing the generated clock signal to not match the frequency of the voltage ripple. This results in the circuit being unable to accurately reduce the power supply ripple. Therefore, after acquiring the power supply ripple, it needs to be filtered. The filtered voltage ripple facilitates more accurate frequency identification by the subsequent frequency conversion section of the circuit.

[0009] Preferably, in step S2, after filtering the power supply noise within the voltage ripple, the filtering section converts the power supply ripple into a sine wave and amplifies it before transmitting it to the frequency conversion section. Upon receiving the sine wave, the frequency conversion section converts it into a square wave and then calculates and transforms the frequency. Power supply ripple is typically a sawtooth or triangular wave. Directly converting it to a square wave might lead to higher harmonic distortion. Therefore, after passing through the filtering section, the power supply ripple is first converted into a sine wave, which is then converted into a square wave by the frequency conversion section. By detecting the time interval between the rising and falling edges of the square wave, its frequency can be determined, thereby generating a more accurate clock signal.

[0010] Preferably, in step S1, after extracting the voltage ripple from the power supply, the signal amplification section amplifies the acquired voltage ripple. Since the original voltage ripple has a low voltage value, processing and confirming the frequency of the signal wave is relatively difficult. Therefore, amplifying the voltage ripple after acquisition facilitates subsequent signal ripple processing.

[0011] Preferably, in step S3, based on the square wave signal generated by the frequency converter, the clock output section uses the square wave signal to generate a clock signal as a switching signal to control the circuit and reduce power supply ripple. The sinusoidal voltage ripple is converted into a square wave after passing through the zero-crossing comparator of the frequency converter. The frequency of the square wave can be calculated based on the interval between its rising and falling edges. After being transmitted to the frequency converter, the frequency is changed according to actual needs and output to the clock output section. The clock output section generates a corresponding clock signal based on the frequency-converted square wave. The voltage ripple reduction circuit can accurately reduce voltage ripple to protect the circuit and its corresponding equipment.

[0012] A circuit for reducing power supply ripple includes a power supply section and a clock output section. A ripple extraction section and a filtering section are located between the power supply section and the clock output section. A signal amplification section is located between the ripple extraction section and the filtering section. A frequency conversion section is located between the filtering section and the clock output section. The ripple extraction section primarily extracts the voltage ripple from the power supply. After extraction, the amplification section amplifies the obtained voltage ripple signal. The filtering section primarily filters noise from the voltage ripple, making the waveform clearer. After filtering noise from the voltage ripple, the frequency conversion section performs waveform conversion and frequency detection, changing the output waveform to a square wave. Finally, the square wave voltage ripple is transmitted to the clock output section to generate the clock signal required for ripple reduction.

[0013] Preferably, the frequency conversion section includes a zero-crossing comparator and a frequency converter, with a frequency detector located between the zero-crossing comparator and the frequency converter. The signal amplification section includes an operational amplifier. The zero-crossing comparator is essentially a zero-crossing circuit. By detecting the zero-crossing moment of a sine wave, it can output a corresponding square wave. After obtaining the square wave, the frequency and frequency point of the voltage ripple can be clearly determined.

[0014] Preferably, the ripple extraction section is equipped with a high-pass filter, and the filtering section is equipped with a filter. After setting the range of voltage ripple to be extracted, the ripple extraction section filters out the remaining ripple signals, retaining only the required voltage ripple signal. However, the acquired voltage ripple signal still contains some noise, so the filtering section further filters the extracted voltage ripple signal and removes excess noise.

[0015] The beneficial effects of this invention are: this invention does not require a separate clock oscillation circuit as a control signal. After processing the power ripple generated by the power supply, the clock signal is generated by frequency conversion and used as a switching signal to control the circuit to reduce power ripple and improve circuit stability. At the same time, the clock oscillation circuit is reduced, simplifying the circuit structure. Attached Figure Description

[0016] Figure 1 This is a flowchart of a method for generating a system clock based on reducing power supply ripple according to the present invention.

[0017] Figure 2 This is a structural diagram of a circuit based on reducing power supply ripple to generate a system clock according to the present invention.

[0018] Figure 3 This is a structural diagram of a method for generating a system clock based on reducing power supply ripple according to the present invention.

[0019] The diagram shows: 1. Ripple extraction section, 2. Signal amplification section, 3. Filtering section, 4. Frequency conversion section, and 5. Clock output section. Detailed Implementation

[0020] The technical solution of the present invention will be further described in detail below through embodiments and in conjunction with the accompanying drawings.

[0021] Example: This example describes a method and circuit for generating a system clock based on reducing power supply ripple, such as... Figure 1 As shown, S1 separates the voltage ripple and amplifies the signal; S2 rectifies the amplified ripple signal and performs frequency detection; S3 generates a clock circuit based on the frequency point to reduce power supply ripple.

[0022] After extracting the voltage ripple from the power supply, the signal amplification section amplifies the acquired voltage ripple. The filtering section filters out power supply noise from the voltage ripple, and the frequency conversion section confirms the frequency of the filtered voltage ripple. The frequency of the ripple after frequency confirmation is then converted. After filtering out power supply noise, the filtering section converts the power supply ripple into a sine wave and amplifies it before transmitting it to the frequency conversion section. Upon receiving the sine wave, the frequency conversion section converts it into a square wave and then calculates and converts the frequency. Based on the square wave signal generated by the frequency conversion section, the clock output section uses the square wave signal to generate a clock signal as a switching signal to control the circuit to reduce power supply ripple.

[0023] During normal operation, the power supply generates voltage ripple due to PWM control during voltage transformation. This voltage ripple travels with the voltage to related chips and devices, affecting system stability. However, since the voltage ripple originates from PWM control, its frequency is fixed. Most existing methods for reducing power supply ripple involve adding a separate clock oscillation circuit to the voltage ripple reduction circuit. The clock oscillation frequency is set and used as the switching signal to reduce the voltage ripple generated by the power supply. This setup requires adding new circuitry, making the overall voltage ripple reduction circuit structure complex. Furthermore, before using the separate clock oscillation circuit, the voltage ripple frequency of the power supply must be recalculated, and a matching oscillation frequency must be set in the clock oscillation circuit to control the circuit and reduce voltage ripple, making the process cumbersome. To address this issue, this implementation combines the voltage ripple reduction circuit with a clock oscillation circuit. Based on the relatively fixed frequency of voltage ripple, this embodiment obtains the voltage ripple generated by the power supply, processes it, and obtains its frequency. This frequency is then used to generate a corresponding clock signal as the switching signal for the entire circuit, controlling the circuit to reduce voltage ripple and improve circuit stability. The bandwidth is determined based on the characteristics of the voltage ripple signal and the tolerable noise level, including determining the frequency range of the bandpass filter. For example, assuming the control PWM is f, then the effective bandwidth is set to f ± 10%. When acquiring the voltage ripple, a filter is needed to filter out excess signals. The filter can be an RC circuit, an LC circuit, or a digital filter. The selection is based on whether the filter can provide a steeper roll-off, as well as the circuit and the longer processing delay. Parameters such as filter order, passband ripple, and stopband attenuation need to be considered. Because the ripple amplitude is relatively small (approximately 1%–5% of the voltage), after filtering out the ripple, the acquired voltage ripple needs to be amplified and rectified. Before amplification and rectification, the required gain needs to be calculated, and then an appropriate amplifier type needs to be selected to achieve that gain. Again, assuming the ripple frequency is f, the ripple magnitude is Vrp, and the amplified value is Vamp, the main principle is as follows: When calculating the required gain, the required voltage gain needs to be calculated first. The gain A can be calculated using the following formula: A = V out / V_in Among them, V out V is the output voltage, and V_in is the input voltage. In this example, V... out =Vamp, V in =Vrp. Substituting these values ​​into the above formula, we get A = Vamp = Vrp, therefore an amplifier with a gain of A is needed. Different types of amplifiers are selected based on the required gain and signal frequency. For a signal f, an operational amplifier (Op-Amp) can be chosen. Operational amplifiers are very common linear integrated circuits that can be used to implement various analog signal processing functions. An operational amplifier will be used to implement non-inverting amplification. To achieve the required gain, a simple operational amplifier, such as a non-inverting amplifier circuit, can be used. This circuit consists of an operational amplifier and two resistors. In the design, first select an operational amplifier suitable for the signal f. When selecting an operational amplifier, ensure that its gain-bandwidth product (GBW) is greater than the product of the required signal frequency and the gain, i.e., the gain-bandwidth product needs to be greater than 60 * f. Then, select an appropriate feedback resistor Rf and input resistor Ri according to the required gain. The gain can be calculated using the following formula: A = 1 + (Rf / Ri). Finally, connect the selected operational amplifier, feedback resistor, and input resistor together to form the non-inverting amplifier circuit. After the voltage ripple is amplified, the filtering section performs noise filtering on the obtained voltage ripple and converts the voltage ripple from a triangular sawtooth wave to a sine wave. During the conversion, a sawtooth wave with frequency f and amplitude Vamp is converted into a sine wave with frequency f. In this real-time example, a low-pass filter (LPF) is used to achieve this. The sawtooth wave contains the fundamental frequency and all its odd harmonics. By using a low-pass filter, harmonic components higher than the fundamental frequency can be filtered out, thus obtaining a waveform close to a sine wave. The Fourier series expression of the sawtooth wave is: In the formula, n is an odd number, and f is the fundamental frequency. This indicates that the sawtooth wave contains the fundamental frequency and all its odd harmonic components. To convert the sawtooth wave into a sine wave, the cutoff frequency of the low-pass filter is slightly higher than the fundamental frequency f. This allows the fundamental frequency to pass through while filtering out harmonic components higher than the fundamental frequency. In practical applications, a suitable cutoff frequency needs to be selected based on signal characteristics, filter performance, and system requirements. Various types of low-pass filters are available in actual production processes, such as RC circuits, LC circuits, or digital filters. The appropriate filter type should be selected based on the application and hardware requirements. In some cases, digital filters may be more suitable for handling complex signal and noise environments. After the voltage ripple passes through the filtering section, frequency detection is required.

[0024] To determine the frequency f of a sine wave during frequency detection, a zero-crossing detection circuit can be used. This circuit converts the sine wave into a square wave, and the period of the square wave is measured to calculate the frequency. The zero-crossing detection circuit detects when the sine wave signal crosses a zero. The output of this circuit changes direction when the sine wave crosses a zero. A typical zero-crossing detection circuit consists of an operational amplifier or comparator. The input signal is compared to a reference voltage (usually 0V or close to 0V). When the input signal is higher than the reference voltage, the output is high; when the input signal is lower than the reference voltage, the output is low. The output of the zero-crossing detection circuit is a square wave signal with the same frequency as the input sine wave. The level of the square wave signal changes direction each time the sine wave crosses a zero. Therefore, measuring the period of the square wave yields the frequency of the sine wave. Alternatively, a microcontroller (MCU) counter / timer can be used: the pulse width or period of the square wave signal can be detected using the MCU's counter / timer function. The frequency of the sine wave is calculated by measuring the period of the square wave. The frequency of the sine wave is equal to the reciprocal of the square wave period T, i.e., f = 1 / T. Alternatively, a dedicated frequency counter chip can be used. Existing frequency counter chips can be used to measure periods or frequencies. Inputting a square wave signal into the frequency counter will output the corresponding sine wave frequency value. Besides, frequency detection of a sine wave can also be achieved using a trigger and a counter. Inputting a square wave signal into a trigger, such as a monostable multivibrator, will allow the trigger's output signal to drive a counter. The number of triggers within a certain time period is recorded. By measuring the number of triggers and the measurement time, the frequency of the sine wave can be calculated. Once the frequency f of the sine wave is detected, the corresponding square wave enters a PLL circuit. The PLL circuit converts the square wave to obtain the frequency point f1 required by the system's CLK. Assuming the ripple frequency range is f (100kHz-2MHz), and the signal frequency range required by the system's CLK is f1 (1MHz-37MHz), the frequency multiple between the input frequency f and the output frequency f1 is first calculated. For example, if the input frequency is 100kHz, to convert it to an output frequency of 1MHz, a circuit with a frequency multiple of 10 is needed. In this embodiment, a digital phase-locked loop (DPLL) is used in the frequency conversion process. DPLL is a closed-loop feedback control system that synchronizes the frequency of the output signal with the frequency of the input signal. A DPLL can be used to implement frequency multiplication. A typical DPLL includes a phase comparator, a loop filter, a voltage-controlled oscillator (VCO), and a frequency divider. During design, a suitable DPLL chip, such as the 74HC4046 or a corresponding PLL device, must first be selected. Ensure the chip has appropriate input and output frequency ranges. Then, select appropriate frequency dividers and multipliers based on the input frequency f and output frequency f1. For example, if the input frequency is 100kHz and the output frequency is 1MHz, a 10x frequency multiplication is required. The frequency divider and multiplier of the DPLL chip can be configured accordingly.When designing the loop filter, select appropriate filter components, such as resistors and capacitors, according to the specifications of the DPLL chip and design requirements. The filter helps improve the performance and stability of the phase-locked loop. Finally, connect the DPLL circuit, connecting the input square wave signal to the input terminal of the DPLL chip, and the frequency-converted square wave signal can be obtained from the output terminal. After the square wave completes frequency conversion, it is fed into the clock output section to generate the required clock signal. The clock signal is fed back to the circuit to accurately reduce voltage ripple.

[0025] like Figure 2 As shown, the circuit for reducing power supply ripple includes a power supply section and a clock output section. Between the power supply section and the clock output section are a ripple extraction section and a filtering section. Between the ripple extraction section and the filtering section is a signal amplification section. Between the filtering section and the clock output section is a frequency conversion section. The frequency conversion section includes a zero-crossing comparator and a frequency converter. Between the zero-crossing comparator and the frequency converter is a frequency detector. The signal amplification section includes an operational amplifier. The ripple extraction section includes a high-pass filter, and the filtering section includes a filter. In the circuit, one end of the power supply is connected to ground and one end of resistor R1. The other end of the power supply is connected to one end of capacitor C1. The other end of capacitor C1 is connected to the other end of resistor R1 and pin 1 of chip U1. Pin 2 is grounded through resistor R2. Pin 2 is also connected to pin A of chip U1 through resistor R3. Pin A is grounded through resistor RL and is also connected to one end of resistor R4. The other end of resistor R4 is grounded through capacitor C3. The other end of resistor R4 is also connected to one end of resistor R5 and capacitor C through resistor R6. One end of resistor R5 is connected to ground via capacitor C4, and also to pin 1 of chip U2. Capacitor C2 is connected to pin A of chip U2, and pin 2 of chip U2 is also connected to pin A. Pin A of chip U2 is connected to pin 1 of chip U3, pin 2 of chip U3 is grounded, pin A of chip U3 is connected to the GPIO pin of MCU and the CLKref pin of chip U4, the SPI pin of chip MCU and the SPI pin of chip U4 are connected, and the PLL pin of chip U4 is connected to the external circuit. In this embodiment, the ripple extraction part of the circuit is mainly a first-order high-pass filter, which is made by capacitor (C1) and resistor (R1). After this part, a 150mV, 500kHz signal will be obtained. When designing this part of the circuit, it is necessary to calculate the required capacitor and resistor values, assuming that the cutoff frequency of the high-pass filter is expected to be close to 500kHz. The cutoff frequency (fc) is given by the following formula: f C=1 / (2*π*R1*C1), choose a suitable resistor value, for example, R1 = 100Ω. Substitute into the cutoff frequency formula to solve for C1, which is a 3.18nF capacitor. The signal amplification section mainly uses a negative feedback amplifier circuit to achieve the desired effect. In this embodiment, amplifying a 150mV, 500kHz signal to 1.8V, 500kHz can be achieved using, but is not limited to, an operational amplifier (Op-Amp). Taking a non-inverting amplifier circuit as an example, the required gain needs to be determined first. Gain is the ratio of output voltage to input voltage. When amplifying 150mV to 1.8V, the gain formula is: Therefore, Gain = 1.8V / 0.15V = 12. Next, select a suitable operational amplifier. Considering the input signal frequency is 500kHz, the operational amplifier's bandwidth needs to be greater than 500kHz. Then, use two resistors to set the negative feedback. According to the formula: Since a gain of 12 is required, R2 = 1kΩ and R3 = 11kΩ can be selected. These values ​​can be fine-tuned in the actual circuit to obtain an accurate gain value. After the circuit is connected, the output signal will be obtained from the output of the operational amplifier, which is 1.8V, 500kHz. In practical applications, the signal amplification section also needs to consider factors such as power supply voltage, power supply noise, and power supply bypass. Since the power supply ripple is a sawtooth / triangular wave containing odd harmonics, directly converting it to a square wave may lead to higher harmonic distortion. Therefore, the amplified power supply ripple needs to be filtered to convert the triangular wave to a sine wave. Then, the frequency conversion section converts the sine wave to a square wave. In this embodiment, the filtering section uses a third-order low-pass filter, and an active filter is designed based on the Sallen-Key topology. The Sallen-Key topology can achieve third-order filtering by cascading two Sallen-Key filters. During the design, the cutoff frequency (fc) is determined and set to 550kHz. Then, the filter type is selected. The Sallen-Key filter can implement various types of filters, such as Butterworth, Chebyshev, or elliptic filters. Because Butterworth filters have flat passband and stopband characteristics, a first-order RC low-pass filter is cascaded with a second-order Sallen-Key Butterworth filter. A sawtooth wave signal is input to the input of the first-order RC low-pass filter, and the output of the first-order filter is connected to the input of the second-order Sallen-Key filter. Finally, the filtered signal is obtained from the output of the second-order Sallen-Key filter. The output of the first-order RC low-pass filter (the junction of the resistor and capacitor) is connected to the input of the second-order Sallen-Key filter (i.e., the non-inverting input of the operational amplifier). The filtered signal is obtained from the output of the second-order Sallen-Key filter. This is the design and connection of a third-order low-pass filter. Through this cascading method, a third-order Butterworth filter with a steeper roll-off characteristic can be achieved. The power supply ripple after filtering enters the frequency converter section in the form of a sine wave for further processing. In this embodiment, after entering the frequency converter section, the frequency point of the sinusoidal voltage ripple needs to be detected. The steps are as follows: the sinusoidal signal from the previous stage is converted into a square wave by a zero-crossing comparator. Using an MCU similar to STM32 or other microcontrollers, input is sent to GPIO. The time interval between rising and falling edges is counted through GPIO to measure the signal period and calculate the frequency. The frequency conversion process is as follows: the frequency information from the previous stage is transmitted to the next-stage frequency conversion chip via a control bus such as SPI / IIC. After receiving the frequency information, the multiplication factor is calculated.Additionally, the square wave signal preceding U3 is simultaneously connected to the reference CLK input point of this module, thereby synthesizing the desired CLK frequency and inputting it into the clock output section. Finally, the clock output section transmits the frequency-converted voltage ripple to the circuit in the form of a clock signal, achieving the effect of reducing voltage ripple. The ripple reduction circuit of this invention eliminates the need for an additional clock oscillation circuit as a control circuit to reduce the voltage ripple switching signal. It utilizes the fixed frequency characteristic of the voltage ripple itself to generate a clock signal as a switch control circuit to process the voltage ripple. This simplifies the circuit structure and combines the clock circuit with the voltage ripple reduction circuit, enabling the circuit to more accurately reduce the harm caused by voltage ripple and improve the stability of the circuit and device.

Claims

1. A method for generating a system clock based on reducing power supply ripple, characterized in that the steps include... include: S1 separates the voltage ripple and amplifies the signal; S2 rectifies the amplified ripple signal and performs frequency detection, including: filtering the power supply noise attached to the amplified voltage ripple, converting the voltage ripple into a sine wave and amplifying it for transmission to the frequency conversion section, and converting the sine wave into a square wave through a zero-crossing comparator after receiving the sine wave, and calculating the frequency of the square wave by the time interval between the rising and falling edges of the square wave. S3 generates a clock circuit based on the frequency point to reduce power supply ripple; it utilizes the fixed frequency point of the voltage ripple itself to generate a clock signal as a switch control circuit to process the voltage ripple.

2. The method for generating a system clock based on reducing power supply ripple according to claim 1, characterized in that, In step S2, after the square wave is transmitted to the frequency converter section, the frequency is changed according to actual needs and then output to the clock output section.

3. The method for generating a system clock based on reducing power supply ripple according to claim 1, characterized in that, In step S1, after the ripple acquisition section extracts the voltage ripple in the power supply, the signal amplification section amplifies the acquired voltage ripple.

4. The method for generating a system clock based on reducing power supply ripple according to claim 1, characterized in that, In step S3, based on the square wave signal generated by the frequency converter, the clock output section uses the square wave signal to generate a clock signal as a switching signal to control the circuit and reduce power ripple.

5. A circuit applied to the method for generating a system clock based on reducing power supply ripple as described in any one of claims 1 to 4, characterized in that, It includes a power supply section and a clock output section. Between the power supply section and the clock output section, there is a ripple extraction section and a filtering section. Between the ripple extraction section and the filtering section, there is a signal amplification section. Between the filtering section and the clock output section, there is a frequency conversion section. After filtering the voltage ripple noise, the frequency conversion section performs waveform conversion and frequency point detection processing, and the output waveform is also changed to a square wave. Finally, the square wave voltage ripple is transmitted to the clock output section to generate the clock signal required to reduce ripple.

6. The circuit according to claim 5, which is characterized in that, The frequency conversion section includes a zero-crossing comparator and a frequency converter, and a frequency detector is provided between the zero-crossing comparator and the frequency converter. The signal amplification section includes an operational amplifier.

7. The circuit according to claim 5, which is characterized in that, The ripple extraction section is equipped with a high-pass filter, and the filtering section is equipped with a filter.

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