Methods and devices for preventing output overflow of sweep frequency phase-locked loop phase detectors and millimeter-wave radar

Abstract

This invention provides a method, apparatus, and millimeter-wave radar for preventing output overflow of a swept-frequency phase-locked loop (PLL) phase detector, relating to the fields of radio frequency and millimeter-wave integrated circuit technology. The method includes: dividing the range of the swept-frequency PLL phase detector into multiple regions; acquiring a first output value and a second output value of the swept-frequency PLL phase detector in adjacent cycles; determining whether the output of the swept-frequency PLL phase detector has overflowed based on the first and second output values ​​and the regions corresponding to each output value; and, in the case of output overflow, setting the output of the swept-frequency PLL phase detector to 0 and correcting the counter value according to the direction of the overflow. This invention prevents erroneous frequency differences from being input into the loop during the overflow cycle, improving the sweep frequency linearity, ensuring loop stability, and avoiding the deterioration of the sweep frequency difference due to phase detector overflow. It also features low implementation cost and robust reliability.

Description

Technical Field

[0001] This invention relates to the field of radio frequency and millimeter-wave integrated circuit technology, and in particular to a method, apparatus and millimeter-wave radar for preventing output overflow of a swept-frequency phase-locked loop phase detector. Background Technology

[0002] Millimeter-wave radar has garnered widespread attention due to its all-weather, low-cost, and high-precision characteristics. In recent years, it has been increasingly applied in fields such as autonomous driving, smart terminals, and industrial production. Frequency Modulated Continuous Wave (FMCW) is a ranging method for millimeter-wave radar. The principle of FMCW ranging is to measure the difference between the transmitted and received frequencies and calculate the distance to the target based on the sweep bandwidth and period.

[0003] Phase-locked loops (PLLs) are a method for generating fixed-frequency and swept-frequency signals, offering advantages such as low power consumption and low cost, making them suitable for mobile terminals. Using a PLL as an FMCW signal source is a cost-effective solution. However, during the swept-frequency process, the nonlinearity of the frequency-control word relationship of the digitally controlled oscillator (DCO) in the PLL circuit can disturb the steady-state of the swept-frequency loop, preventing the phase detector output from stabilizing at zero.

[0004] As the sweep slope increases, the effect of nonlinear disturbance intensifies, causing the phase detector output to fluctuate violently to the point of overflow (i.e., exceeding the phase detector's range). Once phase detector overflow occurs, an erroneous phase detection signal will be input into the loop, causing the loop to be violently disturbed and break out of the locked state, corresponding to a sharp deterioration in the sweep linearity of the output signal.

[0005] Therefore, in order to achieve the generation of fast frequency sweep signals, a new method is proposed to prevent the phase detector of the frequency sweep phase-locked loop from losing lock due to phase detector overflow during the frequency sweep process, which would then worsen the frequency difference during the frequency sweep. Summary of the Invention

[0006] In view of the above problems, the present invention proposes a method, apparatus and millimeter-wave radar for preventing the output overflow of a swept-frequency phase-locked loop phase detector.

[0007] This invention provides a method for preventing output overflow of a swept-frequency phase-locked loop phase detector, the method comprising:

[0008] The range of the sweep frequency phase-locked loop phase detector is divided into multiple regions;

[0009] Obtain the first output value of the sweep frequency phase-locked loop phase detector in the previous cycle, and obtain the second output value of the sweep frequency phase-locked loop phase detector in the current cycle;

[0010] Based on the first output value and the second output value, and combined with the regions corresponding to the two output values, determine whether the output of the sweep frequency phase-locked loop phase detector overflows;

[0011] If the output of the sweep frequency phase-locked loop phase detector overflows, the output of the sweep frequency phase-locked loop phase detector is set to 0;

[0012] In the event of an output overflow from the sweep frequency phase-locked loop phase detector, the count value of the counter is corrected according to the direction of the overflow. The counter is a counter that counts the output signal of the numerically controlled oscillator.

[0013] Optionally, the range of the swept-frequency phase-locked loop phase detector is divided into multiple regions, including:

[0014] The range of the sweep frequency phase-locked loop phase detector is divided into a first region, a second region, and a third region, wherein the first region is adjacent to the second region but not adjacent to the third region, and the second region is adjacent to the third region.

[0015] Optionally, the measuring range includes: a first end boundary region, a second end boundary region, and an intermediate region;

[0016] The range of the sweep frequency phase-locked loop phase detector is divided into a first region, a second region, and a third region, including:

[0017] The first end boundary region in the range is divided into the first region;

[0018] The second end boundary region in the range is divided into the third region;

[0019] The middle region within the range is divided into the second region;

[0020] Among them, the value farthest from the second end boundary region in the first end boundary region is the first value, and the thermometer code value corresponding to the first value is all 1;

[0021] The value furthest from the first end boundary region in the second end boundary region is the second value, and the thermometer code value corresponding to the second value is all 0.

[0022] Optionally, the first end boundary region includes a range region from the first value to the third value;

[0023] The second end boundary region includes the range from the fourth value to the second value;

[0024] The range regions other than those included in the first end boundary region and the second end boundary region are all range regions included in the intermediate region.

[0025] Wherein, the output code value corresponding to the third value is greater than the output code value corresponding to the fourth value, and the sum of the range region length corresponding to the first end boundary region and the range region length corresponding to the second end boundary region is less than the range region length corresponding to the middle region.

[0026] Optionally, obtaining the first output value of the swept-frequency phase-locked loop phase detector in the previous cycle and obtaining the second output value of the swept-frequency phase-locked loop phase detector in the current cycle includes:

[0027] In the previous cycle, the phases of the reference clock and the feedback clock are obtained respectively, and the first output value is obtained based on the difference between the two phases. The first output value falls in one of the first region, the second region, or the third region according to the size of its corresponding code value.

[0028] Within the current period, the phases of the reference clock and the feedback clock are obtained respectively, and the second output value is obtained based on the difference between the two phases. The second output value falls in one of the first region, the second region, or the third region according to the size of its corresponding code value.

[0029] Optionally, based on the first output value, the second output value, and the regions corresponding to each of the two output values, it is determined whether the output of the sweep frequency phase-locked loop phase detector overflows, including:

[0030] If the code value corresponding to the first output value falls in the first region, and the code value corresponding to the second output value falls in the third region, then the output of the sweep frequency phase-locked loop phase detector overflows.

[0031] If the code value corresponding to the first output value falls in the third region, and the code value corresponding to the second output value falls in the first region, then the output of the sweep frequency phase-locked loop phase detector overflows.

[0032] If the code value corresponding to the first output value falls in the first region, and the code value corresponding to the second output value falls in the second region, then the output of the sweep frequency phase-locked loop phase detector will not overflow.

[0033] If the code value corresponding to the first output value falls in the third region, and the code value corresponding to the second output value falls in the second region, then the output of the sweep frequency phase-locked loop phase detector will not overflow.

[0034] If the code value corresponding to the first output value falls in the first region, and the code value corresponding to the second output value also falls in the first region, then the output of the sweep frequency phase-locked loop phase detector will not overflow.

[0035] If the code value corresponding to the first output value falls in the third region, and the code value corresponding to the second output value also falls in the third region, then the output of the sweep frequency phase-locked loop phase detector will not overflow.

[0036] If the code value corresponding to the first output value falls in the second region, and the code value corresponding to the second output value also falls in the second region, then the output of the sweep frequency phase-locked loop phase detector will not overflow.

[0037] Optionally, in the event of an output overflow by the sweep frequency phase-locked loop phase detector, the counter value is corrected according to the direction of the overflow, including:

[0038] If the code value corresponding to the first output value falls in the first region, and the code value corresponding to the second output value falls in the third region, then the count value of the counter is incremented by 1 for correction.

[0039] If the code value corresponding to the first output value falls in the third region, and the code value corresponding to the second output value falls in the first region, then the count value of the counter is decremented by 1.

[0040] Optionally, after determining whether the output of the swept-frequency phase-locked loop phase detector overflows, the method further includes:

[0041] If the output of the sweep frequency phase-locked loop phase detector does not overflow, the sweep frequency phase-locked loop phase detector outputs the value corresponding to the phase difference between the reference clock and the feedback clock.

[0042] This invention also provides a device for preventing output overflow of a swept-frequency phase-locked loop phase detector, the device comprising:

[0043] The partitioning module is used to divide the range of the sweep frequency phase-locked loop phase detector into multiple regions;

[0044] The acquisition module is used to acquire the first output value of the sweep frequency phase-locked loop phase detector in the previous cycle and to acquire the second output value of the sweep frequency phase-locked loop phase detector in the current cycle.

[0045] An overflow detection module is used to determine whether the output of the sweep frequency phase-locked loop phase detector overflows based on the first output value, the second output value, and the regions corresponding to the two output values.

[0046] The 0-setting module is used to set the output of the sweep frequency phase-locked loop phase detector to 0 when the output of the sweep frequency phase-locked loop phase detector overflows.

[0047] The correction module is used to correct the count value of the counter according to the direction of the overflow when the output of the sweep frequency phase-locked loop phase detector overflows. The counter is a counter that counts the output signal of the numerically controlled oscillator.

[0048] Optionally, the measurement range includes: a first end boundary region, a second end boundary region, and an intermediate region; the division module is specifically used for:

[0049] The range of the sweep frequency phase-locked loop phase detector is divided into a first region, a second region, and a third region, wherein the first region is adjacent to the second region but not adjacent to the third region, and the second region is adjacent to the third region.

[0050] The first end boundary region in the range is divided into the first region;

[0051] The second end boundary region in the range is divided into the third region;

[0052] The middle region within the range is divided into the second region;

[0053] Among them, the value farthest from the second end boundary region in the first end boundary region is the first value, and the code value corresponding to the first value is all 1;

[0054] The value furthest from the first end boundary region in the second end boundary region is the second value, and the code value corresponding to the second value is all 0;

[0055] The first end boundary region includes the range from the first value to the third value;

[0056] The second end boundary region includes the range from the fourth value to the second value;

[0057] The range regions other than those included in the first end boundary region and the second end boundary region are all range regions included in the intermediate region.

[0058] Wherein, the output code value corresponding to the third value is greater than the output code value corresponding to the fourth value, and the sum of the range region length corresponding to the first end boundary region and the range region length corresponding to the second end boundary region is less than the range region length corresponding to the middle region.

[0059] Optionally, the acquisition module is specifically used for:

[0060] In the previous cycle, the phases of the reference clock and the feedback clock are obtained respectively, and the first output value is obtained based on the difference between the two phases. The first output value falls in one of the first region, the second region, or the third region according to the size of its corresponding code value.

[0061] Within the current period, the phases of the reference clock and the feedback clock are obtained respectively, and the second output value is obtained based on the difference between the two phases. The second output value falls in one of the first region, the second region, or the third region according to the size of its corresponding code value.

[0062] Optionally, the overflow detection module is specifically used for:

[0063] If the code value corresponding to the first output value falls in the first region, and the code value corresponding to the second output value falls in the third region, then the output of the sweep frequency phase-locked loop phase detector overflows.

[0064] If the code value corresponding to the first output value falls in the third region, and the code value corresponding to the second output value falls in the first region, then the output of the sweep frequency phase-locked loop phase detector overflows.

[0065] If the code value corresponding to the first output value falls in the first region, and the code value corresponding to the second output value falls in the second region, then the output of the sweep frequency phase-locked loop phase detector will not overflow.

[0066] If the code value corresponding to the first output value falls in the third region, and the code value corresponding to the second output value falls in the second region, then the output of the sweep frequency phase-locked loop phase detector will not overflow.

[0067] If the code value corresponding to the first output value falls in the first region, and the code value corresponding to the second output value also falls in the first region, then the output of the sweep frequency phase-locked loop phase detector will not overflow.

[0068] If the code value corresponding to the first output value falls in the third region, and the code value corresponding to the second output value also falls in the third region, then the output of the sweep frequency phase-locked loop phase detector will not overflow.

[0069] If the code value corresponding to the first output value falls in the second region, and the code value corresponding to the second output value also falls in the second region, then the output of the sweep frequency phase-locked loop phase detector will not overflow.

[0070] Optionally, the correction module is specifically used for:

[0071] If the code value corresponding to the first output value falls in the first region, and the code value corresponding to the second output value falls in the third region, then the count value of the counter is incremented by 1 for correction.

[0072] If the code value corresponding to the first output value falls in the third region, and the code value corresponding to the second output value falls in the first region, then the count value of the counter is decremented by 1.

[0073] Optionally, the device further includes:

[0074] The output module is used to output the value corresponding to the phase difference between the reference clock and the feedback clock when the output of the sweep frequency phase-locked loop phase detector does not overflow.

[0075] This invention also provides a millimeter-wave radar, which includes a swept-frequency phase-locked loop (PLL). The swept-frequency PLL is based on any of the methods described above for preventing the output overflow of the PLL phase detector, thereby preventing the output overflow of the PLL phase detector and generating a swept-frequency signal for use by the millimeter-wave radar.

[0076] The method for preventing output overflow of a swept-frequency phase-locked loop (PLL) phase detector provided by the present invention first divides the range of the PLL phase detector into multiple regions; during operation, the first output value of the PLL phase detector in the previous cycle is continuously acquired, and the second output value of the PLL phase detector in the current cycle is continuously acquired.

[0077] Based on the first output value and the second output value, and combined with the regions corresponding to the two output values, determine whether the output of the sweep frequency phase-locked loop (PLL) phase detector has overflowed; if the output of the sweep frequency PLL phase detector overflows, set the output of the sweep frequency PLL phase detector to 0; if the output of the sweep frequency PLL phase detector overflows, correct the counter value according to the direction of the overflow.

[0078] The method proposed in this invention can accurately detect whether the phase detector output of a frequency sweep phase-locked loop (PLL) overflows. If overflow is detected, the phase detector output is set to 0, and the counter value used for integer phase detection is corrected by +1 or -1 according to the direction of the overflow. This ensures that no erroneous frequency difference (i.e., phase detection signal) is input into the loop during the overflow period, improving the frequency sweep linearity, ensuring loop stability, and preventing the deterioration of the frequency sweep difference due to phase detector overflow. It also features low implementation cost, robustness, and reliability, making it highly practical. Attached Figure Description

[0079] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0080] Figure 1 This is a schematic diagram showing the relationship between the intermediate frequency signal and the frequency sweep slope of a millimeter-wave radar.

[0081] Figure 2This is a flowchart of a method for preventing output overflow of a sweep frequency phase-locked loop phase detector according to an embodiment of the present invention;

[0082] Figure 3 This is a schematic diagram of the area division of the digital time converter (TDC) range (64-bit thermometer code) in an embodiment of the present invention;

[0083] Figure 4 This is a schematic diagram illustrating the principle of preventing output overflow of the sweep frequency phase-locked loop phase detector in an embodiment of the present invention.

[0084] Figure 5 This is a diagram of the sweep frequency phase-locked loop structure in an embodiment of the present invention;

[0085] Figure 6 This is a block diagram of a device for preventing the output overflow of a sweep frequency phase-locked loop phase detector according to an embodiment of the present invention. Detailed Implementation

[0086] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention, and are only some, not all, embodiments of the present invention, and are not intended to limit the present invention.

[0087] The inventors discovered that current millimeter-wave radars primarily use continuous wave frequency modulation (FMCW) for ranging. The principle of FMCW ranging is to measure the difference between the transmitted and received frequencies and calculate the distance to the target based on the sweep bandwidth and period. The distance calculation formula is shown below:

[0088]

[0089] In the above formula, R represents distance, f represents intermediate frequency (IF), FMslope represents sweep slope, and C represents the speed of light. It can be seen from the formula that for a target at a certain distance, the larger the sweep slope FMslope, the higher the corresponding IF frequency f. This helps to keep the IF signal away from the noise inflection point 1 / f of the baseband circuit, and for detecting multiple targets, it helps to differentiate the IF peak values ​​corresponding to different targets. Figure 1 The schematic diagram showing the relationship between the intermediate frequency signal and the sweep slope of the millimeter-wave radar provides a better and more intuitive understanding.

[0090] Figure 1For simplicity, the left side exemplifies the structure of a millimeter-wave radar transmitting and receiving intermediate frequency (IF) signals. Here, Chirp Gen represents the IF signal source, PA represents the output amplifier circuit for the IF signal, LNA represents the receiving amplifier circuit for the IF signal feedback, BPF represents the bandpass filter, ADC represents the analog-to-digital converter, and Target1 and Target2 represent two different detection targets, swept using the slow chirp and fast chirp IF signals, respectively.

[0091] Slow chirp represents a smaller sweep slope, i.e., a gentler sweep slope, while fast chirp represents a larger sweep slope, i.e., a steeper sweep slope. The corresponding sweep slope graphs (horizontal axis: time, vertical axis: frequency) show that the sweep slope of the intermediate frequency (IF) signal corresponding to slow chirp is smaller than that corresponding to fast chirp. Where f... TX This represents the frequency curve of the output intermediate frequency signal, f. RX This represents the frequency curve of the received intermediate frequency signal.

[0092] The frequency difference f between the output intermediate frequency signal and the received intermediate frequency signal corresponding to slow chirp. b Compared to the frequency difference f between the output intermediate frequency signal and the received intermediate frequency signal corresponding to FastChirp, b It is also smaller. The difference between the intermediate frequency (IF) peak values ​​of the two detected targets Target1 and Target2 obtained by the slow chirp sweep is smaller than that obtained by the fast chirp sweep, and the IF signal of the detected target Target2 obtained by the slow chirp sweep is closer to the noise inflection point 1 / f of the circuit. In addition, a faster sweep period can reduce the velocity ambiguity of the detected target. Therefore, a steep sweep slope is of great significance for realizing high-precision continuous wave frequency modulation (FMCW).

[0093] Phase-locked loops (PLLs) are a method for generating fixed-frequency and swept-frequency signals, offering advantages such as low power consumption and low cost, making them suitable for mobile terminals. Using a PLL as an FMCW signal source is a cost-effective solution. However, further research by the inventors revealed that during the swept-frequency process, the nonlinearity of the frequency-control word relationship of the digitally controlled oscillator (DCO) in the PLL circuit disturbs the steady state of the swept-frequency loop, preventing the phase detector output of the PLL from stabilizing at zero.

[0094] As the sweep slope increases, the effect of nonlinear disturbance intensifies, causing the phase detector output to fluctuate violently to the point of overflowing, i.e., exceeding the phase detector's range. Once phase detector overflow occurs, an erroneous phase detection signal will be input into the phase-locked loop, causing the loop to be violently disturbed and break out of the locked state. This corresponds to a sharp deterioration in the sweep linearity of the output signal.

[0095] To address the aforementioned problems, the inventors have creatively proposed a method, apparatus, and millimeter-wave radar for preventing output overflow of a swept-frequency phase-locked loop (PLL) phase detector. The following provides a detailed explanation and description of the method, apparatus, and millimeter-wave radar for preventing output overflow of a swept-frequency PLL phase detector according to this invention.

[0096] Reference Figure 2 The flowchart shown is a method for preventing output overflow of a swept-frequency phase-locked loop phase detector according to the present invention. The method for preventing output overflow of a swept-frequency phase-locked loop phase detector includes the following steps:

[0097] Step 201: Divide the range of the sweep frequency phase-locked loop phase detector into multiple regions.

[0098] First, the range of the sweep frequency PLL phase detector is divided into multiple regions. This lays the foundation for subsequently determining whether the output of the sweep frequency PLL phase detector overflows. A preferred division method is as follows:

[0099] The range of the sweep frequency phase-locked loop phase detector is divided into a first region, a second region, and a third region. The first region is adjacent to the second region, and the first region is not adjacent to the third region. The second region is adjacent to the third region.

[0100] Taking a Time-to-Digital Converter (TDC) as the phase detector in a swept-frequency phase-locked loop as an example: the range of the TDC includes a first boundary region, a second boundary region, and an intermediate region. In the first boundary region, the value furthest from the second boundary region is the first value, and the corresponding code value is all 1s. In the second boundary region, the value furthest from the first boundary region is the second value, and the corresponding code value is all 0s.

[0101] The first boundary region of the measurement range is divided into the first region; the second boundary region of the measurement range is divided into the third region; and the middle region of the measurement range is divided into the second region.

[0102] The first boundary region includes the range from the first value to the third value; the second boundary region includes the range from the fourth value to the second value; the range regions other than those included in the first and second boundary regions are all included in the intermediate region. The output code value corresponding to the third value is greater than the output code value corresponding to the fourth value, and the sum of the lengths of the range regions corresponding to the first and second boundary regions is less than the length of the range region corresponding to the intermediate region.

[0103] To better explain the above division of the measurement range, refer to... Figure 3 The diagram shown illustrates the area division of the TDC (64-bit thermometer code) range. Figure 3 Boundary A can be considered the first end boundary region, and is defined as the first region. Boundary B can be considered the second end boundary region, and is defined as the third region. The region sandwiched between the two is the intermediate region, and is defined as the second region. Based on... Figure 3 The diagram shows that the leftmost value is the first value, which corresponds to a code value of 1, and the rightmost value is the second value, which corresponds to a code value of 0.

[0104] Step 202: Obtain the first output value of the sweep frequency phase-locked loop phase detector in the previous cycle, and obtain the second output value of the sweep frequency phase-locked loop phase detector in the current cycle.

[0105] After the range of the swept-frequency phase-locked loop (PLL) phase detector is defined, in actual operation, it is necessary to acquire the output value of the PLL phase detector in each cycle and make continuous judgments based on the output values ​​of the two adjacent cycles. That is, acquire the first output value of the swept-frequency PLL phase detector in the previous cycle and acquire the second output value of the swept-frequency PLL phase detector in the current cycle.

[0106] The output value is obtained as follows: In the previous cycle, the phases of the reference clock and the feedback clock are obtained, and the first output value is obtained based on the difference between these two phases. The first output value will definitely fall into one of the three regions: the first region, the second region, or the third region, depending on the size of its corresponding code value. Similarly, in the current cycle, the phases of the reference clock and the feedback clock are obtained, and the second output value is obtained based on the difference between these two phases. The second output value will also definitely fall into one of the three regions: the first region, the second region, or the third region, depending on the size of its corresponding code value.

[0107] Step 203: Based on the first output value and the second output value, and combined with the regions corresponding to the two output values, determine whether the output of the sweep frequency phase-locked loop phase detector has overflowed.

[0108] After obtaining the output values ​​of two adjacent cycles and determining that each output value falls within its corresponding region, it is possible to determine whether the output of the sweep frequency phase-locked loop phase detector overflows based on these data.

[0109] A better way to determine this is:

[0110] If the code value corresponding to the first output value falls in the first region and the code value corresponding to the second output value falls in the third region, it is considered that the change in the output value between two adjacent cycles is large. This will cause the output of the sweep frequency phase-locked loop phase detector to exceed the range, that is, the output of the sweep frequency phase-locked loop phase detector overflows.

[0111] Similarly, if the code value corresponding to the first output value falls in the third region and the code value corresponding to the second output value falls in the first region, this situation is essentially the same as the previous one. Both belong to the case where the output values ​​of two adjacent cycles change significantly, which will also cause the output of the sweep frequency phase-locked loop phase detector to exceed the range, that is, the output of the sweep frequency phase-locked loop phase detector overflows.

[0112] Unlike the previous two cases, if the code value corresponding to the first output value falls in the first region and the code value corresponding to the second output value falls in the second region, it is considered that the change in the output value between two adjacent cycles is small. This will not cause the output of the sweep frequency phase-locked loop phase detector to exceed the range, that is, the output of the sweep frequency phase-locked loop phase detector will not overflow.

[0113] It is understandable that if the code value corresponding to the first output value falls in the third region, and the code value corresponding to the second output value falls in the second region, then the output of the sweep frequency phase-locked loop (PLL) phase detector will not overflow. Similarly, if the code value corresponding to the first output value falls in the first region, and the code value corresponding to the second output value also falls in the first region, then the output of the sweep frequency PLL phase detector will not overflow; if the code value corresponding to the first output value falls in the third region, and the code value corresponding to the second output value also falls in the third region, then the output of the sweep frequency PLL phase detector will not overflow; and if the code value corresponding to the first output value falls in the second region, and the code value corresponding to the second output value also falls in the second region, then the output of the sweep frequency PLL phase detector will not overflow.

[0114] Step 204: If the output of the sweep frequency phase-locked loop phase detector overflows, set the output of the sweep frequency phase-locked loop phase detector to 0.

[0115] In the case where the output of the sweep frequency phase-locked loop (PLL) phase detector overflows, in order to avoid an erroneous phase detection signal being input into the loop due to the phase detector overflow, the output of the sweep frequency PLL phase detector is directly set to 0. This way, no erroneous phase detection signal will be input into the loop, and the loop will not be subjected to severe disturbances and break out of the locked state, thus improving the sweep frequency linearity.

[0116] Of course, provided that the output of the sweep frequency phase-locked loop phase detector does not overflow, the sweep frequency phase-locked loop phase detector outputs the value corresponding to the phase difference between the reference clock and the feedback clock according to its set function, that is, it outputs the code value corresponding to the frequency of the reference clock and the feedback clock in the current cycle.

[0117] Step 205: In the event of an output overflow of the sweep frequency phase-locked loop phase detector, the count value of the counter is corrected according to the direction of the overflow. The counter is used to count the output signal of the numerically controlled oscillator.

[0118] In a sweep frequency phase-locked loop circuit, the counter is used to count the output signal of the digitally controlled oscillator (DCO), which is the sweep frequency signal. Therefore, when the phase detector of the sweep frequency phase-locked loop overflows, the counter cannot count according to the normal process, but needs to correct the counter value according to the direction of the overflow.

[0119] The specific correction method is as follows:

[0120] If the code value corresponding to the first output value falls in the first region and the code value corresponding to the second output value falls in the third region, then the counter value is incremented by 1; if the code value corresponding to the first output value falls in the third region and the code value corresponding to the second output value falls in the first region, then the counter value is decremented by 1. Figure 3 That is: if the code value corresponding to the first output value falls within boundary A and the code value corresponding to the second output value falls within boundary B, then the counter value is incremented by 1; if the code value corresponding to the first output value falls within boundary B and the code value corresponding to the second output value falls within boundary A, then the counter value is decremented by 1.

[0121] The principle of preventing output overflow of the sweep frequency phase-locked loop phase detector described above can be combined with... Figure 4 The schematic diagram provided provides a better understanding. If the output of the sweep frequency phase-locked loop phase detector does not overflow, i.e., does not exceed the range, the code value corresponding to the phase difference between the TDC output reference clock and feedback clock can be obtained. From this, the frequency difference between the reference clock and feedback clock can also be derived, for example... Figure 4 As shown: the frequency difference sent into the loop is 3. When the output of the sweep frequency PLL phase detector overflows, for example from A to B (i.e., the code value corresponding to the first output value falls in the first region, and the code value corresponding to the second output value falls in the third region), the TDC output is set to 0, and the counter is corrected by +1, its count value becomes N-1. It is naturally understood that if the output overflow of the sweep frequency PLL phase detector is from B to A, the TDC output is set to 0, the counter is corrected by -1, and its count value becomes N+1.

[0122] The method for preventing output overflow of the sweep frequency phase-locked loop phase detector proposed in this invention combines the overall... Figure 5The sweep frequency phase-locked loop (PLL) structure shown can be summarized as follows: A counter uses a reference signal to count the sweep frequency output (i.e., the sweep frequency signal) of the digitally controlled oscillator (DCO). Simultaneously, the sweep frequency signal serves as the feedback signal received by the digital time converter (DTC), and together with the reference signal, enters the DTC. The DTC is subjected to overflow detection according to steps 201 to 203 described above to determine whether the DTC output has overflowed. Simultaneously, the output code value of the DTC enters a selector via a differential.

[0123] If the digital time converter (DTC) output overflows, the selector directly outputs a fractional frequency difference of 0, and simultaneously corrects the counter to obtain a counter correction value of 1 or -1. Both are then added to or subtracted from the frequency control word to obtain the frequency difference, which is transmitted to the digitally controlled oscillator (DCO) via a loop filter. If the DTC output does not overflow, the selector outputs the DTC output code value processed by the differential converter as the fractional frequency difference. No counter correction is required, and the counter correction value is 0. The DTC output code value processed by the differential converter is then added to or subtracted from the frequency control word to obtain the frequency difference, which is transmitted to the digitally controlled oscillator (DCO) via a loop filter.

[0124] Using the above structure and method, the sweep frequency phase-locked loop circuit can accurately detect whether the phase detector output of the sweep frequency phase-locked loop overflows. If overflow is detected, the phase detector output is set to 0, and the count value of the counter used for integer phase detection is corrected by +1 or -1 according to the direction of overflow. This ensures that no erroneous frequency difference is input into the loop during the current overflow period, improving the sweep frequency linearity, ensuring the stability of the loop state, and avoiding the deterioration of the sweep frequency difference due to phase detector overflow.

[0125] Based on the above-described method for preventing output overflow of a swept-frequency phase-locked loop (PLL) phase detector, this invention also provides a device for preventing output overflow of a swept-frequency PLL phase detector, as described above. Figure 6 The device block diagram shown includes:

[0126] The partitioning module 610 is used to divide the range of the sweep frequency phase-locked loop phase detector into multiple regions;

[0127] The acquisition module 620 is used to acquire the first output value of the sweep frequency phase-locked loop phase detector in the previous cycle and to acquire the second output value of the sweep frequency phase-locked loop phase detector in the current cycle.

[0128] The overflow detection module 630 is used to determine whether the output of the sweep frequency phase-locked loop phase detector overflows based on the first output value, the second output value, and the regions corresponding to the two output values.

[0129] The 0-setting module 640 is used to set the output of the sweep frequency phase-locked loop phase detector to 0 when the output of the sweep frequency phase-locked loop phase detector overflows.

[0130] The correction module 650 is used to correct the count value of the counter according to the direction of the overflow when the output of the sweep frequency phase-locked loop phase detector overflows. The counter is a counter that counts the output signal of the numerically controlled oscillator.

[0131] Optionally, the measuring range includes: a first end boundary region, a second end boundary region, and an intermediate region; the division module 610 is specifically used for:

[0132] The range of the sweep frequency phase-locked loop phase detector is divided into a first region, a second region, and a third region, wherein the first region is adjacent to the second region but not adjacent to the third region, and the second region is adjacent to the third region.

[0133] The first end boundary region in the range is divided into the first region;

[0134] The second end boundary region in the range is divided into the third region;

[0135] The middle region within the range is divided into the second region;

[0136] Among them, the value farthest from the second end boundary region in the first end boundary region is the first value, and the code value corresponding to the first value is all 1;

[0137] The value furthest from the first end boundary region in the second end boundary region is the second value, and the code value corresponding to the second value is all 0;

[0138] The first end boundary region includes the range from the first value to the third value;

[0139] The second end boundary region includes the range from the fourth value to the second value;

[0140] The range regions other than those included in the first end boundary region and the second end boundary region are all range regions included in the intermediate region.

[0141] Wherein, the output code value corresponding to the third value is greater than the output code value corresponding to the fourth value, and the sum of the range region length corresponding to the first end boundary region and the range region length corresponding to the second end boundary region is less than the range region length corresponding to the middle region.

[0142] Optionally, the acquisition module 620 is specifically used for:

[0143] In the previous cycle, the phases of the reference clock and the feedback clock are obtained respectively, and the first output value is obtained based on the difference between the two phases. The first output value falls in one of the first region, the second region, or the third region according to the size of its corresponding code value.

[0144] Within the current period, the phases of the reference clock and the feedback clock are obtained respectively, and the second output value is obtained based on the difference between the two phases. The second output value falls in one of the first region, the second region, or the third region according to the size of its corresponding code value.

[0145] Optionally, the overflow detection module 630 is specifically used for:

[0146] If the code value corresponding to the first output value falls in the first region, and the code value corresponding to the second output value falls in the third region, then the output of the sweep frequency phase-locked loop phase detector overflows.

[0147] If the code value corresponding to the first output value falls in the third region, and the code value corresponding to the second output value falls in the first region, then the output of the sweep frequency phase-locked loop phase detector overflows.

[0148] If the code value corresponding to the first output value falls in the first region, and the code value corresponding to the second output value falls in the second region, then the output of the sweep frequency phase-locked loop phase detector will not overflow.

[0149] If the code value corresponding to the first output value falls in the third region, and the code value corresponding to the second output value falls in the second region, then the output of the sweep frequency phase-locked loop phase detector will not overflow.

[0150] If the code value corresponding to the first output value falls in the first region, and the code value corresponding to the second output value also falls in the first region, then the output of the sweep frequency phase-locked loop phase detector will not overflow.

[0151] If the code value corresponding to the first output value falls in the third region, and the code value corresponding to the second output value also falls in the third region, then the output of the sweep frequency phase-locked loop phase detector will not overflow.

[0152] If the code value corresponding to the first output value falls in the second region, and the code value corresponding to the second output value also falls in the second region, then the output of the sweep frequency phase-locked loop phase detector will not overflow.

[0153] Optionally, the correction module 650 is specifically used for:

[0154] If the code value corresponding to the first output value falls in the first region, and the code value corresponding to the second output value falls in the third region, then the count value of the counter is incremented by 1 for correction.

[0155] If the code value corresponding to the first output value falls in the third region, and the code value corresponding to the second output value falls in the first region, then the count value of the counter is decremented by 1.

[0156] Optionally, the device further includes:

[0157] The output module is used to output the value corresponding to the phase difference between the reference clock and the feedback clock when the output of the sweep frequency phase-locked loop phase detector does not overflow.

[0158] Based on the above-described method for preventing the output overflow of the phase detector in a frequency-sweeping phase-locked loop, this embodiment of the invention also provides a millimeter-wave radar, which includes a frequency-sweeping phase-locked loop; the frequency-sweeping phase-locked loop prevents the output overflow of the phase detector in the frequency-sweeping phase-locked loop based on the method for preventing the output overflow of the phase detector in any of steps 201 to 205, and generates a frequency-sweeping signal for use by the millimeter-wave radar.

[0159] In summary, the method for preventing output overflow of a swept-frequency phase-locked loop (PLL) phase detector provided by the present invention first divides the range of the PLL phase detector into multiple regions; during operation, it continuously acquires the first output value of the PLL phase detector in the previous cycle and continuously acquires the second output value of the PLL phase detector in the current cycle.

[0160] Based on the first output value and the second output value, and combined with the regions corresponding to the two output values, determine whether the output of the sweep frequency phase-locked loop (PLL) phase detector has overflowed; if the output of the sweep frequency PLL phase detector overflows, set the output of the sweep frequency PLL phase detector to 0; if the output of the sweep frequency PLL phase detector overflows, correct the counter value according to the direction of the overflow.

[0161] The method proposed in this invention can accurately detect whether the phase detector output of a frequency sweep phase-locked loop (PLL) overflows. If overflow is detected, the phase detector output is set to 0, and the counter value used for integer phase detection is corrected by +1 or -1 according to the direction of the overflow. This ensures that no erroneous frequency difference (i.e., phase detection signal) is input into the loop during the overflow period, improving the frequency sweep linearity, ensuring loop stability, and preventing the deterioration of the frequency sweep difference due to phase detector overflow. It also features low implementation cost, robustness, and reliability, making it highly practical.

[0162] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0163] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0164] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. A method for preventing output overflow of a swept-frequency phase-locked loop phase detector, characterized in that, The method includes: The range of the sweep frequency phase-locked loop phase detector is divided into multiple regions; Obtain the first output value of the sweep frequency phase-locked loop phase detector in the previous cycle, and obtain the second output value of the sweep frequency phase-locked loop phase detector in the current cycle; Based on the first output value and the second output value, and combined with the regions corresponding to the two output values, determine whether the output of the sweep frequency phase-locked loop phase detector overflows; If the output of the sweep frequency phase-locked loop phase detector overflows, the output of the sweep frequency phase-locked loop phase detector is set to 0; if the output of the sweep frequency phase-locked loop phase detector does not overflow, the sweep frequency phase-locked loop phase detector outputs the value corresponding to the phase difference between the reference clock and the feedback clock. In the event of an output overflow from the sweep frequency phase-locked loop phase detector, the count value of the counter is corrected according to the direction of the overflow. The counter is a counter that counts the output signal of the numerically controlled oscillator.

2. The method according to claim 1, characterized in that, The range of the sweep frequency phase-locked loop phase detector is divided into multiple regions, including: The range of the sweep frequency phase-locked loop phase detector is divided into a first region, a second region, and a third region, wherein the first region is adjacent to the second region but not adjacent to the third region, and the second region is adjacent to the third region.

3. The method according to claim 2, characterized in that, The measurement range includes: a first end boundary region, a second end boundary region, and an intermediate region; The range of the sweep frequency phase-locked loop phase detector is divided into a first region, a second region, and a third region, including: The first end boundary region in the range is divided into the first region; The second end boundary region in the range is divided into the third region; The middle region within the range is divided into the second region; Among them, the value that is farthest from the second end boundary region in the first end boundary region is the first value, and the thermometer code value corresponding to the first value is all 1; The value furthest from the first end boundary region in the second end boundary region is the second value, and the thermometer code value corresponding to the second value is all 0.

4. The method according to claim 3, characterized in that, The first end boundary region includes the range from the first value to the third value; The second end boundary region includes the range from the fourth value to the second value; The range regions other than those included in the first end boundary region and the second end boundary region are all range regions included in the intermediate region. Wherein, the output code value corresponding to the third value is greater than the output code value corresponding to the fourth value, and the sum of the range region length corresponding to the first end boundary region and the range region length corresponding to the second end boundary region is less than the range region length corresponding to the middle region.

5. The method according to claim 2, characterized in that, Acquiring the first output value of the swept-frequency phase-locked loop phase detector in the previous cycle and acquiring the second output value of the swept-frequency phase-locked loop phase detector in the current cycle includes: In the previous cycle, the phases of the reference clock and the feedback clock are obtained respectively, and the first output value is obtained based on the difference between the two phases. The first output value falls in one of the first region, the second region, or the third region according to the size of its corresponding code value. Within the current period, the phases of the reference clock and the feedback clock are obtained respectively, and the second output value is obtained based on the difference between the two phases. The second output value falls in one of the first region, the second region, or the third region according to the size of its corresponding code value.

6. The method according to claim 5, characterized in that, Based on the first output value and the second output value, and considering the regions corresponding to each of the two output values, it is determined whether the output of the sweep frequency phase-locked loop phase detector overflows, including: If the code value corresponding to the first output value falls in the first region, and the code value corresponding to the second output value falls in the third region, then the output of the sweep frequency phase-locked loop phase detector overflows. If the code value corresponding to the first output value falls in the third region, and the code value corresponding to the second output value falls in the first region, then the output of the sweep frequency phase-locked loop phase detector overflows. If the code value corresponding to the first output value falls in the first region, and the code value corresponding to the second output value falls in the second region, then the output of the sweep frequency phase-locked loop phase detector will not overflow. If the code value corresponding to the first output value falls in the third region, and the code value corresponding to the second output value falls in the second region, then the output of the sweep frequency phase-locked loop phase detector will not overflow. If the code value corresponding to the first output value falls in the first region, and the code value corresponding to the second output value also falls in the first region, then the output of the sweep frequency phase-locked loop phase detector will not overflow. If the code value corresponding to the first output value falls in the third region, and the code value corresponding to the second output value also falls in the third region, then the output of the sweep frequency phase-locked loop phase detector will not overflow. If the code value corresponding to the first output value falls in the second region, and the code value corresponding to the second output value also falls in the second region, then the output of the sweep frequency phase-locked loop phase detector will not overflow.

7. The method according to claim 5, characterized in that, In the event of an output overflow from the sweep frequency phase-locked loop phase detector, the counter value is corrected according to the direction of the overflow, including: If the code value corresponding to the first output value falls in the first region, and the code value corresponding to the second output value falls in the third region, then the count value of the counter is incremented by 1 for correction. If the code value corresponding to the first output value falls in the third region, and the code value corresponding to the second output value falls in the first region, then the count value of the counter is decremented by 1.

8. A device for preventing output overflow of a sweep frequency phase-locked loop phase detector, characterized in that, The device includes: The partitioning module is used to divide the range of the sweep frequency phase-locked loop phase detector into multiple regions; The acquisition module is used to acquire the first output value of the sweep frequency phase-locked loop phase detector in the previous cycle and to acquire the second output value of the sweep frequency phase-locked loop phase detector in the current cycle. An overflow detection module is used to determine whether the output of the sweep frequency phase-locked loop phase detector overflows based on the first output value, the second output value, and the regions corresponding to the two output values. The 0-setting module is used to set the output of the sweep frequency phase-locked loop phase detector to 0 when the output of the sweep frequency phase-locked loop phase detector overflows. The output module is used to output the value corresponding to the phase difference between the reference clock and the feedback clock of the sweep frequency phase-locked loop phase detector, provided that the output of the sweep frequency phase-locked loop phase detector does not overflow. The correction module is used to correct the count value of the counter according to the direction of the overflow when the output of the sweep frequency phase-locked loop phase detector overflows. The counter is a counter that counts the output signal of the numerically controlled oscillator.

9. A millimeter-wave radar, characterized in that, The millimeter-wave radar includes: a swept-frequency phase-locked loop; The sweep frequency phase-locked loop is based on the method for preventing the output overflow of the sweep frequency phase-locked loop phase detector as described in any one of claims 1-7, to prevent the output overflow of the sweep frequency phase-locked loop phase detector and to generate a sweep frequency signal for use by the millimeter-wave radar.

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