C-PHY data-triggered edge generation with inherent half-rate operation

Abstract

Methods, apparatuses, and systems for clock and data recovery in a C-PHY interface are disclosed. A receiving device has a recovery circuit and a plurality of differential receivers. The differential receivers are configured to generate differential signals. Each differential signal represents a voltage difference between a pair of wires in a three-wire serial bus. The recovery circuit is configured to identify a first differential signal having a largest voltage magnitude among the plurality of differential signals in a first unit interval, and determine a signaling state of the three-wire serial bus for the first unit interval based on an identification of the pair of wires corresponding to the first differential signal and a polarity of the first differential signal in the first unit interval, and generate a first edge in a clock signal in response to a transition of the first differential signal during the first unit interval.

Description

[0001] Cross-reference / priority requirements of related applications

[0002] This patent application claims priority and benefit to Pending Non-Provisional Application No. 17 / 162497, filed January 29, 2021, with the United States Patent and Trademark Office, the entire contents of which are incorporated herein by reference as if their entire contents were fully set forth below for all applicable purposes. Technical Field

[0003] This disclosure generally relates to high-speed data communication interfaces, and more specifically, to improved clock recovery in receivers. Background Technology

[0004] Manufacturers of mobile devices, such as cellular phones, can obtain components from a variety of sources, including different manufacturers. For example, the application processor in a cellular phone might be obtained from a first manufacturer, the imaging device or camera from a second manufacturer, and the display from a third manufacturer. Application processors, imaging devices, display controllers, or other types of devices can be interconnected using standard-based or proprietary physical interfaces. In one example, an imaging device could be connected using the Camera Serial Interface (CSI) defined by the Mobile Industrial Processor Interface (MIPI) Alliance. In another example, the display could include an interface conforming to the Display Serial Interface (DSI) standard defined by the Mobile Industrial Processor Interface (MIPI) Alliance.

[0005] The C-PHY interface is a multiphase three-wire interface defined by the MIPI Alliance, which uses a group of three conductors to transmit information between devices. During symbol transmission, each conductor in the three-wire group (trio) can be in one of three signaling states. Clock information is encoded in the sequence of transmitted symbols, and the receiver generates a clock signal based on the transitions between consecutive symbols. The ability of the clock and data recovery (CDR) circuitry to recover the clock information may be limited by the maximum time variation associated with the transitions of signals transmitted on different conductors of the communication link. The CDR circuitry in a C-PHY receiver may employ a mask designed to block all transition detection except for the first transition between consecutively transmitted symbols. The timing variation of the first transition limits the maximum data throughput through the C-PHY interface due to the jitter it causes in the received clock and the need for a mask that significantly reduces the sampling window used to capture symbols at the receiver. For these and other reasons, there is a continuous need for optimal clock generation circuitry capable of reliably operating at increasingly higher signal frequencies. Summary of the Invention

[0006] The embodiments disclosed herein provide systems, methods, and apparatuses for implementing improved communication over multi-line and / or multi-phase communication links. The communication links can be deployed in devices (such as mobile terminals) having multiple integrated circuit (IC) devices. Certain techniques disclosed herein improve clock information recovery and enable more reliable capture of wire states at higher data rates. In one aspect, jitter can be reduced by generating edges in the received clock and determining the wire state based on the output of one of three differential receivers.

[0007] In various aspects of this disclosure, a data communication method includes: generating a plurality of difference signals, each difference signal representing a voltage difference between a pair of wires in a three-wire serial bus; identifying a first difference signal among the plurality of difference signals, the first difference signal having the largest voltage value among the plurality of difference signals in a first unit interval; determining a signaling state of the three-wire serial bus for the first unit interval based on the identification of the wire pair corresponding to the first difference signal and the polarity of the first difference signal in the first unit interval; and generating a first edge in a clock signal in response to a transition of the first difference signal during the first unit interval.

[0008] In various aspects of this disclosure, an apparatus for data communication includes a recovery circuit and a plurality of differential receivers configured to generate a plurality of difference signals, each difference signal representing a voltage difference between a pair of wires in a three-wire serial bus. The recovery circuit is configured to: identify a first difference signal having the largest voltage value among the plurality of difference signals in a first unit interval; determine a signaling state for the three-wire serial bus for the first unit interval based on the identification of the wire pair corresponding to the first difference signal and the polarity of the first difference signal in the first unit interval; and generate a first edge in a clock signal in response to a transition of the first difference signal during the first unit interval.

[0009] In various aspects of this disclosure, a non-transitory processor-readable storage medium includes code for: generating a plurality of difference signals, each difference signal representing a voltage difference between a pair of wires in a three-wire serial bus; identifying a first difference signal among the plurality of difference signals, the first difference signal having the largest voltage value among the plurality of difference signals in a first unit interval; determining a signaling state of the three-wire serial bus for the first unit interval based on the identification of the wire pair corresponding to the first difference signal and the polarity of the first difference signal in the first unit interval; and generating a first edge in a clock signal in response to a transition of the first difference signal during the first unit interval.

[0010] In various aspects of this disclosure, a non-transitory processor-readable storage medium maintains code for: generating a plurality of difference signals, each difference signal representing a voltage difference between a pair of wires in a three-wire serial bus; identifying a first difference signal among the plurality of difference signals, the first difference signal having the largest voltage value among the plurality of difference signals in a first unit interval; determining a signaling state of the three-wire serial bus for the first unit interval based on the identification of the wire pair corresponding to the first difference signal and the polarity of the first difference signal in the first unit interval; and generating a first edge in a clock signal in response to a transition of the first difference signal during the first unit interval. Attached Figure Description

[0011] Figure 1 An apparatus for employing a data link between IC devices is described, the data link operating selectively according to one of a plurality of available standards or protocols, which may include the C-PHY protocol.

[0012] Figure 2 The system architecture of a device employing a data link between IC devices is shown, which operates selectively according to one of a number of available standards.

[0013] Figure 3 A C-PHY three-phase transmitter is shown.

[0014] Figure 4 The signaling in the C-PHY three-phase coded interface is shown.

[0015] Figure 5 A C-PHY three-phase receiver is shown.

[0016] Figure 6 This is a state diagram illustrating the potential state transitions in the C-PHY three-phase coded interface.

[0017] Figure 7 This is an example of the effect of signal rise time on transition detection in a C-PHY decoder.

[0018] Figure 8 Transition detection in the C-PHY decoder is shown.

[0019] Figure 9 An example of signal transitions occurring between multiple pairs of consecutive symbols transmitted over a C-PHY interface is shown.

[0020] Figure 10 The transition region and eye region in the eye diagram of the C-PHY interface are shown.

[0021] Figure 11An example of a clock generation circuit based on certain aspects disclosed herein is shown.

[0022] Figure 12 It shows the relationship with Figure 11 The timing diagram associated with the clock generation circuit.

[0023] Figure 13 A receiver circuit including clock and data recovery circuitry provided according to certain aspects of this disclosure is shown.

[0024] Figure 14 It shows Figure 13 Some aspects of the operation of the receiver circuit shown.

[0025] Figure 15 A receiver circuit including clock and data recovery circuitry, comprising calibration circuitry, is shown according to certain aspects of this disclosure.

[0026] Figure 16 A calibration sequence for the equalization circuitry in a differential receiver according to certain aspects of this disclosure is shown.

[0027] Figure 17 This is a block diagram illustrating an example of a device employing processing circuitry that can be adapted to certain aspects disclosed herein.

[0028] Figure 18 This is a flowchart of a first calibration method based on certain aspects disclosed herein.

[0029] Figure 19 This is a diagram illustrating a first example of a hardware implementation of a device employing processing circuitry adapted according to certain aspects disclosed herein. Detailed Implementation

[0030] The detailed description that follows, taken in conjunction with the accompanying drawings, is intended as a description of various configurations and not as representing only the configurations in which the concepts described herein can be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some cases, well-known structures and components are shown in block diagram form to avoid obscuring these concepts.

[0031] As used herein, the terms “component,” “module,” “system,” etc., are intended to include computer-related entities such as, but not limited to, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable program, an execution thread, a program, and / or a computer. For illustration, both applications running on computing devices and computing devices can be components. One or more components may reside in a process and / or an execution thread, and components may reside on a single computer and / or be distributed across two or more computers. Furthermore, these components can be executed from various computer-readable media on which various data structures are stored. Components can communicate via local and / or remote processes, such as by means of signals having one or more data packets, such as data from a component that interacts with another component in a local system, a distributed system, and / or with other systems across a network (such as the Internet).

[0032] Furthermore, the term "or" is intended to mean inclusive "or," not exclusive "or." That is, unless otherwise stated or clear from the context, the phrase "X adopts A or B" is intended to mean any natural inclusive arrangement. Specifically, the phrase "X adopts A or B" is satisfied by any instance of: X adopts A; X adopts B; X adopts both A and B. Additionally, the articles "a" and "an" used in this application and the appended claims should generally be interpreted as meaning "one or more," unless otherwise stated or clear from the context for the singular form.

[0033] Overview

[0034] Certain aspects of this invention can be applied to the C-PHY interface defined by the MIPI Alliance, which can be deployed to connect electronic devices as sub-components of mobile devices such as telephones, mobile computing devices, electrical appliances, automotive electronics, avionics systems, etc. Examples of mobile devices include mobile computing devices, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, laptops, notebooks, netbooks, smartbooks, personal digital assistants (PDAs), satellite radios, Global Positioning System (GPS) devices, smart home devices, smart lighting, multimedia devices, video devices, digital audio players (e.g., MP3 players), cameras, game consoles, entertainment devices, vehicle components, avionics systems, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), electrical appliances, sensors, security devices, vending machines, smart meters, drones, multirotors, or any other similarly functional devices.

[0035] The C-PHY interface is a high-speed serial interface capable of providing high throughput on bandwidth-constrained channels. C-PHY interfaces can be deployed to connect application processors to peripheral devices, including displays and cameras. The C-PHY interface encodes data into symbols transmitted via a set of three wires, which can be referred to as a trio or a group of three wires. For each symbol transmission interval, the three-phase signals are transmitted in different phases on the wires of the trio, where the phase of the three-phase signal on each wire is defined by the symbol transmitted in the symbol transmission interval. Each trio provides a channel on the communication link. The symbol transmission interval can be defined as the time interval in which a single symbol controls the signaling state of the trio. In each symbol transmission interval, one wire in the trio is not driven, while the remaining two wires are differentially driven, such that one of the two differentially driven wires presents a first voltage level, and the other differentially driven wire presents a second voltage level different from the first voltage level. Undriven wires can be floated, driven, and / or terminated such that they present a third voltage level, which is at or near an intermediate voltage level between the first and second voltage levels. In one example, the driving voltage levels can be +V and –V, while the undriven voltage is 0V. In another example, the driving voltage levels can be +V and 0V, while the undriven voltage is +½V. Different symbols are transmitted in each consecutive symbol pair, and different wire pairs can be driven differentially at different symbol intervals.

[0036] Certain aspects disclosed herein provide methods and apparatus for recovering clock and data from a serial bus operating according to a C-PHY protocol. A difference signal representing the voltage difference between a pair of wires in a three-wire serial bus is generated and provided to a level detector circuit. A first difference signal having the highest magnitude represents the strongest voltage difference between the two wires of the three-wire serial bus in a first unit interval. The signaling state of the three-wire serial bus in the first unit interval can be determined based on the identification of the wire pair corresponding to the first difference signal in the first unit interval and the polarity of the first difference signal. A first edge in the received clock signal can be generated in response to a transition of the first difference signal during the first unit interval.

[0037] Example of a device using a C-PHY interface

[0038] Figure 1Examples of apparatus 100 adapted to certain aspects disclosed herein are depicted. Apparatus 100 may employ a C-PHY three-phase protocol to implement one or more communication links. Apparatus 100 may include processing circuitry 102 having multiple circuits or devices, which may be implemented in one or more ASICs or SoCs. In one example, apparatus 100 may be a communication device, and processing circuitry 102 may include a processor 112 provided in ASIC 104, one or more peripheral devices 106, and a transceiver 108 that enables the device to communicate with a radio access network, a core access network, the Internet, and / or another network via antenna 124.

[0039] ASIC 104 may have one or more processors 112, one or more modems 110, onboard memory 114, bus interface circuitry 116, and / or other logic circuitry or functions. Processing circuitry 102 may be controlled by an operating system providing an application programming interface (API) layer, which enables one or more processors 112 to execute software modules residing in onboard memory 114 or processor-readable storage device 122 provided on processing circuitry 102. Software modules may include instructions and data stored in onboard memory 114 or other processor-readable storage device 122. ASIC 104 may access its onboard memory 114, processor-readable storage device 122, and / or storage devices external to processing circuitry 102. Onboard memory 114 and processor-readable storage device 122 may include read-only memory (ROM) or random access memory (RAM), electrically erasable programmable ROM (EEPROM), flash memory cards, or any memory device that can be used in processing systems and computing platforms. Processing circuitry 102 may include, implement, or access a local database or other parameter storage device that can maintain operating parameters and other information for configuring and operating device 100 and / or processing circuitry 102. The local database may be implemented using registers, a database module, flash memory, magnetic media, EEPROM, floppy disk, or hard disk, etc. Processing circuitry 102 may also be operatively coupled to external devices such as antenna 124, display 126, operator controls (such as switches or buttons 128, 130 and / or an integrated or external keyboard 132), and other components. The user interface module may be configured to operate with display 126, external keyboard 132, etc., via a dedicated communication link or via one or more serial data interconnects.

[0040] Processing circuitry 102 may provide one or more buses 118a, 118b, 120 that enable communication between certain devices. In one example, ASIC 104 may include bus interface circuitry 116, which includes a combination of circuitry, counters, timers, control logic, and other configurable circuitry or modules. In one example, bus interface circuitry 116 may be configured to operate according to a communication specification or protocol. Processing circuitry 102 may include or control power management functions that configure and manage the operation of device 100.

[0041] Figure 2 This illustration shows certain aspects of an apparatus 200 comprising multiple IC devices that can exchange data and control information via a communication link 220. The communication link 220 can be used to connect pairs of IC devices that are adjacent to each other or physically located in different parts of the apparatus 200. In one example, the communication link 220 may be provided on a chip carrier, substrate, or circuit board carrying the IC devices. In another example, a first IC device 202 may be located in the keypad portion of a flip phone, while a second IC device 230 may be located in the display portion of the flip phone. In yet another example, a portion of the communication link 220 may include a cable or optical connection.

[0042] Communication link 220 may include multiple channels. One or more channels may be bidirectional and may operate in half-duplex and / or full-duplex modes. One or more channels may be unidirectional. Communication link 220 may be asymmetric, providing higher bandwidth in one direction. In one example described herein, the first channel may be referred to as forward channel 222, and the second channel may be referred to as reverse channel 224. The first IC device 202 may be designated as a host system or transmitter, and the second IC device 230 may be designated as a client system or receiver, even if both IC devices are configured to transmit and receive on forward channel 222. In one example, when data is transmitted from the first IC device 202 to the second IC device 230, forward channel 222 may operate at a higher data rate, while reverse channel 224 may operate at a lower data rate when data is transmitted from the second IC device 230 to the first IC device 202.

[0043] Each IC device may include processors 206 and 236, controllers, or other processing and / or computing circuitry or devices. In one example, a first IC device 202 may perform core functions of device 200, including establishing and maintaining wireless communication via wireless transceiver 204 and antenna 214, while a second IC device 230 may support a user interface for managing or operating display controller 232 and may use camera controller 234 to control the operation of a camera or video input device. Other features supported by one or more of the IC devices may include keyboards, voice recognition components, and other input or output devices. Display controller 232 may include circuitry and software drivers supporting displays such as liquid crystal display (LCD) panels, touchscreen displays, indicators, etc. Storage media 208 and 238 may include temporary and / or non-temporary storage devices adapted to maintain instructions and data used by the respective processors 206 and 236 and / or other components of the IC devices. Communication between each processor 206, 236 and its corresponding storage media 208 and 238, as well as other modules and circuits, can be facilitated by one or more internal buses 212 and 242 and / or channels of communication link 220.

[0044] Reverse channel 224 can operate in the same manner as forward channel 222, and forward channel 222 and reverse channel 224 can transmit at comparable or different speeds, where speed can be expressed as data transfer rate, symbol transfer rate, and / or clock rate. Depending on the application, the forward data rate and reverse data rate can be substantially the same or can differ by several orders of magnitude. In some applications, a single bidirectional channel 226 can support communication between the first IC device 202 and the second IC device 230. For example, when forward channel 222 and reverse channel 224 share the same physical connection and operate in half-duplex mode, forward channel 222 and / or reverse channel 224 can be configured to operate in bidirectional mode. In one example, communication link 220 can be operated to transmit control, commands, and other information between the first IC device 202 and the second IC device 230 according to industry standards or other standards.

[0045] Figure 2The communication link 220 can be implemented according to the MIPI Alliance specification for C-PHY and can provide a wired bus including multiple signal wires (represented as M wires). The M wires can be configured to carry N-phase encoded data in a high-speed digital interface such as Mobile Display Digital Interface (MDDI). The M wires can facilitate N-phase polarity encoding on one or more channels in the channel. Physical layer drivers 210 and 240 can be configured or adapted to generate N-phase polarity encoded data for transmission on the communication link 220. The use of N-phase polarity encoding provides high-speed data transfer and can consume half or less power than other interfaces because fewer drivers are active in the N-phase polarity encoded data link.

[0046] When configured for N-phase polarity encoding, physical layer drivers 210 and 240 can typically encode multiple bits for each transition on communication link 220. In one example, a combination of tri-phase encoding and polarity encoding can be used to support a Wide Video Graphics Array (WVGA) LCD driver IC at 80 frames per second without a frame buffer, thereby delivering pixel data for display refresh at 810 Mbps.

[0047] Figure 3 This shows what can be used to implement Figure 2 Figure 300 shows certain aspects of the communication link 220 for a three-wire three-phase polar encoder. The example of three-wire three-phase encoding is chosen merely to simplify the description of certain aspects of this disclosure. The principles and techniques disclosed for the three-wire three-phase encoder can be applied to other configurations of M-wire N-phase polar encoders.

[0048] In a three-wire, three-phase polarity coding scheme, the signaling state defined for each of the three wires can include an undriven state, a positive driven state, and a negative driven state. The positive and negative driven states can be obtained by providing a voltage differential between two of the signal wires 318a, 318b, and / or 318c, and / or by driving current through two of the series-connected signal wires 318a, 318b, and / or 318c so that the current flows in different directions in the two signal wires 318a, 318b, and / or 318c. The undriven state can be achieved by setting the output of the driver for signal wires 318a, 318b, or 318c to a high-impedance mode. Alternatively or additionally, an undriven state can be obtained on signal conductors 318a, 318b, or 318c by passively or actively bringing the "undriven" signal conductors 318a, 318b, or 318c to an intermediate voltage level substantially between the positive and negative voltage levels provided on the driven signal conductors 318a, 318b, and / or 318c. Typically, no significant current flows through the undriven signal conductors 318a, 318b, or 318c. The signaling states defined for a three-wire, three-phase polarity coding scheme can be represented using three voltage or current states (+1, -1, and 0).

[0049] A three-wire, three-phase polar encoder can employ a line driver 308 to control the signaling states of signal lines 318a, 318b, and 318c. The line driver 308 can be implemented as a unit-level current-mode or voltage-mode driver. In some embodiments, each line driver 308 can receive a set of signals 316a, 316b, and 316c that determine the output state of the corresponding signal lines 318a, 316b, and 318c. In one example, each set of signals 316a, 316b, and 316c may include two or more signals, including a pull-up signal (PU signal) and a pull-down signal (PD signal), which, when both the PU and PD signals are high, activate the pull-up and pull-down circuits, driving the signal lines 318a, 318b, and 318c toward a higher or lower voltage level, respectively. In this example, when both the PU and PD signals are low, the signal lines 318a, 318b, and 318c can be terminated to an intermediate voltage level.

[0050] For each transmission symbol interval in the M-line N-phase polarity coding scheme, at least one signal conductor 318a, 318b, or 318c is in an intermediate level / undriven (0) voltage or current state, while the number of positively driven (+1 voltage or current state) signal conductors 318a, 318b, or 318c is equal to the number of negatively driven (-1 voltage or current state) signal conductors 318a, 318b, or 318c, such that the sum of the currents flowing to the receiver is always zero. For each symbol, the signaling state of at least one signal conductor 318a, 318b, or 318c changes from the conductor state transmitted in the preceding transmission interval.

[0051] In operation, mapper 302 can receive 16-bit data 310 and map it to seven symbols 312. In the three-wire example, each of the seven symbols defines the state of signal wires 318a, 318b, and 318c for one symbol interval. The seven symbols 312 can be serialized using a parallel-to-serial converter 304 that provides a timing symbol sequence 314 for each signal wire 318a, 318b, and 318c. The symbol sequence 314 is typically timed using a transmission clock. Three-wire three-phase encoder 306 receives the sequence 314 of the seven symbols generated by the mapper one symbol at a time and calculates the state of each signal wire 318a, 318b, and 318c for each symbol interval. Three-wire three-phase encoder 306 selects the state of signal wires 318a, 318b, and 318c based on the current input symbol 314 and the previous states of signal wires 318a, 318b, and 318c.

[0052] The use of M-line N-phase coding allows multiple bits to be encoded in multiple symbols, where the number of bits in each symbol is not an integer. In the example of a three-wire communication link, there are 3 available combinations of 2 wires that can be driven simultaneously, and 2 possible combinations of polarities on the driven wire pairs, resulting in 6 possible states. Since each transition occurs from the current state, 5 of the 6 states are available at each transition. At each transition, the state of at least one wire needs to be changed. For the 5 states, each symbol can be encoded as log2(5). 2.32 bits. Accordingly, the mapper can accept a 16-bit word and convert it into 7 symbols, since each symbol carries 2.32 bits. 7 symbols can encode 16.24 bits. In other words, a combination of 7 symbols encoding 5 states has 5... 7 (78125) permutations. Correspondingly, 7 symbols can be used to encode 16-bit 2... 16 (65536) permutations.

[0053] Figure 4An example of a timing diagram 400 for a signal encoded using a three-phase modulation data encoding scheme based on a cyclic state diagram 450 is provided. Information can be encoded in a sequence of signaling states, where, for example, a wire or connector is in one of three phase states S1, S2, and S3 defined by the cyclic state diagram 450. Each state can be phase-shifted 120° away from the other states. In one example, data can be encoded in the direction of rotation of the phase states on the wire or connector. The phase states in the signal can rotate in clockwise directions 452 and 452' or counterclockwise directions 454 and 454'. For example, in clockwise directions 452 and 452', the phase states can advance in a sequence including one or more transitions from S1 to S2, from S2 to S3, and from S3 to S1. In counterclockwise directions 454 and 454', the phase states can advance in a sequence including one or more transitions from S1 to S3, from S3 to S2, and from S2 to S1. Three signal wires 318a, 318b, and 318c carry different versions of the same signal, wherein these versions may be phase-shifted relative to each other by 120°. Each signaling state can be represented as a different voltage level on the wire or connector and / or the direction of current flowing through the wire or connector. During each signaling state in the signaling state sequence in a three-wire system, each signal wire 318a, 318b, and 318c is in a different signaling state than the other wires. When more than three signal wires 318a, 318b, and 318c are used in a three-phase coded system, two or more signal wires 318a, 318b, and / or 318c may be in the same signaling state at each signaling interval, although each state exists on at least one signal wire 318a, 318b, and / or 318c in each signaling interval.

[0054] At each phase transition 410, information can be encoded in the direction of rotation, and the three-phase signals can change direction for each signaling state. The direction of rotation can be determined by considering which signal wires 318a, 318b, and / or 318c are in the "0" state before and after the phase transition, since the undriven signal wires 318a, 318b, and / or 318c change direction at each signaling state in the rotating three-phase signals, regardless of the direction of rotation.

[0055] The encoding scheme can also encode information in the polarity 408 of the two actively driven signal wires 318a, 318b, and / or 318c. At any given time in a three-wire implementation, exactly two of the signal wires 318a, 318b, and 318c are driven by currents in opposite directions and / or by voltage differential. In one implementation, two bit values ​​412 can be used to encode data, one bit encoded in the phase transition direction 410 and the second bit encoded in the polarity 408 of the current state.

[0056] Timing diagram 400 illustrates data encoding using phase rotation direction and polarity. For multiple phase states, curves 402, 404, and 406 are associated with signals carried on three signal conductors 318a, 318b, and 318c, respectively. Initially, phase transition 410 is in a clockwise direction, and the most significant bit is set to binary "1" until the rotation of phase transition 410 switches to a counterclockwise direction at time 414, as indicated by the most significant bit being set to binary "0". The least significant bit reflects the polarity 408 of the signal in each state.

[0057] According to certain aspects disclosed herein, a single bit of data can be encoded in a rotation or phase transition in a three-wire three-phase coding system, and additional bits can be encoded in the polarity of the two driving wires. By allowing transitions from the current state to any possible state, additional information can be encoded in each transition of the three-wire three-phase coding system. Given three rotational phases and two polarities for each phase, six states are available in the three-wire three-phase coding system. Accordingly, five states are available from any current state, and each symbol (transition) can have log2(5). 2.32 bits are encoded, which allows mapper 302 to accept 16-bit words and encode them in 7 symbols.

[0058] Figure 5 This is a schematic diagram illustrating certain aspects of a three-wire, three-phase decoder 500. Differential receivers 502a, 502b, 502c and wire state decoder 504 are configured to provide difference signals 522a, 522b, 522c as outputs, respectively. Each of the difference signals 522a, 522b, 522c represents a difference in the state of two of the three signal wires 318a, 318b, and 318c. The difference signals 522a, 522b, 522c are used to detect changes in the state of the three signal wires 318a, 318b, and 318c compared to the state transmitted in the immediately preceding symbol period. Seven consecutive symbols representing the transition are combined by a serial-to-parallel converter 506 to obtain a set of seven symbols 516 for processing by a demapper 508. The demapper 508 generates 16 bits of data 518, which can be buffered in a first-in-first-out (FIFO) register 510 to provide output data 520.

[0059] The wire state decoder 504 can extract a sequence of symbols 514 from the phase-encoded signals received on signal wires 318a, 318b, and 318c. As disclosed herein, symbols 514 are encoded as a combination of phase rotation and polarity. The wire state decoder may include a CDR circuit 524 for extracting a clock 526, which can be used to reliably capture wire states from signal wires 318a, 318b, and 318c. At each symbol boundary, a transition occurs on at least one of the signal wires 318a, 318b, and 318c, and the CDR circuit 524 may be configured to generate clock 526 based on the occurrence of one or more transitions. The edges of the clock may be delayed to allow the time of all signal wires 318a, 318b, and 318c to have stabilized, thereby ensuring that the current wire state is captured for decoding purposes.

[0060] Figure 6 State diagram 600 illustrates possible signaling states 602, 604, 606, 612, 614, and 616 for three wires, with possible transitions shown from each state. In the example of a three-wire, three-phase communication link, six states and 30 state transitions are available. The possible signaling states 602, 604, 606, 612, 614, and 616 in state diagram 600 include and extend to... Figure 4 The states are shown in the cyclic state diagram 450. As exemplified by state element 628, each signaling state 602, 604, 606, 612, 614, and 616 in state diagram 600 defines the voltage signaling state of signal lines 318a, 318b, and 318c, and the difference signals 522a, 522b, and 522c representing the result of subtracting the corresponding line voltage from the corresponding differential receivers 502a, 502b, and 502c. Signal lines 318a, 318b, and 318c are labeled A, B, and C, respectively. For example, in signaling state 602 (+x), line A = +1, line B = -1, and line C = 0, resulting in the outputs of differential receivers 502a (AB) = +2, differential receiver 502b (BC) = -1, and differential receiver 502c (CA) = -1. The phase transition detection circuit in the receiver makes transition decisions based on five possible levels generated by the differential receivers 502a, 502b, and 502c, including voltage states of -2, -1, 0, +1, and +2.

[0061] Transitions in state diagram 600 can be represented by a flip, rotation, and polarity sign (e.g., FRP symbol 626) of one of the three-bit binary values ​​in the set {000, 001, 010, 011, 100}. The rotation bit 622 of FRP symbol 626 indicates the direction of phase rotation associated with the transition to the next state. When the transition to the next state involves a polarity change, the polarity bit 624 of FRP symbol 626 is set to binary 1. When the flip bit 620 of FRP symbol 626 is set to binary 1, the rotation and polarity values ​​can be ignored and / or set to zero. A flip indicates a state transition involving only a polarity change. Accordingly, when a flip occurs, the phases of the three-phase signals are not considered to be rotating, and the polarity bit is redundant when a flip occurs. FRP symbol 626 corresponds to the wire state change for each transition. The state diagram 600 can be divided into an inner circle 608 containing positive polarity signaling states 602, 604, and 606 and an outer circle 618 containing negative polarity signaling states 612, 614, and 616.

[0062] Jitter in three-phase interface

[0063] A three-phase transmitter includes drivers that supply high, low, and medium voltage levels to the transmission path. This results in several variable transitions between consecutive symbol intervals. Low-to-high and high-to-low voltage transitions can be referred to as full-swing transitions, while low-to-medium and high-to-medium voltage transitions can be referred to as half-swing transitions. Different types of transitions can have different rise or fall times and may result in different zero-crossing events at the receiver. These differences can lead to “coded jitter,” which can affect link signal integrity performance.

[0064] Figure 7 Timing diagram 700 illustrates certain aspects of the transition variability at the output of a C-PHY three-phase transmitter. The variability in signal transition times can be attributed to the presence of different voltage and / or current levels used in the three-phase transmission. Timing diagram 700 shows the transition times in signals received from single signal conductors 318a, 318b, or 318c. First symbol Sym n 702 is transmitted during the first symbol interval, when the second symbol Sym... n+1 704 is transmitted during the second symbol interval, while the first symbol interval ends at time 722. When the third symbol Sym... n+2 When 706 is transmitted in the third symbol interval, the second symbol interval can end at time 724, when the fourth symbol Sym... n+3During transmission in the fourth symbol interval 708, the third symbol interval ends at time 726. After a delay 712 caused by a time taken for the voltage in signal wires 318a, 318b, or 318c to reach threshold voltages 718 and / or 720, the transition from the state determined by the first symbol 702 to the state corresponding to the second symbol 704 is detectable. The threshold voltage can be used to determine the state of signal wires 318a, 318b, or 318c. After a delay 714 caused by a time taken for the voltage in signal wires 318a, 318b, or 318c to reach one of the threshold voltages 718 and / or 720, the transition from the state determined by the second symbol 704 to the state of the third symbol 706 is detectable. After a delay 716, caused by the time it takes for the voltage in signal wires 318a, 318b, or 318c to reach threshold voltages 718 and / or 720, the transition from the state defined by the third symbol 706 to the state of the fourth symbol 708 is detectable. Delays 712, 714, and 716 can have different durations, which can be partly attributed to variations in device manufacturing processes and operating conditions, potentially having unequal effects on the transitions between different voltage or current levels associated with the three states and / or different transition values. These differences can lead to jitter and other problems in the C-PHY three-phase receiver.

[0065] Figure 8 Some aspects of the CDR circuitry that can be provided in a receiver within a C-PHY interface 800 are illustrated. Differential receivers 802a, 802b, and 802c are configured to generate a set of difference signals 810a, 810b, and 810c by comparing the signaling states of each distinct pair of signal wires 318a, 318b, and 318c in the three-wire group. In the example shown, the first differential receiver 802a provides an AB difference signal 810a representing the difference in signaling states between signal wire A 318a and signal wire B 318b, the second differential receiver 802b provides a BC difference signal 810b representing the difference in signaling states between signal wire B 318b and signal wire C 318c, and the third differential receiver 802c provides a CA difference signal 810c representing the difference in signaling states between signal wire C 318c and signal wire A 318a. Accordingly, the transition detection circuit 804 can be configured to detect the occurrence of a phase change because the output of at least one of the differential receivers 802a, 802b and 802c changes at the end of each symbol interval.

[0066] Transitions between some consecutively transmitted symbol pairs can be detected by a single differential receiver 802a, 802b, or 802c, while other transitions can be detected by two or more differential receivers 802a, 802b, and 802c. In one example, the state or relative state of two wires may remain unchanged after a transition, and the outputs of the corresponding differential receivers 802a, 802b, or 802c may also remain unchanged after a phase transition. Accordingly, the clock generation circuit 806 may include a transition detection circuit 804 and / or other logic to monitor the outputs of all differential receivers 802a, 802b, and 802c to determine when a phase transition has occurred. The clock generation circuit may generate a receive clock signal 808 based on the detected phase transition.

[0067] The signaling states of the three wires in the three-wire group can be detected at different times, which can cause the difference signals 810a, 810b, and 810c to reach a stable state at different times. After the signaling state of each signal wire 318a, 318b, and / or 318c has transitioned to its state defined for one symbol transmission interval, the states of the difference signals 810a, 810b, and 810c can switch before reaching stability. This variability results in… Figure 8 The timing diagram is shown in 820.

[0068] The timing of signaling state change detection can vary depending on the type of signaling state change that has occurred. Labels 822, 824, and 826 indicate the occurrence of transitions in the difference signals 810a, 810b, and 810c provided to the transition detection circuit 804. For clarity only, labels 822, 824, and 826 are assigned different heights in timing diagram 820, and the relative heights of labels 822, 824, and 826 are not intended to show a specific relationship with the voltage or current levels, polarities, or weighting values ​​used for clock generation or data decoding. Timing diagram 820 illustrates the timing effects of transitions associated with symbols transmitted in phase and polarity on the three signal lines 318a, 318b, and 318c. In timing diagram 820, transitions between some symbols may result in variable capture windows 830a, 830b, 830c, 830d, 830e, 830f and / or 830g (collectively referred to as symbol capture window 830), during which symbols can be reliably captured. The number of detected state changes and their relative timing may cause jitter on clock signal 808.

[0069] The throughput of a C-PHY communication link can be affected by the duration and variability of signal transition times. CDR can use shielding to prevent transitions between symbols reflected in two or more of the difference signals 810a, 810b, 810c from affecting the recovery of the receive clock. In one example, shielding can be implemented by blocking multiple transitions in the difference signals 810a, 810b, 810c after a first transition is detected. In another example, shielding can be implemented by generating a pulse with a duration exceeding the duration of the signal transition region between symbols based on the first transition. The effective duration of shielding can limit the channel bandwidth of the C-PHY interface. The effective duration of shielding is typically calculated to accommodate variability in the operation of the transition detection circuitry. The variability of the transition detection circuitry can be caused by manufacturing process tolerances, variations and stability of voltage and current sources, and operating temperature, and may also be caused by the electrical characteristics of the signal conductors 318a, 318b, and 318c. The variability of the detection circuitry can further limit the channel bandwidth.

[0070] Figure 9 Timing diagrams 900 and 920 include examples of transitions from a first signaling state to a second signaling state between certain consecutive symbols. For illustrative purposes, the signaling state transitions shown in timing diagrams 900 and 920 are chosen, and other transitions and combinations thereof may occur in the MIPI Alliance C-PHY interface. Timing diagrams 900 and 920 relate to an example of a three-wire, three-phase communication link, where multiple receiver output transitions may occur at each symbol interval boundary due to differences in rise and fall times between signal levels on the three wires in a group. See also... Figure 8 A first timing diagram 900 illustrates the signaling states (A, B, and C) of a group of three signal lines 318a, 318b, and 318c before and after the transition, and a second timing diagram 920 illustrates the outputs of differential receivers 802a, 802b, and 802c, which provide difference signals 810a, 810b, and 810c representing the differences between signal lines 318a, 318b, and 318c. In many cases, the set of differential receivers 802a, 802b, and 802c can be configured to capture transitions by comparing different combinations of two signal lines 318a, 318b, and 318c. In one example, these differential receivers 802a, 802b, and 802c can be configured to produce outputs by determining the difference between their respective input voltages (e.g., by subtraction).

[0071] In each example shown in timing diagrams 900 and 920, -z signaling state 616 is represented (see...). Figure 8The initial sign of the signal is changed to a different sign. As shown in timing diagrams 902, 904, and 906, signal A is initially in the +1 state, signal B is in the 0 state, and signal C is in the -1 state. Accordingly, differential receivers 802a and 802b initially measure a level of +100 mV 924, and differential receiver 802c measures a level of -200 mV 926, as shown in timing diagrams 922, 932, and 938 of the differential receiver output.

[0072] In the first example corresponding to timing diagrams 902 and 922, a transition occurs from the symbol representing the -z signaling state 616 to the symbol representing the –x signaling state 612 (see...). Figure 6 In this process, signal A transitions to a -1 state, signal B transitions to a +1 state, and signal C transitions to a 0 state. Differential receiver 802a transitions from a +100mV level 924 to a -200mV level 930, differential receiver 802b remains at a +100mV level 924 and 928, and differential receiver 802c transitions from a -200mV level 926 to a +100mV level 928.

[0073] In the second example corresponding to timing diagrams 904 and 932, a transition occurs from the symbol representing the -z signaling state 616 to the symbol representing the +z signaling state 606, where signal A transitions to the -1 state, signal B remains in the 0 state, and signal C transitions to the +1 state. This occurs when two differential receivers 802a and 802b transition from a +100mV level 924 to a -100mV level 936, and differential receiver 802c transitions from a -200mV level 926 to a +200mV level 934.

[0074] In the third example corresponding to timing diagrams 906 and 938, a transition occurs from the symbol representing the -z signaling state 616 to the symbol representing the +x signaling state 602, where signal A remains in the +1 state, signal B transitions to the -1 state, and signal C transitions to the 0 state. Differential receiver 802a transitions from a +100mV level 924 to a +200mV level 940, differential receiver 802b transitions from a +100mV level 924 to a -100mV level 942, and differential receiver 802c transitions from a -200mV level 926 to a -100mV level 942.

[0075] These examples illustrate the transitions in measuring differences, where the transitions can span levels 0, 1, 2, 3, 4, and 5. The pre-emphasis techniques used in typical differential or single-ended serial transmitters are developed for two-level transitions and can cause some adverse effects if applied to MIPI Alliance C-PHY three-phase signals. Specifically, pre-emphasis circuitry that overdrives the signal during transitions can cause overshoot during transitions spanning 1 or 2 levels and may lead to false triggering in edge-sensitive circuits.

[0076] M-line N-phase encoding systems (such as three-line three-phase encoders) can encode signals that have at least one transition at each symbol boundary, and the receiver can use those guaranteed transitions to recover the clock. In some implementations, the receiver requires that the data signal be stable immediately before the first signal transition at the symbol boundary and must also be able to reliably shield any multiple transitions occurring in multiple transitions associated with the same symbol boundary. Due to the small differences in rise and fall times between the signals carried on the M wires (e.g., three wires in a group), and due to the combination of received signal pairs (e.g., Figure 6 The minute differences in signal propagation time between the differential receivers 802a, 802b, and 802c (AB output, BC output, and CA output) can cause multiple receiver transitions.

[0077] Figure 10 An example of a multi-level eye diagram 1000 generated for the output of a set of three differential receivers is shown, where each differential receiver compares two of the three signals received via a C-PHY interface. This can be achieved by superimposing the outputs from the C-PHY receiver circuitry (see...). Figure 8 The signals output from the differential receivers 802a, 802b, and 802c in the C-PHY bus are used to generate a multi-level eye diagram 1000. The multi-level eye diagram 1000 spans a symbol interval, which may be referred to as a unit interval (UI 1002). UI 1002 may correspond to a period of the transmission clock used to control the transmission of each symbol, or to a period of the receive clock recovered from signaling received from the C-PHY bus.

[0078] In one example, a fixed, sign-independent trigger 1010 can be used to generate a multi-level eye diagram 1000. In the multi-level eye diagram 1000, five nominal voltage levels 1020, 1022, 1024, 1026, and 1028 define the potential states of the outputs of differential receivers 802a, 802b, and 802c. The multi-level eye diagram 1000 illustrates the possible transitions at the outputs of differential receivers 802a, 802b, and 802c used for a three-wire, three-phase encoded signal. The three voltage levels defined for the three-wire, three-phase encoded signal allow differential receivers 802a, 802b, and 802c to generate outputs varying between strong voltage levels (nominal voltage levels 1026 and 1028) and weak voltage levels (nominal voltage levels 1022 and 1024) for both positive and negative polarities. Typically, in any symbol only one signal line 318a, 318b, and 318c is not driven, and differential receivers 802a, 802b, and 802c do not produce a 0-state output corresponding to the 0-volt voltage level 1020.

[0079] The nominal voltage levels 1022, 1024, 1026, and 1028 corresponding to the weak and strong voltage levels do not need to be uniformly spaced relative to the 0-volt voltage level 1020. For example, the weak voltage levels 1022 and 1024 represent a comparison of voltages that may include the midpoint voltage defined for signal lines 318a, 318b, and 318c or the voltage levels reached by undriven signal lines 318a, 318b, and 318c. The multi-level eye diagram 1000 can use reference time points (e.g., based on the triggering of the transmission clock) to overlay the waveforms generated by the differential receivers 802a, 802b, and 802c. In the receiver, three pairs of difference signals are generated simultaneously to achieve data capture at the receiving device. Figure 10 The waveforms shown represent the difference signals 810a, 810b, and 810c (AB, BC, and CA) generated by the differential receivers 802a and 802b.

[0080] The drivers, receivers, and other devices used in a C-PHY three-phase decoder can exhibit different switching characteristics, which can manifest as relative delays between signals received from the three wires. Multiple receiver output transitions can be observed at each symbol interval boundary 1008 and / or 1014 due to differences in rise and fall times between the three signals in a group of three signal wires 318a, 318b, and 318c, and due to differences in signal propagation times between combinations of signal pairs received from signal wires 318a, 318b, and 318c. A multi-level eye diagram 1000 can capture these variations in rise and fall times as relative delays in transitions near each symbol interval boundary 1008 and 1014. In some examples, these variations in rise and fall times can be due to different characteristics of the three-phase drivers. For any given symbol, differences in rise and fall times can also result in a significant shortening or lengthening of the duration of the symbol interval observed or effective at the receiver.

[0081] Signal transition regions 1004 and 1016 represent uncertain times or periods in which variable signal rise times hinder reliable decoding. The signal transition regions 1004 and 1016 shown may begin at symbol interval boundaries 1008 and 1014 and terminate at endpoints 1012 and 1018 corresponding to the final crossing of the 0-volt voltage level 1020 by the difference signals 810a, 810b, and 810c. The signaling state can be reliably determined in "eye-opening" or window 1006, which represents the time period in which symbols are stable and can be reliably received and decoded. In one example, window 1006 can be considered to begin at the endpoint 1012 of the signal transition region 1004, and window 1006 can be considered to close at the next symbol interval boundary 1014 of the symbol interval, and / or close when the signaling state of the signal lines 318a, 318b, 318c and / or the outputs of the three differential receivers 802a, 802b, and 802c have begun to change to reflect the next symbol.

[0082] Compared to window 1006, the maximum transmission speed of the C-PHY interface may be limited by the duration of signal transition regions 1004 and 1016. The receiver can use shielding circuitry that blocks transition detection after the first detected transition during signal transition regions 1004 and 1016. After the first detected transition, the shielding circuitry can ignore subsequent transitions for a duration corresponding to the longest expected or measured signal transition regions 1004 and 1016. The duration of window 1006 is affected by the duration of the shielding.

[0083] Clock generation for high-speed C-PHY three-phase interface

[0084] In some C-PHY CDRs, inverter-based pulse generators can be used to generate short pulses at each rising edge of the CDR input. In one aspect, pulse-based clock generation can mitigate the effects of variations in manufacturing processes, circuit supply voltage, and die temperature (PVT) by separating the pulse generator from the delay loop, which is based on changes in the C-PHY input. In some examples, programmable generators can be used to generate half-UI signals, which are used to sample data, thus eliminating timing constraints inherent in traditional CDR designs.

[0085] Figure 11 An example of a CDR 1100 that separates half-rate clock generation from C-PHY input change pulse generation is shown. As shown, the C-PHY input changes include AB difference signal 1102, BC difference signal 1104, and CA difference signal 1106. Difference signals 1102, 1104, and 1106 are input to a network of logic gates 1108a, 1108b, and 1108c (XOR gates in this example), logic gates 1110a, 1110b, and 1110c, and OR gate 1112 to generate pulses in the first clock signal 1114 based on the transitions of difference signals 1102, 1104, and 1106.

[0086] A clock signal 1114 is input to flip-flop logic 1116, such as a D flip-flop, wherein the flip-flop logic 1116 is timed by pulses in the clock signal 1114, wherein the input value (data or D) is held on the output (Q) until a pulse or assertion value is input at the clock input (CLK). The flip-flop logic 1116 is then coupled in a delay loop, which includes a programmable generator 1118 coupled to the output Q of the flip-flop logic 1116. The programmable generator 1118 may be a half-UI generator configured to generate a half-UI-based recovery clock (i.e., a clock with a rate equal to two UI periods or half the clock rate of the incoming first clock signal or pulse). The generated half-rate or delayed RCLK signal 1120 produced by the programmable generator 1118 is fed back to the data input of the flip-flop logic as part of the delay loop, which includes an inverter 1119 that inverts the signal output by the programmable generator 1118. Since the flip-flop logic 1116 is timed by pulses in the clock signal 1114, and in one aspect utilizes a D flip-flop, resampling performed by the flip-flop logic 1116 will occur with each rising edge of the pulse. Note that the semi-UI generator can be pre-configured or configured according to a predetermined algorithm / metric. Furthermore, the programmable generator 1118 can be pre-calibrated before receiving high-speed data bursts in the receiver. The output Q of the flip-flop logic 1116 is then used to derive the parameters to be applied to the decoder at the receiver (e.g., after passing through inverters 1124 and 1126). Figure 6 The restored clock signal (RCLK) 1122 used in the decoder 600 shown. In one aspect of this disclosure, inverters 1124 and 1126 are provided to act as buffers to drive the loading of the RCLK signal, but the CDR 1100 shown is not limited to using such buffering devices and can operate with other buffering devices, or even operate without buffering in other implementations.

[0087] Once the first data transition is received at CDR 1100, an automatic half-UI tracking pulse is created, regardless of any other possible transitions that may occur in the input data within a UI. The first transition operates as a start indicator for programmable generator 1118 to generate a pulse for the pull-down voltage of flip-flop logic 1116 to generate a half-UI-based recovered clock. The Q output of flip-flop logic 1116 also constitutes the recovered clock signal RCLK 1122, which will be a half-UI or half-rate clock. The circuit structure shown is unaffected by PVT or inter-channel mismatches because the circuit arrangement only considers absolute UI timing relationships.

[0088] Figure 12 It shows Figure 11The timing diagram 1200 shown is an example of a CDR implementation. This timing diagram is merely exemplary and illustrates what might occur... Figure 11 This section describes various scenarios involving pulse and clock signals in the system, and how the CDR 1100 responds and operates in these scenarios, without intending to limit the description of its operation to this single example. As can be seen in Figure 1200, various pulse edges generated by the transitions of the three difference signals AB, BC, and CA are illustrated. For simplicity, the pulse edges of the difference signals are shown; however, those skilled in the art will understand that actual difference signals last for a period of time, during which a signal transition from high to low or from low to high occurs at the pulse edges shown.

[0089] Figure 12 The following are also shown: the signals occurring at the flip-flop logic inputs (i.e., clock signal 1114), the signals occurring at the data (D) inputs (i.e., the delayed RCLK signal 1120), and the signals occurring at the Q outputs (i.e., RCLK signal 1122). As shown, the flip-flop logic clock signal 1114, generated by the transitions of various difference signals AB, BC, and CA, and output from OR gate 1112, will trigger the flip-flop logic 1116 at a period of one UI. See the edge pulse 1202 of the CA difference signal as an example. Figure 12 This shows that the CA edge pulse 1202 will cause the trigger logic as shown by pulse 1204 to be triggered, which is consistent with... Figure 11 The clock signal 1114 in the circuit is related to this. The delayed RCLK signal 1120, which is provided by the programmable generator 1118 to the data input (D) of the flip-flop logic 1116, can be regarded as a half-rate or half-frequency clock signal. It is delayed by half UI from the clock signal 1114 from the input to the flip-flop logic 1116 by the operation of the programmable generator 1118. This is related to the state change on the flip-flop logic 1116 caused by the pulse 1204 and the state of the delayed RCLK signal 1120 being high due to the inversion of the inverter.

[0090] When the next trigger pulse 1206 occurs after a UI time period from the previous pulse 1204, the output Q will be pulled low or grounded because the delayed RCLK signal 1120 input to the flip-flop logic 1116 is low, and the associated recovered RCLK signal 1122 can be seen as at time 1208. In this way, the recovered clock signal RCLK has half the rate of the incoming signals on wires A, B, and C.

[0091] In the case where two transitions occurring between conductors A, B, and C are close in time, resulting in two edge pulses delivered at the output being close together, the first pulse can trigger the flip-flop output Q (i.e., RCLK signal 1122) to be pulled low, as can be seen in the example of pulses (first pulse 1210 and second pulse 1212). However, because the delayed RCLK signal 1120 is low, the second pulse 1212 will not affect the state of output Q, since the output has been pulled low and the delayed RCLK signal 1120 remains low.

[0092] Figure 11 The inverter-based pulse generator CDR 1100 generates a short pulse at each rising edge of the CDR input. As long as the pulse is short enough to prevent overlap between successive UIs, the short pulse can be used to generate timing for transitioning the differential voltage to the appropriate wire state. For all expected variations in PVT conditions, the duration of the minimum pulse width cannot be shorter than the maximum settling time for each wire state. The pulse-generating CDR is inevitably constrained by stringent requirements on the pulse width to be well tuned to the operating conditions. Pulse width tuning is particularly challenging at higher speeds across all possible PVT variations. Furthermore, the pulse-generating CDR can simply OR all pulses used for clock recovery purposes and requires additional half-rate clock recovery circuitry to allow time interleaving and relax channel bandwidth requirements for high-speed applications.

[0093] Certain aspects of this disclosure can utilize unique data patterns in the output of a differential receiver used in a C-PHY interface. In one aspect, the CDR can be configured to operate independently of explicit delay tuning in the pulse generation circuitry. In one example, rules derived from the C-PHY protocol related to the data pattern allow the complete wire state in the UI to be recovered solely based on a comparison of the magnitude and polarity of the voltage on each wire. The term magnitude is used herein to denote the value of a voltage or current regardless of polarity. For example, voltage levels -200 mV and +200 mV have the same magnitude but different polarities. (Continuing to the next section...) Figure 6 , Figure 8 and Figure 9In one example shown, the difference signals 810a, 810b, 810c generated by differential receivers 802a, 802b, 802c can have nominal values ​​of 100 mV or 200 mV and can have positive or negative polarity, thereby generating four possible nominal difference voltages {-200 mV, -100 mV, +100 mV, +200 mV} outside the transition period. Each of the -200 mV and +200 mV levels can be referred to as a strong voltage, a strong voltage level, a strong difference voltage, or a strong difference, and the -100 mV and +100 mV levels can be referred to as a weak voltage, a weak voltage level, a weak difference voltage, or a weak difference.

[0094] Certain aspects of this disclosure enable the determination of the complete signaling state of the three-wire group based on the comparison of the magnitude and polarity of the difference signals 810a, 810b, 810c provided by differential receivers 802a, 802b, and 802c. Rules derived from the C-PHY protocol state that the effective state of the three-wire C-PHY bus guarantees that a strong difference voltage can be observed in only one of the difference signals 810a, 810b, 810c generated by differential receivers 802a, 802b, and 802c in each UI. Detection of the strong difference voltage and its polarity, along with identification of the wire pair generating the strong difference voltage, is sufficient to generate a pulse in the received clock signal and determine the complete wire state of the three-wire group. The validity of the derived rules is determined by… Figure 6 confirm, Figure 6 It is shown that each valid or possible signaling state 602, 604, 606, 612, 614, 616 has only one difference signal under a strong voltage level. Using this rule, the complete signaling state of the three-wire group in any UI can be determined by identifying the difference signals 810a, 810b, 810c in the UI that are at a strong voltage level and the polarity of the strong voltage level.

[0095] Certain aspects of this disclosure provide a CDR that can recover a half-rate clock and reliably capture wire states in each UI based on the identification of differential receivers 802a, 802b, and 802c that generate strong voltage levels at their outputs and the polarity of the strong voltage levels. For example, when differential receiver 802a provides a strong voltage level in the first UI, the states of wires 318a, 318b, and 318c correspond to either +x signaling state 602 or -x signaling state 612. A positive strong voltage determines that +x signaling state 602 is present, and a negative strong voltage determines that -x signaling state 602 is present. It should be understood that different circuit designs may use opposite polarities to represent signaling states or differential outputs.

[0096] Figure 13Receiver circuitry 1300 is shown, which can perform clock and data recovery based on the identification of difference signals 1304a, 1304b, 1304c having strong voltage levels in the UI. The difference signals 1304a, 1304b, 1304c are generated by three differential receivers 1312a, 1312b, 1312c configured to compare the signal states on mutually different pairs of wires 1302a, 1302b, 1302c. The AB differential receiver 1312a compares the reception states of wire A 1302a and wire B 1302b, the BC differential receiver 1312b compares the reception states of wire B 1302b and wire C 1302c, and the CA differential receiver 1312c compares the reception states of wire C 1302c and wire A 1302a. In the example shown, each of the differential receivers 1312a, 1312b, and 1312c includes one or more equalization circuits. In one example, each of the differential receivers 1312a, 1312b, and 1312c includes a continuous-time linear equalizer (CTLE) and a variable-gain amplifier (VGA).

[0097] Each difference signal 1304a, 1304b, 1304c is provided to level detector circuits 1314a, 1314b, 1314c. Each level detector circuit 1314a, 1314b, 1314c is configured to determine whether the voltage on the corresponding difference signal 1304a, 1304b, 1304c exceeds the positive threshold voltage level 1320a, 1320b, 1320c or is less than the negative threshold voltage level 1322a, 1322b, 1322c. In one example, each level detector circuit 1314a, 1314b, 1314c outputs a two-bit level detection (LD) signal (e.g., LD signals 1306a, 1306b, 1306c), where one bit indicates the magnitude of the corresponding difference signal 1304a, 1304b, 1304c indicating a strong difference (e.g., a nominal 200mV relative to a nominal 100mV), and the other bit indicates the polarity of the corresponding difference signal 1304a, 1304b, 1304c. In another example, the LD signals 1306a, 1306b, 1306c output by each level detector circuit 1314a, 1314b, 1314c include a first bit indicating a strong positive difference output when set to high (or, in some examples, low), and a second bit indicating a strong negative difference output when set to high. In the latter example, only one bit of the LD signals 1306a, 1306b, and 1306c can be set high in any UI, and both bits can be set low in one or more UIs. In some examples, the positive threshold voltage levels 1320a, 1320b, and 1320c and the negative threshold voltage levels 1322a, 1322b, and 1322c are configured to have values ​​between 200mV and 100mV.

[0098] Figure 14 This diagram illustrates certain aspects of the operation of receiver circuitry 1300 across five UIs. A first timing diagram 1400 represents the signaling states received from wires 1302a, 1302b, and 1302c of the C-PHY three-wire group during the five UIs. A second timing diagram 14200 represents the difference signals 1304a, 1304b, and 1304c generated by differential receivers 1312a, 1312b, and 1312c based on the signaling states received from wires 1302a, 1302b, and 1302c during the five UIs. A third timing diagram 1440 represents the LD signals 1306a, 1306b, and 1306c output by level detector circuits 1314a, 1314b, and 1314c in response to the difference signals 1304a, 1304b, and 1304c.

[0099] In the second timing diagram 1420, only one strong differential voltage 1402, 1404, 1406, 1408, or 1410 is generated in each UI. The third timing diagram 1440 involves two LD signals 1306a, 1306b, and 1306c. Each LD signal 1306a, 1306b, and 1306c includes a first bit 1412a, 1412b, or 1412c, which is logic high when the corresponding differential signal 1304a, 1304b, or 1304c has a voltage value consistent with a strong differential voltage. Each LD signal 1306a, 1306b, and 1306c includes a second bit 1414a, 1414b, or 1414c indicating the polarity of the corresponding differential signal 1304a, 1304b, or 1304c. For example, strong differential voltages 1408 and 1410 are generated by the AB differential receiver 1312a in the last two UIs, wherein the first strong differential voltage 1408 of these strong differential voltages has a negative polarity and the second strong differential voltage 1410 of these strong differential voltages has a positive polarity, thereby indicating +x signaling state 602, followed by -x signaling state 612 (see...). Figure 6 ).

[0100] The LD signals 1306a, 1306b, and 1306c output by the level detector circuits 1314a, 1314b, and 1314c are provided to the CDR decision logic 1316. The CDR decision logic 1316 is configured to generate a receive clock signal 1310 and a 3-bit wire status signal 1308 representing the current wire status of the UI. In one example, the CDR decision logic 1316 is configured to select among six possible values ​​for the wire status signal 1308. In one example, each LD signal 1306a, 1306b, and 1306c includes a first bit indicating a detected strong difference and a second bit indicating polarity. Only one of the LD signals 1306a, 1306b, and 1306c indicates a detected strong difference, and this LD signal 1306a, 1306b, and 1306c is used to select the value of the wire status signal 1308. For example, when the difference signal 1304a generated by the AB differential receiver 1312a indicates a strong difference, then the CDR decision logic 1316 can be configured to use the polarity information in the difference signal 1304a to select between a value representing the +x signaling state 602 and a value representing the -x signaling state 612 (see...). Figure 6The 3-bit wire status signal 1308 output by the CDR decision logic 1316 is used as the output of the LD signals 1306a, 1306b, and 1306c. In some examples, the CDR decision logic 1316 uses a lookup table indexed by the binary values ​​of the LD signals 1306a, 1306b, and 1306c to select the 3-bit wire status signal 1308 output by the CDR decision logic 1316. In other examples, the 3-bit wire status signal 1308 output by the CDR decision logic 1316 is generated by combinational logic that receives the LD signals 1306a, 1306b, and 1306c generated by the level detector circuits 1314a, 1314b, and 1314c as its input.

[0101] Once the transitions of the LD signals 1306a, 1306b, 1306c generated by the level detector circuits 1314a, 1314b, 1314c indicate a newly detected strong difference between two wires in wires 1302a, 1302b, 1302c, a 3-bit wire status signal 1308 output by the CDR decision logic 1316 can be generated. According to the C-PHY protocol, the same signaling state cannot be repeated in consecutive UIs, allowing the clock signal to be generated directly in response to transitions in the LD signals 1306a, 1306b, 1306c. Each valid signaling state of wires 1302a, 1302b, 1302c ensures that only one of the differential receivers 1312a, 1312b, 1312c generates a strong difference, and each differential receiver 1312a, 1312b, 1312c can indicate whether the difference between its inputs is positive or negative. The CDR decision logic 1316 responds to a change in the first bit 1412a, 1412b, or 1412c of the LD signals 1306a, 1306b, or 1306c indicating strong differences, or to a change in the second bit 1414a, 1414b, or 1414c indicating the polarity of the strong difference voltage. In both cases, the detection of a change associated with a differential receiver 1312a, 1312b, or 1312c is sufficient to generate an edge in the receive clock signal 1310.

[0102] The one-to-one correlation between a strong voltage level and its recovered conductor state enables receiver circuit 1300 to generate complete conductor state information based on the voltage level. The ability to generate complete conductor state information from the voltage level at the output of only one differential receiver 1312a, 1312b, 1312c eliminates the need for explicit delays to accommodate the variable transition times at the outputs of the differential receivers 1312a, 1312b, 1312c. The resulting receiver circuit 1300 is robust, tolerant of PVT variations, and unaffected by inter-symbol interference (ISI).

[0103] The one-to-one correlation between the strong voltage level and its recovered wire state, along with the protocol definition requirements for changing the wire state between each pair of consecutive UIs, enables the recovery of the receive clock signal 1310 from the transitions of a single difference signal 1304a, 1304b, 1304c. The recovered receive clock signal 1310 is naturally reduced to half the data rate, and the need for additional delay elements can be eliminated from the clock recovery circuitry. Compared to, for example... Figure 11 The programmable generator 1118 shown provides further reductions in complexity and calibration requirements.

[0104] In some examples, the wire state signal 1308 output by the CDR decision logic 1316 can be captured in a register representing the current wire state. The current wire state can be compared with the wire state of the immediately preceding UI to generate a three-bit FRP symbol 626 representing the change in wire state between UIs (see...). Figure 6 In one example, the symbol stream is provided to a serial-to-parallel converter, which assembles a group of seven FRP symbols to be submitted to the decoder. In some examples, the receive clock signal 1310 can be further processed to control the timing of symbol generation and decoding.

[0105] In some examples, receiver circuitry 1300 may include termination circuitry 1318 for a three-wire C-PHY bus. In other examples, termination circuitry 1318 for the three-wire C-PHY bus is provided externally.

[0106] Figure 15 Receiver circuitry 1500 is shown. Receiver circuitry 1500 includes calibration circuitry 1520 and can perform clock and data recovery based on the identification of difference signals 1504a, 1504b, 1504c that generate strong voltage levels in the UI. In some respects, receiver circuitry 1500 corresponds to... Figure 13The receiver circuit 1300 is shown. Differential signals 1504a, 1504b, and 1504c are generated by three differential receivers 1512a, 1512b, and 1512c configured to compare the signal states on mutually different pairs of wires 1502a, 1502b, and 1502c. The AB differential receiver 1512a compares the reception states of wire A 1502a and wire B 1502b, the BC differential receiver 1512b compares the reception states of wire B 1502b and wire C 1502c, and the CA differential receiver 1512c compares the reception states of wire C 1502c and wire A 1502a. In the example shown, each of the differential receivers 1512a, 1512b, and 1512c includes one or more equalization circuits. In one example, each of the differential receivers 1512a, 1512b, and 1512c includes CTLE and VGA.

[0107] Each difference signal 1504a, 1504b, 1504c is provided to level detector circuits 1514a, 1514b, 1514c. Each level detector circuit 1514a, 1514b, 1514c is configured to determine whether the voltage on the corresponding difference signal 1504a, 1504b, 1504c exceeds a positive threshold voltage level or is less than a negative threshold voltage level. In one example, each level detector circuit 1514a, 1514b, 1514c outputs a two-bit LD signal (e.g., LD signals 1506a, 1506b, 1506c), where one bit indicates that the magnitude of the corresponding difference signal 1504a, 1504b, 1504c indicates a strong voltage level (e.g., 200mV relative to 100mV), and the other bit indicates the polarity of the corresponding difference signal 1504a, 1504b, 1504c. In another example, the LD signals 1506a, 1506b, 1506c output by each level detector circuit 1514a, 1514b, 1514c include a first bit indicating a strong positive difference when set high (or low in some examples), and a second bit indicating a strong negative difference when set low. In this latter example, only one bit of the LD signals 1506a, 1506b, 1506c can be set high in any UI, and both bits can be set low in one or more UIs.

[0108] The LD signals 1506a, 1506b, and 1506c output by the level detector circuits 1514a, 1514b, and 1514c are provided to the CDR decision logic 1516. The CDR decision logic 1516 is configured to generate a receive clock signal 1510 and a 3-bit wire status signal 1508 representing the current wire status of the UI. In one example, the CDR decision logic 1516 is configured to select among six possible values ​​for the wire status signal 1508. In one example, each LD signal 1506a, 1506b, and 1506c includes a first bit indicating a detected strong voltage level and a second bit indicating polarity. Only one of the LD signals 1506a, 1506b, and 1506c indicates a detected strong voltage level, and this LD signal 1506a, 1506b, and 1506c is used to select the value of the wire status signal 1508. In some examples, the CDR decision logic 1516 uses a lookup table indexed by LD signals 1506a, 1506b, and 1506c to select the 3-bit wire status signal 1508 output by the CDR decision logic 1516. In other examples, the 3-bit wire status signal 1508 output by the CDR decision logic 1516 is generated by combinational logic that receives the LD signals 1506a, 1506b, and 1506c generated by level detector circuits 1514a, 1514b, and 1514c as its input.

[0109] In one aspect of this disclosure, a calibration circuit 1520, including one or more asynchronous counters 1522 and calibration logic 1524, can be used to calibrate the equalization circuitry in differential receivers 1512a, 1512b, and 1512c. In some examples, in addition to combinational logic circuitry, the calibration logic 1524 includes a processor, a state machine, and / or sequencing logic. In some examples, the calibration procedure can be controlled independently by the calibration logic 1524 or in cooperation with processing circuitry in the receiving device. In one example, the calibration circuit 1520 can be enabled during a preamble transmitted via a three-wire group, where the preamble generates a pattern of signaling states over a period of time. In some examples, this pattern can be cyclical. The calibration circuit 1520 can be used to define and configure CTLE coefficients and VGA gains 1518a, 1518b, and 1518c for each of the differential receivers 1512a, 1512b, and 1512c. In some cases, the calibration circuit 1520 can be configured to determine one or more thresholds among the thresholds 1528a, 1528b, 1528c, 1530a, 1530b, and 1530c for determining strong voltage levels in the difference signals 1504a, 1504b, and 1504c.

[0110] In the example shown, calibration involves configuring the CTLE coefficient and gain settings for the VGA in each of the differential receivers 1512a, 1512b, and 1512c. Calibration can begin with low values ​​for the VGA's CTLE coefficient and gain settings. The asynchronous counter 1522 can be configured to count pulses or edges in the LD signals 1506a, 1506b, and 1506c, and the calibration logic 1524 can be configured to compare the output of the asynchronous counter 1522 with a predefined threshold at certain intervals to determine if the current gain setting is sufficient. Otherwise, the calibration logic can continue calibration by increasing the CTLE coefficient and VGA gain. When calibration is complete, the calibration circuit 1520 can provide a completion signal 1526 to the controller of the C-PHY interface.

[0111] Figure 16 This is a timing diagram illustrating calibration sequence 1600, during which the equalization circuitry in the differential receiver can be calibrated according to certain aspects of this disclosure. In one example, using... Figure 15 The calibration circuit 1520 performs the calibration, and includes one or more asynchronous counters 1522 and calibration logic 1524. In some examples, in addition to combinational logic circuitry, the calibration logic 1524 includes a processor, a state machine, and / or sequencing logic. The calibration circuit 1520 can be enabled during a preamble transmitted via a three-wire group, where the preamble generates a signaling state in a pattern over a period of time. In some examples, this pattern can be cyclic.

[0112] The timing diagram shown illustrates a difference signal 1602 generated by the differential receiver, a level detection signal 1604 in response to the voltage level of the difference signal 1602, and a gain control bit 1606 provided to the equalization circuitry in the differential receiver. The difference signal 1602 may correspond to one of the difference signals 1504a, 1504b, 1504c output by the differential receivers 1512a, 1512b, 1512c, and the level detection signal 1604 may be provided by the level detector circuits 1514a, 1514b, 1514c in response to the difference signal 1602. A calibration completion signal 1608 may be provided by the calibration circuit 1520 when calibration of each of the differential receivers 1512a, 1512b, 1512c is confirmed. In the timing diagram shown, the calibration completion signal 1608 is initially at a voltage level 1610 corresponding to a logic low state.

[0113] Gain control bit 1606 can initially be set to a low level or a default level. In one example, gain control bit 1606 can cause the equalization circuitry in the differential receiver to apply unity gain. In other examples, gain control bit 1606 can be initialized to a level equal to or slightly lower than the gain setting of a previous calibration. As shown, gain control bit 1606 is set to an initial level (here, 3'b001) in the first calibration step 1612a and increments in each subsequent calibration step 1612b-1612f until calibration is achieved. The amplitude of the difference signal 1602 increments based on the gain level selected by gain control bit 1606 until a change in gain applied by the equalization circuitry after transition 1614 between calibration steps 1612e-1612f causes the amplitude of the difference signal 1602 to exceed a configured or predefined threshold level 1616 or 1618. The amplitude transition across threshold level 1616 or 1618 is indicated by a transition in level detection signal 1604. The controller in the processing circuitry monitoring the level detection signal 1604 can drive the calibration completion signal 1608 to a voltage level 1620 corresponding to a logic high state to indicate the end of the calibration process. The transition 1622 of the calibration completion signal 1608 can be delayed with respect to the first detection of a difference signal 1602 exceeding a configured or predefined threshold level 1616 or 1618. In some examples, this delay is provided to ensure that transients are not a cause of premature termination of calibration. In some examples, the delay is provided to ensure that all equalization circuitry in the differential receivers 1512a, 1512b, and 1512c has been calibrated, while suppressing changes in the gain control bit 1606 of the calibrated equalization circuitry.

[0114] Examples of processing circuits and methods

[0115] Figure 17 An example of a hardware implementation of a device 1700 employing processing circuitry 1702 is shown. Processing circuitry 1702 can be configured to perform one or more functions disclosed herein. According to various aspects of this disclosure, processing circuitry 1702 can be used to implement the elements disclosed herein, or any portion thereof, or any combination thereof. Processing circuitry 1702 may include certain devices, circuitry, and / or logic supporting the clock recovery techniques disclosed herein.

[0116] Processing circuitry 1702 may include one or more processors 1704 controlled by some combination of hardware and software modules. Examples of processors 1704 include microprocessors, microcontrollers, digital signal processors (DSPs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, sequencers, gating logic, discrete hardware circuitry, and other suitable hardware configured to perform the various functions described throughout this disclosure. One or more processors 1704 may include dedicated processors that perform specific functions and may be configured, enhanced, or controlled by one of the software modules 1716. One or more processors 1704 may be configured by a combination of software modules 1716 loaded during initialization and further configured by loading or unloading one or more software modules 1716 during operation.

[0117] In the illustrated example, processing circuitry 1702 can be implemented using a bus architecture typically represented by bus 1710. Bus 1710 may include any number of interconnect buses and bridges, depending on the specific application and overall design constraints of processing circuitry 1702. In one example, bus 1710 links together various circuits including one or more processors 1704 and processor-readable storage medium 1706. Processor-readable storage medium 1706 may include memory devices and mass storage devices, and may be referred to herein as computer-readable medium and / or processor-readable medium. Bus 1710 may also link various other circuits, such as timing sources, timers, peripheral devices, voltage regulators, and power management circuitry. Bus interface 1708 provides an interface between bus 1710 and one or more transceivers 1712. Transceivers 1712 may be provided for each networking technology supported by the processing circuitry. In some cases, multiple networking technologies may share some or all of the circuitry or processing modules found in transceivers 1712. Each transceiver 1712 provides components for communicating with various other devices via a transmission medium. Depending on the nature of the device 1700, a user interface 1718 (e.g., keypad, display, speaker, microphone, joystick) may also be provided, and may be directly or communicatively coupled to the bus 1710 via the bus interface 1708.

[0118] Processor 1704 may be responsible for managing bus 1710 and general processing, which may include the execution of software stored in a computer-readable medium, including processor-readable storage medium 1706. In this regard, processing circuitry 1702 including processor 1704 may be used to implement any of the methods, functions, and techniques disclosed herein. Processor-readable storage medium 1706 may be used to store data manipulated by processor 1704 during software execution, and the software may be configured to implement any of the methods disclosed herein.

[0119] One or more processors 1704 in processing circuitry 1702 can execute software. Software should be interpreted broadly as instructions, instruction sets, code, code segments, program code, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable programs, threads of execution, procedures, functions, algorithms, etc., whether referred to as software, firmware, middleware, microcode, hardware description languages, or others. Software may reside in a computer-readable form on processor-readable storage medium 1706 or another external processor-readable medium. Processor-readable storage medium 1706 may include non-transitory computer-readable media. For example, non-transitory processor-readable media include magnetic storage devices (e.g., hard disks, floppy disks, magnetic stripes), optical discs (e.g., compact discs (CDs) or digital versatile discs (DVDs)), smart cards, flash memory devices (e.g., "flash drives," cards, sticks, or key drives), random access memory (RAM), ROM, PROM, erasable PROM (EPROM), EEPROM, registers, removable disks, and any other suitable media for storing software and / or instructions that can be accessed and read by a computer. For example, processor-readable storage medium 1706 may also include a carrier wave, a transmission line, and any other suitable media for transmitting software and / or instructions that can be accessed and read by a computer. Processor-readable storage medium 1706 may reside in processing circuitry 1702, in processor 1704, outside of processing circuitry 1702, or distributed across multiple entities including processing circuitry 1702. Processor-readable storage medium 1706 may be embodied in a computer program product. For example, a computer program product may include a computer-readable medium in packaging material. Those skilled in the art will recognize that how best to implement the functionality described throughout this disclosure depends on the specific application and the overall design constraints imposed on the system.

[0120] Processor-readable storage medium 1706 can maintain and / or organize software such as loadable code segments, modules, applications, programs, etc., which may be referred to herein as software module 1716. Each software module 1716 may include instructions and data that, when installed or loaded on processing circuitry 1702 and executed by one or more processors 1704, contribute to a runtime image 1714 that controls the operation of one or more processors 1704. When executed, certain instructions may cause processing circuitry 1702 to perform functions according to certain methods, algorithms, and procedures described herein.

[0121] Some software modules in software module 1716 may be loaded during the initialization of processing circuitry 1702, and these software modules 1716 may configure processing circuitry 1702 to achieve the performance of the various functions disclosed herein. For example, some software modules 1716 may configure the internal devices and / or logic circuitry 1722 of processor 1704, and may manage access to external devices such as transceiver 1712, bus interface 1708, user interface 1718, timers, math coprocessors, etc. Software module 1716 may include a control program and / or operating system that interacts with interrupt handlers and device drivers, and controls access to various resources provided by processing circuitry 1702. Resources may include memory, processing time, access to transceiver 1712, user interface 1718, etc.

[0122] One or more processors 1704 of the processing circuitry 1702 can be multifunctional, whereby some software modules in software module 1716 are loaded and configured to perform different functions or different instances of the same function. One or more processors 1704 can also be adapted to manage background tasks initiated in response to inputs, such as from user interface 1718, transceiver 1712, and device drivers. To support the performance of multiple functions, one or more processors 1704 can be configured to provide a multitasking environment, whereby each of the multiple functions is implemented as a set of tasks served by one or more processors 1704 as needed or desired. In one example, a time-sharing program 1720 can be used to implement the multitasking environment, which passes control of processors 1704 between different tasks, whereby each task, upon completing any unfinished operations and / or in response to inputs such as interrupts, returns control of one or more processors 1704 to the time-sharing program 1720. When a task has control over one or more processors 1704, the processing circuitry is effectively dedicated to the purpose targeted by the function associated with the control task. The time-sharing program 1720 may include an operating system, a main loop that passes control on a loop-based basis, a function that allocates control over one or more processors 1704 according to the priority of functions, and / or an interrupt-driven main loop that responds to external events by providing control over one or more processors 1704 to the processing functions.

[0123] Figure 18This is flowchart 1800 of a data communication method. This method can be performed at a receiving device coupled to a three-wire serial bus. In one example, the three-wire serial bus can operate according to the C-PHY protocol. At block 1802, the receiving device can generate multiple difference signals. Each difference signal can represent the voltage difference between a pair of wires in the three-wire serial bus. In the example of a serial bus operating according to the C-PHY protocol, three difference signals can be generated. The voltage across the wires of the three-wire serial bus is represented as V. A V B and V C The difference signal can then represent the voltage difference V. A - V B V B - V C and V C –V A .

[0124] At block 1804, the receiving device can identify a first difference signal among a plurality of difference signals that has the largest voltage value among the plurality of difference signals in a first UI. In one example, the first UI is one UI in a sequence of consecutive UIs, and data can be encoded in signaling state transitions between successive UIs. At block 1806, the receiving device can determine the signaling state of the three-wire serial bus for the first UI based on the identification of the wire pair corresponding to the first difference signal and the polarity of the first difference signal in the first UI.

[0125] In some aspects, the receiving device can generate a first edge in a clock signal in response to a transition of a first difference signal during a first UI. The receiving device can capture the signaling state of a continuous UI sequence based on the timing provided by the clock signal. The receiving device can decode data from signaling state transitions between consecutive UIs in a continuous UI sequence. The receiving device can identify a second difference signal among a plurality of difference signals that has the largest voltage value among the plurality of difference signals in a second UI. The second difference signal may be different from the first difference signal. The receiving device can determine the signaling state of the three-wire serial bus for the second UI based on the identification of the wire pair corresponding to the second difference signal and the polarity of the second difference signal in the second UI. The receiving device can generate a second edge in a clock signal in response to a transition of the second difference signal, the first edge and the second edge including a rising edge and a falling edge. In the clock signal, the first edge immediately precedes the second edge.

[0126] In some examples, when the first difference signal has a voltage level greater than a first threshold voltage or less than a second threshold voltage, the receiving device can determine that the first difference signal has the largest voltage value among a plurality of difference signals in the first UI. When the voltage of the first difference signal is greater than the first threshold voltage, the receiving device can determine that the first difference signal has positive polarity. When the voltage of the first difference signal is less than the second threshold voltage, the receiving device can determine that the first difference signal has negative polarity.

[0127] In some examples, the receiving device can count the number of UIs in which the first difference signal, having the largest voltage value among multiple difference signals, is identified when the C-PHY preamble is transmitted via a three-wire serial bus. The receiving device can calibrate the equalization circuitry in the differential receiver used to generate the first difference signal based on the number of unit intervals in the C-PHY preamble in which the first difference signal has the largest voltage value.

[0128] Figure 19 This diagram illustrates an example of a hardware implementation of a device 1900 employing processing circuitry 1902. Processing circuitry 1902 typically has at least one processor 1916, which may include a microprocessor, microcontroller, digital signal processor, sequencer, or state machine. Processing circuitry 1902 can be implemented using a bus architecture typically represented by bus 1920. Bus 1920 may include any number of interconnect buses and bridges, depending on the specific application and overall design constraints of processing circuitry 1902. Bus 1920 links together various circuits including one or more processors and / or hardware modules, represented by processor 1916, modules or circuits 1904, 1906, and 1908, differential receiver 1912, and processor-readable storage medium 1918. Bus 1920 may also link various other circuits, such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art and will not be described further.

[0129] Processor 1916 is responsible for general processing, including executing software stored on processor-readable storage medium 1918. When executed by processor 1916, this software causes processing circuitry 1902 to perform the various functions described above for any particular device. Processor-readable storage medium 1918 can also be used to store data manipulated by processor 1916 during software execution, including data decoded from symbols transmitted via connector or wire 1910, which may be configured as a C-PHY bus. Processing circuitry 1902 also includes at least one of modules 1904, 1906, and 1908. Modules 1904, 1906, and 1908 may be software modules running in processor 1916, residing / stored in processor-readable storage medium 1918, one or more hardware modules coupled to processor 1916, or some combination thereof. Modules 1904, 1906, and / or 1908 may include microcontroller instructions, state machine configuration parameters, or some combination thereof. The processing circuitry 1902 also includes a differential receiver 1912 that generates a difference signal 1922, which represents a difference in signaling status between different connector or wire pairs 1910. The processing circuitry 1902 may include a lookup table 1914, which may be implemented in the storage medium 1918 or separately from the storage medium 1918.

[0130] In one configuration, device 1900 may be configured to receive data transmitted according to the C-PHY protocol. Device 1900 may include module and / or circuit 1908 configured to determine the voltage magnitude and polarity of difference signal 1922 and detect a first difference signal whose magnitude is greater than other difference signals. Device 1900 may include module and / or circuit 1906 configured to determine the signaling state of connector or wire 1910 for the first difference signal based on the identification of the wire pair corresponding to the first difference signal and the polarity of the first difference signal in the first UI. Device 1900 may include module and / or circuit 1904 for calibrating equalization circuitry in differential receiver 1912. For example, the equalization circuitry may be calibrated based on the number of UIs in the C-PHY preamble where the first difference signal has the maximum voltage magnitude.

[0131] In one example, device 1900 has a plurality of differential receivers 1912 configured to generate a plurality of difference signals 1922. Each of the plurality of difference signals 1922 represents a voltage difference between a pair of wires coupled to a connector or wire 1910 in a three-wire serial bus. Device 1900 has a recovery circuit configured to identify a first difference signal having the largest voltage value among the plurality of difference signals in a first UI, and to determine the signal state of the three-wire serial bus for the first UI based on the identification of the wire pair corresponding to the first difference signal and the polarity of the first difference signal in the first UI.

[0132] In some examples, the recovery circuit is also configured to generate a first edge in the clock signal in response to a transition of the first difference signal during the first UI. The device 1900 may have a decoding circuit configured to capture the signaling state of a successive UI sequence according to timing provided by the clock signal, and to decode data from signaling state transitions between consecutive UIs in the successive UI sequence. The recovery circuit may also be configured to identify a second difference signal among a plurality of difference signals having the largest voltage value among the plurality of difference signals in the second UI. The second difference signal is different from the first difference signal. The recovery circuit may also be configured to determine the signaling state of the three-wire serial bus for the second UI based on the identification of the wire pair corresponding to the second difference signal and the polarity of the second difference signal in the second UI. The recovery circuit may also be configured to generate a second edge in the clock signal in response to a transition of the second difference signal, the first edge and the second edge including a rising edge and a falling edge. In the clock signal, the first edge immediately precedes the second edge.

[0133] The device 1900 may have multiple level detectors. A first level detector may be configured to determine that the first difference signal has the largest voltage value among multiple difference signals in the first UI when the first difference signal has a voltage level greater than a first threshold voltage or less than a second threshold voltage. The first level detector may also be configured to determine that the first difference signal has positive polarity when the voltage of the first difference signal is greater than the first threshold voltage, and to determine that the first difference signal has negative polarity when the voltage of the first difference signal is less than the second threshold voltage.

[0134] The device 1900 may have a calibration circuit configured to: count the number of UIs in which a first difference signal having the largest voltage value among a plurality of difference signals is identified when the C-PHY preamble is transmitted via a three-wire serial bus, and calibrate the equalizer in the differential receiver used to generate the first difference signal based on the number of UIs counted during the transmission of the C-PHY preamble.

[0135] The processor-readable storage medium 1918 may be a non-transitory storage medium and may store instructions or code that, when executed by the processor 1916, cause the processing circuit 1902 to: generate a plurality of difference signals, each difference signal representing a voltage difference between a pair of wires in a three-wire serial bus; identify a first difference signal among the plurality of difference signals that has the largest voltage value among the plurality of difference signals in a first unit interval; and determine the signaling state of the three-wire serial bus for the first unit interval based on the identification of the wire pair corresponding to the first difference signal and the polarity of the first difference signal in the first unit interval.

[0136] In some examples, the instruction or code may also cause processing circuitry 1902 to generate a first edge in a clock signal in response to a transition of the first difference signal during a first unit interval. The instruction or code may also cause processing circuitry 1902 to: capture the signaling state of a sequence of consecutive unit intervals according to timing provided by the clock signal, and decode data from signaling state transitions between consecutive unit intervals in the sequence of consecutive unit intervals. The instruction or code may also cause processing circuitry 1902 to: identify a second difference signal among a plurality of difference signals that has the largest voltage value among the plurality of difference signals in a second unit interval, and determine the signaling state of the three-wire serial bus for the second unit interval based on the identification of the wire pair corresponding to the second difference signal and the polarity of the second difference signal in the second unit interval. The second difference signal is different from the first difference signal. The instruction or code may also cause processing circuitry 1902 to generate a second edge in a clock signal in response to a transition of the second difference signal, the first edge and the second edge including a rising edge and a falling edge. The first edge immediately precedes the second edge in the clock signal.

[0137] In some examples, the instruction or code may also cause the processing circuit 1902 to: determine that the first difference signal has the largest voltage value among a plurality of difference signals in a first unit interval when the first difference signal has a voltage level greater than a first threshold voltage or less than a second threshold voltage. The instruction or code may also cause the processing circuit 1902 to: determine that the first difference signal has positive polarity when the voltage of the first difference signal is greater than the first threshold voltage, and determine that the first difference signal has negative polarity when the voltage of the first difference signal is less than the second threshold voltage.

[0138] In some examples, the instruction or code may also cause the processing circuit 1902 to count the number of unit intervals of the first difference signal that identifies the largest voltage value among a plurality of difference signals while transmitting the C-PHY preamble via a three-wire serial bus, and to calibrate the equalizer in the differential receiver used to generate the first difference signal based on the number of unit intervals of the first difference signal that identifies the largest voltage value counted during the transmission of the C-PHY preamble.

[0139] Some implementation examples are described in the following numbered clauses: A data communication method includes: generating a plurality of difference signals, each difference signal representing a voltage difference between a pair of wires in a three-wire serial bus; identifying a first difference signal among the plurality of difference signals, the first difference signal having the largest voltage value among the plurality of difference signals in a first unit interval; and determining a signaling state for the three-wire serial bus for the first unit interval based on the identification of the wire pair corresponding to the first difference signal and the polarity of the first difference signal in the first unit interval.

[0140] The method according to Clause 1 further includes: generating a first edge in a clock signal in response to a transition of the first difference signal during a first unit interval.

[0141] The method according to Clause 2 further includes: capturing the signaling state of a continuous unit interval sequence based on timing provided by a clock signal; and decoding data from signaling state transitions between consecutive unit intervals in the continuous unit interval sequence.

[0142] The method according to Clause 2 or Clause 3 further includes: identifying a second differential signal among a plurality of differential signals, the second differential signal having the largest voltage value among the plurality of differential signals in the second unit interval, wherein the second differential signal is different from the first differential signal; and determining the signaling status of the three-wire serial bus for the second unit interval based on the identification of the wire pair corresponding to the second differential signal and the polarity of the second differential signal in the second unit interval.

[0143] The method according to Clause 4 further includes: generating a second edge in a clock signal in response to a transition of the second difference signal, wherein the first edge and the second edge include a rising edge and a falling edge.

[0144] According to the method described in Clause 5, the first edge immediately precedes the second edge in the clock signal.

[0145] The method according to any one of Clauses 1-6 further includes: when the first difference signal has a voltage level greater than a first threshold voltage or less than a second threshold voltage, determining that the first difference signal has the largest voltage value among a plurality of difference signals in a first unit interval.

[0146] The method according to Clause 7 further includes: determining that the first difference signal has a positive polarity when the voltage of the first difference signal is greater than a first threshold voltage; and determining that the first difference signal has a negative polarity when the voltage of the first difference signal is less than a second threshold voltage.

[0147] The method according to any one of Clauses 1-8 further includes: counting the number of unit intervals of a first difference signal that identifies the maximum voltage value among a plurality of difference signals when transmitting the C-PHY preamble via a three-wire serial bus; and calibrating the equalization circuit in the differential receiver used to generate the first difference signal based on the number of unit intervals of the C-PHY preamble in which the first difference signal has the maximum voltage value.

[0148] An apparatus for data communication includes: a plurality of differential receivers configured to generate a plurality of differential signals, each differential signal representing a voltage difference between a pair of wires in a three-wire serial bus; and a recovery circuit configured to: identify a first differential signal having the largest voltage value among the plurality of differential signals in a first unit interval; and determine a signaling state for the three-wire serial bus for the first unit interval based on the identification of the wire pair corresponding to the first differential signal and the polarity of the first differential signal in the first unit interval.

[0149] According to the apparatus of Clause 10, the recovery circuit is further configured to generate a first edge in the clock signal in response to a transition of the first difference signal during a first unit interval.

[0150] The apparatus according to Clause 11 further includes a decoding circuit configured to: capture signaling states of a continuous unit interval sequence based on timing provided by a clock signal; and decode data from signaling state transitions between consecutive unit intervals in the continuous unit interval sequence.

[0151] According to the apparatus of Clause 11 or Clause 12, the recovery circuit is further configured to: identify a second difference signal among a plurality of difference signals, the second difference signal having the maximum voltage value among the plurality of difference signals in the second unit interval, wherein the second difference signal is different from the first difference signal; and determine the signaling state of the three-wire serial bus for the second unit interval based on the identification of the wire pair corresponding to the second difference signal and the polarity of the second difference signal in the second unit interval.

[0152] According to the apparatus of Clause 13, the recovery circuit is further configured to generate a second edge in a clock signal in response to a transition of the second difference signal, wherein the first edge and the second edge include a rising edge and a falling edge.

[0153] The apparatus according to Clause 14, wherein the first edge immediately precedes the second edge in the clock signal.

[0154] The apparatus according to any one of claims 10-15 further includes: a plurality of level detectors, wherein a first level detector is configured to: determine that the first difference signal has the largest voltage value among a plurality of difference signals in a first unit interval when the first difference signal has a voltage level greater than a first threshold voltage or less than a second threshold voltage.

[0155] According to the apparatus of Clause 16, the first level detector is further configured to: determine that the first difference signal has a positive polarity when the voltage of the first difference signal is greater than a first threshold voltage; and determine that the first difference signal has a negative polarity when the voltage of the first difference signal is less than a second threshold voltage.

[0156] The apparatus according to any one of claims 10-17 further includes a calibration circuit configured to: count the number of unit intervals in which a first difference signal having the maximum voltage value among a plurality of difference signals is identified when the C-PHY preamble is transmitted via a three-wire serial bus; and calibrate the equalization circuit in the differential receiver used to generate the first difference signal based on the number of unit intervals in the C-PHY preamble in which the first difference signal has the maximum voltage value.

[0157] A non-transitory processor-readable storage medium includes code for: generating a plurality of difference signals, each difference signal representing a voltage difference between a pair of wires in a three-wire serial bus; identifying a first difference signal among the plurality of difference signals, the first difference signal having the largest voltage value among the plurality of difference signals in a first unit interval; and determining a signaling state for the three-wire serial bus for the first unit interval based on the identification of the wire pair corresponding to the first difference signal and the polarity of the first difference signal in the first unit interval.

[0158] The storage medium according to Clause 19 further includes: generating a first edge in a clock signal in response to a transition of the first difference signal during a first unit interval.

[0159] The storage medium according to Clause 20 further includes: capturing signaling states of a sequence of consecutive unit intervals based on timing provided by a clock signal; and decoding data from signaling state transitions between consecutive unit intervals in the sequence of consecutive unit intervals.

[0160] The storage medium according to Clause 20 or Clause 21 further includes: identifying a second differential signal among a plurality of differential signals, the second differential signal having the largest voltage value among the plurality of differential signals in the second unit interval, wherein the second differential signal is different from the first differential signal; and determining the signaling state of the three-wire serial bus for the second unit interval based on the identification of the wire pair corresponding to the second differential signal and the polarity of the second differential signal in the second unit interval.

[0161] The storage medium according to Clause 22 further includes: generating a second edge in a clock signal in response to a transition of the second difference signal, wherein the first edge and the second edge include a rising edge and a falling edge.

[0162] The storage medium as described in Clause 23, wherein the first edge immediately precedes the second edge in the clock signal.

[0163] The storage medium according to any one of Clauses 19-24 further includes: determining that the first difference signal has the largest voltage value among a plurality of difference signals in a first unit interval when the first difference signal has a voltage level greater than a first threshold voltage or less than a second threshold voltage.

[0164] The storage medium according to Clause 25 further includes: determining that the first difference signal has a positive polarity when the voltage of the first difference signal is greater than a first threshold voltage; and determining that the first difference signal has a negative polarity when the voltage of the first difference signal is less than a second threshold voltage.

[0165] The storage medium according to any one of Clauses 19-26 further includes: counting the number of unit intervals of a first difference signal that identifies the maximum voltage value among a plurality of difference signals when transmitting the C-PHY preamble via a three-wire serial bus; and calibrating the equalization circuitry in the differential receiver used to generate the first difference signal based on the number of unit intervals of the C-PHY preamble in which the first difference signal has the maximum voltage value.

[0166] An apparatus for decoding data transmitted over a three-wire three-phase interface includes: a component for generating a plurality of difference signals, each difference signal representing a voltage difference between a pair of wires in a three-wire serial bus; a component for identifying a first difference signal among the plurality of difference signals, the first difference signal having the largest voltage value among the plurality of difference signals in a first unit interval; and a component for determining a signaling state of the three-wire serial bus for the first unit interval based on the identification of the wire pair corresponding to the first difference signal and the polarity of the first difference signal in the first unit interval.

[0167] The apparatus according to Clause 28 further includes: a component for generating a first edge in a clock signal in response to a transition of the first difference signal during a first unit interval.

[0168] The apparatus according to Clause 29 further includes: means for capturing signaling states of a sequence of consecutive unit intervals based on timing provided by a clock signal; and means for decoding data from signaling state transitions between consecutive unit intervals in the sequence of consecutive unit intervals.

[0169] It should be understood that the specific order or hierarchy of steps in the disclosed process is an illustration of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process can be rearranged. Furthermore, some steps can be combined or omitted. The appended method claims present the elements of the various steps in an illustrative order and are not intended to limit one to the specific order or hierarchy presented.

[0170] The preceding description is provided to enable those skilled in the art to practice the various aspects described herein. Various modifications to these aspects will readily be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects shown herein, but are to be consistent with the full scope of the language claims, wherein, unless specifically stated otherwise, reference to elements in the singular form is not intended to mean “one and only one,” but rather “one or more.” Unless specifically stated otherwise, the term “some” means one or more. All structural and functional equivalents of elements known to or to be known hereafter by those skilled in the art throughout the various aspects described herein are expressly incorporated herein by reference and are intended to be covered by the claims. Furthermore, nothing disclosed herein is intended to be donated to the public, whether or not such disclosure is expressly stated in the claims. No element of a claim shall be construed as a component plus a function unless the element is expressly stated using the phrase “component for…”.

Claims

1. A method for data communication, comprising: Multiple difference signals are generated, each representing the voltage difference between a pair of wires in a three-wire serial bus; A first difference signal is identified among the plurality of difference signals, the first difference signal having the largest voltage value among the plurality of difference signals in a first unit interval; as well as Based on the identification of the wire pair corresponding to the first difference signal and the polarity of the first difference signal in the first unit interval, the signaling status of the three-wire serial bus for the first unit interval is determined.

2. The method according to claim 1, further comprising: In response to the transition of the first difference signal during the first unit interval, a first edge in the clock signal is generated.

3. The method according to claim 2, further comprising: The signaling status of a continuous unit interval sequence is captured based on the timing provided by the clock signal; as well as Decode data from signaling state transitions between consecutive unit intervals in the continuous unit interval sequence.

4. The method according to claim 2, further comprising: A second difference signal is identified among the plurality of difference signals, the second difference signal having the maximum voltage value among the plurality of difference signals in a second unit interval, wherein the second difference signal is different from the first difference signal; as well as Based on the identification of the wire pair corresponding to the second difference signal and the polarity of the second difference signal in the second unit interval, the signaling status of the three-wire serial bus for the second unit interval is determined.

5. The method according to claim 4, further comprising: In response to the transition of the second difference signal, a second edge in the clock signal is generated, wherein the first edge and the second edge include a rising edge and a falling edge.

6. The method of claim 5, wherein the first edge immediately precedes the second edge in the clock signal.

7. The method according to claim 1, further comprising: When the first difference signal has a voltage level greater than the first threshold voltage or less than the second threshold voltage, it is determined that the first difference signal has the largest voltage value among the plurality of difference signals in the first unit interval.

8. The method according to claim 7, further comprising: When the voltage of the first difference signal is greater than the first threshold voltage, it is determined that the first difference signal has a positive polarity; as well as When the voltage of the first difference signal is less than the second threshold voltage, it is determined that the first difference signal has a negative polarity.

9. The method according to claim 1, further comprising: When transmitting the C-PHY preamble via the three-wire serial bus, the number of unit intervals in which the first difference signal, which identifies the largest voltage value among the plurality of difference signals, is counted; as well as The equalization circuit in the differential receiver used to generate the first difference signal is calibrated based on the number of unit intervals in the C-PHY preamble, wherein the first difference signal has the maximum voltage value.

10. An apparatus for data communication, comprising: Multiple differential receivers are configured to generate multiple differential signals, each representing the voltage difference between a pair of wires in a three-wire serial bus; as well as The recovery circuit is configured as follows: A first difference signal is identified, wherein the first difference signal has the largest voltage value among the plurality of difference signals in a first unit interval; as well as Based on the identification of the wire pair corresponding to the first difference signal and the polarity of the first difference signal in the first unit interval, the signaling status of the three-wire serial bus for the first unit interval is determined.

11. The apparatus of claim 10, wherein the recovery circuit is further configured to: In response to the transition of the first difference signal during the first unit interval, a first edge in the clock signal is generated.

12. The apparatus of claim 11, further comprising a decoding circuit, the decoding circuit being configured to: The signaling status of a continuous unit interval sequence is captured based on the timing provided by the clock signal; and Decode data from signaling state transitions between consecutive unit intervals in the continuous unit interval sequence.

13. The apparatus of claim 11, wherein the recovery circuit is further configured to: A second difference signal is identified among the plurality of difference signals, the second difference signal having the largest voltage value among the plurality of difference signals in a second unit interval, wherein the second difference signal is different from the first difference signal; and Based on the identification of the wire pair corresponding to the second difference signal and the polarity of the second difference signal in the second unit interval, the signaling status of the three-wire serial bus for the second unit interval is determined.

14. The apparatus of claim 13, wherein the recovery circuit is further configured to: In response to the transition of the second difference signal, a second edge in the clock signal is generated, wherein the first edge and the second edge include a rising edge and a falling edge.

15. The apparatus of claim 14, wherein the first edge immediately precedes the second edge in the clock signal.

16. The apparatus of claim 10, further comprising: Multiple level detectors, wherein a first level detector is configured to: determine that the first difference signal has the largest voltage value among the multiple difference signals in the first unit interval when the first difference signal has a voltage level greater than a first threshold voltage or less than a second threshold voltage.

17. The apparatus of claim 16, wherein the first level detector is further configured to: When the voltage of the first difference signal is greater than the first threshold voltage, it is determined that the first difference signal has a positive polarity; and When the voltage of the first difference signal is less than the second threshold voltage, it is determined that the first difference signal has a negative polarity.

18. The apparatus of claim 10, further comprising a calibration circuit, the calibration circuit being configured to: When transmitting the C-PHY preamble via the three-wire serial bus, the number of unit intervals in which the first difference signal, which identifies the largest voltage value among the plurality of difference signals, is counted; and The equalization circuit in the differential receiver used to generate the first difference signal is calibrated based on the number of unit intervals in the C-PHY preamble, wherein the first difference signal has the maximum voltage value.

19. A non-transitory processor-readable storage medium comprising code for the following operations: Multiple difference signals are generated, each representing the voltage difference between a pair of wires in a three-wire serial bus; A first difference signal is identified among the plurality of difference signals, the first difference signal having the largest voltage value among the plurality of difference signals within a first unit interval; and Based on the identification of the wire pair corresponding to the first difference signal and the polarity of the first difference signal in the first unit interval, the signaling status of the three-wire serial bus for the first unit interval is determined.

20. The storage medium of claim 19, further comprising code for the following operations: In response to the transition of the first difference signal during the first unit interval, a first edge in the clock signal is generated.

21. The storage medium of claim 20, further comprising code for the following operations: The signaling status of a continuous unit interval sequence is captured based on the timing provided by the clock signal; and Decode data from signaling state transitions between consecutive unit intervals in the continuous unit interval sequence.

22. The storage medium of claim 20, further comprising code for the following operations: A second difference signal is identified among the plurality of difference signals, the second difference signal having the largest voltage value among the plurality of difference signals in a second unit interval, wherein the second difference signal is different from the first difference signal; and Based on the identification of the wire pair corresponding to the second difference signal and the polarity of the second difference signal in the second unit interval, the signaling status of the three-wire serial bus for the second unit interval is determined.

23. The storage medium of claim 22, further comprising code for the following operations: In response to the transition of the second difference signal, a second edge in the clock signal is generated, wherein the first edge and the second edge include a rising edge and a falling edge.

24. The storage medium of claim 23, wherein the first edge immediately precedes the second edge in the clock signal.

25. The storage medium of claim 19, further comprising code for the following operations: When the first difference signal has a voltage level greater than the first threshold voltage or less than the second threshold voltage, it is determined that the first difference signal has the largest voltage value among the plurality of difference signals in the first unit interval.

26. The storage medium of claim 25, further comprising code for the following operations: When the voltage of the first difference signal is greater than the first threshold voltage, it is determined that the first difference signal has a positive polarity; and When the voltage of the first difference signal is less than the second threshold voltage, it is determined that the first difference signal has a negative polarity.

27. The storage medium of claim 19, further comprising code for the following operations: When transmitting the C-PHY preamble via the three-wire serial bus, the number of unit intervals in which the first difference signal, which identifies the largest voltage value among the plurality of difference signals, is counted; and The equalization circuit in the differential receiver used to generate the first difference signal is calibrated based on the number of unit intervals in the C-PHY preamble, wherein the first difference signal has the maximum voltage value.

28. An apparatus for decoding data transmitted over a three-wire three-phase interface, comprising: A component used to generate multiple difference signals, each representing the voltage difference between a pair of wires in a three-wire serial bus; A component for identifying a first difference signal among the plurality of difference signals, the first difference signal having the largest voltage value among the plurality of difference signals in a first unit interval; as well as A component for determining the signaling status of the three-wire serial bus for the first unit interval based on the identification of the wire pair corresponding to the first difference signal and the polarity of the first difference signal in the first unit interval.

29. The apparatus of claim 28, further comprising: A component for generating a first edge in a clock signal in response to a transition of the first difference signal during the first unit interval.

30. The apparatus of claim 29, further comprising: A component for capturing the signaling status of a continuous unit interval sequence based on timing provided by the clock signal; as well as A component for decoding data during signaling state transitions between consecutive unit intervals in the sequence of consecutive unit intervals.

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