Solid-state imaging elements and imaging devices

Abstract

This invention improves image quality in solid-state imaging elements that expose all pixels simultaneously. The solid-state imaging element includes a first pixel and a second pixel. In the first pixel, a first selection transistor is configured at a specific relative position, and a second selection transistor is configured at a different relative position. The first selection transistor turns on and off the path between a first capacitor element and a predetermined node to maintain a predetermined reset level, and the second selection transistor turns on and off the path between a second capacitor element and the node to maintain a signal level corresponding to the exposure amount. In the second pixel, a third selection transistor is configured at a specific relative position, and a fourth selection transistor is configured at a different relative position. The third selection transistor turns on and off the path between a third capacitor element and a predetermined node to maintain a predetermined reset level, and the fourth selection transistor turns on and off the path between a fourth capacitor element and the node to maintain a signal level corresponding to the exposure amount.

Description

Technical Field

[0001] This technology relates to a solid-state imaging element. Specifically, this technology relates to a solid-state imaging element and imaging device that performs analog-to-digital (AD) conversion for each column. Background Technology

[0002] Traditionally, for solid-state imaging elements, column analog-to-digital converters (ADCs) have been used to miniaturize pixels. In this method, pixel signals are read out row by row sequentially using an ADC configured for each column outside the pixel array unit. However, in this column ADC method, rolling shutter distortion can occur when exposure is performed using a rolling shutter method that starts exposure row by row. Therefore, to achieve a global shutter method that starts exposure simultaneously in all pixels, a solid-state imaging element has been proposed in which a pair of capacitors is provided for each pixel, and the capacitors maintain a reset level and a signal level (e.g., see Non-Patent Document 1). A pair of transistors is configured between the pair of capacitors and the preceding circuitry, and the reset level and signal level are supplied to the capacitors via these transistors.

[0003] List of cited references

[0004] Non-patent literature

[0005] Non-patent literature 1: Geunsook Park et al., A 2.2μm Stacked Back Side Illuminated Voltage Domain Global Shutter CMOS Image Sensor, IEDM19-379. Summary of the Invention

[0006] The problem the invention aims to solve

[0007] In the aforementioned conventional techniques, the reset level and signal level are maintained in a pair of capacitors for each pixel, thereby achieving a global shutter mode based on a column ADC. However, in these conventional techniques, noise may be generated due to stray light at the pn junction of each of the pair of transistors connected to the capacitors. The noise level is not necessarily uniform for each pixel, and parasitic light sensitivity (PLS) may degrade due to the inconsistency in noise levels. The image quality of the image data degrades due to the degradation of PLS.

[0008] This technique was developed in light of this situation, and its purpose is to improve image quality in solid-state imaging elements where all pixels are exposed simultaneously.

[0009] Solution to the problem

[0010] This technology is proposed to solve the aforementioned problems, and its first aspect is a solid-state imaging element, comprising: a first pixel, wherein a first selection transistor is disposed at a specific relative position, and a second selection transistor is disposed at a different relative position; the first selection transistor turns on and off a path between a first capacitor element and a predetermined node for maintaining a predetermined reset level; the second selection transistor turns on and off a path between a second capacitor element and the node for maintaining a signal level corresponding to an exposure amount; and a second pixel, wherein a third selection transistor is disposed at a specific relative position, and a fourth selection transistor is disposed at a different relative position; the third selection transistor turns on and off a path between a third capacitor element and a predetermined node for maintaining a predetermined reset level; and the fourth selection transistor turns on and off a path between a fourth capacitor element and the node for maintaining a signal level corresponding to an exposure amount. Therefore, this configuration provides the effect of improving image quality.

[0011] Furthermore, in the first aspect, the second pixel can be adjacent to the first pixel. Therefore, this configuration provides the effect of making noise between adjacent pixels less noticeable.

[0012] Furthermore, in the first aspect, the pixels within the pixel array unit, including the first pixel and the second pixel, can be configured in a Bayer array. Therefore, this configuration provides the effect of improving the image quality of the color image.

[0013] Furthermore, in the first aspect, the pixel array unit may include a first region in which four first pixels are arranged in a 2x2 column configuration, and a second region adjacent to the first region in which four second pixels are arranged in a 2x2 column configuration. Therefore, this configuration provides the effect of improving the image quality of a color image.

[0014] Furthermore, in the first aspect, the pixel array unit may include a first region in which a first pixel and three second pixels are arranged in a 2x2 column configuration, and a second region adjacent to the first region in which the second pixel and three first pixels are arranged in a 2x2 column configuration. Therefore, this configuration provides the effect of improving the image quality of a color image.

[0015] Furthermore, in the first aspect, the pixels within a pixel array unit, including a first pixel and a second pixel, can be configured in a four-Bayer array, and the pixel array unit includes a first region in which the first pixel and three second pixels of the same color as the first pixel are arranged in a 2x2 column configuration, and a second region adjacent to the first region in which the second pixel and three first pixels of the same color as the second pixel are arranged in a 2x2 column configuration. Therefore, this configuration provides the effect of improving the image quality of a color image.

[0016] Furthermore, in the first aspect, the node can be a downstream node, and the pixel block configured with the first pixel and the second pixel can include a first front-end circuit that sequentially generates a first reset level and a first signal level and holds them in first and second capacitor elements; a second front-end circuit that sequentially generates a second reset level and a second signal level and holds them in third and fourth capacitor elements; first, second, third, and fourth capacitor elements; a selection unit that includes a first selection circuit provided with first and second selection transistors and a second selection circuit provided with third and fourth selection transistors; and a downstream circuit that sequentially reads out each of the first and second reset levels and the first and second signal levels via the downstream node. Therefore, this configuration provides the effect of reducing kTC noise.

[0017] Furthermore, in the first aspect, the first front-end circuit may include a first photoelectric conversion element, a first front-end transfer transistor for transferring charge from the first photoelectric conversion element to the first floating diffusion layer, a first reset transistor for initializing the first floating diffusion layer, and a first front-end amplification transistor for amplifying the voltage of the first floating diffusion layer; and the second front-end circuit may include a second photoelectric conversion element, a second front-end transfer transistor for transferring charge from the second photoelectric conversion element to the second floating diffusion layer, a second reset transistor for initializing the second floating diffusion layer, and a second front-end amplification transistor for amplifying the voltage of the second floating diffusion layer. Therefore, this configuration provides the effect of maintaining a voltage level corresponding to the floating diffusion layer.

[0018] Furthermore, in the first aspect, the first front-end circuit may further include a first current source transistor connected to the first front-end node, and the second front-end circuit may further include a second current source transistor connected to the second front-end node. The first front-end amplifying transistor can amplify the voltage of the first floating diffusion layer and output the amplified voltage to the first front-end node. The second front-end amplifying transistor can amplify the voltage of the second floating diffusion layer and output the amplified voltage to the second front-end node. One end of each of the first and second capacitor elements is connected to the first front-end node, and the other end of each is connected to the first selection circuit. One end of each of the third and fourth capacitor elements is connected to the second front-end node, and the other end of each is connected to the second selection circuit. Therefore, this configuration provides the effect of supplying a constant current to each pixel.

[0019] Furthermore, in the first aspect, at a predetermined exposure start time, the first and second front-stage transfer transistors can transfer charge to the first and second floating diffusion layers, and the first and second reset transistors can initialize the first and second photoelectric conversion elements together with the first and second floating diffusion layers; and at a predetermined exposure end time, the first and second front-stage transfer transistors can transfer charge to the first and second floating diffusion layers. Therefore, this configuration provides the effect of simultaneous exposure of all pixels.

[0020] Furthermore, in the first aspect, the selection unit can sequentially execute control to connect one of the first and second capacitor elements to the subsequent node, execute control to connect the other of the first and second capacitor elements to the subsequent node, execute control to connect one of the third and fourth capacitor elements to the subsequent node, and execute control to connect the other of the third and fourth capacitor elements to the subsequent node. Therefore, this configuration provides the effect of sequentially reading the reset level and signal level of each of the two pixels.

[0021] Furthermore, in the first aspect, in a predetermined addition mode, the selection unit can sequentially execute control to connect one of the first and second capacitor elements and one of the third and fourth capacitor elements to the subsequent node, and execute control to connect the other of the first and second capacitor elements and the other of the third and fourth capacitor elements to the subsequent node. Therefore, this configuration provides the effect of reading out the signal obtained by pixel addition.

[0022] Furthermore, in the first aspect, the first preamplifier circuit may further include a first preamplifier selection transistor that outputs a voltage amplified by the first preamplifier transistor to a predetermined preamplifier node according to a predetermined first selection signal. The second preamplifier circuit may further include a second preamplifier selection transistor that outputs a voltage amplified by the second preamplifier transistor to the preamplifier node according to a predetermined second selection signal, and a current source transistor connected to the preamplifier node. One end of each of the first and second capacitor elements is connected to the preamplifier node, and the other end of each is connected to the first selection circuit. Similarly, one end of each of the third and fourth capacitor elements is connected to the preamplifier node, and the other end of each is connected to the second selection circuit. Therefore, this configuration provides the effect of two pixels sharing a current source transistor.

[0023] Furthermore, in the first aspect, the first and second pre-stage selection transistors can sequentially transition to a closed state immediately before and after the predetermined exposure end time. When the first pre-stage selection transistor is closed, the first reset transistor can initialize the first floating diffusion layer; when the second pre-stage selection transistor is closed, the second reset transistor can initialize the second floating diffusion layer. The first and second pre-stage selection transistors can sequentially transition to a closed state immediately after the exposure end time, and the first and second pre-stage transfer transistors can transfer charge at the predetermined exposure end time. Therefore, this configuration provides the effect of simultaneous exposure of all pixels in a configuration where two pixels share a current source transistor.

[0024] Furthermore, in the first aspect, the node may include first and second downstream nodes, and the pixel block configured with four pixels, including a first pixel and a second pixel, may include short-circuit transistors for opening and closing the path between the first and second downstream nodes, first, second, third, and fourth capacitor elements, fifth, sixth, seventh, and eighth capacitor elements, and a selection unit. The selection unit includes a first selection circuit with the first and second selection transistors, a second selection circuit with the third and fourth selection transistors, a third selection circuit connecting one of the fifth and sixth capacitor elements to the second downstream node, and a fourth selection circuit connecting one of the seventh and eighth capacitor elements to the second downstream node. Therefore, this configuration provides the effect of short-circuiting the first and second downstream nodes.

[0025] Furthermore, in the first aspect, in a predetermined non-additive mode, the short-circuit transistor can be in an on state, and in the non-additive mode, the selection unit can execute control in a predetermined sequence to sequentially connect each of the first and second capacitor elements to the first subsequent node, to sequentially connect each of the third and fourth capacitor elements to the first subsequent node, to sequentially connect each of the fifth and sixth capacitor elements to the second subsequent node, and to sequentially connect each of the seventh and eighth capacitor elements to the second subsequent node. Therefore, this configuration provides the effect of sequentially reading the reset level and signal level of each of the four pixels.

[0026] Furthermore, in the first aspect, in the predetermined addition mode, the short-circuit transistor can be in a closed state, and in the addition mode, the selection unit can sequentially execute control to connect one of the first and second capacitor elements and one of the third and fourth capacitor elements to the first downstream node while simultaneously connecting one of the fifth and sixth capacitor elements and one of the seventh and eighth capacitor elements to the second downstream node, and execute control to connect the other of the first and second capacitor elements and the other of the third and fourth capacitor elements to the first downstream node while simultaneously connecting the other of the fifth and sixth capacitor elements and the other of the seventh and eighth capacitor elements to the second downstream node. Therefore, this configuration provides the effect of adding four pixels in pixel addition mode.

[0027] Furthermore, a second aspect of this technology is an imaging device comprising: a first pixel, wherein a first selection transistor is configured at a specific relative position, and a second selection transistor is configured at a different relative position; the first selection transistor turns on and off a path between a first capacitor element and a predetermined node for maintaining a predetermined reset level; the second selection transistor turns on and off a path between a second capacitor element and the node for maintaining a signal level corresponding to an exposure amount; a second pixel, wherein a third selection transistor is configured at a specific relative position, and a fourth selection transistor is configured at a different relative position; the third selection transistor turns on and off a path between a third capacitor element and a predetermined node for maintaining a predetermined reset level; the fourth selection transistor turns on and off a path between a fourth capacitor element and the node for maintaining a signal level corresponding to an exposure amount; and a signal processing circuit that sequentially converts the reset level and the signal level into digital signals. Therefore, this configuration provides the effect of improving the image quality of images captured by the imaging device. Attached Figure Description

[0028] Figure 1 This is a block diagram illustrating an example configuration of an imaging apparatus according to a first embodiment of the present technology.

[0029] Figure 2 This is a block diagram illustrating an example of the configuration of a solid-state imaging element in the first embodiment of the present technology.

[0030] Figure 3 This is a circuit diagram illustrating an example of pixel configuration in the first embodiment of the present technology.

[0031] Figure 4 This illustrates the first embodiment of the present technology with... Figure 3 A circuit diagram illustrating an example of a pixel being composed of adjacent pixels.

[0032] Figure 5This is a circuit diagram illustrating an example of the connection of elements between two adjacent pixels in the first embodiment of this technology.

[0033] Figure 6 This is a diagram illustrating an example of the layout of selection transistors within a pixel in a first embodiment of the present technology.

[0034] Figure 7 This is a diagram of an example of a pixel array unit in the first embodiment of this technology.

[0035] Figure 8 This is a block diagram illustrating an example of the configuration of a column signal processing circuit in the first embodiment of this technology.

[0036] Figure 9 This is a timing diagram illustrating an example of global shutter operation in a first embodiment of the present technology.

[0037] Figure 10 This is a timing diagram illustrating an example of a pixel readout operation in a first embodiment of the present technology.

[0038] Figure 11 This is a circuit diagram showing an example of the pixel configuration in the comparative example.

[0039] Figure 12 This is a diagram illustrating an example of the state of a pixel when reading out the reset level and when initializing a subsequent node, according to a first embodiment of the present technology.

[0040] Figure 13 This is a diagram illustrating an example of the state of a pixel at the readout signal level in a first embodiment of the present technology.

[0041] Figure 14 This is a diagram illustrating an example of image data in a first embodiment of the present technology.

[0042] Figure 15 This is a graph illustrating an example of the average value and standard deviation within a region in the first embodiment of this technology.

[0043] Figure 16 This is a diagram illustrating the effect of PLS ​​in the first embodiment of this technology.

[0044] Figure 17 This is a diagram illustrating an example of a pixel array unit in a first variation of a first embodiment of the present technology.

[0045] Figure 18 This is a diagram illustrating another example of a pixel array unit in a first variation of a first embodiment of the present technology.

[0046] Figure 19 This is a diagram illustrating an example of a pixel array unit in a second variation of a first embodiment of the present technology.

[0047] Figure 20 This is a circuit diagram illustrating an example of the configuration of a pixel block in the second embodiment of the present technology.

[0048] Figure 21 This is a circuit diagram illustrating an example of the configuration of the pre-amplifier circuit and the selection circuit in the second embodiment of this technology.

[0049] Figure 22 This is a timing diagram illustrating an example of global shutter operation in a second embodiment of the present technology.

[0050] Figure 23 This is a timing diagram illustrating an example of the readout operation of the first pixel within a pixel block in a second embodiment of the present technology.

[0051] Figure 24 This is a timing diagram illustrating an example of the readout operation of a second pixel within a pixel block in a second embodiment of the present technology.

[0052] Figure 25 This is a flowchart illustrating an example of the operation of a solid-state imaging element in a second embodiment of the present technology.

[0053] Figure 26 This is a timing diagram illustrating an example of the readout operation of the reset level and signal level in a first variation of the second embodiment of the present technology.

[0054] Figure 27 This is a diagram illustrating an example of the stacked structure of a solid-state imaging element in a second variation of the second embodiment of the present technology.

[0055] Figure 28 This is a circuit diagram illustrating a configuration example of a pixel block in a second variation of the second embodiment of the present technology.

[0056] Figure 29 This is a diagram illustrating an example of the stacked structure of a solid-state imaging element in a third variation of the second embodiment of the present technology.

[0057] Figure 30 This is a plan view illustrating an example of the configuration of a pixel array unit in the third embodiment of the present technology.

[0058] Figure 31 This is a circuit diagram illustrating an example of the configuration of a pixel block in the third embodiment of the present technology.

[0059] Figure 32 This is a circuit diagram illustrating an example of the configuration of the pre-amplifier circuit and the selection circuit in the third embodiment of this technology.

[0060] Figure 33This is a timing diagram illustrating an example of the readout operation of the first and second pixels within a pixel block in a third embodiment of the present technology.

[0061] Figure 34 This is a timing diagram illustrating an example of the readout operation of the third and fourth pixels within a pixel block in a third embodiment of the present technology.

[0062] Figure 35 This is a timing diagram illustrating an example of a readout operation in the addition mode of the third embodiment of this technology.

[0063] Figure 36 This is a circuit diagram illustrating an example of the configuration of a pixel block in the fourth embodiment of the present technology.

[0064] Figure 37 This is a timing diagram illustrating an example of global shutter operation in the fourth embodiment of the present technology.

[0065] Figure 38 This is a timing diagram illustrating an example of control immediately following the end of exposure in the fourth embodiment of this technology.

[0066] Figure 39 This is a block diagram illustrating a schematic example of the configuration of a vehicle control system.

[0067] Figure 40 This is an explanatory diagram showing an example of the mounting position of the imaging unit. Detailed Implementation

[0068] The following will describe the modes of implementing this technology (hereinafter referred to as implementation schemes). They will be described in the following order.

[0069] 1. First implementation scheme (example of swapping the positions of selection transistors in two adjacent pixels)

[0070] 2. Second Implementation Scheme (Example of maintaining multiple capacitors at reset and signal levels)

[0071] 3. Third implementation scheme (example of keeping multiple capacitors at reset and signal levels and short-circuiting subsequent nodes)

[0072] 4. Fourth Implementation Scheme (Example of maintaining multiple capacitors at reset and signal levels and sharing a current source)

[0073] 5. Examples of applications of moving bodies

[0074] <1. First Implementation Plan>

[0075] [Example of Imaging Device Configuration]

[0076] Figure 1This is a block diagram illustrating an example configuration of the imaging apparatus 100 according to the first embodiment of the present technology. The imaging apparatus 100 is a device for capturing image data and includes an imaging lens 110, a solid-state imaging element 200, a recording unit 120, and an imaging control unit 130. As the imaging apparatus 100, a digital camera and an electronic device with imaging capabilities (smartphone, personal computer, etc.) are assumed.

[0077] The solid-state imaging element 200 captures image data under the control of the imaging control unit 130. The solid-state imaging element 200 supplies the image data to the recording unit 120 via signal line 209.

[0078] Imaging lens 110 focuses and directs light to solid-state imaging element 200. Imaging control unit 130 controls solid-state imaging element 200 to capture image data. For example, imaging control unit 130 supplies imaging control signals, including vertical synchronization signal VSYNC, to solid-state imaging element 200 via signal line 139. Recording unit 120 records image data.

[0079] Here, the vertical synchronization signal VSYNC is a signal that indicates the timing of imaging, and a periodic signal with a constant frequency (e.g., 60 Hz) is used as the vertical synchronization signal VSYNC.

[0080] Note that although the imaging device 100 records image data, the image data can be transmitted to an external location. In this case, an external interface for transmitting image data is further provided. Alternatively, the imaging device 100 can further display the image data. In this case, a display unit is further provided.

[0081] [Example of solid-state imaging element configuration]

[0082] Figure 2 This is a block diagram illustrating an example configuration of a solid-state imaging element 200 according to a first embodiment of the present invention. The solid-state imaging element 200 includes a vertical scanning circuit 211, a pixel array unit 220, a timing control circuit 212, a digital-to-analog converter (DAC) 213, a load MOS circuit block 250, and a column signal processing circuit 260. In the pixel array unit 220, multiple pixels, such as pixels 301 and 302, are configured in a two-dimensional lattice. Furthermore, each circuit within the solid-state imaging element 200 is housed, for example, in a single semiconductor chip.

[0083] The timing control circuit 212 controls the operating timing of each of the vertical scanning circuit 211, DAC 213 and column signal processing circuit 260 in sync with the vertical synchronization signal VSYNC from the imaging control unit 130.

[0084] DAC 213 generates a sawtooth-shaped ramp signal through digital-to-analog (DA) conversion. DAC 213 supplies the generated ramp signal to column signal processing circuit 260.

[0085] The vertical scanning circuit 211 sequentially selects and drives rows and outputs analog pixel signals. Pixels perform photoelectric conversion on incident light to generate analog pixel signals. These pixel signals are then supplied to the column signal processing circuit 260 via the load MOS circuit block 250.

[0086] In the load MOS circuit block 250, MOS transistors that provide constant current are set for each column.

[0087] The column signal processing circuit 260 performs signal processing such as AD conversion and correlated double sampling (CDS) processing on each column of pixel signals. The column signal processing circuit 260 supplies image data including the processed signals to the recording unit 120. Note that the column signal processing circuit 260 is an example of the signal processing circuit described in the claims.

[0088] [Example of pixel composition]

[0089] Figure 3 This is a circuit diagram illustrating an example configuration of pixel 301 in the first embodiment of the present invention. Pixel 301 includes a front-end circuit 310, capacitor elements 331 and 332, a selection circuit 350, a rear-end reset transistor 361, and a rear-end circuit 370. For example, capacitors with a metal-insulator-metal (MIM) structure are used as capacitor elements 331 and 332. Note that capacitor elements 331 and 332 are examples of the first and second capacitor elements described in the claims.

[0090] The preamplifier circuit 310 sequentially generates a reset level and a signal level, and maintains the capacitor elements 331 and 332 at the reset level and the signal level. The preamplifier circuit 310 includes a photoelectric conversion element 311, a transmission transistor 312, a floating diffuser (FD) reset transistor 313, an FD 314, a preamplifier transistor 315, and a current source transistor 316.

[0091] The photoelectric conversion element 311 generates charge through photoelectric conversion. The transfer transistor 312 transfers the charge from the photoelectric conversion element 311 to the FD 314 according to the transfer signal trg from the vertical scanning circuit 211.

[0092] The FD reset transistor 313 extracts charge from the FD 314 to initialize it according to the FD reset signal rst from the vertical scan circuit 211. The FD 314 accumulates charge and generates a voltage corresponding to the amount of charge.

[0093] The preamplifier transistor 315 amplifies the voltage level of FD 314 and outputs the amplified voltage to the preamplifier node 330.

[0094] The drains of the FD reset transistor 313 and the preamplifier transistor 315 are respectively connected to the power supply voltage VDD. The current source transistor 316 is connected to the source of the preamplifier transistor 315. The current source transistor 316 supplies current id1 under the control of the vertical scanning circuit 211.

[0095] One end of each of capacitor elements 331 and 332 is connected to the preceding node 330, and the other end of each is connected to the selection circuit 350.

[0096] Selection circuit 350 includes selection transistors 351 and 352. Selection transistor 351 opens and closes the path between capacitor element 331 and subsequent node 360 ​​according to the selection signal Φr from vertical scan circuit 211. Selection transistor 352 opens and closes the path between capacitor element 332 and subsequent node 360 ​​according to the selection signal Φs from vertical scan circuit 211.

[0097] The post-stage reset transistor 361 initializes the level of the post-stage node 360 ​​to a predetermined potential Vreg based on the post-stage reset signal rstb from the vertical scan circuit 211. A potential different from the power supply voltage VDD (e.g., a potential lower than VDD) is set to potential Vreg.

[0098] The post-stage circuit 370 includes a post-stage amplification transistor 371 and a post-stage selection transistor 372. The post-stage amplification transistor 371 amplifies the level of the post-stage node 360. The post-stage selection transistor 372 outputs the signal amplified by the post-stage amplification transistor 371 as a pixel signal to the vertical signal line 308 based on the post-stage selection signal selb from the vertical scanning circuit 211.

[0099] Note that, for example, n-channel metal-oxide-semiconductor (nMOS) transistors are used as various transistors (transmission transistor 312, etc.) within pixel 301.

[0100] Figure 4 This illustrates the first embodiment of the present technology with... Figure 3 A circuit diagram illustrating an example configuration of pixel 302 adjacent to pixel 301. Pixel 302 includes a front-end circuit 320, capacitor elements 336 and 337, a selection circuit 355, a rear-end reset transistor 366, and a rear-end circuit 380. For example, capacitors with a MIM structure are used as capacitor elements 336 and 337. Note that capacitor elements 336 and 337 are examples of the third and fourth capacitor elements described in the claims.

[0101] The preamplifier circuit 320 sequentially generates a reset level and a signal level, and maintains the reset level and the signal level at capacitors 336 and 337. The preamplifier circuit 320 includes a photoelectric conversion element 321, a transmission transistor 322, an FD reset transistor 323, an FD transistor 324, a preamplifier transistor 325, and a current source transistor 326. The circuit configuration of the preamplifier circuit 320 is similar to that of the preamplifier circuit 310.

[0102] One end of each of capacitors 336 and 337 is connected to the preceding node 335, and the other end of each is connected to the selection circuit 355.

[0103] Selection circuit 355 includes selection transistors 356 and 357. The circuit configuration of selection circuit 355 is similar to that of selection circuit 350.

[0104] The post-stage reset transistor 366 initializes the level of the post-stage node 365 to a predetermined potential Vreg based on the post-stage reset signal rstb from the vertical scan circuit 211.

[0105] The post-amplification circuit 380 includes a post-amplification transistor 381 and a post-selection transistor 382. The circuit configuration of the post-amplification circuit 380 is similar to that of the post-amplification circuit 370. The pixel signal of pixel 302 is output to the vertical signal line 309.

[0106] At the start of exposure, the vertical scan circuit 211 supplies a high-level FD reset signal rst and a high-level transmission signal trg to all rows. This initializes the photoelectric conversion elements (311 or 321). This control is referred to below as "PD reset".

[0107] Then, immediately before the end of the exposure, the vertical scan circuit 211 supplies a high-level FD reset signal rst during the pulse period while setting all subsequent reset signals rstb and selection signals Φr to a high level. Therefore, FDs 314 and 324, and the levels corresponding to the levels of FDs 314 and 324 at this time, are held in capacitors 331 and 336. This control is referred to below as "FD reset".

[0108] The voltage levels of FD 314 and 324 during FD reset, and the corresponding voltage levels (holding voltage levels of capacitors 331 and 336 and the voltage levels of the vertical signal lines) are collectively referred to below as "P phase" or "reset voltage".

[0109] At the end of the exposure, the vertical scan circuit 211 supplies a high-level transmission signal trg during the pulse period while setting all subsequent stage reset signals rstb and selection signals Φs to high levels. Therefore, signal charge corresponding to the exposure amount is transferred to FDs 314 and 324, and the levels corresponding to the current levels of FDs 314 and 324 are held in capacitors 332 and 337.

[0110] The levels of FD 314 and 324 during signal charge transmission, and the corresponding levels (the holding levels of capacitors 332 and 337 and the level of the vertical signal line) are collectively referred to below as "D phase" or "signal level".

[0111] Exposure control that starts and ends exposure simultaneously for all pixels in this manner is called global shutter mode. With this exposure control, the pre-amplifier circuits 310 and 320 for all pixels sequentially generate reset and signal levels. The reset level is held in capacitors 331 and 336, and the signal level is held in capacitors 332 and 337.

[0112] After exposure, the vertical scan circuit 211 sequentially selects rows and sequentially outputs the reset level and signal level for that row. When outputting the reset level, the vertical scan circuit 211 sets the FD reset signal rst and the subsequent selection signal selb of the selected row to high levels while simultaneously supplying a high-level selection signal Φr for a predetermined period. Therefore, capacitors 331 and 336 are connected to subsequent nodes 360 and 365, and the reset level is read out.

[0113] After reading the reset level, the vertical scan circuit 211 supplies a high-level subsequent reset signal rstb during the pulse period while keeping the FD reset signal rst of the selected row and the subsequent selection signal selb high. At this time, the selection transistors 351, 352, 356, and 357 are in the off state, and the capacitors 331, 332, 336, and 337 are disconnected from the subsequent nodes 360 and 365.

[0114] After the initialization of the downstream nodes 360 and 365, the vertical scan circuit 211 supplies a high-level selection signal Φs for a predetermined period while the FD reset signal rst and the downstream selection signal selb for the selected row are held high. Therefore, capacitors 332 and 337 are connected to the downstream nodes 360 and 365, and the signal levels are read out.

[0115] Through the above-described readout control, the selection circuit 350 of the selected row sequentially executes control to connect capacitor element 331 to the subsequent node 360, executes control to disconnect capacitor elements 331 and 332 from the subsequent node 360, and executes control to connect capacitor element 332 to the subsequent node 360.

[0116] Furthermore, when capacitors 331, 332, 336, and 337 are disconnected from subsequent nodes 360 and 365, the subsequent reset transistor 361 of the selected row initializes the levels of subsequent nodes 360 and 365. Additionally, subsequent circuits 370 and 380 of the selected row sequentially read the reset level and signal level from capacitors 331 and 332 (optionally, capacitors 336 and 337) via subsequent nodes 360 and 365, and output them to vertical signal line 309.

[0117] Note that the circuit configuration of each of pixels 301 and 302 is not limited to... Figure 3 and Figure 4 The circuit configuration is illustrated in the example. As long as the pixel is equipped with a pair of capacitors and a pair of select transistors, the select transistors can open and close the path between the capacitors and the node. Figure 3 and Figure 4 Other than pixels. For example, pixels described in Non-Patent Document 1 may be used.

[0118] Figure 5 This is a circuit diagram illustrating an example of the connection between elements of two adjacent pixels in the first embodiment of this technology. In the pixel array unit 220, multiple signal lines are wired for transmitting control signals from the vertical scanning circuit 211 along the horizontal direction. The row-by-row transmission includes six control signals: a transmission signal trg, an FD reset signal rst, a selection signal Φr, a selection signal Φs, a subsequent reset signal rstb, and a subsequent selection signal selb. Therefore, for each row, six signal lines are wired in the horizontal direction. Among these, the signal line transmitting the selection signal Φr is selection line 223, and the signal line transmitting the selection signal Φs is selection line 224.

[0119] In the diagram, the selection transistors located on the upper and lower sides of pixel 301 function in the opposite way to the selection transistors located on the upper and lower sides of pixel 302. This configuration can be easily achieved by reversing the selection lines connecting the destinations of the various selection transistors on the upper and lower sides of pixel 302 with the selection lines of pixel 301.

[0120] For example, in pixel 301, the selection transistor 351 disposed on the upper side is connected to the reset-side selection line 223, and the selection transistor 352 disposed on the lower side is connected to the signal-side selection line 224. On the other hand, in pixel 302, the selection transistor 357 disposed on the upper side is connected to the signal-side selection line 224, and the selection transistor 356 disposed on the lower side is connected to the reset-side selection line 223.

[0121] Here, when the column signal processing circuit 260 performs readout row by row after exposure using a global shutter method, each pixel within a row needs to retain charge for a period from the end of exposure to readout. If the charge retention period is long, there is a possibility of noise charge being generated at the pn junctions of selection transistors 351 and 352 due to photoelectric conversion of stray light incident during this period. In the figure, sector markers indicate pn junctions that generate noise charge.

[0122] The noise charges generated in the selection transistors 351 and 352 within pixel 301 are represented by p1 and p2, respectively, and the capacitance value of each of the capacitor elements 331 and 332 is represented by C. In this case, the noise level Δ of pixel 301 after CDS processing is represented by the following formula.

[0123] Δ = (q1) / C - (q2) / C (Equation 1)

[0124] Furthermore, the noise charges generated in the selection transistors 356 and 357 within pixel 302 are represented by p1' and p2', respectively, and the capacitance value of each of the capacitor elements 336 and 337 is represented by C. In this case, the noise level Δ' of pixel 302 after CDS processing is represented by the following formula.

[0125] Δ' = (q1') / C - (q2') / C (Equation 2)

[0126] Due to differences in the layout of the junction pn between the selection transistors 351 and 352 within the pixel, or differences in the amount of stray light at the pn junction, q1 and q2 may not necessarily be identical. As illustrated in Equations 1 and 2, residual components caused by stray light still exist even after CDS processing. This residual component leads to degradation of the PLS. The image quality of the image data may be degraded due to the degradation of the PLS.

[0127] Therefore, as described above, in adjacent pixels 301 and 302, the positions of the reset-side selection transistors (351 and 356) and the signal-side selection transistors (352 and 357) are reversed. Using this arrangement, a correlation is established for the noise charge of pixels 301 and 302, expressed by the following formula.

[0128] Equation 3: q1≈q2

[0129] q2≈q1' Equation 4

[0130] By substituting equations 3 and 4 into equation 2, we can obtain the following equation.

[0131] Δ' ≈ (q2) / C - (q1) / C = -Δ Equation 5

[0132] As illustrated in Equation 5, the absolute values ​​of the noise caused by stray light from adjacent pixels 301 and 302 are substantially the same, and their signs are opposite.

[0133] Figure 6 This is a diagram illustrating an example layout of the selection transistors within a pixel according to a first embodiment of the present technology. It is assumed that in each pixel, the horizontal direction is the x-direction and the vertical direction is the y-direction. Furthermore, the position of the transistor within the pixel is represented by its relative position to a predetermined reference position of that pixel (e.g., the top-left vertex).

[0134] In addition, the gray areas in the diagram represent metal wiring (select lines 223 and 224, etc.). Cross marks indicate the locations of vias that connect metal wiring to other metal wiring or transistors.

[0135] In pixel 301, the selection transistor 351 connected to the reset-side selection line 223 is configured at a relative position (x1, y1) relative to the reference position x1 in the horizontal direction and y1 in the vertical direction. The selection transistor 352 connected to the signal-side selection line 224 is configured at a relative position (x2, y2).

[0136] On the other hand, in pixel 302, the selection transistor 356 connected to the reset-side selection line 223 is configured at a relative position (x2, y2). The selection transistor connected to the signal-side selection line 224 is configured at a relative position (x1, y1).

[0137] As shown in the figure, in two adjacent pixels, the configuration of the reset-side selection transistors (351 and 356) is reversed compared to the configuration of the signal-side selection transistors (352 and 357). Therefore, the correlations of Equations 3 and 4 are established for the noise charges q1, q2, q1', and q2'.

[0138] Note that pixels 301 and 302 are examples of the first and second pixels described in the claims. Selector transistor 351 is an example of the first selector transistor described in the claims, and selector transistor 352 is an example of the second selector transistor described in the claims. Selector transistor 356 is an example of the third selector transistor described in the claims, and selector transistor 357 is an example of the fourth selector transistor described in the claims.

[0139] Figure 7 This is a diagram illustrating an example of the pixel array unit 220 in the first embodiment of this technology. In the diagram, white squares indicate the locations of reset-side selection transistors (351 and 356). Black squares indicate the locations of signal-side selection transistors (352 and 357). Furthermore, it is assumed that no color filter is provided in each pixel. Therefore, the image data is a monochrome image.

[0140] As shown in the figure, pixels 301 and 302 are arranged adjacent to each other in the row direction. Furthermore, in the row direction, pixels with a similar layout to pixel 301 and pixels with a similar layout to pixel 302 are arranged alternately. Similarly, in the column direction, pixels with a similar layout to pixel 301 and pixels with a similar layout to pixel 302 are arranged alternately. With this configuration, the sign of the generated noise can be reversed in any of the two adjacent pixels. Therefore, when observing the entire image data with these pixels configured, the noise of two adjacent pixels cancels each other out, and the noise caused by stray light becomes less noticeable. Thus, image quality degradation due to PLS degradation can be suppressed.

[0141] [Example of signal processing circuit configuration]

[0142] Figure 8 This is a block diagram illustrating an example configuration of the column signal processing circuit 260 in the first embodiment of the present technology.

[0143] In the load MOS circuit block 250, the vertical signal lines 309 are wired for each column. With a column number of I (I being an integer), I vertical signal lines 309 are wired. Furthermore, a load MOS transistor 251 supplying a constant current id2 is connected to each vertical signal line 309.

[0144] The column signal processing circuit 260 includes multiple ADCs 261 and digital signal processing units 262. Each ADC 261 is configured for each column. With I columns, I ADCs 261 are configured.

[0145] ADC 261 uses the ramp signal Rmp from DAC 213 to convert the analog pixel signal from the corresponding column into a digital signal. ADC 261 supplies the digital signal to digital signal processing unit 262. For example, a single-slope ADC including a comparator and a counter is configured as ADC 261.

[0146] The digital signal processing unit 262 performs predetermined signal processing, such as CDS processing, on each digital signal in each column. The digital signal processing unit 262 supplies image data including the processed digital signals to the recording unit 120.

[0147] [Example of solid-state imaging element operation]

[0148] Figure 9 This is a timing diagram illustrating an example of global shutter operation in a first embodiment of the present technology. The vertical scan circuit 211 supplies a high-level FD reset signal rst and a high-level transmission signal trg to all rows (in other words, all pixels) during the period from timing T0 immediately before the start of exposure to timing T1 after the pulse period has elapsed. Therefore, all pixels are reset by the PD, and exposure begins simultaneously in all rows.

[0149] Here, rst_[n] and trg_[n] in the diagram represent the signal to the nth pixel in the N rows. N is an integer indicating the total number of rows with 300 pixel blocks, and n is an integer from 1 to N.

[0150] At timing T2, immediately before the end of the exposure period, the vertical scan circuit 211 supplies a high-level FD reset signal rst during the pulse period while simultaneously setting the subsequent reset signal rstb and selection signal Φr to high levels for all rows. Therefore, all pixels are FD reset, and the reset level is sampled and held. Here, rstb_[n] and Φr_[n] in the figure represent the signals up to the nth row of pixels.

[0151] At timing T3, following timing T2, the vertical scan circuit 211 returns the selection signal Φr to a low level.

[0152] At the end of exposure T4, the vertical scan circuit 211 supplies a high-level transmission signal trg during the pulse period while simultaneously setting the subsequent reset signal rstb and selection signal Φs to high levels for all rows. Therefore, the signal level is sampled and held. Furthermore, in the figure, Φs_[n] represents the signal up to the pixel in the nth row.

[0153] At timing T5, following timing T4, the vertical scan circuit 211 returns the selection signal Φs to a low level.

[0154] Figure 10 This is a timing diagram illustrating an example of the pixel readout operation in the first embodiment of this technology. During the readout period of the nth row after timing T10, the vertical scan circuit 211 sets the FD reset signal rst and the subsequent selection signal selb of the nth row to a high level. Furthermore, at timing T10, the subsequent reset signal rstb of all rows is controlled to a low level. Here, selb_[n] in the diagram represents the signal to the pixel in the nth row.

[0155] During the period from timing T11 to timing T12, immediately following timing T10, the vertical scan circuit 211 supplies a high-level selection signal Φr to the nth row. The potentials of subsequent nodes 360 and 365 become reset levels. This reset level is then converted to an analog-to-digital converter by ADC 261.

[0156] The vertical scanning circuit 211 supplies a high-level subsequent reset signal rstb during the pulse period starting from timing T13 immediately following timing T12. Therefore, in the case of parasitic capacitance in subsequent nodes 360, the history of previous signals retained in parasitic capacitance can be eliminated.

[0157] During the period from timing T14 to timing T15 immediately following the initialization of subsequent nodes 360, the vertical scan circuit 211 supplies a high-level selection signal Φs to the nth row. The potentials of subsequent nodes 360 and 365 become the signal level Vsig. This signal level is converted by ADC 261. The difference between the reset level Vrst and the signal level Vsig corresponds to the net signal level from which the reset noise and offset noise of the FD have been removed.

[0158] Note that the solid-state imaging element 200 reads out the signal level after the reset level, but is not limited to this order. The solid-state imaging element 200 may also read out the reset level after the signal level. In this case, the vertical scan circuit 211 supplies a high-level selection signal Φr after the high-level selection signal Φs. Furthermore, in this case, the slope of the ramp signal needs to be reversed.

[0159] Figure 11 This is a circuit diagram illustrating a pixel configuration example in the comparative example. In this comparative example, the selection circuit 350 is not provided, and a transmission transistor is inserted between the front-end node 330 and the front-end circuit. Furthermore, capacitors C1 and C2 are inserted instead of capacitors 331 and 332. Capacitor C1 is inserted between the front-end node 330 and the ground terminal, and capacitor C2 is inserted between the front-end node 330 and the rear-end node 360.

[0160] The exposure control and readout control of the pixels in this comparative example are described, for example, in "Jae-kyu Lee, et al., A 2.1e-Temporal Noise and -105dB Parasitic Light Sensitivity Backside-Illuminated 2.3μm-Pixel Voltage-Domain Global Shutter CMOS Image Sensor Using High-Capacity DRAM Capacitor Technology, ISSCC 2020" (Jae-kyu Lee et al., A 2.1e-Temporal Noise and -105dB Parasitic Light Sensitivity Backside-Illuminated 2.3μm-Pixel Voltage-Domain Global Shutter CMOS Image Sensor Using High-Capacity DRAM Capacitor Technology, ISSCC 2020). Figure 5 In section 5.2, in this comparative example, assuming the capacitance of each of capacitors C1 and C2 is C, the level Vn of the kTC noise during exposure and readout is expressed by the following formula.

[0161] Vn = (3*kT / C) 1 / 2 Formula 6

[0162] In the above formula, k is the Boltzmann constant, with units such as joules per kelvin (J / k). T is the absolute temperature, with units such as kelvin (K). Furthermore, Vn is in units such as volts (V), and C is in units such as farads (F).

[0163] Figure 12 This is a diagram illustrating an example of the state of pixel 301 when reading the reset level and when initializing the subsequent node, according to the first embodiment of this technology. Figure a represents the state of pixel 301 when reading the reset level, and figure b represents the state of pixel 301 when initializing the subsequent node 360. Furthermore, in the figure, for ease of explanation, selection transistor 351, selection transistor 352, and subsequent reset transistor 361 are represented by switch graphic symbols.

[0164] As shown in Figure a, the vertical scanning circuit 211 closes the selection transistor 351 and opens the selection transistor 352 and the subsequent reset transistor 361. Therefore, the reset level of the first pixel is read out via the subsequent circuit 370.

[0165] As shown in Figure b, after reading the reset level, the vertical scan circuit 211 turns on select transistors 351 and 352 and turns off the subsequent reset transistor 361. Therefore, capacitors 331 and 332 are disconnected from the subsequent node 360, and the level of the subsequent node 360 ​​is initialized.

[0166] The parasitic capacitance Cp of the downstream node 360, which is disconnected from capacitor elements 331 and 332 in this way, is assumed to be very small compared to capacitor elements 331 and 332. For example, if the parasitic capacitance Cp is assumed to be several nanofarads (fF), then capacitor elements 331 and 332 are on the order of tens of nanofarads.

[0167] Figure 13 This is a diagram illustrating an example of the state of pixel 301 at the readout signal level in a first embodiment of the present technology.

[0168] After the initialization of the subsequent node 360, the vertical scan circuit 211 closes the selection transistor 352 and opens the selection transistor 351 and the subsequent reset transistor 361. Therefore, the signal level of the first pixel is read out via the subsequent circuit 370.

[0169] Here, we consider the kTC noise during pixel exposure. During exposure, kTC noise occurs in each of the reset level sampling and signal level sampling immediately preceding the end of exposure. Assuming the capacitance value of each of capacitors 331 and 332 is C, the level Vn of the kTC noise during exposure is expressed by the following formula.

[0170] Vn = (2*kT / C) 1 / 2 Formula 7

[0171] In addition, such as Figure 12 and Figure 13 As shown, kTC noise occurs during readout because the subsequent reset transistor 361 is driven. However, capacitors 331 and 332 are disconnected when the subsequent reset transistor 361 is driven, and the parasitic capacitance Cp is small at this time. Therefore, the kTC noise during readout can be ignored compared to the kTC noise during exposure. Therefore, the kTC noise during exposure and readout is represented by Equation 7.

[0172] Using Equations 6 and 7, the kTC noise in pixel block 300 where the capacitor is disconnected during readout is less than the kTC noise in the comparative example where the capacitor cannot be disconnected during readout. Therefore, the image quality of the image data can be improved.

[0173] Figure 14 This is a diagram illustrating an example of image data according to a first embodiment of the present technology. In the diagram, each of the image data 501-506 includes a region pls1 surrounded by a dashed line and a region pls2 surrounded by a single-dotted line. Furthermore, it is assumed that in the image data, the region other than regions pls1 and pls2 is designated as region ref.

[0174] In each pixel within region pls1, the configuration of the reset-side selection transistor and the signal-side selection transistor are identical. Furthermore, it is assumed that noise is generated in region pls1.

[0175] In region pls2, the configuration of the reset-side selection transistors is reversed compared to the signal-side selection transistors in two adjacent pixels. In other words, noise countermeasures are implemented through layout. Furthermore, it is assumed that noise similar to that in region pls1 is generated in region pls2.

[0176] In each pixel within the region ref, the configuration of the reset-side selection transistor and the signal-side selection transistor are identical. Furthermore, it is assumed that no noise is generated in the region ref.

[0177] Furthermore, it is assumed that the amount of random noise RN is the same in image data 501–506 when PLS is zero. On the other hand, image data 501–506 differ in terms of PLS, and the PLS / RN value of image data 501 is 1 / 10. The PLS / RN values ​​of the remaining image data 502–506 are 2 / 10, 3 / 10, 4 / 10, 5 / 10, and 6 / 10, respectively.

[0178] Here, the value of PLS ​​is, for example, the ratio of the standard deviation σ and the average value AVE of the output in the region where uniform light with 50% saturation is applied, σ / AVE.

[0179] As shown in the figure, in image data 501 with a relatively small PLS, there is almost no difference between pls1 without noise countermeasures and pls2 with noise countermeasures, and the noise is not obvious.

[0180] However, in image data 502–506, as PLS increases, the noise in pls1 becomes more pronounced, and the difference between pls1 and pls2 becomes significant in image data 506.

[0181] Figure 15 This is a diagram illustrating an example of the average value and standard deviation within a region in the first embodiment of this technology. As described above, no noise is generated in region ref, and no noise countermeasures are taken. In region pls1, noise is generated, and no noise countermeasures are taken. In region pls2, noise is generated, and noise countermeasures are taken through layout.

[0182] Assume the average pixel signal in region ref is REF in LSB conversion, and the standard deviation is 30. Then, the average pixel signal in region pls1 is REF+18, with a standard deviation of 30. On the other hand, the average pixel signal in region pls2 is REF, with a standard deviation of 35.

[0183] Figure 16 This is a diagram illustrating the effect of PLS ​​in the first embodiment of the present technology. As described above, the random noise RN has the same value when the PLS of each of the image data 501 to 505 is zero. On the other hand, the image data 501 to 505 differ in terms of PLS, and the values ​​of PLS ​​relative to RN are "0.1", "0.2", "0.3", "0.4" and "0.5".

[0184] Here, the random noise RN' in the case of PLS ​​is obtained by the following formula.

[0185] RN' = (RN 2 + PLS 2 ) 1 / 2 Formula 8

[0186] Equation 8 is used to calculate “1.0005”, “1.020”, “1.044”, “1.057” and “1.118” for image data 501 to 505 respectively.

[0187] The degree of degradation of random noise caused by the degradation of PLS ​​is expressed by the following formula.

[0188] r = (RN' - RN) × 100 (Equation 9)

[0189] Using Equation 9, the percentages (%) of “0.5”, “2.0”, “4.4”, “7.7” and “11.8” are calculated for image data 501 to 505 respectively.

[0190] As mentioned above, when PLS / RN is approximately 0.2, the increase in random noise is only about 2 percent (%), which is negligible. On the other hand, when PLS / RN is approximately 0.5, the increase in random noise increases to 11.8 percent (%). However, as... Figure 14 As shown, despite the increase in random noise, the region pls2 that takes noise countermeasures is in a state that is difficult to visually distinguish from the region ref that has no noise.

[0191] As described above, according to the first embodiment of this technology, in adjacent pixels 301 and 302, due to the reversed configuration of the two selection transistors, the signs of the noise generated in each pixel are opposite. Therefore, the noise in the image data can be made less noticeable, and the image quality can be improved.

[0192] [First Variation]

[0193] In the first embodiment described above, no color filter is provided in the pixel, but a color filter can be provided for each pixel to capture a color image. The solid-state imaging element 200 in the first variation of the first embodiment differs from the first embodiment in that the pixels are configured in a Bayer array.

[0194] Figure 17 This is a diagram illustrating an example of a pixel array unit 220 in a first variation of a first embodiment of the present technology. In the pixel array unit 220 of the first variation of the first embodiment, a color filter is provided for each pixel. Assume that pixels with a red color filter are R pixels, pixels with a green color filter are Gr pixels or Gb pixels, and pixels with a blue color filter are B pixels. These pixels are configured in a Bayer array.

[0195] Suppose that a 2-row x 2-column area adjacent to a predetermined 2-row x 2-column area 225 is designated as area 226. In area 225, four pixels with a layout similar to pixel 301 are configured. Conversely, in area 226, four pixels with a layout similar to pixel 302 are configured. This also applies to the two adjacent areas outside of areas 225 and 226.

[0196] As shown in the figure, the image quality of a color image can be improved by reversing the configuration of two selection transistors in two adjacent regions.

[0197] Note that, as Figure 18 As shown, any pixel within region 225 (e.g., a Gr pixel) can have a layout similar to pixel 302, and the other three pixels can have a layout similar to pixel 301. In this case, in the adjacent region 226, the pixel with a layout similar to pixel 301 is configured as a Gr pixel, and the pixel with a layout similar to pixel 302 is configured as the other three pixels.

[0198] As described above, in a first variation of the first embodiment of the present technology, the image quality of a color image can be improved because the pixels having a similar layout to pixels 301 and 302 are configured in a Bayer array.

[0199] [Second variation]

[0200] In the first embodiment described above, no color filter is provided in the pixel, but a color filter can be provided for each pixel to capture a color image. The solid-state imaging element 200 in the second variation of the first embodiment differs from that in the first embodiment in that the pixels are configured in a quad Bayer array.

[0201] Figure 19 This is a diagram illustrating an example of a pixel array unit 220 in a second variation of the first embodiment of the present technology. In the pixel array unit 220 of the second variation of the first embodiment, R pixels, Gr pixels, Gb pixels, and B pixels are configured in a quad Bayer array. In the quad Bayer array, four pixels of the same color are arranged in a 2x2 area.

[0202] Assume that a green area with 2 rows x 2 columns, adjacent to the red area 225 (2 rows x 2 columns), is designated as area 226. A pixel with a similar layout to pixel 302 is positioned anywhere within area 225 (e.g., the upper right), and three pixels with a similar layout to pixel 301 are positioned in the remaining positions. Conversely, in the adjacent area 226, a pixel with a similar layout to pixel 301 is positioned in the upper right, and three pixels with a similar layout to pixel 302 are positioned in the remaining positions. This also applies to two adjacent areas outside of areas 225 and 226.

[0203] As described above, in a second variation of the first embodiment of the present technology, the image quality of the color image can be improved because the pixels having a similar layout to pixels 301 and 302 are configured in a four-Bayer array.

[0204] <2. Second Implementation Plan>

[0205] In the first embodiment described above, a post-stage reset transistor and a selection circuit are configured for each pixel; however, this configuration makes it difficult to reduce the circuit size. The solid-state imaging element 200 of the second embodiment differs from the first embodiment in that adjacent pixels share the post-stage reset transistor and the selection circuit.

[0206] Figure 20 This is a circuit diagram illustrating an example of the configuration of pixel block 300 in the second embodiment of the present technology. In the pixel array unit 220 of the second embodiment, a plurality of pixel blocks 300 are configured. Each pixel block 300 is configured with pixels 301 and 302.

[0207] The pixel block 300 includes a front-end circuit block 305, capacitor elements 331, 332, 336 and 337, a selection unit 340, a rear-end reset transistor 361 and a rear-end circuit 370.

[0208] Furthermore, preamplifier circuits 310 and 320 are configured in preamplifier circuit block 305. Selection circuits 350 and 355 are configured in selection unit 340. The postamplifier circuit 370 includes postamplifier amplification transistor 371 and postamplifier selection transistor 372.

[0209] Selection circuit 350 connects one of capacitor elements 331 and 332 to subsequent node 360. Selection circuit 355 connects one of capacitor elements 336 and 337 to subsequent node 360. Note that selection circuit 350 is an example of the first selection circuit described in the claims, and selection circuit 355 is an example of the second selection circuit described in the claims.

[0210] Figure 21 This is a circuit diagram illustrating an example configuration of the preamplifier circuits 310 and 320 and the selection circuits 350 and 355 in the second embodiment of this technology.

[0211] The preamplifier circuit 310 includes a photoelectric conversion element 311, a transmission transistor 312, an FD reset transistor 313, an FD transistor 314, a preamplifier transistor 315, and a current source transistor 316.

[0212] In addition, the preamplifier circuit 320 includes a photoelectric conversion element 321, a transmission transistor 322, an FD reset transistor 323, an FD 324, a preamplifier transistor 325, and a current source transistor 326.

[0213] Photoelectric conversion elements 311 and 321 generate charge through photoelectric conversion. Transfer transistor 312 transfers charge from photoelectric conversion element 311 to FD 314 according to the transfer signal trg1 from the vertical scanning circuit 211. Transfer transistor 322 transfers charge from photoelectric conversion element 321 to FD 324 according to the transfer signal trg2 from the vertical scanning circuit 211.

[0214] Note that photoelectric conversion elements 311 and 321 are examples of the first and second photoelectric conversion elements described in the claims. Note that transmission transistors 312 and 322 are examples of the first and second transmission transistors described in the claims.

[0215] FD reset transistor 313 initializes itself by drawing charge from FD 314 according to the FD reset signal rst1 from the vertical scan circuit 211. FD reset transistor 323 initializes itself by drawing charge from FD 324 according to the FD reset signal rst2 from the vertical scan circuit 211. FDs 314 and 324 accumulate charge and generate a voltage corresponding to the amount of charge.

[0216] Note that FD reset transistors 313 and 323 are examples of the first and second reset transistors described in the claims. FD 314 and 324 are examples of the first and second floating diffusion layers described in the claims.

[0217] Preamplifier transistor 315 amplifies the voltage level of FD 314 and outputs the amplified voltage to preamplifier node 330. Preamplifier transistor 325 amplifies the voltage level of FD 324 and outputs the amplified voltage to preamplifier node 335. Note that preamplifier transistors 315 and 325 are examples of the first and second preamplifier transistors described in the claims.

[0218] The drains of reset transistors 313 and 323, and preamplifier transistors 315 and 325, are connected to the power supply voltage VDD. Current source transistor 316 is connected to the source of preamplifier transistor 315. Current source transistor 316 supplies current id11 under the control of vertical scan circuit 211. Current source transistor 326 is connected to the source of preamplifier transistor 325. Current source transistor 326 supplies current id12 under the control of vertical scan circuit 211.

[0219] Note that current source transistors 316 and 326 are examples of the first and second current source transistors described in the claims.

[0220] One end of each of capacitors 331 and 332 is connected to the preceding node 330, and the other end of each is connected to the selection circuit 350. One end of each of capacitors 336 and 337 is connected to the preceding node 335, and the other end of each is connected to the selection circuit 355.

[0221] Selection circuit 350 includes selection transistors 351 and 352. Selection transistor 351 opens and closes the path between capacitor element 331 and subsequent node 360 ​​according to selection signal Φr1 from vertical scan circuit 211. Selection transistor 352 opens and closes the path between capacitor element 332 and subsequent node 360 ​​according to selection signal Φs1 from vertical scan circuit 211.

[0222] Selection circuit 355 includes selection transistors 356 and 357. Selection transistor 356 opens and closes the path between capacitor element 336 and subsequent node 360 ​​according to selection signal Φr2 from vertical scan circuit 211. Selection transistor 357 opens and closes the path between capacitor element 337 and subsequent node 360 ​​according to selection signal Φs2 from vertical scan circuit 211.

[0223] Note that, for example, nMOS transistors are used as various transistors (transfer transistor 312, etc.) within pixel block 300.

[0224] The circuit described above, including pre-amplifier circuit 310, capacitors 331 and 332, selection circuit 350, post-amplifier reset transistor 361, and post-amplifier circuit 370, serves as one pixel. Furthermore, the circuit described above, including pre-amplifier circuit 320, capacitors 336 and 337, selection circuit 355, post-amplifier reset transistor 361, and post-amplifier circuit 370, also serves as one pixel. Post-amplifier reset transistor 361 and post-amplifier circuit 370 are shared by these two pixels.

[0225] Furthermore, two pixels within pixel block 300 may be arranged, for example, in a column direction. In other words, these two pixels are configured in odd-numbered rows and even-numbered rows. Note that the positional relationship between two pixels within pixel block 300 is not limited to this odd-numbered rows and even-numbered rows. For example, two pixels may be configured in odd-numbered columns and even-numbered columns. Alternatively, one of the two pixels may be configured diagonally above the other pixel.

[0226] Figure 22 This is a timing diagram illustrating an example of global shutter operation in a second embodiment of the present technology. The vertical scan circuit 211 supplies high-level FD reset signals rst1 and rst2 and high-level transmission signals trg1 and trg2 to all rows (in other words, all pixels) during the period from timing T0 immediately before the start of exposure to timing T1 after the pulse period has elapsed. Therefore, all pixels are reset by the PD, and exposure begins simultaneously in all rows.

[0227] Here, rst1_[n], rst2_[n], trg1_[n], and trg2_[n] in the diagram represent signals to the pixel in the nth row of N rows. N is an integer indicating the total number of rows in the pixel block 300, and n is an integer from 1 to N. When two pixels within the pixel block 300 are pixels in an even-numbered row and an odd-numbered row, the nth row of the pixel block 300 includes both the odd-numbered and even-numbered rows.

[0228] At timing T2, immediately before the end of the exposure period, the vertical scan circuit 211 supplies high-level FD reset signals rst1 and rst2 during the pulse period while setting the subsequent reset signal rstb and selection signals Φr1 and Φr2 to high levels for all rows. Therefore, all pixels are FD reset, and the reset level is sampled and held. Here, rstb_[n], Φr1_[n], and Φr2_[n] in the figure represent the signals up to the nth row of pixels.

[0229] At timing T3, following timing T2, the vertical scanning circuit 211 returns the selection signals Φr1 and Φr2 to a low level.

[0230] At the end of exposure T4, the vertical scan circuit 211 supplies high-level transmission signals trg1 and trg2 during the pulse period while setting the subsequent reset signal rstb and selection signals Φs1 and Φs2 to high levels for all rows. Therefore, the signal levels are sampled and held. Furthermore, Φs1_[n] and Φs2_[n] in the figure represent the signals up to the nth row pixel.

[0231] At timing T5, following timing T4, the vertical scan circuit 211 returns the selection signals Φs1 and Φs2 to a low level.

[0232] Figure 23 This is a timing diagram illustrating an example of the readout operation of the first pixel within pixel block 300 in the second embodiment of this technology. During the readout period of the nth row after timing T10, the vertical scan circuit 211 sets the FD reset signals rst1 and rst2 of the nth row and the subsequent selection signal selb to a high level. Furthermore, at timing T10, the subsequent reset signals rstb of all rows are controlled to a low level. Here, selb_[n] in the figure represents the signal to the pixel in the nth row.

[0233] During the period from timing T11 to timing T12, immediately following timing T10, the vertical scan circuit 211 supplies a high-level selection signal Φr1 to the nth row. The potential of the subsequent node 360 ​​becomes the reset level Vrst1. This reset level is then converted by the ADC 261.

[0234] During the pulse period starting from timing T13 immediately following timing T12, the vertical scan circuit 211 supplies a high-level subsequent reset signal rstb to the nth row. Therefore, in the event of parasitic capacitance in the subsequent node 360, the history of previous signals held in the parasitic capacitance can be eliminated.

[0235] During the period from timing T14 to timing T15 immediately following the initialization of the subsequent node 360, the vertical scan circuit 211 supplies a high-level selection signal Φs1 to the nth row. The potential of the subsequent node 360 ​​becomes the signal level Vsig1. This signal level is converted by ADC 261. The difference between the reset level Vrst1 and the signal level Vsig1 corresponds to the net signal level from which the reset noise and offset noise of the FD have been removed.

[0236] Figure 24 This is a timing diagram illustrating an example of the readout operation of the second pixel within pixel block 300 in the second embodiment of the present technology.

[0237] During the pulse period starting from timing T16 immediately following timing T15, the vertical scan circuit 211 supplies a high-level subsequent reset signal rstb to the nth row.

[0238] During the period from timing T17 to timing T18 immediately following the initialization of the subsequent node 360, the vertical scan circuit 211 supplies a high-level selection signal Φr2 to the nth row. The potential of the subsequent node 360 ​​then becomes the reset level Vrst2. This reset level is then converted by the ADC 261.

[0239] During the pulse period starting from timing T19 immediately following timing T18, the vertical scan circuit 211 supplies a high-level subsequent reset signal rstb to the nth row.

[0240] During the period from timing T20 to timing T21 immediately following the initialization of the subsequent node 360, the vertical scan circuit 211 supplies a high-level selection signal Φs2 to the nth row. The potential of the subsequent node 360 ​​then changes to the signal level Vsig2. This signal level is then converted to an analog-to-digital converter (ADC) by ADC 261.

[0241] In addition, at timing T21, the vertical scan circuit 211 returns the FD reset signals rst1 and rst2 of the nth row and the subsequent selection signal selb to a low level.

[0242] like Figure 23 and Figure 24 As shown, high-level selection signals Φr1, Φs1, Φr2, and Φs2 are supplied sequentially. Based on these selection signals, selection unit 340 connects capacitor elements 331, 332, 336, and 337 sequentially to the subsequent node 360. Then, the reset level Vrst1 and signal level Vsig1 of the first pixel and the reset level Vrst2 and signal level Vsig2 of the second pixel within pixel block 300 are read sequentially.

[0243] Figure 25 This is a flowchart illustrating an example of the operation of the solid-state imaging element 200 in the second embodiment of the present technology. For example, operation begins when a predetermined application for capturing image data is performed.

[0244] The vertical scanning circuit 211 exposes all pixels (step S901). Then, the vertical scanning circuit 211 selects the row of pixel block 300 to be read out (step S902). The column signal processing circuit 260 reads the reset level of the first pixel in the pixel block 300 of that row (step S903), and then reads the signal level of that pixel (step S904). Subsequently, the column signal processing circuit 260 reads the reset level of the second pixel (step S905), and then reads the signal level of that pixel (step S906).

[0245] The solid-state imaging element 200 determines whether all rows have been read out (step S907). If not, (step S907: No) the solid-state imaging element 200 repeats step S902 and subsequent steps. On the other hand, if all rows have been read out (step S907: Yes) the solid-state imaging element 200 performs CDS processing, etc., and ends the imaging operation. When multiple image data are captured consecutively, steps S901 to S907 are repeated synchronously with the vertical synchronization signal.

[0246] Note that the first and second variations of the first implementation scheme can also be applied to the second implementation scheme.

[0247] As described above, according to the second embodiment of the present technology, since the two pixels share the subsequent reset transistor 361 and the subsequent circuit 370, the circuit size of the pixel array unit 220 can be reduced compared to the case where they do not share.

[0248] [First Variation]

[0249] In the second embodiment described above, the solid-state imaging element 200 sequentially reads the pixel signal of each of two pixels within the pixel block 300. However, with this configuration, there is a possibility of insufficient readout speed. The solid-state imaging element 200 of the first variation of the second embodiment differs from the second embodiment in that it performs pixel addition.

[0250] Figure 26 This is a timing diagram illustrating an example of the readout operation of the reset level and signal level in a first variation of the second embodiment of the present invention. In the solid-state imaging element 200 of the first variation of the second embodiment, any one of a plurality of modes is set, including a non-additive mode that does not perform pixel addition and an additive mode that performs pixel addition. The global shutter operation and readout operation in the non-additive mode are similar to those in the second embodiment. The global shutter operation in the additive mode is similar to that in the non-additive mode.

[0251] When reading is performed in addition mode, as shown in the figure, at the start time T10 of reading in the nth row, the vertical scan circuit 211 supplies high-level FD reset signals rst1 and rst2 during the pulse period. Furthermore, during the reading period from time T10 to time T15, the vertical scan circuit 211 sets the subsequent stage selection signal selb to a high level.

[0252] During the period from timing T11 to timing T12 immediately following timing T10, the vertical scan circuit 211 supplies high-level selection signals Φr1 and Φs2 to the nth row. Therefore, the potential of the subsequent node 360 ​​becomes the reset level Vrst. The reset level Vrst is a value obtained by adding the reset levels of two pixels within the pixel block 300.

[0253] During the pulse period starting from timing T13 immediately following timing T12, the vertical scan circuit 211 supplies a high-level subsequent reset signal rstb to the nth row.

[0254] During the period from timing T14 to timing T15 immediately following the initialization of the subsequent node 360, the vertical scan circuit 211 supplies high-level selection signals Φr2 and Φs2 to the nth row. Therefore, the potential of the subsequent node 360 ​​becomes the signal level Vsig. The signal level Vsig is a value obtained by adding the signal levels of two pixels within the pixel block 300.

[0255] As shown in the figure, high-level selection signals Φr1 and Φs1 are supplied, and according to these selection signals, selection unit 340 connects capacitor elements 331 and 336 to the subsequent node 360. In other words, capacitor elements 331 and 336 are short-circuited. Therefore, the reset levels of the two pixels are added together. Furthermore, high-level selection signals Φr2 and Φs2 are supplied, and according to these selection signals, selection unit 340 connects capacitor elements 332 and 337 to the subsequent node 360. In other words, capacitor elements 332 and 337 are short-circuited. Therefore, the signal levels of the two pixels are added together. This pixel addition improves sensitivity and readout speed compared to not adding pixels. Furthermore, since the number of rows to be read is reduced by pixel addition, power consumption is reduced.

[0256] Note that the solid-state imaging element 200 reads out the signal level after the reset level, but is not limited to this order, and the reset level can be read out after the signal level.

[0257] Note that the first and second variations of the first embodiment can also be applied to the first variation of the second embodiment.

[0258] As described above, according to the first variation of the second embodiment of this technology, since the selection unit 340 connects capacitor elements 331 and 336 to the subsequent node 360 ​​and capacitor elements 332 and 337 to the subsequent node 360, the respective pixel signals of the two pixels can be added together. Therefore, compared with the case where no addition is performed, sensitivity and readout speed can be improved, and power consumption can be reduced.

[0259] [Second variation]

[0260] In the second embodiment described above, the circuitry within the solid-state imaging element 200 is housed within a single semiconductor chip. However, with this configuration, there is a possibility that components cannot be accommodated within the semiconductor chip when pixels are miniaturized. The solid-state imaging element 200 in the second variation of the second embodiment differs from the second embodiment in that the circuitry within the solid-state imaging element 200 is distributed across two semiconductor chips.

[0261] Figure 27 This is a diagram illustrating an example of the stacked structure of a solid-state imaging element 200 in a second variation of the second embodiment of the present invention. The solid-state imaging element 200 of the second variation of the second embodiment includes a lower pixel chip 202 and an upper pixel chip 201 stacked on the lower pixel chip 202. These chips are electrically connected, for example, by Cu-Cu bonding. Note that in addition to Cu-Cu bonding, connections can also be made via vias or bumps.

[0262] The upper pixel array unit 221 is disposed in the upper pixel chip 201. The lower pixel array unit 222 and the column signal processing circuit 260 are disposed in the lower pixel chip 202. For each pixel in the pixel array unit 220, a portion of the pixel is disposed in the upper pixel array unit 221, and the remainder is disposed in the lower pixel array unit 222.

[0263] In addition, the lower pixel chip 202 also includes a vertical scanning circuit 211, a timing control circuit 212, a DAC 213, and a load MOS circuit block 250. These circuits are omitted in the accompanying drawings.

[0264] Furthermore, the upper pixel chip 201 is manufactured, for example, using a pixel-specific process, and the lower pixel chip 202 is manufactured, for example, using a complementary MOS (CMOS) process. Note that the upper pixel chip 201 is an example of the first chip described in the claims, and the lower pixel chip 202 is an example of the second chip described in the claims.

[0265] Figure 28 This is a circuit diagram illustrating a configuration example of pixel block 300 in a second variation of the second embodiment of the present invention. In pixel block 300, front-end circuit block 305 is disposed in upper pixel chip 201, and other circuits and components (such as capacitors 331 and 332) are disposed in lower pixel chip 202. Note that current source transistors 316 and 326 may be further disposed in lower pixel chip 202. As shown, by dispersing the components within pixel block 300 in the stacked upper pixel chip 201 and lower pixel chip 202, the pixel area can be reduced, and pixel miniaturization is facilitated.

[0266] Note that the first and second variations of the first embodiment can also be applied to the second variation of the second embodiment.

[0267] As described above, according to the second variation of the second embodiment of the present technology, since the circuits and components within the pixel block 300 are distributed in two semiconductor chips, pixel miniaturization is advantageous.

[0268] [Third variation]

[0269] In the second variation of the second embodiment described above, a portion of the pixel block 300 and peripheral circuitry (such as the column signal processing circuitry 260) are disposed in the lower circuit chip 202. However, with this configuration, the area of ​​the circuitry and components on the circuit chip 202 side is larger than the area of ​​the peripheral circuitry on the upper pixel chip 201, and there is a possibility of creating unnecessary space in the upper pixel chip 201 where there is no circuitry or components. The solid-state imaging element 200 of the third variation of the second embodiment differs from the second variation of the second embodiment in that the circuitry within the solid-state imaging element 200 is distributed across three semiconductor chips.

[0270] Figure 29 This is a diagram illustrating an example of the stacked structure of a solid-state imaging element 200 in a third variation of the second embodiment of the present invention. The solid-state imaging element 200 of the third variation of the second embodiment includes an upper pixel chip 201, a lower pixel chip 202, and a circuit chip 203. These chips are stacked and electrically connected, for example, by Cu-Cu bonding. Note that in addition to Cu-Cu bonding, connections can also be made vias or bumps.

[0271] The upper pixel array unit 221 is disposed in the upper pixel chip 201. The lower pixel array unit 222 is disposed in the lower pixel chip 202. For each pixel in the pixel array unit 220, a portion of the pixel is disposed in the upper pixel array unit 221, and the remainder is disposed in the lower pixel array unit 222.

[0272] In addition, circuit chip 203 includes column signal processing circuit 260, vertical scanning circuit 211, timing control circuit 212, DAC 213, and load MOS circuit block 250. Circuits other than column signal processing circuit 260 are omitted in the figure.

[0273] Note that the upper pixel chip 201 is an example of the first chip described in the claims, and the lower pixel chip 202 is an example of the second chip described in the claims. The circuit chip 203 is an example of the third chip described in the claims.

[0274] By employing a three-layer structure as shown in the figure, unnecessary space can be reduced and pixel miniaturization can be further achieved compared to a two-layer structure. Furthermore, the lower pixel chip 202 of the second layer can be manufactured using specialized processes for capacitors and switches.

[0275] Note that the first and second variations of the first embodiment can also be applied to the third variation of the second embodiment.

[0276] As described above, in the third variation of the second embodiment of this technology, since the circuitry within the solid-state imaging element 200 is distributed across three semiconductor chips, the pixels can be further miniaturized compared to the case where the circuitry is distributed across two semiconductor chips.

[0277] <3. Third Implementation Plan>

[0278] In the second embodiment described above, the solid-state imaging element 200 sequentially reads the pixel signal of each of two pixels within the pixel block 300. However, with this configuration, there is a possibility of insufficient readout speed. The solid-state imaging element 200 in the third embodiment differs from the second embodiment in that it performs pixel addition.

[0279] Figure 30 Figure 1 is a plan view illustrating an example configuration of the pixel array unit 220 in the third embodiment of the present technology. Figure 2a is a plan view illustrating an example of the pixel array unit 220 in a Bayer array. Figure 2b is a plan view illustrating an example of the pixel array unit 220 in a quad Bayer array. In the pixel array unit 220 shown in the figures, for example, the layout of the first and second variations of the first embodiment is applicable.

[0280] As shown in Figure a, in the pixel array unit 220 of the second embodiment, red (R), green (G), and blue (B) pixels are arranged in a Bayer array. Among these pixels, the solid-state imaging element 200 can add the pixel signals of R pixel 301 and its adjacent R pixels 302-304. Similarly, for G and B pixels, the solid-state imaging element 200 can add the pixel signals of four adjacent pixels.

[0281] Note that instead of a Bayer array, pixels can be arranged in a quad Bayer array as shown in Figure b. In a quad Bayer array, four pixels of the same color are arranged adjacently in a 2x2 row configuration. Then, focusing on the four R pixels, four B pixels are positioned to the lower right of the four R pixels, and four G pixels are positioned to the right and bottom. Among these pixels, the solid-state imaging element 200 can add the pixel signals of four adjacent pixels of the same color (pixels 301-304, etc.).

[0282] Note that the arrangement of pixels is not limited to a Bayer array or a quad Bayer array. For example, R, G, B, and W (white) pixels can be arranged.

[0283] Figure 31 This is a circuit diagram illustrating an example of the configuration of pixel block 300 in the third embodiment of the present technology. In the pixel block 300 of the third embodiment, four pixels are configured to be added when pixel addition is performed. For example, Figure 30 Pixels 301 to 304 are configured within pixel block 300.

[0284] The pixel block 300 in the third embodiment also includes capacitor elements 431, 432, 436, and 437, a short-circuit transistor 480, a post-stage reset transistor 461, and a post-stage circuit 470. Furthermore, in the third embodiment, the pre-stage circuits 410 and 420 are further configured in the pre-stage circuit block 305, and the selection circuits 450 and 455 are further configured in the selection unit 340. The vertical scan circuit 211 supplies the post-stage reset signal rstb1 to the post-stage reset transistor 361 and the post-stage reset signal rstb2 to the post-stage reset transistor 461.

[0285] The post-amplifier transistor 471 and the post-selection transistor 472 are configured in the post-stage circuit 470. For example, nMOS transistors are used as these transistors. Furthermore, the circuit configuration of the post-reset transistor 461 and the post-stage circuit 470 is similar to that of the post-reset transistor 361 and the post-stage circuit 370. Post-stage circuits 370 and 470 are connected to the same vertical signal line 309. The vertical scan circuit 211 supplies the post-stage selection signal selb1 to the post-stage selection transistor 372 and the post-stage selection signal selb2 to the post-stage selection transistor 472.

[0286] The preamplifier circuit 410 sequentially generates a reset level and a signal level, and maintains capacitor elements 431 and 432 at the reset level and signal level, respectively. The preamplifier circuit 420 sequentially generates a reset level and a signal level, and maintains capacitor elements 436 and 437 at the reset level and signal level, respectively. Note that capacitor elements 431 and 432 are examples of the fifth and sixth capacitor elements described in the claims, and capacitor elements 436 and 437 are examples of the seventh and eighth capacitor elements described in the claims.

[0287] Furthermore, selection circuit 450 connects one of capacitor elements 431 and 432 to subsequent node 460, and selection circuit 455 connects one of capacitor elements 436 and 437 to subsequent node 460. Note that selection circuit 450 is an example of the third selection circuit described in the claims, and selection circuit 455 is an example of the fourth selection circuit described in the claims. Furthermore, subsequent node 360 ​​is an example of the first subsequent node described in the claims, and subsequent node 460 is an example of the second subsequent node described in the claims.

[0288] The short-circuit transistor 480 opens and closes the path between the downstream node 360 ​​and the downstream node 460 according to the short-circuit signal sht from the vertical scanning circuit 211. For example, an nMOS transistor is used as the short-circuit transistor 480.

[0289] Figure 32 This is a circuit diagram illustrating an example configuration of the preamplifier circuits 410 and 420 and the selection circuits 450 and 455 in the third embodiment of this technology.

[0290] The preamplifier circuit 410 includes a photoelectric conversion element 411, a transmission transistor 412, an FD reset transistor 413, an FD 414, a preamplifier transistor 415, and a current source transistor 416. The vertical scanning circuit 211 supplies the transmission signal trg3 and the FD reset signal rst3 to the transmission transistor 412 and the FD reset transistor 413.

[0291] In addition, the preamplifier circuit 420 includes a photoelectric conversion element 421, a transmission transistor 422, an FD reset transistor 423, an FD 424, a preamplifier transistor 425, and a current source transistor 426. The vertical scanning circuit 211 supplies the transmission signal trg4 and the FD reset signal rst4 to the transmission transistor 422 and the FD reset transistor 423.

[0292] Selection circuit 450 includes selection transistors 451 and 452, and selection circuit 455 includes selection transistors 456 and 457. Vertical scanning circuit 211 supplies selection signals Φr3 and Φs3 to selection transistors 451 and 452, and selection signals Φr4 and Φs4 to selection transistors 456 and 457.

[0293] The circuit configurations of the preamplifier circuits 410 and 420 are similar to those of the preamplifier circuits 310 and 320. Furthermore, the circuit configurations of the selection circuits 450 and 455 are similar to those of the selection circuits 350 and 355.

[0294] Figure 33This is a timing diagram illustrating an example of the readout operation of the first and second pixels within pixel block 300 in the third embodiment of the present technology. In the solid-state imaging element 200 of the third embodiment, any one of a plurality of modes is set, including a non-additive mode that does not perform pixel addition and an additive mode that performs pixel addition. The global shutter operation and readout operation in the non-additive mode are similar to those in the second embodiment. The global shutter operation in the additive mode is similar to that in the non-additive mode.

[0295] In non-additive mode, the vertical scan circuit 211 sets the short-circuit signal sht to a low level. Furthermore, at the start of readout of the pixel block 300 in the nth row, the vertical scan circuit 211 sets the FD reset signals rst1 to rst4 to a high level. Additionally, during the period from time T10 to time T18, the vertical scan circuit 211 sets the subsequent stage selection signal selb1 to a high level and sets the subsequent stage selection signal selb2 to a low level.

[0296] Furthermore, the vertical scanning circuit 211 supplies a high-level subsequent reset signal rstb1 during the pulse period from timing T10 to timing T11, and a high-level selection signal Φr1 during the period from timing T11 to timing T12. During this period, the reset level Vrst1 of the first pixel is read out via the vertical signal line 309.

[0297] The vertical scanning circuit 211 supplies a high-level post-stage reset signal rstb1 during the pulse period from timing T12 to timing T13, and a high-level selection signal Φs1 during the period from timing T13 to timing T14. During this period, the signal level Vsig1 of the first pixel is read out via the vertical signal line 309.

[0298] Subsequently, the vertical scanning circuit 211 supplies a high-level post-stage reset signal rstb1 during the pulse period from timing T14 to timing T15, and a high-level selection signal Φr2 during the period from timing T15 to timing T16. During this period, the reset level Vrst2 of the second pixel is read out via the vertical signal line 309.

[0299] The vertical scanning circuit 211 supplies a high-level post-stage reset signal rstb1 during the pulse period from timing T16 to timing T17, and a high-level selection signal Φs2 during the period from timing T17 to timing T18. During this period, the signal level Vsig2 of the second pixel is read out via the vertical signal line 309.

[0300] Figure 34 This is a timing diagram illustrating an example of the readout operation of the third and fourth pixels within pixel block 300 in the third embodiment of the present technology.

[0301] During the period from timing T18 to timing T26, the vertical scan circuit 211 sets the subsequent stage selection signal selb1 to a low level and sets the subsequent stage selection signal selb2 to a high level.

[0302] Furthermore, the vertical scanning circuit 211 supplies a high-level subsequent reset signal rstb2 during the pulse period from timing T18 to timing T19, and a high-level selection signal Φr3 during the period from timing T19 to timing T20. During this period, the reset level Vrst3 of the third pixel is read out via the vertical signal line 309.

[0303] The vertical scanning circuit 211 supplies a high-level post-stage reset signal rstb2 during the pulse period from timing T20 to timing T21, and a high-level selection signal Φs3 during the period from timing T21 to timing T22. During this period, the signal level Vsig3 of the third pixel is read out via the vertical signal line 309.

[0304] Subsequently, the vertical scanning circuit 211 supplies a high-level post-stage reset signal rstb2 during the pulse period from timing T22 to timing T23, and a high-level selection signal Φr4 during the period from timing T23 to timing T24. During this period, the reset level Vrst4 of the fourth pixel is read out via the vertical signal line 309.

[0305] The vertical scanning circuit 211 supplies a high-level post-stage reset signal rstb2 during the pulse period from timing T24 to timing T25, and a high-level selection signal Φs4 during the period from timing T25 to timing T26. During this period, the signal level Vsig4 of the fourth pixel is read out via the vertical signal line 309.

[0306] Furthermore, at the end of the reading of the nth row, T26, the vertical scan circuit 211 sets the FD reset signals rst1 to rst4 to a low level.

[0307] like Figure 33 and Figure 34As shown, in the non-additive mode, the short-circuit transistor 480 is controlled to be in the on state. Furthermore, capacitors 331 and 332 are sequentially connected to the subsequent node 360, and the reset level and signal level of the first pixel are read out sequentially. Capacitors 336 and 337 are sequentially connected to the subsequent node 360, and the reset level and signal level of the second pixel are read out sequentially. Subsequently, capacitors 431 and 432 are sequentially connected to the subsequent node 460, and the reset level and signal level of the third pixel are read out sequentially. Capacitors 436 and 437 are sequentially connected to the subsequent node 460, and the reset level and signal level of the fourth pixel are read out sequentially. In this way, the reset level and signal level of each of the four pixels within the pixel block 300 are read out sequentially.

[0308] Figure 35 This is a timing diagram illustrating an example of readout operation in the addition mode according to the third embodiment of the present technology. In the addition mode, the vertical scan circuit 211 sets the short-circuit signal sht to a high level. From timing T10 to timing T14, which is the readout period of the pixel block 300 in the nth row, the vertical scan circuit 211 sets the FD reset signals rst1 to rst4 and the subsequent selection signals selb1 and selb2 to a high level.

[0309] Furthermore, the vertical scanning circuit 211 supplies high-level subsequent reset signals rstb1 and rstb2 during the pulse period from timing T10 to timing T11, and supplies high-level selection signals Φr1 to Φr4 during the period from timing T11 to timing T12. During this period, the reset level Vrst is read out via the vertical signal line 309. The reset level Vrst is a value obtained by adding the reset levels of the four pixels within the pixel block 300.

[0310] Subsequently, the vertical scanning circuit 211 supplies high-level subsequent reset signals rstb1 and rstb2 during the pulse period from timing T12 to timing T13, and high-level selection signals Φs1 to Φs4 during the period from timing T13 to timing T14. During this period, the signal level Vsig is read out via the vertical signal line 309. The signal level Vsig is a value obtained by adding the signal levels of the four pixels within the pixel block 300.

[0311] Here, in the pixel block 300 of the second embodiment, the four pixels can be added together by increasing the number of pixels in the shared subsequent circuit 370 to four. However, increasing the number of pixels in the shared subsequent circuit 370 has adverse effects. When the number of pixels in the shared subsequent circuit 370 is four, the wiring of the subsequent node 360 ​​extends across four pixels, and the parasitic capacitance of the subsequent node 360 ​​increases. Due to the increase in parasitic capacitance, the signal gain decreases when pixel addition is not performed. This is because when capacitor elements 331 or 332 are connected to the subsequent node 360, the voltage held in capacitor elements 331 and 332 is reduced by the parasitic capacitance. This decrease in gain leads to a decrease in the signal-to-noise (SN) ratio.

[0312] On the other hand, in the third embodiment where the short-circuit transistor 480 is configured, by setting the short-circuit transistor 480 to the on state in the non-addition mode, the number of pixels sharing each of the subsequent circuits 370 and 470 can be two. Therefore, compared to the case where four pixels share the subsequent circuit 370, the increase in parasitic capacitance of the subsequent nodes can be suppressed. With this configuration, the decrease in the SN ratio in the non-addition mode can be suppressed while achieving the addition of more than two pixels.

[0313] Note that in Figure 31 In the pixel block 300 shown, a vertical signal line 309 is shared by subsequent circuits 370 and 470, but this technology is not limited to this configuration. Vertical signal lines 309-1 and 309-2 can be wired, with subsequent circuit 370 connected to vertical signal line 309-1 and subsequent circuit 470 connected to vertical signal line 309-2. In this case, the number of load MOS transistors 251 and ADCs 261 in the subsequent circuits, along with the number of vertical signal lines, needs to be doubled. Conversely, in non-additive mode, one of the two pixels sharing subsequent circuit 370 and one of the two pixels sharing subsequent circuit 470 can be read simultaneously, thus improving readout speed. Furthermore, in additive mode, only one of vertical signal lines 309-1 and 309-2 is used, and the corresponding load MOS transistor 251 is controlled to be in an off state.

[0314] Note that the first to third variations of the second implementation scheme can also be applied to the third implementation scheme.

[0315] As described above, according to the third embodiment of this technology, since the short-circuit transistor 480 short-circuits the subsequent node 360, the pixel block 300 can add the individual pixel signals of the four pixels. Therefore, compared with the case where no addition is performed, sensitivity and readout speed can be improved, and power consumption can be reduced.

[0316] <4. Fourth Implementation Plan>

[0317] In the first embodiment described above, the current source transistors (316 or 326) are configured for each pixel; however, with this configuration, pixel miniaturization may become difficult. The solid-state imaging element 200 of the fourth embodiment differs from the first embodiment in that the current source transistors are shared by multiple pixels.

[0318] Figure 36 This is a circuit diagram illustrating an example of the configuration of pixel block 300 in the fourth embodiment of the present technology. The pixel block 300 of the fourth embodiment differs from that of the second embodiment in that it also includes front-end selection transistors 317 and 327, and does not include a current source transistor 316.

[0319] The preamplifier selection transistor 317 outputs the voltage amplified by the preamplifier transistor 315 to the preamplifier node 338 based on the preamplifier selection signal sel1 from the vertical scanning circuit 211. The preamplifier selection transistor 327 outputs the voltage amplified by the preamplifier transistor 325 to the preamplifier node 338 based on the preamplifier selection signal sel2 from the vertical scanning circuit 211. Furthermore, a current source transistor 326 is connected to the preamplifier node 338.

[0320] Furthermore, one end of each of capacitors 331, 332, 336, and 337 is connected to the preceding node 339, and the other end of each is connected to selection circuits 350 and 355. The preceding node 339 is connected to the preceding node 338.

[0321] Furthermore, the circuits and components within the solid-state imaging element 200 are distributed across the upper pixel chip 201 and the lower pixel chip 202. For example, the front-end circuits 310 and 320 are disposed in the upper pixel chip 201, and the subsequent circuits are configured in the circuit chip 203. Then, the front-end nodes 338 and 339 are connected via Cu-Cu connections or the like.

[0322] In a second embodiment where a current source transistor is configured for each pixel, in the case of using a stacked structure, such as Figure 28 As shown, Cu-Cu connections need to be performed for each pixel. In particular, when capacitor elements 331 with MIM structures, etc., are configured in the circuit chip 203, the chip thickness increases, making it difficult to planarize the surfaces connecting the upper and lower chips, and limiting the spacing of the Cu-Cu connections. For example, although the size of the micropixels in image sensors for mobile applications is micrometers (μm) or larger, the spacing of the Cu-Cu connections is several micrometers (μm). Therefore, miniaturization is difficult in the configuration of current source transistors for each pixel.

[0323] On the other hand, in which the current source transistor 326 is shared by two pixels. Figure 36 In this configuration, the number of Cu-Cu connections can be reduced. Therefore, pixel miniaturization is beneficial. Furthermore, the current during global shutter operation can be reduced. Additionally, the current source transistors 326 are typically cascaded to suppress current fluctuations caused by the channel length modulation effect of the transistors. By sharing the relatively large current source transistors 326, the transistor area can be reduced.

[0324] Note that although the current source transistor 326 is shared by two pixels, the number of pixels sharing the current source transistor is not limited to two, and can be more than three.

[0325] Figure 37 This is a timing diagram illustrating an example of global shutter operation in the fourth embodiment of the present technology. The vertical scanning circuit 211 supplies high-level FD reset signals rst1 and rst2, and high-level transmission signals trg1 and trg2 to all rows during the period from timing T0 immediately before the start of exposure to timing T1 after the pulse period has elapsed. Therefore, all pixels are reset by the PD, and exposure begins simultaneously in all rows.

[0326] During the period from timing T2, immediately preceding the end of exposure, to timing T5, the vertical scan circuit 211 sets the pre-stage selection signal sel1 for all rows to a high level. At timing T3 within this period, the vertical scan circuit 211 simultaneously sets the post-stage reset signal rstb and the selection signal Φr1 for all rows to a high level and supplies a high-level FD reset signal rst1 during the pulse period. Therefore, the first pixel within the pixel block 300 is FD reset, and the reset level is sampled and held.

[0327] At time T4, the vertical scan circuit 211 returns the selection signal Φr1 to a low level. Furthermore, during the period from time T5 to time T8, the vertical scan circuit 211 sets the pre-stage selection signal sel1 for all rows to a low level and sets the pre-stage selection signal sel2 to a high level. During time T6 of this period, the vertical scan circuit 211, while setting the post-stage reset signal rstb and the selection signal Φr2 for all rows to a high level, simultaneously supplies a high-level FD reset signal rst2 during the pulse period. Therefore, the second pixel within the pixel block 300 is FD reset, and the reset level is sampled and held.

[0328] Then, at time T7, the vertical scanning circuit 211 returns all row selection signals Φr2 to a low level, and at time T8 sets the pre-stage selection signal sel2 to a low level and the pre-stage selection signal sel1 to a high level.

[0329] Here, sel1_[n] and sel2_[n] in the figure represent the signals of the pixels up to the nth row.

[0330] As shown in the figure, the vertical scanning circuit 211 sequentially turns off the pre-stage selection transistors 317 and 327 immediately before the end of the exposure. Then, with the pre-stage selection transistor 317 in the closed state, the FD reset transistor 313 performs an FD reset, and with the pre-stage selection transistor 327 in the closed state, the FD reset transistor 323 performs an FD reset.

[0331] Figure 38 This is a timing diagram illustrating an example of control immediately following the end of exposure in the fourth embodiment of the present technology. At the end of exposure T9, the vertical scan circuit 211 supplies high-level transmission signals trg1 and trg2 during the pulse period for all rows.

[0332] Then, during the period from timing T10 to timing T11, the vertical scan circuit 211 is set to a high level for all row selection signals Φs1. Therefore, the signal level of the first pixel within the pixel block 300 is sampled and held.

[0333] At time T12, the vertical scan circuit 211 sets the preamp selection signal sel1 of all rows to low level and sets the preamp selection circuit signal sel2 to high level.

[0334] Then, during the period from timing T13 to timing T14, the vertical scan circuit 211 is set to a high level for all row selection signals Φs2. Therefore, the signal level of the second pixel within the pixel block 300 is sampled and held.

[0335] At timing T15, the vertical scanning circuit 211 returns the pre-stage selection signal sel2 of all rows to a low level.

[0336] As shown in the figure, the vertical scanning circuit 211 sequentially turns off the pre-stage selection transistors 317 and 327 at the end of the exposure. Then, at the end of the exposure, the vertical scanning circuit 211 enables the transfer transistors 312 and 322 to transfer charge, and then sequentially turns off the pre-stage selection transistors 317 and 327.

[0337] Note that the first and second variations of the first embodiment, the first and third variations of the second embodiment, and the third embodiment can be applied to the fourth embodiment.

[0338] As described above, according to the fourth embodiment of this technology, since the current source transistor 326 is shared by two pixels, the number of Cu-Cu connections between chips can be reduced. Therefore, pixel miniaturization is beneficial.

[0339] <5. Examples of applications of moving objects>

[0340] The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein can be implemented as a device installed on various types of mobile bodies such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, unmanned aerial vehicles, ships, robots, etc.

[0341] Figure 39 This is a block diagram illustrating a schematic configuration example of a vehicle control system, which is an example of a mobile body control system applicable to the technology of this disclosure.

[0342] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 39 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a main system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and a comprehensive control unit 12050. Furthermore, as functional components of the comprehensive control unit 12050, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0343] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 is used as a control device such as a drive force generating device for generating drive force for a vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting drive force to the wheels, a steering mechanism for adjusting the vehicle's steering angle, and a braking device for generating braking force for the vehicle.

[0344] The main system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the main system control unit 12020 is used as a control device for keyless entry systems, smart key systems, power windows, or various lights such as headlights, taillights, brake lights, turn signals, or fog lights. In this case, radio waves transmitted from a portable device or signals from various switches, used to replace buttons, can be input to the main system control unit 12020. The main system control unit 12020 receives the input radio waves or signals and controls the vehicle's door locking devices, power windows, lights, etc.

[0345] The exterior information detection unit 12030 detects external information of the vehicle on which the vehicle control system 12000 is installed. For example, the exterior information detection unit 12030 is connected to the imaging unit 12031. The exterior information detection unit 12030 causes the imaging unit 12031 to capture images of the exterior of the vehicle and receives the captured images. Based on the received images, the exterior information detection unit 12030 can perform object detection processing such as people, cars, obstacles, signs, and text on the road, or distance detection processing. For example, the exterior information detection unit 12030 performs image processing on the received images and performs object detection processing or distance detection processing based on the results of the image processing.

[0346] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output an electrical signal as an image or as ranging information. Furthermore, the light received by the imaging unit 12031 can be visible light or invisible light such as infrared light.

[0347] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 for detecting the driver's state. For example, the driver state detection unit 12041 includes a camera that captures images of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level, or determine whether the driver is dozing off.

[0348] For example, the microcomputer 12051 can calculate the control target values ​​for the drive force generating device, steering mechanism, or braking device based on information about the vehicle's interior and exterior obtained by the external information detection unit 12030 or the internal information detection unit 12040, and can output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control to realize the functions of an advanced driver assistance system (ADAS), including collision avoidance or collision mitigation, distance-based tracking, speed maintenance, collision warning, and lane departure warning.

[0349] Furthermore, the microcomputer 12051 can coordinate and control the drive force generating device, steering mechanism, braking device, etc., based on information about the vehicle's surroundings obtained by the external information detection unit 12030 or the internal information detection unit 12040, in order to achieve autonomous driving, where the vehicle drives itself without relying on the driver's operation.

[0350] Furthermore, the microcomputer 12051 can output control commands to the main system control unit 12020 based on information about the exterior of the vehicle obtained by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 controls the headlights according to the position of the vehicle in front or oncoming vehicle detected by the vehicle exterior information detection unit 12030 to perform coordinated control, such as switching the high beams to low beams to prevent glare.

[0351] The sound / image output unit 12052 transmits at least one of sound and image output signals to an output device capable of visually or audibly informing vehicle occupants or the outside of the vehicle. Figure 39 In the example, an audio speaker 12061, a display unit 12062, and a dashboard 12063 are shown as output devices. For example, the display unit 12062 may include at least one of an in-vehicle display and a head-up display.

[0352] Figure 40 This is a diagram showing an example of the mounting position of the imaging unit 12031.

[0353] exist Figure 40 In the imaging unit 12031, there are imaging units 12101, 12102, 12103, 12104 and 12105.

[0354] Imaging units 12101, 12102, 12103, 12104, and 12105 are disposed in locations such as the front of the vehicle 12100, side mirrors, rear bumper, rear door, and the upper part of the windshield inside the vehicle. Imaging unit 12101, disposed in the front of the vehicle, and imaging unit 12105, disposed on the upper part of the windshield inside the vehicle, primarily acquire images of the front of the vehicle 12100. Imaging units 12102 and 12103, disposed in the side mirrors, primarily acquire images of the sides of the vehicle 12100. Imaging unit 12104, disposed in the rear bumper or rear door, primarily acquires images of the rear of the vehicle 12100. Imaging unit 12105, disposed on the upper part of the windshield inside the vehicle, is mainly used to detect vehicles, pedestrians, obstacles, traffic signals, traffic signs, lanes, etc., ahead.

[0355] Incidentally, Figure 40 An example of the imaging range of imaging units 12101 to 12104 is shown. Imaging range 12111 represents the imaging range of imaging unit 12101 located in the front of the vehicle; imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103 located in the side mirrors, respectively; and imaging range 12114 represents the imaging range of imaging unit 12104 located in the rear bumper or rear door. For example, image data captured by imaging units 12101 to 12104 can be superimposed to obtain a bird's-eye view of the vehicle 12100 from above.

[0356] At least one of the imaging units 12101 to 12104 may have the function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0357] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within each imaging range 12111 to 12114 and the time change of that distance (relative speed relative to the vehicle 12100) based on distance information obtained from the imaging units 12101 to 12104. This allows it to extract, in particular, the closest three-dimensional object located on the vehicle 12100's travel path and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the vehicle ahead. Furthermore, the microcomputer 12051 can set a pre-defined distance between vehicles in front of the vehicle ahead and can perform automatic braking control (including tracking stop control), automatic acceleration control (including tracking start control), etc. Therefore, coordinated control such as autonomous driving, where the vehicle drives itself without relying on driver operation, can be performed.

[0358] For example, the microcomputer 12051 can extract three-dimensional data about objects by classifying them into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from imaging units 12101 to 12104, and automatically avoid obstacles using the extracted data. For example, the microcomputer 12051 identifies obstacles around vehicle 12100 as obstacles that can be visually recognized by the driver of vehicle 12100 and obstacles that are difficult to visually recognize. Then, the microcomputer 12051 determines the collision risk, indicating the degree of danger of colliding with each obstacle, and when the collision risk is equal to or higher than a set value and there is a possibility of collision, the microcomputer 12051 can provide collision avoidance driving assistance by outputting a warning to the driver via audio speaker 12061 and display unit 12062 or by performing forced deceleration or evasive steering via drive system control unit 12010.

[0359] At least one of the imaging units 12101 to 12104 can be an infrared camera for detecting infrared light. For example, the miniature calculator 12051 can identify a pedestrian by determining whether a pedestrian exists in the images captured by the imaging units 12101 to 12104. For example, pedestrian identification is performed by extracting feature points from the images captured by the imaging units 12101 to 12104, which are infrared cameras, and by performing pattern matching processing on a series of feature points indicating the outline of an object to determine whether the object is a pedestrian. When the miniature calculator 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 to display superimposed quadrilateral outlines to emphasize the identified pedestrian. Furthermore, the sound / image output unit 12052 can control the display unit 12062 to display an icon indicating the pedestrian at a desired location.

[0360] Examples of vehicle control systems to which the technology according to this disclosure is applicable have been described above. The technology according to this disclosure is applicable to the imaging unit 12031 in the above-described configuration. Specifically, for example, Figure 1 The imaging device 100 can be applied to the imaging unit 12031. By applying the technology according to this disclosure to the imaging unit 12031, noise can be minimized and captured images that are easier to view can be obtained, thereby reducing driver fatigue.

[0361] Note that the above embodiments illustrate examples for implementing this technology, and the matters in the embodiments correspond to the matters of the invention specified in the claims. Similarly, the matters of the invention specified in the claims correspond to the matters with the same names in the embodiments of this technology. However, this technology is not limited to the embodiments and can be implemented by various modifications to the embodiments without departing from its spirit.

[0362] Note that the effects described in this specification are illustrative and not limiting, and other effects may be provided.

[0363] Note that this technology may also have the following configurations.

[0364] (1) A solid-state imaging element, comprising:

[0365] A first pixel, wherein a first selection transistor is configured at a specific relative position, and a second selection transistor is configured at a different relative position; the first selection transistor turns on and off the path between a first capacitor element and a predetermined node to maintain a predetermined reset level; the second selection transistor turns on and off the path between a second capacitor element and the node to maintain a signal level corresponding to the exposure amount; and

[0366] The second pixel, wherein a third selection transistor is configured at a specific relative position, and a fourth selection transistor is configured at a different relative position from the specific relative position, the third selection transistor turns on and off the path between a third capacitor element and a predetermined node for maintaining a predetermined reset level, and the fourth selection transistor turns on and off the path between a fourth capacitor element and the node for maintaining a signal level corresponding to the exposure amount.

[0367] (2) The solid-state imaging element according to (1), wherein

[0368] The second pixel is adjacent to the first pixel.

[0369] (3) The solid-state imaging element according to (1), wherein

[0370] The pixels within the pixel array unit, including the first pixel and the second pixel, are configured in a Bayer array.

[0371] (4) The solid-state imaging element according to (3), wherein

[0372] The pixel array unit includes

[0373] The first pixel of each of the four is arranged in a first region of 2 rows x 2 columns, and

[0374] The second region is a second region consisting of four second pixels adjacent to the first region, arranged in a 2-row × 2-column configuration.

[0375] (5) The solid-state imaging element according to (3), wherein

[0376] The pixel array unit includes

[0377] The first pixel and three of the second pixels are arranged in a first region in a 2-row x 2-column configuration, and

[0378] The second region is adjacent to the first region and the second pixel and three of the first pixels are arranged in a 2-row × 2-column configuration.

[0379] (6) The solid-state imaging element according to (1), wherein

[0380] The pixels within the pixel array unit, including the first and second pixels, are configured in a four-Bayer array, and

[0381] The pixel array unit includes

[0382] The first pixel and three second pixels of the same color as the first pixel are arranged in a first region in a 2-row x 2-column configuration, and

[0383] The second region is a second pixel that is adjacent to the first region and has three first pixels of the same color as the second pixel, arranged in a 2-row × 2-column configuration.

[0384] (7) The solid-state imaging element according to any one of (1) to (6), wherein

[0385] The node mentioned is a subsequent node, and

[0386] A pixel block configured with a first pixel and a second pixel includes

[0387] The first pre-amplifier circuit sequentially generates a first reset level and a first signal level, and holds them in the first and second capacitor elements.

[0388] The second preamplifier circuit sequentially generates the second reset level and the second signal level, and holds them in the third and fourth capacitor elements.

[0389] The first, second, third, and fourth capacitor elements,

[0390] The selection unit includes a first selection circuit with first and second selection transistors and a second selection circuit with third and fourth selection transistors.

[0391] The subsequent circuit sequentially reads each of the first and second reset levels and the first and second signal levels via the subsequent node.

[0392] (8) The solid-state imaging element according to (7), wherein

[0393] The first pre-amplifier circuit includes

[0394] First photoelectric conversion element,

[0395] The first front-end transfer transistor transfers charge from the first photoelectric conversion element to the first floating diffusion layer.

[0396] Initialize the first reset transistor of the first floating diffusion layer, and

[0397] The first preamplifier transistor that amplifies the voltage of the first floating diffusion layer, and

[0398] The second pre-amplifier circuit includes

[0399] Second photoelectric conversion element,

[0400] The second front-end transfer transistor transfers charge from the second photoelectric conversion element to the second floating diffusion layer.

[0401] Initialize the second reset transistor of the second floating diffusion layer, and

[0402] The second preamplifier transistor amplifies the voltage of the second floating diffusion layer.

[0403] (9) The solid-state imaging element according to (8), wherein

[0404] The first front-end circuit also includes a first current source transistor connected to the first front-end node.

[0405] The second preamplifier circuit also includes a second current source transistor connected to the second preamplifier node.

[0406] The first preamplifier transistor amplifies the voltage of the first floating diffusion layer and outputs the amplified voltage to the first preamplifier node.

[0407] The second preamplifier transistor amplifies the voltage of the second floating diffusion layer and outputs the amplified voltage to the second preamplifier node.

[0408] One end of each of the first and second capacitor elements is connected to the first pre-amplifier node, and the other end of each is connected to the first selection circuit.

[0409] One end of each of the third and fourth capacitor elements is connected to the second preamplifier node, and the other end of each is connected to the second selection circuit.

[0410] (10) The solid-state imaging element according to (8) or (9), wherein

[0411] At the predetermined exposure start time, the first and second front-end transfer transistors transfer charge to the first and second floating diffusion layers, and the first and second reset transistors, together with the first and second floating diffusion layers, initialize the first and second photoelectric conversion elements.

[0412] At the predetermined end of the exposure, the first and second front-end transfer transistors transfer charge to the first and second floating diffusion layers.

[0413] (11) The solid-state imaging element according to any one of (8) to (10), wherein

[0414] The selection unit sequentially executes control to connect one of the first and second capacitor elements to the subsequent node, executes control to connect the other of the first and second capacitor elements to the subsequent node, executes control to connect one of the third and fourth capacitor elements to the subsequent node, and executes control to connect the other of the third and fourth capacitor elements to the subsequent node.

[0415] (12) The solid-state imaging element according to any one of (8) to (11), wherein

[0416] In the predetermined addition mode, the selection unit sequentially executes control to connect one of the first and second capacitor elements and one of the third and fourth capacitor elements to the subsequent node, and executes control to connect the other of the first and second capacitor elements and the other of the third and fourth capacitor elements to the subsequent node.

[0417] (13) The solid-state imaging element according to (8), wherein

[0418] The first preamplifier circuit also includes a first preamplifier selection transistor that outputs the voltage amplified by the first preamplifier transistor to a predetermined preamplifier node according to a predetermined first selection signal.

[0419] The second preamplifier circuit also includes

[0420] The voltage amplified by the second preamplifier transistor is output to the second preamplifier selection transistor of the preamplifier node according to the predetermined second selection signal, and

[0421] Current source transistors connected to the preceding node.

[0422] One end of each of the first and second capacitor elements is connected to the preceding node, and the other end of each is connected to the first selection circuit.

[0423] One end of each of the third and fourth capacitor elements is connected to the preceding node, and the other end of each is connected to the second selection circuit.

[0424] (14) The solid-state imaging element according to (13), wherein

[0425] The first and second front-end selection transistors sequentially switch to the closed state immediately before and after the predetermined exposure end time.

[0426] With the first front-end selection transistor in the closed state, the first reset transistor initializes the first floating diffusion layer.

[0427] With the second front-end selection transistor in the closed state, the second reset transistor initializes the second floating diffusion layer.

[0428] The first and second pre-stage selection transistors sequentially transition to the closed state immediately following the end of the exposure.

[0429] The first and second pre-stage transfer transistors transfer charge at the predetermined end of the exposure.

[0430] (15) The solid-state imaging element according to (1), wherein

[0431] The nodes include first and second successor nodes, and

[0432] A pixel block consisting of four pixels, including the first pixel and the second pixel, is configured.

[0433] The short-circuit transistor that turns the path between the first and second subsequent nodes on and off.

[0434] The first, second, third, and fourth capacitor elements,

[0435] The fifth, sixth, seventh, and eighth capacitor elements, and

[0436] The selection unit includes a first selection circuit with first and second selection transistors, a second selection circuit with third and fourth selection transistors, a third selection circuit connecting one of a fifth and sixth capacitor element to a second subsequent node, and a fourth selection circuit connecting one of a seventh and eighth capacitor element to the second subsequent node.

[0437] (16) The solid-state imaging element according to (15), wherein

[0438] In the predetermined non-addition mode, the short-circuit transistor is in the on state, and

[0439] In the non-additive mode, the selection unit executes control in a predetermined order to sequentially connect each of the first and second capacitor elements to the first subsequent node, to sequentially connect each of the third and fourth capacitor elements to the first subsequent node, to sequentially connect each of the fifth and sixth capacitor elements to the second subsequent node, and to sequentially connect each of the seventh and eighth capacitor elements to the second subsequent node.

[0440] (17) The solid-state imaging element according to (15) or (16), wherein

[0441] In the predetermined addition mode, the short-circuit transistor is in the closed state, and

[0442] In the addition mode, the selection unit sequentially executes control to connect one of the first and second capacitor elements and one of the third and fourth capacitor elements to the first post-stage node while simultaneously connecting one of the fifth and sixth capacitor elements and one of the seventh and eighth capacitor elements to the second post-stage node, and executes control to connect the other of the first and second capacitor elements and the other of the third and fourth capacitor elements to the first post-stage node while simultaneously connecting the other of the fifth and sixth capacitor elements and the other of the seventh and eighth capacitor elements to the second post-stage node.

[0443] (18) An imaging device, comprising:

[0444] A first pixel, wherein a first selection transistor is configured at a specific relative position, and a second selection transistor is configured at a different relative position from the specific relative position, the first selection transistor turns on and off the path between a first capacitor element and a predetermined node to maintain a predetermined reset level, and the second selection transistor turns on and off the path between a second capacitor element and the node to maintain a signal level corresponding to the exposure amount;

[0445] The second pixel, wherein a third selection transistor is configured at a specific relative position, and a fourth selection transistor is configured at a different relative position, the third selection transistor turns on and off the path between a third capacitor element and a predetermined node to maintain a predetermined reset level, and the fourth selection transistor turns on and off the path between a fourth capacitor element and the node to maintain a signal level corresponding to the exposure amount; and

[0446] The signal processing circuit sequentially converts the reset level and the signal level into digital signals.

[0447] List of reference numerals

[0448] 100 Imaging Device 110 Imaging Lens

[0449] 120 Recording Unit 130 Imaging Control Unit

[0450] 200 solid-state imaging element 201 upper pixel chip

[0451] 202 Lower pixel chip 203 Circuit chip

[0452] 211 Vertical scanning circuit 212 Timing control circuit

[0453] 213DAC 220 pixel array unit

[0454] 221 Upper pixel array unit 222 Lower pixel array unit

[0455] 250 load MOS circuit block 251 load MOS transistor

[0456] 260-column signal processing circuit 261ADC

[0457] 262 digital signal processing units, 300 pixel blocks

[0458] 301-304 pixel 305 preamplifier circuit block

[0459] 310, 320, 410, 420 preamplifier circuits

[0460] 311, 321, 411, 421, 511~513 photoelectric conversion elements

[0461] 312, 322, 412, 422, 514-516 transfer transistors

[0462] 313, 323, 413, 423FD reset transistors

[0463] 314,324,414,424FD

[0464] 315, 325, 415, 425 preamplifier transistors

[0465] 316, 326, 416, 426 current source transistors

[0466] 317, 327 Preamplifier Selection Transistors

[0467] 331, 332, 336, 337, 431, 432, 436, 437, 531~533 Capacitor Components

[0468] 340 selection unit

[0469] 350, 355, 450, 455 selector circuit

[0470] 351, 352, 356, 357, 451, 452, 456, 457, 551-553 select transistors

[0471] 361, 366, 461 Post-stage Reset Transistor

[0472] 370, 380, 470 power amplifier circuits

[0473] 371, 381, 471 power amplifier transistors

[0474] 372, 382, ​​472 power stage selection transistors

[0475] 480 short-circuit transistor

[0476] 12031 Imaging Unit

Claims

1. A solid-state imaging element, comprising: The first pixel includes: A first front-end node, one end of each of the first capacitor element and the second capacitor element is connected to the first front-end node, and the other end of each of the first capacitor element and the second capacitor element is connected to a first selection circuit provided with a first selection transistor and a second selection transistor. The first selection transistor, which turns on and off the path between the first capacitor element and the first subsequent node to maintain a predetermined reset level, and The second selection transistor, which turns on and off the path between the second capacitor element and the first subsequent node for maintaining a signal level corresponding to the exposure; and The second pixel includes: One end of each of the second front-end node, the third capacitor element, and the fourth capacitor element is connected to the second front-end node, and the other end of each of the third capacitor element and the fourth capacitor element is connected to a second selection circuit equipped with a third selection transistor and a fourth selection transistor. The third selection transistor, which turns on and off the path between the third capacitor element and the second subsequent node for maintaining a predetermined reset level, and The fourth selection transistor turns on and off the path between the fourth capacitor element and the second subsequent node to maintain a signal level corresponding to the exposure amount, wherein... The position of the third selection transistor within the second pixel is defined by a first coordinate (x2, y2) relative to a first predetermined reference position within the second pixel, and is the same as the position of the second selection transistor within the first pixel defined by the same first coordinate (x2, y2) relative to a second predetermined reference position within the first pixel. The position of the second predetermined reference position within the first pixel is the same as the position of the first predetermined reference position within the second pixel. The position of the fourth selection transistor within the second pixel is defined by a second coordinate (x1, y1) relative to the first predetermined reference position within the second pixel, and is the same as the position of the first selection transistor within the first pixel defined by the same second coordinate (x1, y1) relative to the second predetermined reference position within the first pixel.

2. The solid-state imaging element according to claim 1, wherein... The second pixel is adjacent to the first pixel.

3. The solid-state imaging element according to claim 1, wherein... The pixels within the pixel array unit, including the first pixel and the second pixel, are configured in a Bayer array.

4. The solid-state imaging element according to claim 3, wherein The pixel array unit includes The first pixel of each of the four is arranged in a first region of 2 rows × 2 columns, and The second region consists of four second pixels adjacent to the first region, arranged in a 2-row × 2-column configuration.

5. The solid-state imaging element according to claim 3, wherein... The pixel array unit includes The first pixel and three of the second pixels are arranged in a first region in a 2-row × 2-column configuration, and The second region is adjacent to the first region and the second pixel and three of the first pixels are arranged in a 2-row × 2-column configuration.

6. The solid-state imaging element according to claim 1, wherein... The pixels within the pixel array unit, including the first and second pixels, are configured in a four-Bayer array. The pixel array unit includes The first pixel and three second pixels of the same color as the first pixel are arranged in a first region in a 2-row × 2-column configuration. The second region is a second pixel that is adjacent to the first region and has three first pixels of the same color as the second pixel, arranged in a 2-row × 2-column configuration.

7. The solid-state imaging element according to any one of claims 1 to 6, wherein A pixel block configured with a first pixel and a second pixel includes The first pre-amplifier circuit sequentially generates a first reset level and a first signal level, and holds them in the first and second capacitor elements. The second preamplifier circuit sequentially generates the second reset level and the second signal level, and holds them in the third and fourth capacitor elements. The first, second, third, and fourth capacitor elements, The selection unit includes a first selection circuit and a second selection circuit. The subsequent circuitry sequentially reads each of the first and second reset levels and the first and second signal levels via a third subsequent node connected to the first and second subsequent nodes.

8. The solid-state imaging element according to claim 7, wherein The first pre-amplifier circuit includes First photoelectric conversion element, The first front-end transfer transistor transfers charge from the first photoelectric conversion element to the first floating diffusion layer. Initialize the first reset transistor of the first floating diffusion layer, and The first preamplifier transistor amplifies the voltage of the first floating diffusion layer, and The second pre-amplifier circuit includes Second photoelectric conversion element, The second front-end transfer transistor transfers charge from the second photoelectric conversion element to the second floating diffusion layer. Initialize the second reset transistor of the second floating diffusion layer, and The second preamplifier transistor amplifies the voltage of the second floating diffusion layer.

9. The solid-state imaging element according to claim 8, wherein The first front-end circuit also includes a first current source transistor connected to the first front-end node. The second preamplifier circuit also includes a second current source transistor connected to the second preamplifier node. The first preamplifier transistor amplifies the voltage of the first floating diffusion layer and outputs the amplified voltage to the first preamplifier node. The second preamplifier transistor amplifies the voltage of the second floating diffusion layer and outputs the amplified voltage to the second preamplifier node.

10. The solid-state imaging element according to claim 8, wherein At the predetermined exposure start time, the first and second front-end transfer transistors transfer charge to the first and second floating diffusion layers, and the first and second reset transistors, together with the first and second floating diffusion layers, initialize the first and second photoelectric conversion elements. At the predetermined end of the exposure, the first and second front-end transfer transistors transfer charge to the first and second floating diffusion layers.

11. The solid-state imaging element according to claim 7, wherein The selection unit sequentially executes control to connect one of the first and second capacitor elements to the third downstream node, executes control to connect the other of the first and second capacitor elements to the third downstream node, executes control to connect one of the third and fourth capacitor elements to the third downstream node, and executes control to connect the other of the third and fourth capacitor elements to the third downstream node.

12. The solid-state imaging element according to claim 7, wherein In the predetermined addition mode, the selection unit sequentially executes control to connect one of the first and second capacitor elements and one of the third and fourth capacitor elements to the third subsequent node, and executes control to connect the other of the first and second capacitor elements and the other of the third and fourth capacitor elements to the third subsequent node.

13. The solid-state imaging element according to claim 8, wherein The first preamplifier circuit also includes a first preamplifier selection transistor that outputs a voltage amplified by the first preamplifier transistor to a third preamplifier node connected to the first preamplifier node and the second preamplifier node according to a predetermined first selection signal. The second preamplifier circuit also includes The voltage amplified by the second preamplifier transistor is output to the second preamplifier selection transistor of the third preamplifier node according to the predetermined second selection signal, and A current source transistor connected to the third front-end node.

14. The solid-state imaging element according to claim 13, wherein The first and second front-end selection transistors sequentially switch to the closed state immediately before and after the predetermined exposure end time. With the first front-end selection transistor in the closed state, the first reset transistor initializes the first floating diffusion layer. With the second front-end selection transistor in the closed state, the second reset transistor initializes the second floating diffusion layer. The first and second pre-stage selection transistors sequentially transition to the closed state immediately following the end of the exposure. The first and second pre-stage transfer transistors transfer charge at the predetermined end of the exposure.

15. The solid-state imaging element of claim 1, wherein the pixel block comprising four pixels, including a first pixel and a second pixel, includes... Turn on and off the short-circuit transistors connecting the first and second downstream nodes to the path between the third and fourth downstream nodes. The first, second, third, and fourth capacitor elements, The fifth, sixth, seventh, and eighth capacitor elements, and The selection unit includes a first selection circuit, a second selection circuit, a third selection circuit that connects one of the fifth and sixth capacitor elements to the fourth subsequent node, and a fourth selection circuit that connects one of the seventh and eighth capacitor elements to the fourth subsequent node.

16. The solid-state imaging element according to claim 15, wherein In the predetermined non-additive mode, the short-circuit transistor is in the on state, and In the non-additive mode, the selection unit executes control in a predetermined order to sequentially connect each of the first and second capacitor elements to the third subsequent node, to sequentially connect each of the third and fourth capacitor elements to the third subsequent node, to sequentially connect each of the fifth and sixth capacitor elements to the fourth subsequent node, and to sequentially connect each of the seventh and eighth capacitor elements to the fourth subsequent node.

17. The solid-state imaging element according to claim 15 or 16, wherein In the predetermined addition mode, the short-circuit transistor is in the closed state, and In the addition mode, the selection unit sequentially executes control to connect one of the first and second capacitor elements and one of the third and fourth capacitor elements to the third downstream node while simultaneously connecting one of the fifth and sixth capacitor elements and one of the seventh and eighth capacitor elements to the fourth downstream node, and executes control to connect the other of the first and second capacitor elements and the other of the third and fourth capacitor elements to the third downstream node while simultaneously connecting the other of the fifth and sixth capacitor elements and the other of the seventh and eighth capacitor elements to the fourth downstream node.

18. An imaging device, comprising: Solid-state imaging element according to any one of claims 1-17; and The signal processing circuit sequentially converts the reset level and the signal level into digital signals.

Images