A method for double-side polishing a wafer

CN116728170BActive Publication Date: 2026-09-18ZING SEMICON CORP
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Patent Information

Application Number
CN202310723166.5
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2023-06-16
Publication Date
2026-09-18
Estimated Expiration
2043-06-16

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Technical Problem

然而目前双面抛光制程无法体现晶圆整体厚度形貌是凹陷还是凸起

Benefits of technology

[0044] The method for double-sided polishing of wafers provided by the present invention adjusts the distance parameters between the upper and lower disks based on the first thickness difference between two points in the center region of the wafer, and automatically adjusts the thickness parameters of the wafer center based on the second thickness difference between two points in the edge region of the wafer, thereby characterizing the thickness morphology of the wafer in the double-sided polishing process and improving the flatness of the wafer.

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Abstract

The application discloses a method for double-side polishing of a wafer, comprising the following steps: obtaining a first thickness difference between two points in a center area of the wafer, and / or obtaining a second thickness difference between two points in an edge area of the wafer; automatically adjusting a distance parameter of upper and lower discs based on the first thickness difference; and automatically adjusting a thickness parameter of the center of the wafer based on the second thickness difference. According to the method for double-side polishing of the wafer provided by the application, the distance parameter of the upper and lower discs is adjusted based on the first thickness difference between the two points in the center area of the wafer, and the thickness parameter of the center of the wafer is automatically adjusted based on the second thickness difference between the two points in the edge area of the wafer, so that the thickness profile of the wafer in the double-side polishing process is characterized, and the flatness of the wafer is improved.
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Description

Technical Field

[0001] This invention relates to the field of crystal growth technology, and more specifically to a method for double-sided polishing of wafers. Background Technology

[0002] In wafer manufacturing, processes such as dicing, grinding, polishing, and cleaning are required. Polishing treats the wafer surface to achieve the technical specifications required for integrated circuit wafers. Typically, to achieve the desired polishing precision, two polishing steps are performed: rough polishing and fine polishing. Rough polishing usually includes polishing both the front and back sides of the wafer, while fine polishing typically focuses only on the front side. When performing step-by-step chemical mechanical polishing (CMP) on the wafer surface, the polishing fluid and corresponding process conditions differ for each step, resulting in varying required processing precision for each step.

[0003] In Double Side Polishing (DSP) processes, the wafer is loosely inserted into a carrier, and polishing is performed simultaneously on both the front and back sides in a "free-floating" manner between upper and lower polishing pads covered by free polishing cloths. To achieve good wafer flatness in the final product, the DSP process, in addition to achieving good SFQR / GBIR, also needs to control the overall wafer thickness profile to match the profile of the subsequent single-sided polishing process, resulting in a better SFQR / GBIR for the final product. However, current DSP processes cannot accurately reflect whether the overall wafer thickness profile is concave or convex. Summary of the Invention

[0004] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] This invention provides a method for double-sided polishing of wafers, comprising:

[0006] Obtain the first thickness difference between two points in the center region of the wafer, and / or obtain the second thickness difference between two points in the edge region of the wafer;

[0007] The distance parameters between the upper and lower plates are automatically adjusted based on the first thickness difference;

[0008] The thickness parameters at the wafer center are automatically adjusted based on the second thickness difference.

[0009] For example, obtaining the first thickness difference between two points in the center region of the wafer includes:

[0010] Obtain the average thickness T at a distance X1 from the wafer center. X1 ;

[0011] Obtain the average thickness T at a distance X2 from the wafer center. X2 Where X1 < X2;

[0012] The first thickness difference DT1 between two points in the central region of the wafer is T X1 -T X2 .

[0013] For example, obtaining the second thickness difference between two points in the wafer edge region includes:

[0014] Obtain the average thickness T at a distance X3 from the wafer center. X3 ;

[0015] Obtain the average thickness T at a distance of X4 from the wafer center. X4 Where X3 < X4;

[0016] The second thickness difference DT2 between two points in the wafer edge region is T X3 -T X4 .

[0017] For example, when the first thickness difference is within the first thickness preset range, the distance parameter between the upper and lower plates is not adjusted, wherein the first thickness preset range is obtained based on the first target thickness and the first preset floating interval.

[0018] For example, when the first thickness difference is not within the preset range of the first thickness, automatically adjusting the distance parameters between the upper and lower plates based on the first thickness difference includes:

[0019] The first thickness variable is obtained based on the first thickness difference:

[0020] △DT1=DT1-DT 目标1

[0021] Where △DT1 represents the first thickness variable; DT1 represents the first thickness difference; DT 目标1 Indicates the thickness of the first target;

[0022] Based on the first thickness variable, obtain the distance variables between the upper and lower plates:

[0023] △DT1=K1×△D gap +B1

[0024] Where △DT1 represents the first thickness variable; △D gap The distance variables between the upper and lower plates are represented by K1 and B1, which are constants.

[0025] Exemplarily, the method further includes:

[0026] The distance parameters of the upper and lower plates are obtained based on the distance variables of the upper and lower plates and the current distance between the upper and lower plates:

[0027] D gap '=D gap +△D gap

[0028] Among them, D gap ' represents the distance parameter between the upper and lower plates; D gap Indicates the current distance between the upper and lower plates; △D gap This represents the distance variable between the upper and lower plates.

[0029] For example, when the second thickness difference is within the second thickness preset range, the thickness parameter of the wafer center is not adjusted, wherein the second thickness preset range is obtained based on the second target thickness and the second preset floating range.

[0030] For example, when the second thickness difference is not within the preset range of the second thickness, adjusting the thickness parameter of the wafer center based on the second thickness includes:

[0031] The second thickness variable is obtained based on the second thickness difference:

[0032] △DT2=DT2-DT 目标2

[0033] Where △DT2 represents the second thickness variable; DT2 represents the second thickness difference; DT 目标2 Indicates the thickness of the second target;

[0034] The thickness variable at the center of the wafer is obtained based on the second thickness variable:

[0035] △DT2=K2×△D thicknesscenter +B2

[0036] Where △DT2 represents the second thickness variable; △D thicknesscenter K2 represents the thickness variable at the center of the wafer; B2 and K2 represent constants.

[0037] Exemplarily, the method further includes:

[0038] The thickness parameter of the wafer center is obtained based on the thickness variable at the wafer center and the current thickness of the wafer center:

[0039] D thicknesscenter '=D thicknesscenter +△D thicknesscenter

[0040] Among them, D thicknesscenter'Indicates the thickness parameter at the center of the wafer; D thicknesscenter Indicates the thickness at the current wafer center; △D thicknesscenter This represents the thickness variable at the center of the wafer.

[0041] For example, before obtaining the first thickness difference between two points in the wafer center region and / or obtaining the second thickness difference between two points in the wafer edge region, the method further includes the step of:

[0042] Obtain the difference between the thickness at the wafer center and the thickness of the carrier;

[0043] The difference is compared with a preset threshold, wherein the preset threshold is 10 μm.

[0044] The method for double-sided polishing of wafers provided by the present invention adjusts the distance parameters between the upper and lower disks based on the first thickness difference between two points in the center region of the wafer, and automatically adjusts the thickness parameters of the wafer center based on the second thickness difference between two points in the edge region of the wafer, thereby characterizing the thickness morphology of the wafer in the double-sided polishing process and improving the flatness of the wafer. Attached Figure Description

[0045] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.

[0046] In the attached image:

[0047] Figure 1 This is a schematic diagram of a polishing apparatus for double-sided polishing wafers according to an embodiment of the present invention;

[0048] Figure 2 This is a schematic flowchart of a method for double-sided polishing of wafers according to an embodiment of the present invention;

[0049] Figure 3 This is a schematic diagram showing locations at distances of X1, X2, X3, and X4 from the wafer center according to an embodiment of the present invention.

[0050] Figure 4A This is a schematic diagram illustrating the relationship between the first thickness variable and the center thickness variable of the wafer according to an embodiment of the present invention;

[0051] Figure 4B This is a schematic diagram illustrating the relationship between the first thickness variable and the distance variable between the upper and lower plates according to an embodiment of the present invention.

[0052] Figure 5A This is a schematic diagram illustrating the relationship between the second thickness variable and the center thickness variable of the wafer according to an embodiment of the present invention;

[0053] Figure 5BThis is a schematic diagram illustrating the relationship between the second thickness variable and the distance variable between the upper and lower plates according to an embodiment of the present invention. Detailed Implementation

[0054] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.

[0055] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0056] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0057] To fully understand this invention, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by this invention. Preferred embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0058] like Figure 1 As shown, the polishing apparatus for performing double-sided polishing on a wafer includes at least a lower polishing disk 101 located below the wafer, an upper polishing disk 102 located above the wafer, and a carrier 103 for placing the wafer 100. Further, polishing pads 104 are provided on the surfaces of both the lower polishing disk 101 (i.e., the contact surface between the lower polishing disk and the wafer) and the upper polishing disk (i.e., the contact surface between the upper polishing disk and the wafer). Further, the polishing apparatus also includes a slurry supply system (not shown).

[0059] In the double-sided polishing process, such as Figure 1As shown, the wafer 100 is loosely inserted into the carrier 103 and polished simultaneously on the front and back sides in a "free-floating" manner between the upper polishing disk 102 and the lower polishing disk 101 covered by each free polishing pad 104.

[0060] For example, the lower polishing disk 101 and the upper polishing disk 102 provide a certain pressure and friction to the wafer 100, so as to achieve mechanical action with the wafer 100 to remove damage and dirt from the wafer surface and achieve the purpose of flatness polishing; at the same time, the polishing slurry supply system provides polishing slurry 105 containing alkaline substances such as KOH, which generates chemical corrosion when in contact with the wafer surface, so as to remove damage and dirt from the wafer surface by chemical action and achieve the flatness requirements of the wafer surface.

[0061] For large-size wafers, a combination of double-sided and single-sided polishing methods is typically used. In some products, an epitaxial layer is even grown on the wafer after single-sided polishing. To achieve good wafer flatness in the final product, the double-sided polishing process, in addition to achieving good SFQR / GBIR, also needs to control the wafer's thickness morphology to match the thickness morphology of the epitaxial layer formed in subsequent processes, thus achieving a better SFQR / GBIR result in the final product. Currently, the double-sided polishing process uses ESFQR / SFQR and GBIR to characterize the thickness morphology after polishing. This only characterizes the overall flatness of the wafer and cannot indicate whether the overall thickness morphology of the wafer is concave or convex.

[0062] To address the above problems, this invention provides a method for double-sided polishing of wafers, such as... Figure 2 As shown, it includes the following steps:

[0063] Step S210: Obtain the first thickness difference between two points in the center region of the wafer, and / or obtain the second thickness difference between two points in the edge region of the wafer;

[0064] Step S220: Automatically adjust the distance parameters between the upper and lower plates based on the first thickness difference;

[0065] Step S230: Automatically adjust the thickness parameters of the wafer center based on the second thickness difference.

[0066] For example, before performing step S210, the method further includes the steps of: obtaining the difference between the thickness of the wafer center and the thickness of the carrier; comparing the difference with a preset threshold, wherein the preset threshold is 10 μm.

[0067] In one embodiment, the thickness of the wafer center is the wafer center thickness value obtained in real time during the double-sided polishing process; the carrier thickness can be a pre-measured constant value or a carrier thickness value obtained in real time; the difference between the wafer center thickness and the carrier thickness is calculated. When the difference between the wafer center thickness and the carrier thickness is greater than a preset threshold, step S210 is not executed; when the difference between the wafer center thickness and the carrier thickness is less than or equal to the preset threshold, step S210 is executed.

[0068] In one embodiment, the preset threshold is 10 μm. That is, when the difference between the thickness at the center of the wafer and the thickness of the carrier is detected to be equal to or less than 10 μm, step S210 is started.

[0069] Next, refer to Figure 3 Step S210: Obtain the first thickness difference between two points in the center region of the wafer, and / or obtain the second thickness difference between two points in the edge region of the wafer.

[0070] In one embodiment, the surface of the wafer includes a central region and an edge region. Specifically, for a wafer with radius R, the central region may include a circular region with the center of the wafer as the center and a radius of R / 2, and the edge region may include the remaining annular region. It should be noted that the above division of the wafer surface region is merely exemplary, and the central region and edge region of the wafer can be divided as needed; the present invention does not impose any limitations on this.

[0071] For example, obtaining the first thickness difference between two points in the wafer center region includes: obtaining the average thickness T at a distance X1 from the wafer center. X1 Obtain the average thickness T at a distance X2 from the wafer center. X2 Where X1 < X2; the first thickness difference DT1 between two points in the central region of the wafer is T X1 -T X2 .

[0072] In one embodiment, a first radius X1 is obtained within the wafer center region, where the first radius X1 represents a distance X1 from the wafer center O, and the average thickness T at the first radius is obtained. X1 Furthermore, a second radius X2 is obtained within the wafer center region, where the second radius X2 represents the distance from the wafer center O by X2, and X1 < X2, indicating that the first radius X1 is closer to the wafer center O than the second radius X2. The average thickness T at the second radius is also obtained. X2 Therefore, the first thickness difference can be expressed as:

[0073] DT1 = T X1 -T X2 (Equation 1)

[0074] Where DT1 represents the first thickness difference; T X1 T represents the average thickness at the first radius X1; X2 This represents the average thickness at the second radius X2.

[0075] For example, obtaining the second thickness difference between two points in the wafer edge region includes: obtaining the average thickness T at a distance of X3 from the wafer center. X3 Obtain the average thickness T at a distance of X4 from the wafer center. X4 Where X3 < X4; the second thickness difference DT2 between two points in the wafer edge region is T X3 -T X4 .

[0076] In one embodiment, a third radius X3 is obtained within the wafer edge region, where the third radius X3 represents a distance of X3 from the wafer center O, and the average thickness T at the third radius is obtained. X3 Furthermore, a fourth radius X4 is obtained within the wafer edge region, where the fourth radius X4 represents a distance of X4 from the wafer center O, and X3 < X4, indicating that the fourth radius X4 is closer to the wafer edge than the third radius X3. The average thickness T at the fourth radius is also obtained. X4 Therefore, the second thickness difference can be expressed as:

[0077] DT2 = T X3 -T X4 (Equation 2)

[0078] Where DT2 represents the second thickness difference; T X3 T represents the average thickness at the third radius X3; X4 This represents the average thickness at the fourth radius X4.

[0079] Before step S220, the method further includes a step of comparing the first thickness difference with a first preset thickness range. Specifically, when the first thickness difference is within the first preset thickness range, step S220 is not executed; and when the first thickness difference is not within the first preset thickness range, step S220 is executed.

[0080] For example, the first thickness preset range is obtained based on the first target thickness and the first preset floating range, wherein the first target thickness can be set as needed, and the first preset floating range includes -30nm to 30nm.

[0081] In one embodiment, when the first target thickness is 0, the preset range of the first thickness is -30nm to 30nm; when the first thickness difference is within the range of (-30 to 30)nm, the distance parameter between the upper and lower plates does not need to be adjusted; when the first thickness difference is not within the range of (-30 to 30)nm, the distance parameter between the upper and lower plates needs to be adjusted. When the first target thickness is 5nm, the preset range of the first thickness is -25nm to 35nm; when the first thickness difference is within the range of (-25 to 35)nm, the distance parameter between the upper and lower plates does not need to be adjusted; when the first thickness difference is not within the range of (-25 to 35)nm, the distance parameter between the upper and lower plates needs to be adjusted.

[0082] Next, step S220 is executed: the distance parameters between the upper and lower plates are automatically adjusted based on the first thickness difference.

[0083] For example, automatically adjusting the distance parameters of the upper and lower plates based on the first thickness difference includes: obtaining a first thickness variable based on the first thickness difference; obtaining a distance variable between the upper and lower plates based on the first thickness variable; and obtaining the distance parameters between the upper and lower plates based on the distance variable between the upper and lower plates and the current distance between the upper and lower plates.

[0084] In one embodiment, firstly, a first thickness variable ΔDT1 is obtained based on a first thickness difference DT1:

[0085] △DT1=DT1-DT 目标1 (Equation 3)

[0086] Where △DT1 represents the first thickness variable; DT1 represents the first thickness difference; DT 目标1 This indicates the thickness of the first target.

[0087] Then, based on the first thickness variable △DT1 and the distance variable △D between the upper and lower plates... gap The relationship between the upper and lower plates yields the distance variable △D. gap :

[0088] △DT1=K1×△D gap +B1 (Equation 4)

[0089] Where △DT1 represents the first thickness variable; △D gap The distance variables between the upper and lower plates are represented by K1 and B1, which are constants.

[0090] In one embodiment, such as Figure 4A and 4B As shown, the first thickness variable ΔDT1 and the center thickness variable ΔD of the wafer are... thicknesscenter The relationship is non-linear, with the first thickness variable △DT1 and the distance variable △D between the upper and lower plates. gap It exhibits a linear relationship, for Figure 4BThe first thickness variable △DT1 and the distance variable △D between the upper and lower plates gap Perform a linear fit to obtain the values ​​of K1 and B1.

[0091] Next, based on the distance variable △D between the upper and lower plates in equation (4) gap The current distance D between the upper and lower plates gap The distance parameter D between the upper and lower plates gap The relationship between the upper and lower plates yields the distance parameter D. gap ':

[0092] D gap '=D gap +△D gap (Equation 5)

[0093] Among them, D gap ' represents the distance parameter between the upper and lower plates; D gap Indicates the current distance between the upper and lower plates; △D gap This represents the distance variable between the upper and lower plates.

[0094] In one embodiment, the first thickness difference DT1 of the currently processed wafer is -40 nm, and the first target thickness DT 目标1 =5nm, the current distance D between the upper and lower plates gap =-10um. In equation (3), K1=15, B1=0, then (-40-5)=15×△D gap +0, we can get △D gap = -3um, if △D gap If the value is not an integer, it is rounded to the nearest integer. According to equation (5), we can obtain D. gap = -10 + (-3) = -13um.

[0095] Before step S230, the method further includes a step of comparing the second thickness difference with a second preset thickness range. Specifically, when the second thickness difference is within the second preset thickness range, step S230 is not executed; and when the second thickness difference is not within the second preset thickness range, step S230 is executed.

[0096] For example, the second thickness preset range is obtained based on the second target thickness and the second preset floating range, wherein the second target thickness can be set as needed, and the second preset floating range includes -10nm to 10nm.

[0097] In one embodiment, when the second target thickness is 0, the preset range of the second thickness is -10nm to 10nm; when the second thickness difference is within the range of (-10 to 10)nm, the distance parameter between the upper and lower plates does not need to be adjusted; when the second thickness difference is not within the range of (-10 to 10)nm, the distance parameter between the upper and lower plates needs to be adjusted. When the second target thickness is 5nm, the preset range of the second thickness is -5nm to 15nm; when the second thickness difference is within the range of (-5 to 15)nm, the distance parameter between the upper and lower plates does not need to be adjusted; when the second thickness difference is not within the range of (-5 to 15)nm, the distance parameter between the upper and lower plates needs to be adjusted.

[0098] Next, step S230 is executed: the thickness parameters at the wafer center are automatically adjusted based on the second thickness difference.

[0099] For example, adjusting the thickness parameter of the wafer center based on the second thickness includes: obtaining a second thickness variable based on the second thickness difference; obtaining a thickness variable of the wafer center based on the second thickness variable; and obtaining the thickness parameter of the wafer center based on the thickness variable of the wafer center and the current thickness of the wafer center.

[0100] In one embodiment, firstly, the second thickness variable ΔDT2 is obtained based on the second thickness difference DT2:

[0101] △DT2=DT2-DT 目标2 (Equation 6)

[0102] Where △DT2 represents the second thickness variable; DT2 represents the second thickness difference; DT 目标2 This indicates the thickness of the second target.

[0103] Then, based on the second thickness variable ΔDT2 and the thickness variable ΔD at the wafer center... thicknesscenter The relationship yields the thickness variable ΔD at the wafer center. thicknesscenter :

[0104] △DT2=K2×△D thicknesscenter +B2 (Equation 7)

[0105] Where △DT2 represents the second thickness variable; △D thicknesscenter K2 represents the thickness variable at the center of the wafer; B2 and K2 represent constants.

[0106] In one embodiment, such as Figure 5A and 5B As shown, the second thickness variable ΔDT2 and the thickness variable ΔD at the wafer center are... thicknesscenter The relationship is linear, with the second thickness variable △DT2 and the distance variable △D between the upper and lower plates. gap It exhibits a non-linear relationship, for Figure 5AThe second thickness variable ΔDT2 and the thickness variable ΔD at the wafer center thicknesscenter Perform a linear fit to obtain the values ​​of K2 and B2.

[0107] Next, based on the thickness variable ΔD at the wafer center in equation (7) thicknesscenter The current thickness D at the center of the wafer thicknesscenter The thickness parameter D at the center of the wafer thicknesscenter The relationship between ' and ' yields the thickness parameter D at the wafer center. thicknesscenter ':

[0108] D thicknesscenter '=D thicknesscenter +△D thicknesscenter (Equation 8)

[0109] Among them, D thicknesscenter 'Indicates the thickness parameter at the center of the wafer; D thicknesscenter Indicates the thickness at the current wafer center; △D thicknesscenter This represents the thickness variable at the center of the wafer.

[0110] In one embodiment, the second thickness difference DT2 of the currently processed wafer is -20 nm, and the second target thickness DT 目标2 =0nm, the current thickness D at the center of the wafer thicknesscenter =772.5um. In equation (7), K2 = -10 and B2 = 0, then (-20-0) = -10 × △D thicknesscenter +0, we can get △D thicknesscenter =2um, according to equation (8) we can get D thicknesscenter =772.5 + 2 = 774.5um.

[0111] The method for double-sided polishing of wafers provided by the present invention adjusts the distance parameters between the upper and lower disks based on the first thickness difference between two points in the center region of the wafer, and automatically adjusts the thickness parameters of the wafer center based on the second thickness difference between two points in the edge region of the wafer, thereby characterizing the thickness morphology of the wafer in the double-sided polishing process and improving the flatness of the wafer.

[0112] The present invention has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, those skilled in the art will understand that the present invention is not limited to the above embodiments, and many more variations and modifications can be made based on the teachings of the present invention, all of which fall within the scope of protection claimed by the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for double-sided polishing of wafers, characterized in that, include: Obtain the first thickness difference between two points in the center region of the wafer, and obtain the second thickness difference between two points in the edge region of the wafer; The first thickness difference between two points in the center region of the wafer is obtained by: Obtain the average thickness T at a distance X1 from the wafer center. X1 ; Obtain the average thickness T at a distance X2 from the wafer center. X2 Where X1 < X2; The first thickness difference DT1 between two points in the central region of the wafer is T X1 - T X2 ; The process of obtaining the second thickness difference between two points in the wafer edge region includes: Obtain the average thickness T at a distance X3 from the wafer center. X3 ; Obtain the average thickness T at a distance of X4 from the wafer center. X4 Where X3 < X4; The second thickness difference DT2 between two points in the wafer edge region is T X3 - T X4 ; Based on the first thickness difference, when the first thickness difference is not within the first thickness preset range, the distance parameters between the upper polishing pad and the lower polishing pad are automatically adjusted, wherein the first thickness preset range is obtained based on the first target thickness and the first preset floating range; Based on the second thickness difference, when the second thickness difference is not within the second thickness preset range, the thickness parameter of the wafer center is automatically adjusted, wherein the second thickness preset range is obtained based on the second target thickness and the second preset floating range.

2. The method as described in claim 1, characterized in that, When the first thickness difference is within the first thickness preset range, the distance parameters between the upper polishing disk and the lower polishing disk are not adjusted.

3. The method as described in claim 2, characterized in that, When the first thickness difference is not within the preset range of the first thickness, automatically adjusting the distance parameters between the upper and lower polishing disks based on the first thickness difference includes: The first thickness variable is obtained based on the first thickness difference: △DT1=DT1-DT 目标1 Where △DT1 represents the first thickness variable; DT1 represents the first thickness difference; DT 目标1 Indicates the thickness of the first target; The distance variable between the upper and lower polishing disks is obtained based on the first thickness variable: △DT1=K1×△D gap +B1 Where △DT1 represents the first thickness variable; △D gap K1 represents the distance variable between the upper and lower polishing disks; B1 and B1 represent constants.

4. The method as described in claim 3, characterized in that, Also includes: The distance parameters of the upper and lower polishing disks are obtained based on the distance variables between the upper and lower polishing disks and the current distance between the upper and lower polishing disks: D gap ’=D gap +△D gap Among them, D gap ' represents the distance parameter between the upper and lower polishing disks; D gap This represents the distance between the upper and lower polishing disks; △D gap This represents the distance variable between the upper and lower polishing disks.

5. The method as described in claim 1, characterized in that, When the second thickness difference is within the second thickness preset range, the thickness parameter of the wafer center is not adjusted.

6. The method as described in claim 5, characterized in that, When the second thickness difference is not within the preset range of the second thickness, adjusting the thickness parameter of the wafer center based on the second thickness includes: The second thickness variable is obtained based on the second thickness difference: △DT2=DT2-DT 目标2 Where △DT2 represents the second thickness variable; DT2 represents the second thickness difference; DT 目标2 Indicates the thickness of the second target; The thickness variable at the center of the wafer is obtained based on the second thickness variable: △DT2=K2×△D thicknesscenter +B2 Where △DT2 represents the second thickness variable; △D thicknesscenter K2 represents the thickness variable at the center of the wafer; B2 and K2 represent constants.

7. The method as described in claim 6, characterized in that, Also includes: The thickness parameter of the wafer center is obtained based on the thickness variable at the wafer center and the current thickness of the wafer center: D thicknesscenter ’=D thicknesscenter +△D thicknesscenter Among them, D thicknesscenter 'Indicates the thickness parameter at the center of the wafer; D thicknesscenter Indicates the thickness at the current wafer center; △D thicknesscenter This represents the thickness variable at the center of the wafer.

8. The method as described in claim 1, characterized in that, Before obtaining the first thickness difference between two points in the wafer center region and the second thickness difference between two points in the wafer edge region, the method further includes the following steps: Obtain the difference between the thickness at the wafer center and the thickness of the carrier; The difference is compared with a preset threshold, wherein the preset threshold is 10 μm.

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