Photonic computing array for on-chip large-scale matrix multiplication operations

Abstract

The application discloses a photonic computing array for on-chip large-scale matrix multiplication operation, comprising: a photonic computing unit based on carrier light absorption effect, a crossbar switch matrix architecture and a waveguide coupling device; the photonic computing unit comprises an optical waveguide and an electro-optic modulator; the optical waveguide of each photonic computing unit is coupled with the adjacent waveguide through the waveguide coupling device, and the waveguide coupling device evanescently couples a part of optical power from the adjacent input row waveguide, wherein the coupled optical power depends on the length of the part of the waveguide coupling device which is placed adjacent to the input row waveguide and extends parallel to the input row waveguide. The photonic computing array provided by the application is a novel photonic computing chip technology path, the basic computing unit of which has a small volume, a fast modulation speed, only two electrodes for each basic computing unit, a small number of wirings, and low design difficulty and packaging complexity.

Description

Technical Field

[0001] This invention relates to the field of photonic computing technology, and more particularly to a photonic computing array for on-chip large-scale matrix multiplication operations. Background Technology

[0002] As human society enters the era of big data, the demand for ultra-fast data processing places increasingly higher requirements on the computing power and speed of computer systems. With Moore's Law approaching its physical limits, electronic chips face significant challenges in terms of computing speed and power consumption. Traditional matrix operations, such as those disclosed in Chinese patent CN111158636, require computers to repeatedly store and retrieve intermediate data. As the size of the matrix increases, the computation time also multiplies. Therefore, people have begun to seek a more efficient method for large-scale matrix operations.

[0003] Photonic computing structures possess characteristics such as high speed and parallelism, offering significant advantages in handling linear computations and becoming a current international research hotspot. Researchers are using novel optical materials such as optical waveguide micro / nano structures and microlens arrays to construct photonic computing chips for application in various scenarios.

[0004] Photonic computing chips, built using optical devices as basic units and networked with photonic components, can utilize high-speed parallelism and low-power photons as information carriers. This is considered the most promising solution for high-speed, ultra-large-scale, large-data-volume, artificial intelligence, and neuromorphic computing, and is expected to drive a new industrial revolution. Silicon-based optoelectronics technology leverages the unique advantages of photons in speed, bandwidth, and interference resistance, while also possessing integration processes compatible with CMOS technology. This can overcome the development limitations of integrated circuits and further enhance chip computing power. Unlike the binary electronic computing system composed of 0s and 1s, photons have more controllable modulation and multiplexing dimensions, such as phase, wavelength, polarization, and mode. This gives them unique advantages in analog and multi-bit computing, and they are highly suitable for massive parallel computing, making them one of the important directions for integrated circuit development in the post-Moore's Law era.

[0005] Existing photonic computing chip technologies utilize Mach-Zehnder interferometers (MZI) or microring structures (MMR) to achieve photonic computing, as disclosed in Chinese patents CN115905792 and CN113392965. Computing arrays based on these methods are shown in Chinese patents CN10407644 and CN116107037. However, these technologies generally suffer from the following shortcomings:

[0006] 1. Limitation of computing array size: The basic computing unit area of ​​MZI-based photonic computing chips is relatively large. When fabricating on silicon photonics platforms, it is difficult to achieve the application-level scale of computing array using photomasks with conventional wafer area.

[0007] 2. Slow computation speed: This is mainly due to the use of the thermo-optical tuning principle based on silicon-based optoelectronic technology, which also results in temperature drift (especially noticeable in MMR structures), affecting the refractive index of the optical waveguide.

[0008] 3. High design and packaging difficulty: Each basic computing unit of the MZI-based photonic computing chip has more than 10 electrodes, resulting in a huge number of wirings and high design and packaging complexity. Summary of the Invention

[0009] The purpose of this invention is to overcome the shortcomings of the existing technology and provide a photonic computing array for on-chip large-scale matrix multiplication operations.

[0010] The objective of this invention is achieved through the following technical solution:

[0011] A photonic computing array for large-scale on-chip matrix multiplication operations includes:

[0012] A photonic computing unit based on carrier optical absorption effect; the photonic computing unit includes an optical waveguide and an electro-optic modulator based on optical absorption effect located on the optical waveguide; the electro-optic modulator uses an electrical signal as an external excitation, and changes the concentration of free carriers (charge or hole) in its doped region by injecting current or applying voltage, thereby changing the absorption coefficient α of the optical waveguide containing free carriers, so that the optical signal passing through the optical waveguide is absorbed by the free carriers to realize multiplication operation;

[0013] Crossbar architecture; the crossbar architecture is formed by a set of parallel input row waveguides and a set of parallel output column waveguides crossing each other;

[0014] At each intersection of the input row waveguide and the output column waveguide in the photonic computing array, there is a photonic computing unit for multiplication operations. The optical waveguide of each photonic computing unit is coupled to the adjacent waveguide through a waveguide coupling device. The waveguide coupling device evanescently couples a portion of the optical power from the adjacent input row waveguide, wherein the coupled optical power depends on the length of the portion of the waveguide coupling device that is placed adjacent to the input row waveguide and extends parallel to the adjacent input row waveguide.

[0015] Preferably, a cross-optical waveguide is provided at the intersection of each of the input row waveguides and the output column waveguides that intersect with them.

[0016] Preferably, the input row waveguide is perpendicular to the output column waveguide.

[0017] Preferably, the wavelengths of the input optical signals in the different rows of input waveguides are different.

[0018] Preferably, the input optical signal, under the action of the waveguide coupling device, has its optical power evenly distributed to each photonic computing unit in the same row.

[0019] Preferably, the number of rows of the input row waveguide and the number of columns of the output column waveguide of the photonic computing array are at least greater than or equal to 2.

[0020] Preferably, the size of the photonic computing unit is less than 100 μm.

[0021] Preferably, the voltage amplitude of the electrical signal used as an external excitation is less than 10V and the duration is less than 100μs.

[0022] Preferably, the relative positions of the optical waveguide and the electro-optic modulator can be on the same plane or not on the same plane.

[0023] Preferably, the input end of the input row waveguide of the photonic computing array is connected to a multiplexer (MUX), and the output end of the output column waveguide is connected to a demultiplexer (DEMUX).

[0024] The beneficial effects of this invention are mainly reflected in: providing a novel photonic computing array for large-scale matrix multiplication operations on a chip, which is a new type of photonic computing chip technology path. Its basic computing unit area is small, and the mask under the conventional wafer area can make the computing array scale up to the application level.

[0025] It has a fast modulation speed, which can be increased to the nanosecond level through electrical pulses, thereby improving the computing performance of photonic computing chips, without causing temperature drift.

[0026] Each basic computing unit has only 2 electrodes, resulting in a small number of wiring connections and low design difficulty and packaging complexity. Attached Figure Description

[0027] The technical solution of the present invention will be further described below with reference to the accompanying drawings:

[0028] Figure 1 : A schematic diagram of the photonic computing array of the present invention;

[0029] Figure 2 : A schematic diagram illustrating the extended application of the photonic computing array of the present invention;

[0030] Figure 3 : A schematic diagram of a 3*3 photonic computing array according to an embodiment of the present invention;

[0031] Figure 4 : A schematic diagram illustrating an extended application of a 3x3 photonic computing array according to an embodiment of the present invention;

[0032] Figure 5: A schematic diagram of the structure of the photonic computing unit provided in this embodiment of the invention.

[0033] Figure 6 : A schematic diagram illustrating the working principle of the photonic computing unit multiplication calculation provided in this embodiment of the invention. Detailed Implementation

[0034] The present invention will now be described in detail with reference to the specific embodiments shown in the accompanying drawings. However, these embodiments are not limited to the present invention, and any structural, methodological, or functional modifications made by those skilled in the art based on these embodiments are included within the scope of protection of the present invention.

[0035] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0036] like Figure 1 As shown, this invention discloses a photonic computing array for on-chip large-scale matrix multiplication operations, including a photonic computing unit 1 based on carrier optical absorption effect, a waveguide coupling device 2, and a crossbar architecture. Specifically, the crossbar architecture is formed by a set of parallel input row waveguides 31 and a set of parallel output column waveguides 32; preferably, the input row waveguides 31 and the output column waveguides 32 are perpendicular to each other.

[0037] In the photonic computing array of the present invention, the number of rows of the input row waveguide 31 and the number of columns of the output column waveguide 32 are at least greater than or equal to 2. Preferably, a cross optical waveguide 4 is provided at the intersection point of each input row waveguide 31 and the output column waveguide 32 that intersects with it, so as to realize low-loss transmission of optical signals at the waveguide intersection.

[0038] At each intersection of the input row waveguide 31 and the output column waveguide 32 in the photonic computing array, there is a photonic computing unit 1 for multiplication operations. The photonic computing unit 1 includes an optical waveguide 11 and an electro-optic modulator 12 based on the light absorption effect located on the optical waveguide 11. The electro-optic modulator 12 uses an electrical signal as an external excitation, injecting current or applying voltage to its doped region to change the concentration of free carriers (charge or hole), thereby changing the absorption coefficient α of the optical waveguide 11 containing free carriers. This allows the optical signal passing through the optical waveguide 11 to be absorbed by the free carriers, thus realizing the multiplication operation. The injected current or applied voltage is mainly in the form of electrical pulses, with the duration on the nanosecond level. The duration of the electrical pulses determines the modulation speed of the photonic computing array, and thus its computing performance; it also avoids temperature drift.

[0039] The photonic computing array of this invention performs multiplication operations as follows: Figure 5 , Figure 6As shown, it includes the following steps:

[0040] The multiplier value is encoded into the write signal 108;

[0041] The write signal 108 is used to map the multiplier value to the state of the electro-optic modulator 12, which represents the absorption coefficient α of the optical waveguide to light under different free carrier concentrations.

[0042] The multiplied value is encoded into the input optical signal 106;

[0043] When the input optical signal 106 passes through the optical absorption region of the electro-optic modulator 12 via the optical waveguide 11, an output signal 107 is generated, wherein the product of the multiplier and the multiplicand is encoded in the optical power of the output signal.

[0044] The write signal 108 used to change the free carrier concentration in the electro-optic modulator 12 is provided by the electrical signal generator 105. Two electrically interconnected devices in the metal layer of the electrical signal generator 105 transmit the generated electrical signals to the doped regions 103a and 103b of the electro-optic modulator 12 via the first contact electrode 104a and the second contact electrode 104b, respectively. The electrical signals cause free carriers to move directionally under the influence of an electric field, and changes in the parameters of the electrical signals can alter the free carrier concentration in the doped regions, thereby changing the light absorption coefficient of the optical waveguide containing free carriers. The electro-optic modulator based on the light absorption effect includes a doped region based on semiconductor doping techniques such as ion implantation or high-temperature diffusion, and a pair of contact electrodes forming ohmic or Schottky contacts with the doped region.

[0045] The electrical signal generator 105 uses an external electrical signal—namely, the write signal 108—to map the multiplier value b to the light absorption coefficient α of the optical waveguide containing free carriers. The electro-optic modulator 12 injects current or applies voltage to change the concentration of free carriers (charges or holes) in the doped region, thereby altering the light absorption coefficient α of the optical waveguide containing free carriers. The energy Pwrite of the external electrical signal has an elementary or rational function mapping to the light absorption coefficient α. The input optical signal 106 decays inversely proportional to the light absorption coefficient α of the optical waveguide containing free carriers, thereby generating a multiplicative output signal 107 corresponding to the external electrical signal—the write signal 108—and the input optical signal 106. The output signal Pout = α × Pin of the optical waveguide 11 is the result of mapping the multiplier value b to α and the multiplicand value a to Pin.

[0046] The photonic computing unit of this invention has a size of less than 100 μm, preferably 20–30 μm. Currently, photonic computing units based on MZI structures have a size of 200–300 μm, while the photonic computing unit provided in this embodiment is significantly smaller, achieving miniaturization and high integration of the photonic computing unit. As the size of a single photonic computing unit decreases, the actual area of ​​each device on the chip decreases. During silicon photonics platform fabrication, optical masks within a conventional wafer area (e.g., an 8-inch wafer) can support a larger number of photonic computing units, forming a larger-scale matrix of photonic computing arrays, thereby improving the integration of the photonic computing chip.

[0047] Existing MZI-based photonic computing arrays are relatively large. When fabricating on silicon photonics platforms, masks with conventional wafer areas (such as 8-inch wafers) cannot support photonic computing arrays with a matrix size of 128*128. However, a photonic computing array with a matrix size of 128*128 is a threshold for commercial applications. The novel photonic computing array proposed in this invention for large-scale on-chip matrix multiplication can achieve a matrix size of 400*400 with a mask with a conventional wafer area, which is far greater than the threshold for commercial applications.

[0048] In this embodiment, the voltage amplitude of the electrical signal is less than 10V and the duration is less than 100μs. In some preferred embodiments, the voltage amplitude of the electrical signal is less than 5V and the duration is less than 100ns. Currently, the modulation speed of MZI photonic computing units based on thermo-optic modulation is on the order of microseconds, while the electro-optic modulator provided in this embodiment, utilizing doped semiconductor devices, can achieve a modulation speed of less than 100ns, or even less than 10ns, greatly improving the computing speed of the photonic computing unit. The amplitude of the electrical signal is preferably less than 5V, thus ensuring good compatibility with existing electrical chip levels. No additional circuit design is required; the optical signal in the photonic computing unit can be directly modulated by pulses emitted from the electrical chip.

[0049] In terms of modulators, MZI-based photonic computing arrays have more than 10 electrodes per computing unit, while the novel photonic computing array proposed in this invention for large-scale on-chip matrix multiplication has only 2 electrodes per photonic computing unit. From a design and packaging perspective, its difficulty is far less than that of MZI-based photonic computing arrays.

[0050] In a preferred embodiment of the present invention, the optical waveguide 11 of each photonic computing unit 1 is coupled to an adjacent waveguide via the waveguide coupling device 2. For example, one end of the optical waveguide 11 is coupled to an adjacent input row waveguide 31 via a row waveguide coupling device 21, and the other end is coupled to an adjacent output column waveguide 32 via a column waveguide coupling device 22. The waveguide coupling device 2 gradually couples a portion of the optical power from the adjacent input row waveguide 31, wherein the coupled optical power depends on the length of the portion of the waveguide coupling device 2 that is placed adjacent to the input row waveguide 31 and extends parallel to the adjacent input row waveguide 31.

[0051] The key feature of this invention is the use of waveguide coupling devices and a crossbar matrix architecture to interconnect individual photonic computing units performing multiplication operations, forming a crossbar matrix architecture to achieve large-scale matrix multiplication. Specifically, after each photonic computing unit undergoes the multiplication operation described above, the output signal containing the product is summed on the output column waveguide 32 via the column waveguide coupling device 22. The sum is encoded into the input signal of the output column waveguide. The column waveguide coupling device ensures that the common factor of optical power at each wavelength is the same. The output signals of the input row waveguide and the input signals of the output column waveguide are coupled to generate an output signal, where the sum of the product and the sum is encoded in the optical power of the output signal of the output column waveguide. Of course, the order of the input row waveguide and the output column waveguide is not fixed; multiplication can be performed using the column waveguide input optical signal, and the sum can be accumulated using the row waveguide before output.

[0052] This invention achieves low-loss transmission of optical signals between rows and columns of a large-scale matrix through a cross-switch matrix architecture, ultimately enabling large-scale matrix multiplication operations. In a preferred embodiment, the wavelengths of the input optical signals in the input waveguides 31 of different rows are different, avoiding interference during addition operations that could affect the accuracy of photonic computation.

[0053] Specifically, such as Figure 1 As shown, this invention provides a method for performing matrix multiplication in the optical domain, which calculates an m×n matrix P×U=A:

[0054]

[0055] Specifically, the following steps are included:

[0056] (1) Encode the weight matrix U into the written signal. For example, input the code U11 into the photonic computing unit in the first row and first column, input the code U12 into the photonic computing unit in the first row and second column, input the code U21 into the photonic computing unit in the second row and first column, and so on.

[0057] (2) Using a write signal to map the multiplier value to the state of the electro-optic modulator in each photonic computing unit, the state being represented by the absorption coefficient α of the optical waveguide to light;

[0058] (3) The input data matrix P is encoded into the input optical signal. Under the action of the row waveguide coupling device 21, the optical power of the input optical signal is evenly distributed to each unit in the same row; for example, the input row waveguide of the first row is encoded with P1, the input row waveguide of the second row is encoded with P2, and so on.

[0059] (4) When the input optical signal passes through the optical absorption region of the electro-optic modulator of the photonic computing unit through the optical waveguide, an output signal is generated. The product of the multiplier and the multiplicand is encoded in the output signal. The optical power of the output signal is summed on the column waveguide through the column waveguide coupling device 22. The column waveguide coupling device can make the common factor of the optical power at each wavelength the same.

[0060] For example: The output optical power of the first column is:

[0061]

[0062] The common factor in the above formula is 1 / m*n. And so on.

[0063] like Figure 2 The diagram illustrates an extended application of the photonic computing array of the present invention. A multiplexer (MUX) is connected to the input terminal of the input row waveguide 31 of the photonic computing array, and a demultiplexer (DEMUX) is connected to the output terminal of the output column waveguide 32. Each component of the input matrix uses multiple optical signals of different wavelengths, and the number of channels in the multiplexer determines the factor by which the computing power of the photonic computing array is increased.

[0064] Figure 3 A schematic diagram of a 3x3 photonic computing array is shown, which realizes the calculation of a third-order matrix P×U=A.

[0065]

[0066] in:

[0067] 101a, 101b, 101c: Input traveling waveguides;

[0068] 102a, 102b, 102c: Output column waveguides;

[0069] P1, P2, P3: Input (read) optical signals;

[0070] A1, A2, A3: Output signals;

[0071] U11, U12, U13, U21, U22, U23, U31, U32, U33: Photonic computing units used for multiplication operations;

[0072] r11, r12, r13, r21, r22, r23, r31, r32, r33: traveling waveguide coupling devices;

[0073] c11, c12, c13, c21, c22, c23, c31, c32, c33: Column waveguide coupling devices;

[0074] According to the method of the present invention, the optical power output of the first column can be calculated as follows:

[0075]

[0076] The common factor in the above formula is 1 / 9.

[0077] Similarly, Figure 4 As shown Figure 3 Extended applications of the photonic computing array in the embodiment of the present invention. By adding a multiplexer (MUX) at the input end of the photonic computing array and a demultiplexer (DEMUX) at the output end, each component of the input matrix uses three different wavelengths, thereby increasing the computing power of the photonic computing array by three times.

[0078] The detailed descriptions listed above are merely specific descriptions of feasible embodiments of the present invention, and are not intended to limit the scope of protection of the present invention. All equivalent embodiments or modifications made without departing from the spirit of the present invention should be included within the scope of protection of the present invention.

Claims

1. A photonic computing array for on-chip large-scale matrix multiplication operations, characterized in that: include Photonic computing unit (1) based on carrier optical absorption effect; the photonic computing unit (1) includes an optical waveguide (11) and an electro-optic modulator (12) based on optical absorption effect located on the optical waveguide (11); the electro-optic modulator (12) uses an electrical signal as an external excitation, and changes the free carrier concentration in its doped region by injecting current or applying voltage, thereby changing the absorption coefficient α of the optical waveguide (11) containing free carriers, so that the optical signal passing through the optical waveguide (11) is absorbed by the free carriers to realize the multiplication operation; Cross-switch matrix architecture; the cross-switch matrix architecture is formed by a set of mutually parallel input row waveguides (31) and a set of mutually parallel output column waveguides (32); At each intersection of the input row waveguide (31) and the output column waveguide (32) in the photonic computing array, there is a photonic computing unit (1) for multiplication operations. The optical waveguide (11) of each photonic computing unit (1) is coupled to an adjacent waveguide via a waveguide coupling device (2), which evanescently couples a portion of the optical power from the adjacent input row waveguide (31), wherein the coupled optical power depends on the length of the portion of the waveguide coupling device (2) that is placed adjacent to the input row waveguide (31) and extends parallel to the adjacent input row waveguide (31).

2. The photonic computing array as described in claim 1, characterized in that: A cross-optical waveguide (4) is provided at the intersection of each of the input row waveguide (31) and the output column waveguide (32) that intersects with it.

3. The photonic computing array as described in claim 1, characterized in that: The input row waveguide (31) is perpendicular to the output column waveguide (32).

4. The photonic computing array as described in claim 1, characterized in that: The wavelengths of the input optical signals in the input waveguides (31) of different rows are different.

5. The photonic computing array as described in claim 4, characterized in that: The input optical signal, under the action of the waveguide coupling device (2), has its optical power evenly distributed to each photonic computing unit (1) on the same row.

6. The photonic computing array as described in claim 1, characterized in that: The number of rows in the input row waveguide (31) and the number of columns in the output column waveguide (32) of the photonic computing array are at least greater than or equal to 2.

7. The photonic computing array as described in claim 1, characterized in that: The size of the photonic computing unit (1) is less than 100 μm.

8. The photonic computing array as described in claim 1, characterized in that: The voltage amplitude of the electrical signal used as an external excitation is less than 10V and the duration is less than 100μs.

9. The photonic computing array as described in claim 1, characterized in that: The relative positions of the optical waveguide (11) and the electro-optic modulator (12) may be on the same plane or not on the same plane.

10. The photonic computing array as described in any one of claims 1 to 9, characterized in that: The input end of the input row waveguide (31) of the photonic computing array is connected to a multiplexer (MUX), and the output end of the output column waveguide (32) is connected to a demultiplexer (DEMUX).

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