Memory system

Abstract

This invention provides a memory system capable of efficient operation. The memory system includes multiple semiconductor memory devices and a control device. Each semiconductor memory device includes: a first power pad, first to fourth signal pads for inputting first to fourth signals, a memory cell array, a sense amplifier, a data register, and control circuitry capable of performing data output operations. After the first power pad is powered, the control device performs a mode setting operation, which involves switching a third signal while at least one of the first or second signals is switched; then, it performs an initial setting operation, which is a read command to power on the semiconductor memory device; then, it sends a data output command instructing the semiconductor memory device to perform a data output operation, and the semiconductor memory device retrieves the data output command via a second signal pad.

Description

[0001] [Related Applications]

[0002] This application enjoys priority based on Japanese Patent Application No. 2022-031154 (filed on March 1, 2022). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field

[0003] This embodiment relates to a memory system. Background Technology

[0004] A memory system having multiple semiconductor memory devices and a control device is known. The semiconductor memory devices include: a memory cell array comprising a string of multiple memory cell transistors connected in series; and a control circuit connected to the memory cell array, outputting user data in response to an input of a command set containing command data and address data. Summary of the Invention

[0005] The present invention provides a memory system that can operate reliably.

[0006] One embodiment of the memory system includes a semiconductor memory device and a control device. The semiconductor memory device includes: a first signal pad capable of receiving a first signal; a second signal pad capable of receiving a second signal; a third signal pad capable of receiving a third signal; a fourth signal pad; a memory cell array comprising a string of multiple memory cell transistors connected in series; a sense amplifier module connected to the memory cell array; and a data register connected to the sense amplifier module, capable of storing data read from the memory cell array. After the control device is powered on, a mode setting operation is performed after a first predetermined time. The mode setting operation involves switching (toggling) the third signal sent to the third signal pad while at least one of the first signal sent to the first signal pad or the second signal sent to the second signal pad is set to a predetermined voltage. After a second predetermined time after the mode setting operation is completed, an initial setting operation is started. The initial setting operation includes sending a power-on read command to the second signal pad and receiving initial setting information sent from the fourth signal pad. After a third predetermined time after the initial setting operation is completed, a data output command instructing a data output operation is sent to the second signal pad. After a fourth predetermined time after sending the data output command, the data sent from the fourth signal pad is received. Attached Figure Description

[0007] Figure 1 This is a schematic block diagram showing the configuration of the memory system 10 in the first embodiment.

[0008] Figure 2 (a) is a schematic side view showing an example of the configuration of the package PKG, and (b) is a schematic top view showing an example of the configuration of the package PKG.

[0009] Figure 3 This is a schematic side view showing an example of the configuration of the memory system 10.

[0010] Figure 4 This is a schematic block diagram representing the structure of a memory die (MD).

[0011] Figure 5 This is a schematic circuit diagram representing a portion of a memory die (MD).

[0012] Figure 6 This is a schematic 3D diagram representing a portion of a memory die (MD).

[0013] Figure 7 This is a schematic circuit diagram representing a portion of a memory die (MD).

[0014] Figure 8 This is a schematic circuit diagram representing a portion of a memory die (MD).

[0015] Figure 9 This is a diagram used to illustrate the MODEA action mode.

[0016] Figure 10 This is a diagram used to illustrate the action mode MODEb.

[0017] Figure 11 It is a truth table used to describe the action mode MODEa.

[0018] Figure 12 It is a truth table used to describe the action mode MODEb.

[0019] Figure 13 It is a truth table used to describe the action mode MODEb.

[0020] Figure 14 It is a schematic waveform diagram used to illustrate the action mode MODEa.

[0021] Figure 15 It is a schematic waveform diagram used to illustrate the action mode MODEb.

[0022] Figure 16 It is a schematic timing diagram used to illustrate the action mode MODEa.

[0023] Figure 17 It is a schematic timing diagram used to illustrate the action mode MODEa.

[0024] Figure 18 (a) and (b) are schematic timing diagrams used to illustrate action mode MODEb.

[0025] Figure 19 It is a schematic timing diagram used to illustrate the action mode MODEb.

[0026] Figure 20 This is a schematic flowchart used to illustrate the mode setting operation of a comparative example semiconductor memory device.

[0027] Figure 21 This is a schematic timing diagram used to illustrate the mode setting operation of the comparative example semiconductor memory device.

[0028] Figure 22 This is a schematic flowchart used to explain the mode setting operation of the semiconductor memory device in the first embodiment.

[0029] Figure 23 This is a schematic timing diagram used to explain the mode setting operation of the semiconductor memory device in the first embodiment.

[0030] Figure 24 This is a schematic timing diagram used to illustrate the mode setting operation of the semiconductor memory device in the second embodiment. Detailed Implementation

[0031] Next, the memory system of the embodiment will be described in detail with reference to the accompanying drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the present invention.

[0032] Additionally, when referred to as a "memory system" in this specification, it sometimes means a system containing a controller die, such as a memory card or an SSD (Solid State Drive). Furthermore, it sometimes means a system containing a host, such as a smartphone, tablet, or personal computer.

[0033] Furthermore, in this specification, when the first component and the second component are described as "electrically connected," it can mean that the first component and the second component are directly connected, or that the first component and the second component are connected via wiring, semiconductor components, or transistors. For example, in the case of three transistors connected in series, even if the second transistor is in an OFF state, the first transistor is still "electrically connected" to the third transistor.

[0034] Additionally, in this specification, when it is stated that the first component is "connected" between the second and third components, it sometimes means that the first, second, and third components are connected in series, and the second component is connected to the third component via the first component.

[0035] [First Embodiment]

[0036] [Memory System 10]

[0037] Figure 1 is a schematic block diagram showing the configuration of the memory system 10 according to the first embodiment.

[0038] The memory system 10 reads, writes, erases, etc. user data according to signals sent from the host 20. The memory system 10 is, for example, a memory card, an SSD, or other systems capable of storing user data. The memory system 10 includes a plurality of packages PKG, and a controller die CD connected to the plurality of packages PKG and the host 20. Each package PKG includes a plurality of memory dies MD. Each memory die MD can store user data. The controller die CD includes, for example, a processor, a RAM (Random Access Memory), etc., and performs processes such as conversion between logical addresses and physical addresses, bit error detection / correction, garbage collection (compression), wear leveling, etc.

[0039] Figure 2 is a diagram showing a configuration example of the package PKG included in the memory system 10 of the present embodiment. More specifically, Figure 2 (a) is a schematic side view showing a configuration example of the package PKG, Figure 2 (b) is a schematic top view showing a configuration example of the package PKG. In addition, Figure 3 is a schematic side view showing a configuration example of the memory system 10. For ease of explanation, Figure 2 and Figure 3 part of the configuration is omitted.

[0040] As Figure 2As shown in (a), the package PKG of this embodiment includes a memory die mount substrate (MSB) and multiple memory dies (MDs) stacked on the MSB. A pad electrode P is provided at the end region in the Y direction on the upper surface of the MSB, and another portion of the pad electrode P is bonded to the lower surface of the memory die MD via an adhesive or the like. A pad electrode P is provided at the end region in the Y direction on the upper surface of the memory die MD, and other regions are bonded to the lower surface of another memory die MD via an adhesive or the like. Corresponding pad electrodes P are connected in common by bonding lines B between the multiple memory die MDs. Electrode terminals T are provided on the lower surface of the MSB. The pad electrodes P on the upper surface of the MSB and the electrode terminals T on the lower surface are respectively connected. The MSB may be, for example, a grid array substrate. The multiple memory die MDs and the bonding lines B are covered, for example, by a sealing resin (not shown) on the upper surface of the MSB.

[0041] In addition, such as Figure 2 As shown in (b), the memory die mounting substrate (MSB) and multiple memory dies (MDs) each have multiple pad electrodes P arranged in the X direction. The multiple pad electrodes P of each memory die MD correspond to the following external control terminals / CE, CLE, ALE, / WE, / RE, RE, / WP, data signal input / output terminals DQ0 to DQ7, data strobe signal input / output terminals DQS, / DQS, and terminal RY / / BY.

[0042] Multiple bonding pads P on the memory die mount substrate (MSB) and multiple memory dies (MDs) are interconnected via bonding wires B. For example, the bonding pads P corresponding to the external control terminal CLE and the bonding pads P corresponding to the external control terminal ALE in the multiple memory dies are interconnected. The same applies to other terminals. Therefore, the bonding pads P of each memory die MD inside the package PKG are connected to the outside of the package PKG via electrode terminals T on the lower surface of the memory die mount substrate (MSB).

[0043] Figure 3 This is a schematic side view illustrating a configuration example of the memory system 10 according to this embodiment. The memory system 10 includes a system mounting substrate (SSB), multiple memory dies (PKGs) disposed on the SSB, and a controller die (CD). The controller die (CD) and some of the PKGs are disposed on the upper surface of the SSB. Other PKGs are disposed on the lower surface of the SSB.

[0044] The controller die CD has multiple pad electrodes P. The pad electrodes P of the controller die CD are connected to the system mounting substrate SSB via bonding wires B. The electrode terminals T of multiple package PKGs are connected to the system mounting substrate SSB via solder balls SB. The pad electrodes P of the controller die CD and the electrode terminals T of the multiple package PKGs are connected by wiring (not shown) formed on the upper and lower surfaces of the system mounting substrate SSB. The upper and lower surfaces of the system mounting substrate SSB are connected by through electrodes TV.

[0045] A portion of the electrode terminals T of the package PKG disposed on the upper surface of the system mounting substrate SSB and a portion of the electrode terminals T of the package PKG disposed on the lower surface of the system mounting substrate SSB can be connected via a through electrode TV. More specifically, the electrode terminals T of the package PKG disposed on the upper surface of the system mounting substrate SSB corresponding to the data signal input / output terminals DQ0 to DQ7, and the electrode terminals T of the package PKG disposed on the lower surface of the system mounting substrate SSB corresponding to the data signal input / output terminals DQ0 to DQ7, can be connected via the through electrode TV.

[0046] When the package PKGs have the same configuration, for example, the electrode terminal T in one package PKG corresponding to the data signal input / output terminal DQ0 and the electrode terminal T in another package PKG corresponding to the data signal input / output terminal DQ7 are connected ( Figure 3 Here, one package PKG is referred to as the positive connection package PKGa, and the other package PKG is referred to as the reverse connection package PKGb. The electrode terminals T in the positive connection package PKGa corresponding to the data signal input / output terminals DQ1, 2, 3, 4, 5, 6, 7 are connected to the electrode terminals T in the reverse connection package PKGb corresponding to the data signal input / output terminals DQ6, 5, 4, 3, 2, 1, 0. This connection method is called mirror connection.

[0047] Furthermore, the electrode terminals T corresponding to other external control terminals are individually connected to the pad electrodes P of the controller die CD. For example, the electrode terminal T corresponding to the external control terminal CLE in one package PKG (positive connection package PKGa) and the electrode terminal T corresponding to the external control terminal CLE in another package PKG (reverse connection package PKGb) are connected to the pad electrodes P of the controller die CD using different wiring. Additionally, the electrode terminal T corresponding to the external control terminal ALE in one package PKG (positive connection package PKGa) and the electrode terminal T corresponding to the external control terminal ALE in another package PKG (reverse connection package PKGb) are connected to the pad electrodes P of the controller die CD using different wiring.

[0048] also, Figure 2 and Figure 3 The configurations shown are only examples, and the specific configurations can be adjusted appropriately. For example, Figure 2 in the example shown, multiple memory dies MD are stacked, and these configurations are connected using bonding wires B. However, the multiple memory dies MD can also be connected to each other via through electrodes or the like without going through the bonding wires B. Additionally, Figure 3 in the example shown, an example is illustrated where the electrode terminals T (data signal input / output terminals DQ0 to DQ7) of the package PKG disposed above and below the system mounting substrate SSB are mirror-connected via through electrodes TV. However, the electrode terminals T (data signal input / output terminals DQ0 to DQ7) of the package PKG may not be mirror-connected.

[0049] [Configuration of Memory Die MD]

[0050] Figure 4 is a schematic block diagram showing the configuration of the memory die MD of the first embodiment. Figure 5 is a schematic circuit diagram showing a part of the configuration of the memory die MD. Figure 6 is a schematic perspective view showing a part of the configuration of the memory die MD. Figure 7 and Figure 8 is a schematic circuit diagram showing a part of the configuration of the memory die MD. For ease of explanation, Figures 4-8 a part of the configuration is omitted.

[0051] In addition, Figure 4 multiple control terminals and the like are shown in. These multiple control terminals may be in a situation where they represent control terminals corresponding to a high-level signal (positive logic signal), a situation where they represent control terminals corresponding to a low-level signal (negative logic signal), and a situation where they represent control terminals corresponding to both a high-level signal and a low-level signal. Figure 4 In, the symbol of the control terminal corresponding to the low-level signal includes an overline. In this specification, the symbol of the control terminal corresponding to the low-level signal includes a slash (“ / ”). Additionally, Figure 4 the description is an example, and the specific form can be adjusted appropriately. For example, a part or all of the high-level signals can be made into low-level signals, or a part or all of the low-level signals can be made into high-level signals.

[0052] Furthermore, on one side of the multiple control terminals shown in Figure 4 arrows indicating the input / output direction are shown. Figure 4 In, the control terminal marked with an arrow from left to right can be used to input data or other signals from the controller die CD to the memory die MD. Figure 4In the diagram, the control terminals marked with arrows from right to left can be used to output data or other signals from the memory die MD to the controller die CD. Figure 4 The control terminals marked with bidirectional arrows can be used for the following two operations: inputting data or other signals from the controller die CD to the memory die MD, and outputting data or other signals from the memory die MD to the controller die CD.

[0053] like Figure 4 As shown, the memory die MD includes memory cell arrays MCA0 and MCA1 for storing user data, and peripheral circuitry PC connected to the memory cell arrays MCA0 and MCA1. Furthermore, in the following description, the memory cell arrays MCA0 and MCA1 are sometimes referred to as memory cell array MCA. Additionally, the memory cell arrays MCA0 and MCA1 are sometimes referred to as memory surfaces PLN0 and PLN1.

[0054] [Composition of a Memory Cell Array (MCA)]

[0055] like Figure 5 As shown, the memory cell array (MCA) has multiple memory blocks (BLK). Each of these memory blocks (BLK) has multiple string components (SU). Each of these string components (SU) has multiple memory strings (MS). One end of each of these memory strings (MS) is connected to the peripheral circuitry (PC) via a bit line (BL). The other end of each of these memory strings (MS) is connected to the peripheral circuitry (PC) via a common source line (SL).

[0056] A memory string (MS) includes: a drain-side selection transistor (STD) connected in series between the bit line (BL) and the source line (SL), multiple memory cells (MCs) (memory cell transistors), a source-side selection transistor (STS), and a source-side selection transistor (STSb). Hereinafter, the drain-side selection transistor (STD), the source-side selection transistor (STS), and the source-side selection transistor (STSb) will sometimes be referred to simply as selection transistors (STD, STS, STSb).

[0057] A memory cell (MC) is a field-effect transistor (FET) comprising a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film contains a charge storage film. The threshold voltage of the memory cell (MC) varies according to the amount of charge in the charge storage film. The memory cell (MC) stores one or more bits of user data. Furthermore, the gate electrodes of multiple memory cells (MCs) corresponding to a memory string (MS) are connected to word lines (WL). These word lines (WL) are shared with all memory strings (MS) in a memory block (BLK).

[0058] Select transistors (STD, STS, STSb) are field-effect transistors (FETs) comprising a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate electrodes of the select transistors (STD, STS, STSb) are connected to select gate lines (SGD, SGS, SGSb), respectively. The drain-side select gate line SGD corresponds to a string assembly SU and is shared with all memory strings MS in one string assembly SU. The source-side select gate line SGS is shared with all memory strings MS in the memory block BLK. The source-side select gate line SGSb is shared with all memory strings MS in the memory block BLK.

[0059] For example, such as Figure 6 As shown, the memory cell array MCA is disposed above the semiconductor substrate 100. Furthermore, Figure 6 In the example, a plurality of transistors Tr that constitute the peripheral circuit PC are provided between the semiconductor substrate 100 and the memory cell array MCA.

[0060] The memory cell array (MCA) has multiple memory blocks (BLKs) arranged in the Y direction. In addition, an inter-block insulating layer (ST) such as silicon oxide (SiO2) is provided between two adjacent memory blocks (BLKs) in the Y direction.

[0061] For example, such as Figure 6 As shown, the storage block BLK includes: multiple conductive layers 110 arranged in the Z direction; multiple semiconductor pillars 120 extending in the Z direction; and multiple gate insulating films 130 disposed between the multiple conductive layers 110 and the multiple semiconductor pillars 120.

[0062] The conductive layer 110 is a generally plate-shaped conductive layer extending in the X direction. The conductive layer 110 may include a laminated film containing barrier conductive films such as titanium nitride (TiN) and metal films such as tungsten (W). Alternatively, the conductive layer 110 may also contain, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101 such as silicon oxide (SiO2) is provided between the plurality of conductive layers 110 arranged in the Z direction.

[0063] In addition, two or more of the bottom conductive layers 110 among the multiple conductive layers 110 serve as source-side selected gate lines SGS, SGSb ( Figure 5 The gate electrodes of the multiple source-side selection transistors STS and STSb connected to them function. These multiple conductive layers 110 are electrically independent in each memory block BLK.

[0064] Additionally, multiple conductive layers 110 located further up serve as word lines WL ( Figure 5 ) and its connected multiple storage units MC ( Figure 5The gate electrode of the ) functions. These multiple conductive layers 110 are electrically independent in each memory block BLK.

[0065] Additionally, one or more conductive layers 110 located further above serve as drain-side selected gate lines SGD and multiple drain-side selected transistors STD connected thereto. Figure 5 The gate electrode of the conductive layers 110 functions. The width of these multiple conductive layers 110 in the Y direction is smaller than that of the other conductive layers 110.

[0066] A semiconductor layer 112 is provided below the conductive layer 110. The semiconductor layer 112 may, for example, contain polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). In addition, an insulating layer 101 such as silicon oxide (SiO2) is provided between the semiconductor layer 112 and the conductive layer 110.

[0067] Semiconductor layer 112 serves as the source line SL ( Figure 5 This allows it to perform its function. For example, the source line SL is a common setting for all memory blocks BLK contained in the memory cell array MCA.

[0068] For example, such as Figure 6 As shown, the semiconductor pillars 120 are arranged in a prescribed pattern in the X and Y directions. The semiconductor pillars 120 serve as a memory string (MS). Figure 5 The multiple memory cells MC and the channel regions of the selection transistors (STD, STS, STSb) contained therein function. The semiconductor pillar 120 is, for example, a semiconductor layer such as polysilicon (Si). For example, as... Figure 6 As shown, the semiconductor pillar 120 has a generally bottomed cylindrical shape, with an insulating layer 125 such as silicon oxide disposed in the central portion. In addition, the outer peripheral surfaces of the semiconductor pillar 120 are surrounded by conductive layers 110, which face each other.

[0069] An impurity region 121 containing N-type impurities such as phosphorus (P) is provided at the upper end of the semiconductor pillar 120. The impurity region 121 is connected to the bit line BL via contact Ch and contact Cb.

[0070] The gate insulating film 130 has a generally bottomed cylindrical shape covering the outer peripheral surface of the semiconductor pillar 120. The gate insulating film 130 may include, for example, a tunnel insulating film, a charge storage film, and a barrier insulating film deposited between the semiconductor pillar 120 and the conductive layer 110. The tunnel insulating film and the barrier insulating film may be, for example, insulating films such as silicon oxide (SiO2). The charge storage film may be, for example, a film capable of storing charge such as silicon nitride (Si3N4). The tunnel insulating film, the charge storage film, and the barrier insulating film have a generally cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor pillar 120, except for the contact portion between the semiconductor pillar 120 and the semiconductor layer 112.

[0071] Furthermore, the gate insulating film 130 may also have a floating gate, for example, containing polysilicon or other materials with N-type or P-type impurities.

[0072] Multiple conductive layers 110 have multiple contacts CC at their ends in the X direction. The multiple conductive layers 110 are connected to the surrounding circuit PC via these multiple contacts CC. For example... Figure 6 As shown, these multiple contacts CC extend in the Z direction and are connected to the conductive layer 110 at their lower ends. The contacts CC may, for example, comprise a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0073] [Composition of the peripheral circuit PC]

[0074] For example, such as Figure 4 As shown, the peripheral circuit PC includes line decoders RD0 and RD1, and sense amplifiers SA0 and SA1, respectively connected to the memory cell arrays MCA0 and MCA1. Additionally, the peripheral circuit PC includes a voltage generation circuit VG and a sequence generator SQC. Furthermore, the peripheral circuit PC includes: input / output control circuit (I / O), logic circuit CTR, address register ADR, command register CMR, status register STR, and data output timing adjustment unit TCT. In the following description, line decoders RD0 and RD1 are sometimes referred to as line decoders RD, and sense amplifiers SA0 and SA1 are sometimes referred to as sense amplifiers SA.

[0075] [The structure of the line decoder RD]

[0076] Line decoder RD( Figure 4 For example, Figure 5 As shown, it includes: an address decoder 22, which adds address data (Add( Figure 4 The address decoder 22 decodes the signal; and the block selection circuit 23 and voltage selection circuit 24 transmit the operating voltage to the memory cell array MCA according to the output signal of the address decoder 22.

[0077] Address decoder 22 has multiple block select lines BLKSEL and multiple voltage select lines 33. Address decoder 22, for example, refers sequentially to address register ADR based on control signals from sequence generator SQC. Figure 4 The row address RA is decoded, and the corresponding block selection transistor 35 and voltage selection transistor 37 are turned on (ON), while other block selection transistors 35 and voltage selection transistors 37 are turned off. For example, the voltage of the specified block selection line BLKSEL and voltage selection line 33 is set to "H", and other voltages are set to "L". Furthermore, when using P-channel transistors instead of N-channel transistors, a reverse voltage is applied to these lines.

[0078] Furthermore, in the example shown, the address decoder 22 has one block selection line (BLKSEL) for each storage block (BLK). However, this configuration can be modified appropriately. For example, one block selection line (BLKSEL) can also be set for every two or more storage blocks (BLK).

[0079] The block selection circuit 23 includes multiple block selection sections 34 corresponding to memory blocks BLK. Each of these multiple block selection sections 34 includes multiple block selection transistors 35 corresponding to word lines WL and select gate lines (SGD, SGS, SGSb). The block selection transistors 35 are, for example, field-effect transistors. The drain electrodes of the block selection transistors 35 are electrically connected to the corresponding word lines WL or select gate lines (SGD, SGS, SGSb). The source electrodes are electrically connected to the voltage supply line 31 via wiring CG and voltage selection circuit 24. The gate electrode is commonly connected to the corresponding block selection line BLKSEL.

[0080] In addition, the block selection circuit 23 also includes a plurality of transistors (not shown). These transistors are field-effect transistors connected to the select gate lines (SGD, SGS, SGSb) and the supplied ground voltage V. SS These transistors supply ground voltage V to the select gate lines (SGD, SGS, SGSb) contained in the non-select memory block BLK. SS In addition, the multiple word lines (WL) contained in the non-selected storage block (BLK) are in a floating state.

[0081] The voltage selection circuit 24 includes multiple voltage selection sections 36 corresponding to word lines WL and select gate lines (SGD, SGS, SGSb). Each of these multiple voltage selection sections 36 includes multiple voltage selection transistors 37. The voltage selection transistors 37 are, for example, field-effect transistors. The drain terminals of the voltage selection transistors 37 are electrically connected to the corresponding word lines WL or select gate lines (SGD, SGS, SGSb) via wiring CG and block selection circuit 23. The source terminals are electrically connected to the corresponding voltage supply lines 31. The gate electrodes are connected to the corresponding voltage selection lines 33.

[0082] [Composition of the Sensing Amplifier SA]

[0083] Sensing amplifiers SA0, SA1 ( Figure 4 Each of the two modules has a sense amplifier module (SAM0, SAM1) and a high-speed cache memory (CM0, CM1, data register). The high-speed cache memory (CM0, CM1) has latch circuits (XDL0, XDL1).

[0084] In addition, in the following description, the sense amplifier modules SAM0 and SAM1 are sometimes referred to as sense amplifier modules SAM, the cache memory CM0 and CM1 are referred to as cache memory CM, and the latch circuits XDL0 and XDL1 are referred to as latch circuits XDL.

[0085] The sense amplifier module (SAM) includes, for example, sense circuits corresponding to multiple bit lines (BL) and multiple latch circuits connected to the sense circuits.

[0086] The cache memory CM has multiple latch circuits XDL. Each latch circuit XDL is connected to a latch circuit within the sense amplifier module SAM. The latch circuits XDL store, for example, user data Dat written to or read from the memory unit MC.

[0087] For example, such as Figure 7 As shown, the column decoder COLD is connected to the cache memory CM. The column decoder COLD will access the address register ADR (... Figure 4 The column address CA stored in the memory is decoded, and the latch circuit XDL corresponding to the column address CA is selected.

[0088] Furthermore, the user data Dat contained in these multiple latch circuits XDL is sequentially transmitted to the latch circuits within the sense amplifier module SAM during write operations. Additionally, the user data Dat contained in the latch circuits within the sense amplifier module SAM is sequentially transmitted to the latch circuits XDL during read operations. Furthermore, the user data Dat contained in the latch circuits XDL is sequentially transmitted to the input / output control circuit I / O via the column decoder COLD and the multiplexer MPX during the data output operations described below.

[0089] [Construction of the voltage generation circuit VG]

[0090] Voltage generation circuit VG ( Figure 4 For example, Figure 5 The circuit shown is connected to multiple voltage supply lines 31. The voltage generation circuit VG includes, for example, a step-down circuit such as a regulator and a step-up circuit such as a charge pump circuit 32. These step-down and step-up circuits are connected to the supplied power supply voltage V. CC and grounding voltage V SS ( Figure 4 The voltage supply lines are connected to, for example, the reference voltage supply lines. Figure 2 , Figure 3The pad electrode P is connected as described. The voltage generation circuit VG, for example, generates multiple operating voltages to be applied to the bit line BL, source line SL, word line WL, and select gate lines (SGD, SGS, SGSb) during read, write, and erase operations for the memory cell array MCA, according to control signals from the sequence generator SQC, and simultaneously outputs these voltages to multiple voltage supply lines 31. The operating voltages output from the voltage supply lines 31 are appropriately adjusted according to the control signals from the sequence generator SQC.

[0091] [Structure of Sequence Generator (SQC)]

[0092] Sequence generator SQC ( Figure 4 According to the command data Cmd stored in the command register CMR, internal control signals are output to the line decoders RD0 and RD1, the sense amplifier modules SAM0 and SAM1, and the voltage generation circuit VG. In addition, the sequence generator SQC outputs the status data Stt, which represents the status of the memory die MD, to the status register STR.

[0093] Additionally, the sequence generator SQC generates a ready / busy signal and outputs it to the RY / / BY terminal. The RY / / BY terminal is in the "L" state when performing operations that supply voltage to the memory cell array MCA, such as read, write, or erase operations; otherwise, it is in the "H" state. Furthermore, even when performing operations that do not supply voltage to the memory cell array MCA, such as data output or status read operations, the RY / / BY terminal will not be in the "L" state. During the period when the RY / / BY terminal is in the "L" state (busy period), access to the memory die MD is essentially prohibited. Conversely, during the period when the RY / / BY terminal is in the "H" state (ready period), access to the memory die MD is permitted. Furthermore, for example, using a reference... Figure 2 , Figure 3 The pad electrode P described herein is used to realize the terminal RY / / BY.

[0094] Additionally, the sequence generator SQC has a feature register FR. The feature register FR is a register that stores feature data Fd. Feature data Fd may contain, for example, control parameters for the memory die MD. Feature data Fd may also contain values ​​indicating which of the following operating modes, MODEa and MODEb, the memory die MD should operate in.

[0095] [Structure of the Address Register (ADR)]

[0096] like Figure 4As shown, the address register ADR is connected to the input / output control circuit (I / O) and stores the address data Add input from the I / O circuit. The address register ADR may have multiple 8-bit register rows. These register rows, for example, store the address data Add corresponding to the internal action being performed, such as a read, write, or erase operation.

[0097] In addition, the address data Add, for example, includes the column address CA ( Figure 4 ) and row address RA ( Figure 4 The row address RA, for example, contains: a specific outgoing storage block BLK (). Figure 5 The block address of the specific output string component SU and word line WL, the memory plane address of the specific output memory cell array MCA (memory plane), and the chip address of the specific output memory die MD.

[0098] [Composition of the Command Register (CMR)]

[0099] The command register (CMR) is connected to the input / output control circuit (I / O) and stores the command data (Cmd) input from the I / O. The command register CMR, for example, has at least one set of 8-bit register rows. When the command data Cmd is stored in the command register CMR, a control signal is sent to the sequence generator (SQC).

[0100] [The structure of the status register STR]

[0101] The status register STR is connected to the input / output control circuit (I / O) and stores status data Stt output to the I / O circuit. The status register STR may have multiple 8-bit register lines. For example, when performing internal operations such as read, write, or erase, each register line stores status data Stt related to the ongoing internal operation. Additionally, each register line may store ready / busy information for memory cell arrays MCA0 and MCA1.

[0102] [Structure of the Data Output Timing Adjustment Unit (TCT)]

[0103] The data output timing adjustment unit (TCT) is connected to the bus line DB between the cache memories CM0 and CM1 and the input / output control circuit (I / O). For example, when the following data output operations are performed continuously on the cache memories CM0 and CM1, in order to start the data output operation of the cache memory CM1 immediately after the data output operation of the cache memory CM0 is completed, the data output timing adjustment unit (TCT) adjusts the start time of the data output operation of the cache memory CM1.

[0104] [Composition of Input / Output Control Circuit (I / O)]

[0105] Input / output control circuit I / O ( Figure 4 It features: data signal input / output terminals DQ0~DQ7, data strobe signal input / output terminals DQS, / DQS, shift register, buffer circuit, and connection change circuit SW.

[0106] For example, using references Figure 2 , Figure 3 The pad electrodes P described herein are used to implement data signal input / output terminals DQ0 to DQ7, and data strobe signal input / output terminals DQS and / DQS, respectively. Data input via data signal input / output terminals DQ0 to DQ7, corresponding to internal control signals from the logic circuit CTR, is input from the buffer circuit to the cache memory CM, address register ADR, or command register CMR. Conversely, data output via data signal input / output terminals DQ0 to DQ7, corresponding to internal control signals from the logic circuit CTR, is input from the cache memory CM or status register STR to the buffer circuit.

[0107] Signals input via data strobe input / output terminals DQS and / DQS (e.g., data strobe signals and their complementary signals) are used when data is input via data signal input / output terminals DQ0 to DQ7. The data input via data signal input / output terminals DQ0 to DQ7 is captured into a shift register within the input / output control circuit I / O at the times of the rising edge of the voltage at data strobe input / output terminal DQS (input signal switching) and the falling edge of the voltage at data strobe input / output terminal / DQS (input signal switching), and at the times of the falling edge of the voltage at data strobe input / output terminal DQS (input signal switching) and the rising edge of the voltage at data strobe input / output terminal / DQS (input signal switching).

[0108] For example, Figure 8 As shown, the data signal input / output terminals DQ0 to DQ7 and the data strobe signal input / output terminals DQS and / DQS are connected to the input circuit 201 and the output circuit 202, respectively. The input circuit 201 is, for example, a comparator or other receiver. The output circuit 202 is, for example, an OCD (Off-Chip Driver) circuit or other driver.

[0109] The connection change circuit SW is a circuit that changes the order of data input from the external memory die MD to the data signal input / output terminals DQ0-DQ7 and then retrieves it into the memory die MD. More specifically, for example, when command data Cmd or address data Add is input to the data signal input / output terminals DQ0-DQ7 of the memory die MD contained in the reverse connection package PKGb, the connection change circuit SW changes the data order of the command data Cmd or address data Add and then retrieves it into the command register CMR or address register ADR. On the other hand, when command data Cmd or address data Add is input to the data signal input / output terminals DQ0-DQ7 of the memory die MD contained in the forward connection package PKGa, the connection change circuit SW does not change the data order and retrieves it into the command register CMR or address register ADR. It can also be configured such that when feature data Fd is input to the data signal input / output terminals DQ0-DQ7 of the memory die MD contained in the reverse connection package PKGb, the connection change circuit SW also changes the data order. Alternatively, it can be configured such that when characteristic data Fd or status data Stt is output from the memory die MD contained in the reverse connection package PKGb, the connection change circuit SW changes the data order and outputs it to the data signal input / output terminals DQ0 to DQ7.

[0110] For example, in such Figure 3 In the connection configuration shown, when the controller die CD outputs command data Cmd corresponding to "70h" (01110000), a signal corresponding to "70h" (01110000) is input to the data signal input / output terminals DQ0 to DQ7 of the memory die MD contained in the positive connection package PKGa, and a signal corresponding to "8Fh" (10001111) is input to the data signal input / output terminals DQ0 to DQ7 of the memory die MD contained in the reverse connection package PKGb. Furthermore, the command register CMR of the memory die MD contained in the positive connection package PKGa directly stores the data corresponding to "70h" (01110000), while the command register CMR of the memory die MD contained in the reverse connection package PKGb stores the data corresponding to "70h" (01110000) via the connection change circuit SW.

[0111] Each memory die MD determines whether it is contained in the forward interconnect package PKGa or the reverse interconnect package PKGb, based on the feature data Fd stored in the feature register FR.

[0112] [Construction of the CTR logic circuit]

[0113] Logic circuit CTR ( Figure 4It includes: multiple external control terminals / CE, CLE, ALE, / WE, / RE, RE, / WP, and logic circuitry connected to these external control terminals / CE, CLE, ALE, / WE, / RE, RE, / WP. The logic circuitry CTR receives external control signals from the controller die CD via the external control terminals / CE, CLE, ALE, / WE, / RE, RE, / WP, and outputs internal control signals to the input / output control circuitry (I / O) accordingly.

[0114] For example, Figure 8 As shown, the external control terminals / CE, CLE, ALE, / WE, / RE, RE, and / WP are connected to the input circuit 201. In addition, the external control terminals CLE, ALE, and / WP are connected to the output circuit 202, in addition to being connected to the input circuit 201. For example, using reference... Figure 2 , Figure 3 The pad electrodes P described are used to implement the external control terminals / CE, CLE, ALE, / WE, / RE, RE, and / WP, respectively.

[0115] Signals input via the external control terminal / CE (e.g., chip enable signal) are used when selecting the memory die MD. A memory die MD with "L" input to the external control terminal / CE is in a state where it can input / output user data Dat, command data Cmd, address data Add, and status data Stt (hereinafter, sometimes simply referred to as "data"). A memory die MD with "H" input to the external control terminal / CE is in a state where it cannot input / output data. Furthermore, as... Figure 8 As shown, the external control terminal / CE is connected to the input circuit 201.

[0116] Signals input via the external control terminal CLE (e.g., command latch enable signal) are used when using the command register CMR. Furthermore, in this embodiment, signals input via the external control terminal CLE are used when using the command register CMR, and are also used as command data Cmd and address data Add. Furthermore, status data Stt is output from the status register STR via the external control terminal CLE. The function of the external control terminal CLE will be described below.

[0117] Signals input via the external control terminal ALE (e.g., the address latch enable signal) are used when using the address register ADR. Furthermore, in this embodiment, signals input via the external control terminal ALE are used when using the address register ADR, and are also used as command data Cmd and address data Add. Furthermore, status data Stt is output from the status register STR via the external control terminal ALE. The functions of the external control terminal ALE will be described below.

[0118] Signals input via the external control terminal / WE (e.g., write enable signal) are used when inputting data from the controller die CD to the memory die MD. The function of the external control terminal / WE will be described below.

[0119] Signals input via external control terminals / RE and RE (e.g., read enable signal and its complementary signal) are used when outputting data via data signal input / output terminals DQ0 to DQ7. Data output from data signal input / output terminals DQ0 to DQ7 is switched at the falling edge (input signal switching) and rising edge (input signal switching) of the voltage at external control terminal / RE, and at the falling edge (input signal switching) and rising edge (input signal switching) of the voltage at external control terminal / RE.

[0120] Signals input via the external control terminal / WP (e.g., write protection signal) are used to restrict the input of user data such as Dat from the controller die CD to the memory die MD. Signals input via the external control terminal / WP can be used as command data Cmd and address data Add, and status data Stt can also be output from the status register STR via the external control terminal / WP.

[0121] [Motion Mode MODEa and Action Mode MODEb]

[0122] The semiconductor memory device of this embodiment can operate in operating mode MODEa and operating mode MODEb. Hereinafter, refer to... Figures 9-19 The descriptions of action modes MODEa and MODEb are provided.

[0123] [The function of external terminals in each mode]

[0124] Figure 9 This is a schematic diagram used to explain the function of the signal input / output terminals and external control terminals when the memory die MD is set to operating mode MODEa. Figure 10 This is a schematic diagram used to explain the function of the signal input / output terminals and external control terminals when the memory die MD is set to operating mode MODEb. Furthermore, in the following description, data signal input / output terminals DQ0 to DQ7 may sometimes be referred to as data signal input / output terminals DQ<7:0>.

[0125] In the action mode MODEa, for example... Figure 9 As shown, the data signal input / output terminals DQ<7:0> are used for the input / output of user data Dat and the output of status data Stt, and for the input of command data Cmd and address data Add.

[0126] On the other hand, in the action mode MODEb, for example... Figure 10 As shown, the data signal input / output terminals DQ<7:0> are used for the input and output of user data Dat, but not for the input of command data Cmd and address data Add, or the output of status data Stt. In operation mode MODEb, the external control terminals CLE and ALE are used for the input of command data Cmd and address data Add, and the output of status data Stt.

[0127] [The function of external terminals in MODEa]

[0128] Figure 11 This is a truth table used to explain the function of external terminals when the memory die MD is set to operating mode MODEa. Furthermore, Figure 11 In this code, "Z" indicates that either "H" or "L" can be used as the input. "X" indicates that the input signal is fixed at either "H" or "L". "Input" indicates data input. "Output" indicates data output.

[0129] When command data Cmd is input in the operation mode MODEa, the controller die CD sets the voltage of the data signal input / output terminal DQ<7:0> to "H" or "L" for each bit of the 8-bit command data Cmd. When "H" is input to the external control terminal CLE and "L" is input to the external control terminal ALE, the external control terminal / WE is boosted from "L" to "H".

[0130] When the external control terminals CLE and ALE are input with "H" or "L", the data input via the data signal input / output terminals DQ<7:0> is stored as command data Cmd in the buffer memory within the input / output control circuit I / O, and then transferred to the command register CMR. Figure 4 ).

[0131] Additionally, when the address data Add is input, the controller die CD sets the voltage of the data signal input / output terminal DQ<7:0> to "H" or "L" for each bit of the 8-bit data that constitutes the address data Add. When "L" is input to the external control terminal CLE and "H" is input to the external control terminal ALE, the external control terminal / WE is boosted from "L" to "H".

[0132] When the external control terminals CLE and ALE are input with "L" or "H", the data input via the data signal input / output terminals DQ<7:0> is stored as address data Add in the buffer memory within the input / output control circuit I / O and then transferred to the address register ADR. Figure 4 ).

[0133] Additionally, when user data Dat is input, the controller die CD sets the voltage of the data signal input / output terminals DQ<7:0> to "H" or "L" for each bit of the 8-bit data constituting user data Dat. When "L" is input to the external control terminal CLE and "L" is input to the external control terminal ALE, the input signals of the data strobe signal input / output terminals DQS and / DQS are switched.

[0134] When both external control terminals CLE and ALE are input with "L", the data input via the data signal input / output terminals DQ<7:0> is stored as user data Dat in the buffer memory within the input / output control circuit I / O, and then transferred to the high-speed cache memory CM via the bus DB. Figure 4 ).

[0135] Additionally, when outputting user data Dat, the controller die CD switches the input signals of external control terminals / RE and RE. Subsequently, 8 bits of the desired user data Dat are output to data signal input / output terminals DQ0 to DQ7. Furthermore, the output signals of data strobe signal input / output terminals DQS and / DQS are switched.

[0136] Additionally, when the memory die MD is set to standby mode, the controller die CD, for example, inputs "H" to the external control terminal / CE.

[0137] Additionally, when the memory die MD is set to bus idle state, the controller die CD, for example, inputs "H" to the external control terminal / WE.

[0138] [The function of external terminals in MODEb]

[0139] Figure 12 and Figure 13 This is a truth table used to explain the function of external terminals when the memory die MD is set to operating mode MODEb. Furthermore, Figure 12 and Figure 13 In this code, "Z" indicates that either "H" or "L" can be used as the input. "X" indicates that the input signal is fixed at either "H" or "L". "Input" indicates data input. "Output" indicates data output.

[0140] As described above, in operation mode MODEb, the external control terminals CLE and ALE are used for inputting command and address data, and for outputting status data Stt. Here, refer to... Figure 15As described below, when command data Cmd or address data Add is input in Operation Mode MODEb, the controller die CD inputs the following signal to the memory die MD, indicating whether the next input data is command data Cmd or address data Add. This signal will be referred to as the input / output data selection signal. In Operation Mode MODEb, the input / output data selection signal can be called the header, and the command data Cmd, address data Add, status data Stt, etc., input / output following the input / output data selection signal can be called the body. Furthermore, a combination of one header and one body can be called a frame. Additionally, the input / output data selection signal can also be called the frame selection signal.

[0141] Figure 12 FSel (indicates the input / output data selection signal during input) Figure 15 The function of the external control terminals. Figure 13 S_In represents the period after the input / output data selection signal is input. Figure 15 ) or during the period S_Out( Figure 18 (b)) Function of the external control terminal.

[0142] When the input / output data selection signal for inputting command data Cmd is input during the FSel input period, the controller die CD, for example, in the state of inputting "H" to the external control terminal CLE and inputting "L" to the external control terminal ALE, causes the external control terminal / WE to be boosted from "L" to "H".

[0143] When "H" is input to external control terminal CLE and "L" is input to external control terminal ALE during period FSel, the data input during period S_In immediately following FSel is stored as command data Cmd in the buffer memory within the input / output control circuit I / O and transferred to the command register CMR. Figure 4 ).

[0144] Additionally, when the input / output data selection signal for inputting address data Add is input during the FSel input period, the controller die CD, for example, in the state of inputting "L" to the external control terminal CLE and inputting "H" to the external control terminal ALE, causes the external control terminal / WE to be boosted from "L" to "H".

[0145] When during period FSel, the external control terminal CLE is input with "L" and the external control terminal ALE is input with "H", the data input during period S_In immediately following period FSel is stored as address data in the buffer memory within the input / output control circuit I / O and transferred to the address register ADR. Figure 4 ).

[0146] When command data Cmd or address data Add is input during the S_In period, the controller die CD, for example, sets the voltage of the external control terminals CLE and ALE to "H" or "L" for each bit corresponding to the 2 bits constituting the command data Cmd or address data Add, so that the external control terminal / WE is boosted from "L" to "H".

[0147] Furthermore, when user data Dat is input in operation mode MODEb, the controller die CD sets the voltage of the data signal input / output terminals DQ<7:0> to "H" or "L" corresponding to each bit of the 8-bit data constituting user data Dat. While inputting "H" or "L" to the external control terminals / RE and RE, the input signals to the data strobe signal input / output terminals DQS and / DQS are switched. This operation can be performed during FSel or during S_In.

[0148] In operation mode MODEb, the data input via the data signal input / output terminals DQ<7:0> is stored as user data Dat in the buffer memory within the input / output control circuit I / O, and then transmitted to the high-speed buffer memory CM via the bus DB.

[0149] When the input / output data selection signal for outputting status data Stt is input at FSel during the period, the controller die CD, for example, in the state of inputting "L" to external control terminal CLE and inputting "L" to external control terminal ALE, causes external control terminal / WE to boost from "L" to "H".

[0150] When, during period FSel, the external control terminal CLE is input with "L" and the external control terminal ALE is input with "L", and the status data Stt is output during period S_Out immediately following period FSel, the controller die CD, for example, steps down the input signal of the external control terminal / WE. Figure 13 Subsequently, using the output circuit 202, two bits of the status data Stt are output from the external control terminals CLE and ALE to the controller die CD.

[0151] Additionally, when the memory die MD is set to standby mode, the controller die CD, for example, inputs "H" to the external control terminal / CE.

[0152] Additionally, when the memory die MD is set to bus idle state, the controller die CD, for example, inputs "H" to the external control terminal / WE.

[0153] [Signal input / output examples in each mode]

[0154] Figure 14 and Figure 15This is a schematic waveform diagram used to illustrate the operation of the memory die MD in the first embodiment.

[0155] Figure 14 The waveforms of the input command data Cmd and address data Add are shown when the memory die MD is set to the operation mode MODEa. Figure 14 In the example shown, at time t101, the controller die CD inputs command data Cmd to the memory die MD. Additionally, at time t102, the controller die CD inputs address data Add to the memory die MD. Furthermore, in the example shown, between times t102 and t103, 8 bits of data constituting the address data Add are input, but the number of cycles can be less than or more than 5. Also, at time t103, the controller die CD inputs command data Cmd to the memory die MD. Finally, at time t104, actions such as readout begin, causing the voltage at terminals RY / / BY to drop from "H" to "L".

[0156] Figure 15 The waveforms of the input command data Cmd and address data Add are shown when the memory die MD is set to the operation mode MODEb. Figure 15 In the example, "L" and "H" are input to the external control terminal / WE at approximately fixed intervals. Furthermore, the period from the start of one voltage reduction of the input signal to the external control terminal / WE at a specified time until the next voltage reduction is denoted as the period FSel. Additionally, the period from the start of voltage reduction of the input signal to the external control terminal / WE at the end of period FSel until the input signal to the external control terminal / WE is further reduced four times is denoted as the period S_In.

[0157] Figure 15 In the example, during the period FSel from time t201 to t202, the controller die CD inputs the input / output data selection signal of the specified input command data Cmd to the memory die MD.

[0158] Additionally, during the period S_In from time t202 to t203, the controller die CD inputs command data Cmd to the memory die MD.

[0159] Here, Figure 15In the example, during S_In, the controller die CD divides the 8-bit command data Cmd into 4 cycles, inputting it into the memory die MD in 2-bit units. For example, the 8-bit command data Cmd is set to bits "7" to "0". First, in the data input of the first cycle, when the voltage of the external control terminals CLE and ALE is set to "H" or "L" corresponding to bits "7" and "6", the external control terminal / WE is boosted from "L" to "H". The data input of the second to fourth cycles is the same; when the voltage of the external control terminals CLE and ALE is set to "H" or "L" corresponding to bits "5", "4", "3", "2", and "1", "0", the external control terminal / WE is boosted from "L" to "H".

[0160] Additionally, during the period FSel from time t203 to t204, the controller die CD inputs an input / output data selection signal with the specified input address data Add to the memory die MD.

[0161] Additionally, during the period S_In from time t204 to t205, the controller die CD inputs address data Add to the memory die MD.

[0162] Here, Figure 15 In the example, during the S_In period, the controller die CD divides the 8-bit data that constitutes the address data Add into 4 cycles and inputs it into the memory die MD in 2-bit units.

[0163] Furthermore, although the illustration is omitted, the same applies to times t205 to t206, where the data constituting the address data Add is entered in units of 2 bits.

[0164] Additionally, during the period FSel from time t206 to t207, the input / output data selection signal for the specified input command data Cmd is input, similar to the input / output data selection signal from time t201 to t202.

[0165] Additionally, during the period S_In from time t207 to t208, the controller die CD inputs command data Cmd to the memory die MD. Also, during S_In, at the moment when the external control terminal / WE finally rises from "L" to "H", readout operations begin, causing the voltage at terminal RY / / BY to drop from "H" to "L".

[0166] Furthermore, during period FSel, when the controller die CD inputs an input / output data selection signal to the memory die MD specifying input command data Cmd or address data Add, the following period is period S_In. However, during period FSel, when the controller die CD inputs an input / output data selection signal to the memory die MD intended to output status data Stt, as described below, the following period is period S_Out.

[0167] [action]

[0168] Next, the operation of the memory die MD will be explained.

[0169] The memory die (MD) is configured to perform a read operation. The read operation involves using the sense amplifier module (SAM) to read user data (Dat) from the memory cell array (MCA) and transferring the read user data (Dat) to the latch circuit (XDL). During the read operation, the user data (Dat) read from the memory cell array (MCA) is transferred to the latch circuit (XDL) via the bit line (BL) and the sense amplifier module (SAM).

[0170] Furthermore, the memory die MD is configured to perform data output operations. The data output operation is the action of outputting the user data Dat contained in the latch circuit XDL to the controller die CD. During the data output operation, the user data Dat contained in the latch circuit XDL is referenced... Figure 7 The described column decoder COLD, multiplexer MPX, bus wiring DB, and input / output control circuit I / O outputs to the controller die CD.

[0171] Furthermore, the memory die MD is configured to perform status reads. A status read is the operation of outputting the status data Stt contained in the status register STR to the controller die CD. During a status read, the status data Stt contained in the status register STR is output to the controller die CD via the input / output control circuit I / O or the logic circuit CTR.

[0172] [Read-out and data output actions in MODEa]

[0173] Figure 16 This is a schematic timing diagram illustrating the execution of read and data output actions in the MODEa action mode. Figure 16 In the example, the memory die MD is set to the action mode MODEa.

[0174] Figure 16In the example, firstly, command data "00h", address data Add, and command data "30h" are sequentially input via the data signal input / output terminals DQ<7:0>. Command data "00h" is the initial command data Cmd input in the command set indicating the read operation. Command data "30h" is the final command data Cmd input in the command set indicating the read operation.

[0175] With the input of command data "00h", address data Add, and command data "30h", the read operation begins, and the voltage at terminal RY / / BY drops from "H" to "L". Meanwhile, user data Dat is transmitted to the latch circuit XDL. At the end of the read operation, the voltage at terminal RY / / BY rises from "L" to "H".

[0176] Next, command data "05h", address data Add, and command data "E0h" are sequentially input via the data signal input / output terminals DQ<7:0>. Command data "05h" is the initial command data Cmd input in the command set indicating the data output action. Command data "E0h" is the final command data Cmd input in the command set indicating the data output action.

[0177] With the input of command data "05h", address data Add, and command data "E0h", after a specified standby time, the controller die CD switches the input signals of the external control terminals / RE and RE. This initiates the data output operation, outputting user data Dat via the data signal input / output terminal DQ.

[0178] Figure 17 This is a schematic timing diagram representing other situations when performing read and data output actions in the action mode MODEa. Figure 17 In the example, the memory die MD is set to the action mode MODEa.

[0179] Figure 17 In the example, firstly, command data "00h", address data Add, and command data "30h" are sequentially input via the data signal input / output terminals DQ<7:0>. The address data Add included in this command set contains the memory plane PLN0 (which is the target of the read operation). Figure 4 The information is used as the memory surface address.

[0180] With the input of command data "00h", address data Add, and command data "30h", the reading operation of memory surface PLN0 begins, and user data Dat is transferred to latch circuit XDL0.

[0181] Next, command data "00h", address data Add, and command data "30h" are sequentially input via the data signal input / output terminals DQ<7:0>. The address data Add included in this command set contains the memory plane PLN1 (which is the target of the read operation). Figure 4 The information is used as the memory surface address.

[0182] With the input of command data "00h", address data Add, and command data "30h", the reading operation of memory surface PLN1 begins, and user data Dat is transferred to latch circuit XDL1.

[0183] Next, the command data "70h" is input via the data signal input / output terminals DQ<7:0>. The command data "70h" is the command data indicating the status read. With the input of the command data "70h", the status is read, and the status data Stt is output via the data signal input / output terminals DQ<7:0>.

[0184] Next, command data "05h", address data Add, and command data "E0h" are sequentially input via the data signal input / output terminals DQ<7:0>. The address data Add included in this command set contains the memory plane PLN0 (which is the target of the data output action). Figure 4 The information is used as the memory surface address.

[0185] With the input of command data "05h", address data Add, and command data "E0h", after a specified standby time, the controller die CD switches the input signals of external control terminals / RE and RE. This initiates data output to memory surface PLN0, outputting user data "DataOut" via data signal input / output terminals DQ<7:0>.

[0186] After the data output operation to memory surface PLN0 is completed, the command data "70h" is input via the data signal input / output terminal DQ<7:0>. With the input of the command data "70h", the status is read again, and the status data Stt is output via the data signal input / output terminal DQ<7:0>.

[0187] Next, similar to the data output operation for PLN0, command data "05h", address data Add, and command data "E0h" are sequentially input via the data signal input / output terminals DQ<7:0>. The address data Add included in this command set contains the memory plane PLN1 (which is the target of the data output operation). Figure 4 The information is used as the memory surface address.

[0188] After a specified time, the controller CD switches the input signals of the external control terminals / RE and RE. This initiates data output to the memory side PLN1, outputting user data "DataOut" via the data signal input / output terminals DQ<7:0>.

[0189] [Read-out actions and data output actions in the MODEb mode]

[0190] Figure 18 (a) is a schematic timing diagram showing the situation when the read action and data output action are executed in action mode MODEb. Figure 18 In example (a), the memory die MD is set to the action mode MODEb.

[0191] Figure 18 In example (a), firstly, a command set containing command data "00h" is input via external control terminals CLE and ALE. Next, a command set containing command data "05h" is input via external control terminals CLE and ALE. Furthermore, in operation mode MODEb, data input / output via data signal input / output terminals DQ<7:0> and data input / output via external control terminals CLE and ALE can be performed independently at different times. For example, Figure 18 In example (a), the input of these command sets is performed during the execution of the data output action (during the switching of the input signals of the external control terminal / RE, RE).

[0192] [Reading the state action in the MODEb mode]

[0193] Figure 18 (b) is a schematic timing diagram showing the situation when the state reading action is executed in action mode MODEb. Figure 18 In example (b), the memory die MD is set to the operating mode MODEb.

[0194] Figure 18 In example (b), "L" and "H" are input to the external control terminal / WE at approximately fixed intervals. Furthermore, the period from the start of one voltage reduction of the input signal to the external control terminal / WE at a specified time to the start of another voltage reduction is denoted as the period FSel. Additionally, the period from the start of voltage reduction of the input signal to the external control terminal / WE at the end of period FSel to the point where the input signal to the external control terminal / WE is reduced four times is denoted as period S_In or period S_Out.

[0195] In other words, during period FSel, when the controller die CD inputs an input / output data selection signal to the memory die MD specifying input command data Cmd or address data Add, the period immediately following it becomes period S_In; during period FSel, when the controller die CD inputs an input / output data selection signal to the memory die MD intended to output status data Stt, the period immediately following it becomes period S_Out.

[0196] First, input the command data "70h" via the external control terminals CLE and ALE. Next, input / output data selection signals are input to select the output status data Stt. More specifically, as follows... Figure 18 As shown in (b), during the operation mode MODEb, in order to input the input / output data selection signal intended to output the status data Stt, the controller die CD, for example, in the state of inputting "L" to the external control terminal CLE and inputting "L" to the external control terminal ALE, boosts the external control terminal / WE from "L" to "H".

[0197] In addition, such as Figure 18 As shown in (b), during the S_Out period of the operation mode MODEb, in order to output the status data Stt, the controller die CD, for example, steps down the input signal of the external control terminal / WE. Subsequently, using the output circuit 202, two bits of the status data Stt are output from the external control terminals CLE and ALE to the controller die CD. When the status data Stt is 8 bits, it is output in 2-bit units in 4 cycles.

[0198] Figure 19 This is a schematic timing diagram representing other situations when the read action and data output action are performed in the action mode MODEb. Figure 19 In the example, the memory die MD is set to the action mode MODEb.

[0199] Figure 19 In the example, firstly, command data "00h", address data Add, and command data "30h" are sequentially input via external control terminals CLE and ALE. The address data Add included in this command set contains the memory plane PLN0 (which is the target of the read operation). Figure 4 The information is used as the memory surface address.

[0200] Next, command data "00h", address data Add, and command data "30h" are sequentially input via external control terminals CLE and ALE. The address data Add included in this command set contains the memory plane PLN1 (which is the target of the read operation). Figure 4 The information is used as the memory surface address.

[0201] Next, the command data "70h" is input via the external control terminals CLE and ALE. With the input of the command data "70h", the status is read and the status data Stt is output via the external control terminals CLE and ALE.

[0202] Next, command data "05h", address data Add, and command data "E0h" are sequentially input via external control terminals CLE and ALE. The address data Add contains the memory plane PLN0, which is the target of the data output action. Figure 4 The information is used as the memory surface address.

[0203] After the specified standby time, the data output operation begins on the memory surface PLN0, and the user data "DataOut" is output through the data signal input / output terminals DQ<7:0>.

[0204] in addition, Figure 19 In the example, during the data output operation to the memory surface PLN0, command data "70h" is input via external control terminals CLE and ALE. Along with the input of command data "70h", a status read is performed, and status data Stt is output via external control terminals CLE and ALE. In other words, in this embodiment, the status read operation can be performed in parallel with the data output operation.

[0205] Next, command data "05h", address data Add, and command data "E0h" are sequentially input via external control terminals CLE and ALE. The address data Add contains the memory plane PLN1, which is the target of the data output action. Figure 4 The address of the memory plane is used as the address of the memory plane.

[0206] Here, in action mode MODEb, unlike action mode MODEa, the data output timing adjustment unit TCT (…) Figure 4 Adjust the start time of the data output operation to memory surface PLN1. After the data output operation to memory surface PLN0 is completed, in response to the internal signal issued by the data output timing adjustment unit TCT, the data output operation to memory surface PLN1 is started, and the user data "DataOut" is output through the data signal input / output terminals DQ<7:0>.

[0207] [Mode setting action for comparison example]

[0208] Next, refer to Figure 20 and Figure 21 The mode setting operation of the comparative example semiconductor memory device will be explained. Figure 20 This is a schematic flowchart used to illustrate the mode setting operation of a comparative example semiconductor memory device. Figure 21This is a timing diagram used to explain the mode setting operation of the comparative example semiconductor memory device.

[0209] [Flowchart of pattern setting actions including comparison examples]

[0210] First, use Figure 20 The process of setting the mode in the comparative example is explained step by step. Figure 20 Each step of the process shown is executed, for example, by the controller on the bare CD.

[0211] In step S101x, the power supply operation is performed as described below. Immediately after the power supply operation in step S101x, the memory die MD is in the operating mode MODEa state.

[0212] In step S102x, the controller die CD selects whether to switch the memory die MD from operation mode MODEa to operation mode MODEb. When switched to operation mode MODEb, proceed to step S103x. When not switched to operation mode MODEb, proceed to step S106x.

[0213] In step S103x, with the memory die MD set to operation mode MODEa, the initial setup action described below is performed. The initial setup action includes, for example, the power-on read action and the mirror connection confirmation action described below. That is, the controller die CD sends command data "FFh" and command data "70h" to the data signal input / output terminals DQ<7:0> of the memory die MD. The command data "FFh" is command data Cmd indicating the power-on read action, and the command data "70h" is command data Cmd indicating the mirror connection confirmation action.

[0214] In step S104x, a mode setting operation is performed. The mode setting operation is, for example, the controller die CD changing the memory die MD from operation mode MODEa to operation mode MODEb. That is, the controller die CD sends command data "EFh", address data Add, and data Dat as a command set indicating the mode setting operation to the data signal input / output terminals DQ<7:0> of the memory die MD.

[0215] In step S105x, with the memory die MD set to operation mode MODEb, various operations such as read, write, erase, data output, and status reading are initiated based on instructions from the controller die CD. For example, the controller die CD sends a set of commands instructing the data output operation to the external control terminals CLE and ALE of the memory die MD.

[0216] On the other hand, in step S106x, with the memory die MD set to operation mode MODEa, an initial setup operation is performed based on instructions from the controller die CD. Step S106x is the same operation as step S103x. For example, the controller die CD sends command data "FFh" and command data "70h" to the data signal input / output terminals DQ<7:0> of the memory die MD. The command data "FFh" is command data Cmd indicating a power-on read operation, and the command data "70h" is command data Cmd indicating a mirror connection confirmation operation.

[0217] In step S107x, with the memory die MD set to operation mode MODEa, various operations as described above are initiated based on instructions from the controller die CD. For example, the controller die CD sends a set of commands instructing data output operations to the data signal input / output terminals DQ<7:0> of the memory die MD.

[0218] [Timing diagram of pattern setting actions including comparison examples]

[0219] Figure 21 This is a schematic timing diagram illustrating the execution of the initial setting action and the mode setting action in the comparative example. Figure 21 In the example, at the beginning of the timing diagram, the power supply voltage V is activated via the power on action. CC The memory die MD is set to operating mode MODEa immediately after the power supply operation. In other words, the memory die MD is configured to operate in MODEa when the power supply is interrupted.

[0220] Figure 21 In the example, when the memory die MD is set to operating mode MODEa immediately after power-on, the controller die CD inputs command data "FFh" via the data signal input / output terminals DQ<7:0>. Command data "FFh" is command data Cmd indicating the initial setting operation.

[0221] Upon input of command data "FFh", the initial setting operation begins when the voltage at the external control terminal / WE rises from "L" to "H", and the voltage at terminal RY / / BY drops from "H" to "L". Furthermore, after a specified period, at the end of the initial setting operation, the voltage at terminal RY / / BY rises from "L" to "H".

[0222] then, Figure 21In the example, with the memory die MD set to operating mode MODEa, the controller die CD inputs command data "70h" via the data signal input / output terminals DQ<7:0>. Command data "70h" is command data Cmd indicating the mirror connection confirmation action.

[0223] Upon input of command data "70h", the mirror connection confirmation operation begins when the voltage at the external control terminal / WE rises from "L" to "H", and the voltage at terminal RY / / BY drops from "H" to "L". Furthermore, after a specified period, at the end of the mirror connection confirmation operation, the voltage at terminal RY / / BY rises from "L" to "H".

[0224] Next, with the memory die MD set to operating mode MODEa, the controller die CD sequentially inputs the command set indicating the mode setting operation via data signal input / output terminals DQ<7:0>. The command set indicating the mode setting operation includes command data "EFh", address data Add, and data Dat. Command data "EFh" is the command data Cmd indicating the mode setting operation, address data Add is the characteristic address, and data Dat is the characteristic data.

[0225] For example, Figure 21 In the example, after inputting the command data "EFh" and the address data Add, 8 bits of data × 4 cycles constituting the data Dat are input. As the last cycle of Dat is input, the mode setting operation begins when the voltage at the data strobe signal input / output terminals DQS and / DQS drops from "H" to "L," and the voltage at terminals RY / / BY drops from "H" to "L." Furthermore, after a predetermined period, at the end of the mode setting operation, the voltage at terminals RY / / BY rises from "L" to "H."

[0226] After the above actions, the memory die MD can perform normal read or write operations in operation mode MODEb.

[0227] [Mode setting operation in the first embodiment]

[0228] Next, refer to Figure 22 and Figure 23 The mode setting operation of the semiconductor memory device of the first embodiment will be explained. Figure 22 This is a schematic flowchart used to explain the mode setting operation of the semiconductor memory device in the first embodiment. Figure 23 This is a timing diagram used to explain the mode setting operation of the semiconductor memory device in the first embodiment.

[0229] [Flowchart including the mode setting action of the first embodiment]

[0230] First, use Figure 22 The steps of the process including the mode setting operation of the first embodiment will be described. Figure 22 The steps of the process shown are executed, for example, using a controller bare CD.

[0231] In step S101, a power supply operation is performed. The power supply operation, for example, involves supplying power to the corresponding bonding pad electrode P(…) of the memory die MD. Figure 4 The operation of supplying power voltage VCC. As a power supply operation, power voltage VCC can be supplied to the controller die CD and the memory die MD. Alternatively, power voltage VCC can be supplied to the memory die MD while maintaining power supply to the controller die CD, or vice versa. Immediately after the power supply operation in step S101, the memory die MD is in operating mode MODEa.

[0232] In step S102, the controller CD selects whether to switch the memory die MD from operation mode MODEa to operation mode MODEb. When switched to operation mode MODEb, proceed to step S103. When not switched to operation mode MODEb, proceed to step S106.

[0233] In step S103, the mode setting operation is performed. The mode setting operation begins, for example, after a first predetermined time has elapsed since power was initially supplied to the controller die CD and memory die MD. This mode setting operation is performed using external control terminals CLE, ALE, and / WE.

[0234] As described above, immediately after power supply, the memory die MD is set to operating mode MODEa. For example, before executing step S103, the feature register FR stores feature data Fd, which is intended to enable the memory die MD to operate in operating mode MODEa. If a second predetermined time elapses after the mode setting operation, the feature data Fd of the memory die MD is erased, and the feature data Fd intended to enable the memory die MD to operate in operating mode MODEb is reset in the feature register FR. Thus, the switch from operating mode MODEa to operating mode MODEb is completed.

[0235] In step S104, the memory die MD, in operation mode MODEb, performs an initial setup operation. This initial setup operation includes, for example, sending a command to instruct the memory die MD to perform a power-on read operation and a command to instruct the memory die MD to perform a mirror connection confirmation operation. Specifically, the controller die CD, as part of the initial setup operation, sends command data "FFh" and command data "70h" to the external control terminals CLE and ALE of the memory die MD. Command data "FFh" serves as command data Cmd instructing the power-on read operation, and command data "70h" serves as command data Cmd instructing the mirror connection confirmation operation. Furthermore, before a third predetermined time elapses after the transmission of the command data "FFh" instructing the memory die MD to perform a power-on read operation, the memory die MD cannot perform normal read, write, or data output operations.

[0236] The power-on read operation includes, for example, the action of reading the initial setting information required for the operation of the memory die MD from a designated area (setting information storage block) of the memory cell array MCA, and the action of storing the required initial information into the register in the sequence generator SQC. Alternatively, after the controller die CD sends the command data Cmd instructing the power-on read operation to the memory die MD, all or part of the initial setting information can be sent from the data signal input / output terminals DQ0 to DQ7 of the memory die MD or the external control terminals CLE and ALE to the controller die CD.

[0237] The initial setup information contains information used to ensure proper operation of the memory die (MD). This initial setup information includes, for example, information indicating defective blocks or defective column components, and information indicating driver settings for data signal input / output terminals DQ0 to DQ7. The initial setup information is stored in registers, for example, within the sequence generator (SQC), during the operation of the memory die (MD). However, the information stored in these registers is lost when power is cut off. Therefore, to retain the initial setup information even after power is cut off, it is stored, for example, in a designated area (setting information storage block) of the memory cell array (MCA). Furthermore, upon power resumption, the initial setup information is read from the designated area (setting information storage block) of the memory cell array (MCA) via a power-on read operation, and this information is stored in registers within the sequence generator (SQC).

[0238] If used Figure 3 As explained, the mirrored connection verification operation is performed when the memory system 10 has a positive connection package PKGa and a reverse connection package PKGb and includes a mirrored connection. For example, Figure 3In the example, the signals input to the data signal input / output terminals DQ1, 2, 3, 4, 5, 6, and 7 are reversed between the positive connection package PKGa and the reverse connection package PKGb. Especially when data other than user data Dat (e.g., command data Cmd, address data Add, status data Stt, and feature data Fd) is reversed, there is a possibility that the memory die MD will perform unexpected actions. Therefore, in the first embodiment, each package PKG performs a mirror connection confirmation operation to determine whether its state is positive or reverse connection.

[0239] The mirror connection confirmation operation is performed when the memory die MD is set to operating mode MODEa, for example, by inputting asymmetric sequence command data to the data signal input / output terminals DQ<7:0>. When the asymmetric sequence command data is input to the forward connection package PKGa, the command data is input normally. In this case, the package PKG determines itself to be the forward connection package PKGa. On the other hand, when the asymmetric sequence command data is input to the reverse connection package PKGb, the command data is input in reverse. In this case, the package PKG determines itself to be the reverse connection package PKGb. However, when the memory die MD is set to operating mode MODEb, command data is not input via the data signal input / output terminals DQ<7:0>, therefore the memory die MD cannot determine whether it is the forward connection package PKGa or the reverse connection package PKGb based solely on the command data. Therefore, when the memory die MD is set to the operation mode MODEb, and a mirror connection confirmation operation is performed, as described below, after the command data indicating the mirror connection confirmation operation (e.g., "70h"), virtual data for mirror connection confirmation (e.g., "70h") is input via the data signal input / output terminal DQ<7:0>.

[0240] In step S105, with the memory die MD set to operation mode MODEb, various operations as described above are initiated based on instructions from the controller die CD. For example, the controller die CD sends a set of commands instructing a data output operation to the external control terminals CLE and ALE of the memory die MD. The transmission of the command set instructing the data output operation, for example, occurs after a predetermined time (e.g., a third predetermined time) following the completion of the transmission of the instruction data "FFh" from the controller die CD to the memory die MD in the initial setting information, instructing the execution of a power-on read operation. Then, the controller die CD switches the input signals of the external control terminals / RE and RE, and receives user data transmitted from the data signal input / output terminals DQ<7:0> of the memory die MD. Receiving user data using the controller die CD occurs, for example, after a fourth predetermined time following the transmission of the command set instructing the data output operation by the controller die CD.

[0241] In step S106, with the memory die MD set to operation mode MODEa, an initial setup operation is performed based on instructions from the controller die CD. For example, the controller die CD sends command data "FFh" and command data "70h" to the data signal input / output terminals DQ<7:0> of the memory die MD. The command data "FFh" is command data Cmd indicating a power-on read operation, and the command data "70h" is command data Cmd indicating a mirror connection confirmation operation.

[0242] Step S106 is the same action as step S103x in the comparative example.

[0243] In step S107, with the memory die MD set to operation mode MODEa, various operations as described above are initiated based on instructions from the controller die CD. For example, the controller die CD sends a set of commands instructing data output operations to the data signal input / output terminals DQ<7:0> of the memory die MD. Step S107 is the same operation as step S107x in the comparative example.

[0244] [Timing diagram including the mode setting operation of the first embodiment]

[0245] Figure 23 This is a schematic timing diagram illustrating the situation when performing the execution mode setting action and the initial setting action in the first embodiment. Figure 23 In the example, at the beginning of the timing diagram, the power supply voltage VCC is supplied through the power supply action. In addition, the memory die MD is set to the operation mode MODEa.

[0246] After a predetermined time (e.g., the first predetermined time) has elapsed since the power supply operation began, and after the supplied power voltage VCC has stabilized, the following operation is performed. Figure 23 In the example, with both the external control terminal CLE and ALE inputting "H", the controller die CD switches the input signal of the external control terminal / WE four times. For example, if the input signal level of the external control terminal / WE is "H", the four switches will occur in the order of "L", "H", "L", "H". During the final switch, at the moment when the external control terminal / WE rises from "L" to "H", the voltage at the terminal RY / / BY on the memory die MD drops from "H" to "L". Furthermore, after a predetermined time (e.g., a second predetermined time) has elapsed after the mode setting operation ends, the voltage at the terminal RY / / BY rises from "L" to "H".

[0247] also, Figure 23 In this example, as a mode setting operation performed after a predetermined time has elapsed since the power supply operation, an example is shown where the input signal of the external control terminal / WE is switched four times ("L", "H", "L", "H") while the controller die CD is inputting "H" to the external control terminal CLE and to the external control terminal ALE. However, this is not a limitation. For example, the number of times the controller die CD switches the input signal of the external control terminal / WE does not need to be four times; it can be two times ("L", "H") or six times ("L", "H", "L", "H", "L", "H") or more. Furthermore, the controller die CD can input "L" to the external control terminal CLE and "H" to the external control terminal ALE, or it can input "L" to the external control terminal CLE and "L" to the external control terminal ALE. However, when “H” is input to the external control terminal CLE and “L” is input to the external control terminal ALE, the voltage status of the data signal input / output terminal DQ<7:0> may indicate that the memory die MD is being read by power-on in the indicated operation mode MODEa. Therefore, it is preferable to input a combination of voltages other than these to the external control terminals CLE and ALE.

[0248] then, Figure 23 In the example, when the memory die MD is set to operation mode MODEb, the input / output data selection signal (header) for the specified command data Cmd is input via the external control terminals CLE and ALE, along with the 8-bit data constituting the command data "FFh". The command data "FFh" is the command data Cmd that instructs the memory die MD to perform a power-on read operation during the initial setup operation.

[0249] Figure 23In the example, when the header and command data "FFh" are input, the input signal of the external control terminal / WE is switched 10 times ("L", "H", "L", "H", "L", "H", "L", "H", "L", "H"). During the final switch, at the moment when the external control terminal / WE rises from "L" to "H", the power-on read operation begins on the memory die MD, and the voltage of the terminal RY / / BY drops from "H" to "L". Furthermore, after sending the command data "FFh" instructing the execution of the power-on read operation to the memory die MD (if no mirror connection confirmation operation is performed on the memory die MD, this is after the initial setup operation is completed), after a predetermined time (e.g., the third predetermined time), at the moment when the power-on read operation ends on the memory die MD, the voltage of the terminal RY / / BY rises from "L" to "H".

[0250] then, Figure 23 In the example, with the memory die MD set to operating mode MODEb, the input / output data selection signal (header) specifying the input command data Cmd and the command data "70h" are input via the external control terminals CLE and ALE. The command data "70h" is the command data Cmd indicating the mirror connection confirmation action.

[0251] When the header and command data "70h" are input, the input signal of the external control terminal / WE is switched 10 times. During the final switch, at the moment the external control terminal / WE rises from "L" to "H", the asymmetric virtual data required for mirror connection confirmation, such as "70h", is input via the data signal input / output terminal DQ<7:0>. Furthermore, at the moment when the data strobe signal input / output terminals DQS and / DQS, which switch with the input of "70h", finally drop from "H" to "L", the mirror connection confirmation operation begins on the memory die MD, and the voltage at terminal RY / / BY drops from "H" to "L". Additionally, after a predetermined time has elapsed after sending the instruction data "70h" instructing the execution of the mirror connection confirmation operation to the memory die MD, at the moment the mirror connection confirmation operation ends on the memory die MD, the voltage at terminal RY / / BY rises from "L" to "H".

[0252] After the above actions, the memory die MD can perform normal read operations, normal write operations, and normal data output operations in the operation mode MODEb.

[0253] [Effect]

[0254] As explained above, the semiconductor memory device in the comparative example operates in MODEa mode immediately after power is turned on. The initial setup and mode setting operations immediately after power is turned on must be performed in MODEa mode. Therefore, even when the controller CD controls the normal operation of the memory die MD in MODEb mode, it must control the memory system in MODEa mode immediately after power is turned on, which sometimes complicates the control operation of the controller CD.

[0255] In contrast, the semiconductor memory device of this embodiment operates in mode MODEa immediately upon power-on, but can be switched from mode MODEa to mode MODEb via operation of external control terminals CLE and ALE. In other words, to switch the memory die MD from mode MODEa to mode MODEb, signal input via data signal input / output terminals DQ<7:0> is unnecessary. Furthermore, initial setup can also be performed while the memory die MD is set to mode MODEb. Therefore, the control operation of the controller die CD is prevented from becoming complex.

[0256] [Second Implementation]

[0257] Next, refer to Figure 24 The semiconductor memory device of the second embodiment will be described. Figure 24 This is a timing diagram used to explain the mode setting operation of the semiconductor memory device according to the second embodiment. Furthermore, in the following description, configurations and operations identical to those in the first embodiment are sometimes omitted.

[0258] [Mode setting operation in the second embodiment]

[0259] Figure 24 In the example, at the beginning of the timing diagram, the power supply voltage VCC is supplied through the power supply action. In addition, the memory die MD is set to the operation mode MODEa.

[0260] Figure 24 In the example, similar to the first embodiment, when the external control terminal CLE is input with "H" and the external control terminal ALE is input with "H", the controller die CD switches the input signal of the external control terminal / WE four times to perform a mode setting operation that changes the memory die MD from operation mode MODEa to operation mode MODEb.

[0261] then, Figure 24 In the example, similar to the first implementation, in the action mode MODEb, the header and command data "FFh" are input to perform the initial setting action.

[0262] Here, in the semiconductor memory device of the second embodiment, after the controller die CD sends an instruction to the memory die MD to instruct the execution of a power-on read operation during the initial setup operation, it does not send an instruction to the memory die MD to instruct the execution of a mirror connection confirmation operation. In other words, the memory die MD does not perform a mirror connection confirmation operation after the power-on read operation is completed. This configuration can also be used when data other than user data Dat (e.g., command data Cmd, address data Add, status data Stt, feature data Fd) is not input / output via the data signal input / output terminals DQ<7:0>.

[0263] After the above actions, the memory die MD can perform normal read or write operations in operation mode MODEb.

[0264] [other]

[0265] Furthermore, in the description of the above embodiments, during the mode setting operation, an example was shown of inputting "H" to the external control terminal CLE and inputting "H" to the external control terminal ALE. However, during the mode setting operation, it is also possible to input "L" to the external control terminal CLE and input "L" to the external control terminal ALE, or it is also possible to input "L" to the external control terminal CLE and input "H" to the external control terminal ALE.

[0266] Additionally, the mode setting operation shows an example where the input signal of the external control terminal / WE is switched four times. However, during the mode setting operation, the input signal of the external control terminal / WE can be switched two times, or even six times or more.

[0267] Furthermore, the above description illustrates an example where, when input immediately after a power-on operation, the command data "FFh" becomes the command data Cmd indicating a power-on read operation. However, when input after a power-on read operation is completed, the command data "FFh" can also become the command data Cmd indicating a reset operation.

[0268] Additionally, an example is shown where, immediately after a power-on read operation, the command data "70h" is the command data Cmd indicating a mirror connection confirmation operation. However, in cases other than immediately after a power-on read operation, the command data "70h" can also be the command data Cmd indicating a status read.

[0269] In other words, a memory die can be configured to perform different actions when receiving a command data at the first moment (e.g., immediately after power-on operation) and when receiving a command data at the second moment (after power-on read operation is completed).

[0270] Furthermore, in the above explanation, in operation mode MODEb, 2-bit data input / output was performed using the external control terminals CLE and ALE. However, this method is only an example, and the specific method can be adjusted accordingly. For example, in operation mode MODEb, other terminals can be used for input / output of 3 or more bits of data. More specifically, as terminals other than the external control terminals CLE and ALE, for example, reference [reference / reference] can be used. Figure 4 The external control terminal / WP is as described above. Furthermore, if the selection state of the memory die MD remains unchanged even after the input of the external control terminal / CE has changed, the external control terminal / CE can be used as a terminal other than the external control terminals CLE and ALE. Additionally, one or two terminals can be selected from the terminals including the external control terminals CLE and ALE for 1-bit or 2-bit data input / output. Similarly, during mode setting operations, terminals other than the external control terminals CLE and ALE can be used instead, or other terminals besides the external control terminals CLE and ALE can be used.

[0271] While several embodiments of the invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included in the scope of the invention as set forth in the claims and equivalents thereof.

[0272] [Symbol Explanation]

[0273] MC storage unit

[0274] MCA storage cell array

[0275] PC peripheral circuits

[0276] ADR Address Register

[0277] CMR command register.

Claims

1. A memory system having: Semiconductor memory devices; and Control device; The semiconductor memory device has: The first signal pad is capable of receiving the first signal; The second signal pad is capable of receiving the second signal; The third signal pad is capable of receiving the third signal; 4th signal pad; A memory cell array, comprising: a string of multiple memory cell transistors connected in series; The sensing amplifier module is connected to the memory cell array; and A data register, connected to the sensing amplifier module, is capable of storing data read from the storage cell array; The control device is: After a first predetermined time has elapsed since the control device has been powered on, A mode setting operation is performed, wherein the mode setting operation is to switch the third signal sent to the third signal pad while at least one of the first signal sent to the first signal pad or the second signal sent to the second signal pad is set to a specified voltage. After the mode setting action is completed and a second predetermined time has elapsed, The initial setup process begins, which includes sending a power-on read command to the second signal pad and receiving initial setup information from the fourth signal pad. After the initial setting action is completed and a third predetermined time has elapsed, Send a data output command indicating the data output action to the second signal pad; After the fourth predetermined time has elapsed since the data output command was sent, Receive the data transmitted from the fourth signal pad.

2. The memory system according to claim 1, wherein: During the mode setting operation, the control device... The third signal is switched more than 4 times.

3. The memory system according to claim 1 or 2, wherein: The control device, during the initial setting action... Send the power-on read command to the first signal pad and the second signal pad. The control device is: After the initial setting action is performed and the third predetermined time has elapsed, the data output command is sent to the first signal pad and the second signal pad.

4. The memory system according to claim 1, wherein: The semiconductor memory device further includes a fifth signal pad, which is capable of receiving a fifth signal. The control device is: In the mode setting action, With the second signal sent to the second signal pad and the fifth signal sent to the fifth signal pad respectively set to a predetermined voltage, the third signal sent to the third signal pad is switched. Send the power-on read command and the data output command to the second signal pad and the fifth signal pad. The data output command includes command data and address data. The control device is: When sending the command data The third signal undergoes a first conversion, and after setting the second signal to a first voltage and the fifth signal to a second voltage different from the first voltage, The third signal is switched for the second time and thereafter, and the command data is sent to the second signal pad and the fifth signal pad; When sending the address data The third signal undergoes a first conversion, and the second signal is set to the second voltage, while the fifth signal is set to the first voltage. The third signal is switched for the second time and thereafter, and the address data is sent to the second signal pad and the fifth signal pad.

5. The memory system according to claim 1, wherein: The semiconductor memory device has multiple [devices / facilities]. Each of the plurality of semiconductor memory devices further includes a sixth signal pad. The fourth signal pad of one of the semiconductor memory devices is connected to the sixth signal pad of the other semiconductor memory devices. The sixth signal pad of one of the semiconductor memory devices is connected to the fourth signal pad of the other semiconductor memory devices. The control device is: After performing the initial setting action, a first command, different from the power-on read command, is sent to the second signal pad of the plurality of semiconductor memory devices. After sending the first command, the first data is sent to the fourth signal pad and the sixth signal pad of the plurality of semiconductor memory devices.

6. The memory system according to claim 5, wherein: The first data consists of a first sequence comprising multiple bits. When the sequence obtained by reversing the permutation of the first sequence is designated as the second sequence, The second sequence is different from the first sequence.

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