Apparatuses and non-transitory computer-readable media of memory device access techniques

Abstract

This disclosure relates to apparatuses and non-transitory computer-readable media for memory device access techniques. This disclosure relates to memory device access techniques. A memory system can be enabled to allow device-controlled access to a portion of volatile memory at a host system. By enabling the memory system to access the volatile memory at the host system, the memory system can perform access operations that can reduce an amount of messages exchanged between the memory system and the host system. The host system can allocate a list of memory resources in the volatile memory associated with a first access command. The host system can allocate the same memory resources for a second access command. By allocating the same memory resources, the memory device can transmit a ready-to-transfer (RTT) message for multiple access commands rather than for each command. In some cases, reducing the amount of RTT messages can reduce latency and improve performance at the memory system.

Description

[0001] Cross-referencing

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 692,873, entitled “Memory Device Access Technologies,” filed March 11, 2022, by Carriello et al., which is assigned to the assignee and is expressly incorporated herein by reference. Technical Field

[0003] The technical field relates to memory device access technology. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to one of two supported states, often corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access the information stored by the memory device, a component can read (e.g., sense, detect, retrieve, identify, determine, evaluate) the state of one or more memory cells within the memory device. To store information, a component can write (e.g., program, set, assign) one or more memory cells within the memory device to the corresponding state.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR and NAND memory devices, etc. Memory devices can be described in terms of volatile or non-volatile configurations. Volatile memory cells (e.g., DRAM) may lose their programmed state over time unless periodically refreshed by an external power supply. Non-volatile memory cells (e.g., NAND) can maintain their programmed state for a long period of time even in the absence of an external power supply. Summary of the Invention

[0006] An apparatus is described. The apparatus may include a controller associated with a memory device, wherein the controller is configured to cause the apparatus to: receive a first command to perform a first access operation; receive a second command to perform a second access operation before transmitting a response to the first command; and transmit an indication of a ready state for the memory device to receive data in response to the first command and the second command.

[0007] An apparatus is described. The apparatus may include a controller associated with a host device, wherein the controller is configured to cause the apparatus to: transmit a first command to a memory device to perform a first access operation; store first information associated with the first command in a memory resource list; transmit a second command to the memory device to perform a second access operation; store second information associated with the second command in the memory resource list; and, in response to the first command and the second command, receive an indication at the host device of a ready state for receiving data from the memory device.

[0008] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code including instructions executable by a processor to perform: receiving a first command to perform a first access operation; receiving a second command to perform a second access operation before transmitting a response to the first command; and transmitting an indication of a ready state for the memory device to receive data in response to the first command and the second command. Attached Figure Description

[0009] Figure 1 Examples of systems that support memory device access technologies according to the examples disclosed herein are shown.

[0010] Figure 2 Examples of systems that support memory device access technologies according to the examples disclosed herein are shown.

[0011] Figure 3 Examples of systems that support memory device access technologies according to the examples disclosed herein are shown.

[0012] Figure 4 Examples of process flows supporting memory device access techniques, based on the examples disclosed herein, are shown.

[0013] Figure 5 A block diagram of a memory device supporting memory device access technology according to the examples disclosed herein is shown.

[0014] Figure 6 A block diagram of a host device supporting memory device access technology according to the examples disclosed herein is shown.

[0015] Figure 7 and 8 A flowchart illustrating one or more methods for supporting memory device access techniques according to examples disclosed herein is shown. Detailed Implementation

[0016] In some memory systems, a host device can transmit commands to a memory device. The commands may indicate a dataset stored at the memory device and request access to that dataset (e.g., request to perform a read or write operation). In response to the command, the memory device may send a Ready to Transmit (RTT) message, which may initiate the data transfer associated with the access command. In some instances, the RTT message may, for example, indicate the status of the memory device to the host device. In some cases, one RTT message may be sent for each command received from the host device. The host device may have a relatively small amount of memory (e.g., static random access memory (SRAM)), which in some cases may be fully allocated for use by the flash translation layer (FTL). The host device may therefore rely on storage at one or more memory devices to support functionality and may transmit and receive multiple commands associated with each access operation at the memory device. In some cases, the number of commands associated with each access operation can increase latency and reduce the efficiency of the host system.

[0017] Systems, apparatuses, and techniques are described as improving latency by supporting memory device access with fewer commands. For example, in some cases, a memory device may be configured to enable device-controlled access to a portion of volatile memory (e.g., dynamic random access memory (DRAM), SRAM) at a host device. By enabling the memory device to access volatile memory at the host device, the memory device can reduce the amount of RTT messages transferred from the memory device to the host device to perform the access operation. For example, the host device may allocate a list of memory resources (e.g., a Physical Region Description Table (PRDT)) in volatile memory associated with a first access command. The host device may allocate the same PRDT for a second access command. That is, the first and second access commands may address the same location in volatile memory at the host device. By allocating the same PRDT, the memory device can respond to the first and second access commands instead of transmitting a single RTT message for each access command. In some cases, reducing the number of RTT messages can reduce latency and improve performance at the memory system.

[0018] First refer to Figures 1 to 3 Features of this disclosure are described in the context of systems, devices, and circuits. References Figure 4 The features of this disclosure are described in the context of process flow. References Figure 5-7The device diagrams and flowcharts relating to memory device access technology further illustrate and describe these and other features of this disclosure.

[0019] Figure 1 An example of a system 100 supporting memory device access technology according to the examples disclosed herein is shown. System 100 includes a host system 105 coupled to a memory system 110.

[0020] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other possibilities.

[0021] System 100 may be included in a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capability, embedded computer (e.g., embedded computer included in a vehicle, industrial equipment or networked business device), or any other computing device that includes memory and processing means.

[0022] System 100 may include a host system 105 that can be coupled to a memory system 110. In some instances, this coupling may include an interface to a host system controller 106, which may be an instance of a controller or control component configured to cause the host system 105 to perform various operations as described herein. The host system 105 may include one or more devices, and in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory native to the host system 105 or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to and read data from the memory system 110. Although in Figure 1The diagram shows a memory system 110, but the host system 105 can be coupled to any number of memory systems 110.

[0023] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., to exchange or otherwise transmit control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Dual Data Rate (DDR) interfaces, DIMM interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), and Low Power Dual Data Rate (LPDDR) interfaces. In some instances, one or more such interfaces may be contained in or otherwise supported between host system controller 106 of host system 105 and memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 included in memory system 110 or via a corresponding physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0024] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although in Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0025] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations as described herein. The memory system controller 115 may also be coupled to and communicate with the memory device 130 to perform operations at the memory device 130 that are generally referred to as access operations, such as reading data, writing data, erasing data, or refreshing data, and other such operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute these commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 may translate responses associated with the memory device 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0026] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling, garbage collection, error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0027] The memory system controller 115 may include hardware such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-decoded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuitry system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry system.

[0028] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory capable of storing operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions belonging to the memory system controller 115 herein. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory available for internal storage or computation by the memory system controller 115, for example, internal storage or computation related to the functions belonging to the memory system controller 115 herein. Additionally or alternatively, local memory 120 may be used as a cache for the memory system controller 115. For example, if data is read from or written to memory device 130, then data may be stored in local memory 120, and the data may be available within local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 (e.g., with reduced latency relative to memory device 130) according to a caching strategy.

[0029] although Figure 1 The example of memory system 110 described herein includes memory system controller 115; however, in some cases, memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105) or one or more local controllers 135 within memory device 130 to perform the functions attributed herein to memory system controller 115. Generally, one or more functions attributed herein to memory system controller 115 may, in some cases, be performed alternatively by host system 105, local controller 135, or any combination thereof. In some cases, memory device 130, at least partially managed by memory system controller 115, may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0030] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively or additionally, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as DRAM memory cells and synchronous DRAM (SDRAM) memory cells.

[0031] In some instances, memory device 130 may include (e.g., on the same die or within the same package) a local controller 135 that can operate on one or more memory cells of the respective memory device 130. The local controller 135 may operate in conjunction with memory system controller 115, or may perform one or more functions attributed herein to memory system controller 115. For example, as Figure 1 As shown, memory device 130-a may include local controller 135-a, and memory device 130-b may include local controller 135-b.

[0032] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package including one or more dies 160. In some instances, die 160 may be a block of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, wherein each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0033] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information; these memory cells may be referred to as single-level cells (SLCs). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information; if configured to store two bits of information, it may be referred to as a multi-level cell (MLC); if configured to store three bits of information, it may be referred to as a three-level cell (TLC); if configured to store four bits of information, it may be referred to as a four-level cell (QLC), or more generally, a multi-level memory cell. Multi-level memory cells can provide greater storage density compared to SLC memory cells, but in some cases, this may involve narrower read or write margins or greater complexity for supporting circuitry.

[0034] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may be performed within different planes 165. For example, memory cells within different blocks 170 may be operated on in parallel, as long as the different blocks 170 are located in different planes 165. In some cases, individual blocks 170 may be referred to as physical blocks, and virtual blocks 180 may refer to a group of blocks 170 within which parallel operations can occur. For example, parallel operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d within planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as virtual blocks 180. In some cases, a virtual block may contain blocks 170 from different memory devices 130 (e.g., blocks in one or more planes including memory devices 130-a and 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be “block 0” of plane 165-a, block 170-b may be “block 0” of plane 165-b, etc.). In some cases, parallel operations in different planes 165 may be subject to one or more restrictions, such as parallel operations on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0035] In some cases, block 170 may contain memory cells organized into rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may alternatively be referred to as a bit line) (e.g., coupled thereto).

[0036] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level), but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 may be the smallest unit of memory (e.g., a set of memory cells) that can be independently programmed or read (e.g., simultaneously programmed or read as part of a single programming or reading operation), and block 170 may be the smallest unit of memory (e.g., a set of memory cells) that can be independently erased (e.g., simultaneously erased as part of a single erase operation). Furthermore, in some cases, NAND memory cells may be erased before they can be rewritten with new data. Therefore, for example, in some cases, the used page 175 may not be updated until the entire block 170 containing page 175 has been erased.

[0037] In some cases, to update some data within block 170 while preserving other data within block 170, memory device 130 may copy the data to be preserved to a new block 170 and write the updated data to one or more remaining pages of the new block 170. Memory device 130 (e.g., local controller 135) or memory system controller 115 may mark or otherwise represent data held in the old block 170 as invalid or obsolete, and may update the logical-to-physical (L2P) mapping table so that the logical address (e.g., LBA) of the data is associated with the new valid block 170, rather than the old invalid block 170. For example, in some cases, such copying and remapping may be performed due to latency or wear considerations, rather than erasing and rewriting the entire old block 170. In some cases, one or more copies of the L2P mapping table may be stored within memory cells of memory device 130 (e.g., within one or more blocks 170 or plane 165) for use by local controller 135 or memory system controller 115 (e.g., for reference and updating).

[0038] In some cases, an L2P mapping table can be maintained, and data can be marked as valid or invalid at the page level. Page 175 may contain valid data, invalid data, or no data. Invalid data may be outdated data due to a newer or more recent version of the data being stored in a different page 175 of memory device 130. Invalid data may have previously been programmed into an invalid page 175 but may no longer be associated with a valid logical address (e.g., a logical address referenced by host system 105). Valid data may be the latest version of such data stored on memory device 130. Page 175 that does not contain data may be a page 175 that has never been written to or has been erased.

[0039] In some cases, the memory system controller 115 or the local controller 135 may perform operations on the memory device 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background refresh, garbage collection, cleanup, block scanning, health monitoring, or other operations, or any combination thereof. For example, within the memory device 130, block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting for all pages 175 in block 170 to have invalid data in order to erase and reuse block 170, an algorithm called “garbage collection” may be invoked to allow block 170 to be erased and freed up as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations that include, for example, selecting block 170 containing valid and invalid data, selecting pages 175 in the block containing valid data, copying the valid data from the selected pages 175 to a new location (e.g., a free page 175 in another block 170), marking the data in the previously selected pages 175 as invalid, and erasing the selected block 170. Therefore, the number of erased blocks 170 can be increased, allowing more blocks 170 to be used to store subsequent data (e.g., data subsequently received from the host system 105).

[0040] System 100 may include any amount of non-transitory computer-readable media that supports memory device access technologies. For example, host system 105, memory system controller 115, or memory device 130 (e.g., local controller 135) may include or otherwise have access to one or more non-transitory computer-readable media storing instructions (e.g., firmware) for performing the functions attributed herein to host system 105, memory system controller 115, or memory device 130. For example, such instructions, if executed by host system 105 (e.g., by host system controller 106), memory system controller 115, or memory device 130 (e.g., by local controller 135), may cause host system 105, memory system controller 115, or memory device 130 to perform one or more of the related functions described herein.

[0041] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and associated circuitry combined with a local (e.g., on-die or in-package) controller (e.g., local controller 135). An example of a managed memory system is a managed NAND (MNAND) system.

[0042] In some cases, host system 105 can access information at one or more memory devices 130 of memory system 110 by transmitting access commands to memory system controller 115. In some cases, in response to each access command, memory system controller 115 may send an RTT message to indicate the readiness status for receiving data from host system controller 106. Sending an RTT message after each access command can increase latency at system 100. Alternatively, memory system 110 may not be able to access memory at host system 105, which can further reduce efficiency.

[0043] To improve efficiency and reduce latency at system 100, host system 105 and memory system 110 may be configured to support device-controlled access to a portion of volatile memory. For example, the portion of volatile memory may be a portion of DRAM or SRAM located at host system 105 or memory system 110. For each access command, host system 105 may allocate the same memory resource (e.g., PRDT) at the volatile memory. That is, multiple access commands may address the same location in the volatile memory at host system 105. By allocating the same memory resource, host system 105 can reduce the amount of RTT messages sent by memory system 110. For example, in some cases, memory system 110 may send an RTT message after multiple access commands (e.g., a read command and a write command pair), thereby reducing latency at system 100.

[0044] Figure 2 An example of a system 200 supporting memory device access technology according to the examples disclosed herein is shown. System 200 may be used as a reference. Figure 1 An example of system 100 described in the description or its aspects. System 200 may include a memory system 210 configured to store data received from host system 205 and to send data to host system 205 if requested by host system 205 using an access command (e.g., a read command or a write command). System 200 may implement references Figure 1 Aspects of the system 100 described. For example, memory system 210 and host system 205 may be instances of memory system 110 and host system 105, respectively.

[0045] Memory system 210 may include memory device 240 for storing, for example, data transferred between memory system 210 and host system 205 in response to receiving an access command from host system 205, as described herein. Memory device 240 may include references Figure 1The memory device 240 may include one or more memory devices as described. For example, memory device 240 may include NAND memory, PCM, self-select memory, 3D cross-point, other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, or OxRAM.

[0046] Memory system 210 may include a memory controller 230 for controlling the transfer of data directly to and from memory device 240, such as for storing data, retrieving data, and determining memory locations where data is to be stored and retrieved. The memory controller 230 may communicate with memory device 240 directly or via a bus (not shown) using protocols specific to each type of memory device 240. In some cases, a single memory controller 230 may be used to control multiple memory devices 240 of the same or different types. In some cases, memory system 210 may include multiple memory controllers 230 (e.g., different memory controllers 230 for each type of memory device 240). In some cases, the memory controller 230 may implement a reference... Figure 1 Aspects of the local controller 135 described.

[0047] The memory system 210 may additionally include an interface 220 for communicating with the host system 205 and a buffer 225 for temporary storage of data transferred between the host system 205 and the memory device 240. The interface 220, buffer 225, and memory controller 230 can be used to convert data between the host system 205 and the memory device 240, for example, as shown by data path 250, and can be collectively referred to as the data path components.

[0048] Using buffer 225 to temporarily store data during transmission allows data to be buffered while commands are being processed, thereby reducing latency between commands and allowing for arbitrary data sizes associated with commands. This also allows for handling command bursts, and buffered data can be stored or transmitted (or both) once the burst stops. Buffer 225 may contain relatively fast memory (e.g., some type of volatile memory such as SRAM or DRAM) or hardware accelerators or both to allow for fast storage and retrieval of data in and out of buffer 225. Buffer 225 may include data path switching components for bidirectional data transfer between buffer 225 and other components.

[0049] The temporary storage of data in buffer 225 refers to the storage of data in buffer 225 during the execution of an access command. That is, after the access command is completed, the associated data may no longer be maintained in buffer 225 (e.g., it may be overwritten by data from an additional access command). Furthermore, buffer 225 may be a non-cached buffer. That is, the host system 205 may not read data directly from buffer 225. For example, a read command may be added to a queue without performing an operation to match the address with an address already existing in buffer 225 (e.g., no cached address matching or lookup operation).

[0050] The memory system 210 may additionally include a memory system controller 215 for executing commands received from the host system 205 and controlling data path components when moving data. The memory system controller 215 may be as described in the reference... Figure 1 An example of the described memory system controller 115. Bus 235 can be used for communication between system components.

[0051] In some cases, one or more queues (e.g., command queue 260, buffer queue 265, and storage queue 270) can be used to control the processing of access commands and the movement of corresponding data. For example, this can be advantageous if the memory system 210 processes more than one access command from the host system 205 in parallel. As examples of possible implementations, command queue 260, buffer queue 265, and storage queue 270 are depicted at interface 220, memory system controller 215, and storage controller 230, respectively. However, they can be located anywhere within the memory system 210 if used.

[0052] Data transferred between host system 205 and memory device 240 may take a different path within memory system 210 than non-data information (e.g., commands, status information). For example, system components in memory system 210 may communicate with each other using bus 235, while data may use data path 250 via data path components instead of bus 235. Memory system controller 215 may control how and whether data is transferred between host system 205 and memory device 240 by communicating with data path components via bus 235 (e.g., using a protocol specific to memory system 210).

[0053] If host system 205 transmits access commands to memory system 210, the commands can be received by interface 220, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). Therefore, interface 220 can be considered as the front end of memory system 210. Upon receiving each access command, interface 220 can transmit the command to memory system controller 215, for example, via bus 235. In some cases, each command can be added to command queue 260 via interface 220 to transmit the command to memory system controller 215.

[0054] The memory system controller 215 can determine that an access command has been received based on a transmission from interface 220. In some cases, the memory system controller 215 can determine that the access command has been received by retrieving the command from command queue 260. The command can be removed from command queue 260 after it has been retrieved, for example, through the memory system controller 215. In some cases, the memory system controller 215 can cause interface 220 to remove the command from command queue 260, for example, via bus 235.

[0055] Once it is determined that an access command has been received, the memory system controller 215 can execute the access command. For a read command, this may mean obtaining data from the memory device 240 and transferring the data to the host system 205. For a write command, this may mean receiving data from the host system 205 and moving the data to the memory device 240.

[0056] In either case, the memory system controller 215 may use the buffer 225 to temporarily store data received from or sent to the host system 205, and for other purposes. The buffer 225 may be considered as an intermediate part of the memory system 210. In some cases, buffer address management (e.g., addressing pointers to locations in the buffer 225) may be performed by hardware (e.g., dedicated circuitry) in the interface 220, the buffer 225, or the memory controller 230.

[0057] In order to process a write command received from host system 205, memory system controller 215 may first determine whether buffer 225 has sufficient available space to store the data associated with the command. For example, memory system controller 215 may determine the amount of space available in buffer 225 to store the data associated with the write command, for example via firmware (e.g., controller firmware).

[0058] In some cases, buffer queue 265 can be used to control the flow of commands associated with data stored in buffer 225, including write commands. Buffer queue 265 may contain access commands associated with data currently stored in buffer 225. In some cases, commands in command queue 260 can be moved to buffer queue 265 via memory system controller 215 and can remain in buffer queue 265 while the associated data is stored in buffer 225. In some cases, each command in buffer queue 265 may be associated with an address at buffer 225. That is, a pointer indicating where the data associated with each command is stored in buffer 225 can be maintained. Using buffer queue 265, multiple access commands can be received sequentially from host system 205 and at least some portions of the access commands can be processed in parallel.

[0059] If buffer 225 has sufficient space to store the write data, memory system controller 215 may cause interface 220 to transmit an availability indication (e.g., a "ready to transfer" indication) to host system 205, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). When interface 220 subsequently receives data associated with the write command from host system 205, interface 220 may use data path 250 to transfer the data to buffer 225 for temporary storage. In some cases, interface 220 may obtain the location of the stored data within buffer 225 from buffer 225 or buffer queue 265. Interface 220 may indicate to memory system controller 215, for example, via bus 235 whether the data transfer to buffer 225 has been completed.

[0060] Once written data has been stored in buffer 225 via interface 220, the data can be transferred outside buffer 225 and stored in memory device 240. This can be accomplished using memory controller 230. For example, memory system controller 215 can cause memory controller 230 to retrieve data outside buffer 225 using data path 250 and transfer the data to memory device 240. Memory controller 230 can be considered as the back-end of memory system 210. Memory controller 230 can, for example, indicate to memory system controller 215 via bus 235 that data transfer to memory device 240 has been completed.

[0061] In some cases, memory queue 270 can be used to assist in the transfer of write data. For example, memory system controller 215 can push write commands from buffer queue 265 (e.g., via bus 235) to memory queue 270 for processing. Memory queue 270 may contain entries for each access command. In some instances, memory queue 270 may additionally contain: a buffer pointer (e.g., an address) indicating where in buffer 225 the data associated with the command is stored; and a memory pointer (e.g., an address) indicating the location in memory device 240 associated with the data. In some cases, memory controller 230 can obtain the location of data to be retrieved from buffer 225 from buffer 225, buffer queue 265, or memory queue 270. Memory controller 230 can manage the location of stored data in memory device 240 (e.g., for wear leveling, garbage collection, and the like). Entries can be added to memory queue 270, for example, via memory system controller 215. After the data transfer is complete, the entry can be removed from the storage queue 270, for example, by the storage controller 230 or the memory system controller 215.

[0062] In order to process a read command received from host system 205, memory system controller 215 may again first determine whether buffer 225 has sufficient available space to store the data associated with the command. For example, memory system controller 215 may determine the amount of space available in buffer 225 to store the data associated with the read command, for example via firmware (e.g., controller firmware).

[0063] In some cases, buffer queue 265 can be used to supplement buffer storage of data associated with read commands in a manner similar to that discussed above regarding write commands. For example, if buffer 225 has sufficient space to store read data, memory system controller 215 can cause memory controller 230 to retrieve the data associated with the read command from memory device 240 and store the data in buffer 225 for temporary storage using data path 250. Memory controller 230 can indicate to memory system controller 215, for example, via bus 235, when data transfer to buffer 225 has been completed.

[0064] In some cases, the storage queue 270 can be used to assist in the transfer of read data. For example, the memory system controller 215 can push a read command to the storage queue 270 for processing. In some cases, the storage controller 230 can obtain the location of data retrieved from the memory device 240 from the buffer 225 or the storage queue 270. In some cases, the storage controller 230 can obtain the location of data stored in the buffer 225 from the buffer queue 265. In some cases, the storage controller 230 can obtain the location of stored data in the buffer 225 from the storage queue 270. In some cases, the memory system controller 215 can move a command processed by the storage queue 270 back to the command queue 260.

[0065] Once data has been stored in buffer 225 by storage controller 230, it can be transferred from buffer 225 and sent to host system 205. For example, storage system controller 215 may enable interface 220 to retrieve data from buffer 225 using data path 250 and transfer the data to host system 205, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). For example, interface 220 may process commands from command queue 260 and may indicate to storage system controller 215, for example, via bus 235, that the data transfer to host system 205 has been completed.

[0066] The memory system controller 215 can execute received commands in a sequence (e.g., according to the order of command queue 260, in a first-in, first-out order). For each command, the memory system controller 215 can cause the data corresponding to the command to move in and out of buffer 225, as discussed above. While the data is moving into and stored in buffer 225, the command can remain in buffer queue 265. If processing of the command has been completed (e.g., if the data corresponding to the access command has been transferred out of buffer 225), the command can be removed from buffer queue 265, for example, via the memory system controller 215. If the command is removed from buffer queue 265, the address where the data previously associated with the command was stored can be used to store the data associated with the new command.

[0067] The memory system controller 215 may be additionally configured for operations associated with one or more memory devices 240. For example, the memory system controller 215 may perform or manage operations such as wear leveling, garbage collection, error control (e.g., error detection or error correction), encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., LBAs) associated with commands from the host system 205 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 240. That is, the host system 205 may issue commands indicating one or more LBAs, and the memory system controller 215 may recognize one or more physical block addresses indicated by the LBAs. In some cases, one or more consecutive LBAs may correspond to non-consecutive physical block addresses. In some cases, the memory controller 230 may be configured to perform one or more of the above operations in conjunction with or in place of the memory system controller 215. In some cases, the memory system controller 215 may perform the functions of the memory controller 230, and the memory controller 230 may be omitted.

[0068] In some cases, host system 205 can access information at one or more memory devices 240 at memory system 210 by transmitting access commands to interface 220. For example, interface 220 may be as described in reference... Figure 1 An example of a memory system controller is described. In some cases, in response to each access command, interface 220 may send an RTT message to indicate a ready state for receiving data from host system 205. In some instances, host system 205 may store the state of memory system 210 based on the RTT message. Sending an RTT message after each access command can increase latency at system 200. Alternatively, memory system 210 may be unable to access memory at host system 205, which can further reduce efficiency.

[0069] To improve efficiency and reduce latency at system 200, host system 205 and memory system 210 may be configured to support device-controlled access to a portion of volatile memory. For example, the portion of volatile memory may be a portion of DRAM or SRAM located at host system 205 or memory system 210. For example, one or more of memory devices 240 may be a dedicated portion of volatile memory. For each access command, host system 205 may allocate the same memory resource (e.g., PRDT) at volatile memory. That is, multiple access commands may address the same location in volatile memory, for example, at host system 205. By allocating the same memory resource, host system 205 can reduce the amount of RTT messages sent by memory system 210. For example, in some cases, memory system 210 may send RTT messages in response to multiple access commands (e.g., a read command and a write command pair), thereby reducing latency at system 200.

[0070] Figure 3 An example of a system 300 supporting memory device access technology according to the examples disclosed herein is shown. System 300 may be as described in the references... Figure 1 and 2 Examples of the described system 100 or system 200. System 300 may include a memory system 310 and a host system 305. Memory system 310 may include a controller 315 and a memory device 330-a configured to store data. Host system 305 may include a memory device 330-b configured to store data. System 300 may support an interface of host system 305 to transmit access commands 320 (e.g., start commands, read commands, or write commands) to memory system 310 and receive a ready status indicator (e.g., RTT message 325) from memory system 310 in response to access commands 320. In some instances, host system 305 may store the state of memory system 310 (e.g., at memory device 330-b) based on RTT message 325.

[0071] The memory system 310 may include a controller 315, which may act as an interface between the host system 305 and the memory system 310. The controller 315 may be as described in the reference. Figure 2 The described exemplary apparatus may be an example of one or a combination thereof. For example, controller 315 may be an example of interface 220, memory system controller 215, memory controller 230, or a combination thereof. Memory system 310 may include memory device 330-a, which may be a reference... Figure 1 and 2Examples of the described memory devices. For example, memory device 330-a may be non-volatile memory (e.g., NAND), or in some cases may be volatile memory (e.g., DRAM). In some cases, memory system 310 may include a plurality of memory devices 330, each of which may be coupled to controller 315.

[0072] The host system 305 may transmit one or more access commands 320, which may instruct operations to be performed by the memory system 310. The host system 305 may transmit the access commands 320 to the controller 315, and the controller 315 may decode the access commands 320 and access the associated data stored in the memory device 330-a, or forward the access commands 320 to the memory device 330-a (e.g., the local controller of the memory device 330-a). In some instances, the size of the data associated with each access command 320 may be a maximum allowable size (e.g., 2 gigabytes (GB)), such as the maximum allowable size according to industry standard specifications (e.g., the UFS specification or the Non-Volatile Memory High Speed ​​(NVMe) specification).

[0073] In some instances, host system 305 may include memory device 330-b. In some cases, controller 315 may access memory device 330-b directly at host system 305. For example, memory device 330-b may be an instance of SRAM or DRAM. Controller 315 at memory system 310 may be configured to initiate device-controlled access to memory device 330-b, which may reduce the number of commands exchanged between memory system 310 and host system 305. For example, in some cases, memory system 310 may send an indication of the ready status of received data (e.g., RTT message 325) after receiving two access commands from host system 305.

[0074] Memory device 330-b may contain a list of memory resources (e.g., a PRDT) associated with one or more access commands 320. For example, host system 305 may allocate a PRDT for a first access command 320. At a later time, host system 305 may allocate the same PRDT for a second access command 320. That is, the first and second access commands 320 may address the same location in memory device 330-b. In some cases, the PRDT may be located at memory device 330-a. By allocating the same PRDT for both access commands 320, memory system 310 may transmit a single RTT message 325 for both access commands 320.

[0075] In some cases, host system 305 may transmit access command 320 to initiate data transfer between memory system 310 and host system 305. In some cases, host system 305 may transmit access command 320 to perform an access operation (e.g., a read operation of a write operation). Access command 320 may indicate the address of a starting logical block in memory device 330-a and the amount of consecutive logical blocks of data for the corresponding access operation (e.g., a range or set of data).

[0076] Controller 315 can receive and decode access command 320 to identify the dataset. Controller 315, memory system 310, memory device 330-a, or any combination thereof can perform the access operation. In some instances, controller 315 can determine the readiness state for receiving data from host system 305 and can transmit RTT message 325 to host system 305. In some cases, during the decoding of access command 320, controller 315 can determine whether errors exist in the dataset (e.g., whether the data is valid). In some instances, controller 315 can transmit RTT message 325 via UFS Protocol Interface Unit (UPIU). In some cases, controller 315 can transmit RTT message 325 after receiving a pair of access commands 320, rather than after receiving each access command 320. Host system 305 can thus receive RTT message 325, which indicates a readiness state for receiving data without initiating a read operation, which can reduce processing and latency.

[0077] Figure 4 An example of a process flow 400 supporting memory device access technology according to the embodiments disclosed herein is shown. Process flow 400 can be illustrated as described in reference... Figure 1-3 The process implemented by the described system 100 (or one or more components thereof), system 200 (or one or more components thereof), or system 300 (or one or more components thereof). Process flow 400 may describe the process for accessing a memory device.

[0078] Aspects of process flow 400 may be implemented by one or more controllers and other components (e.g., the memory system controller of memory system 410 or the host system controller of host system 405). Alternatively or additionally, aspects of process flow 400 may be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to memory system 410). For example, instructions, when executed by a controller, may cause the controller to perform operations of process flow 400. In some cases, alternative instances may be implemented, some of which may be performed in a different order than described or not at all. In some cases, operations may include features not mentioned below, or additional operations may be added.

[0079] At 415, a first access command can be transmitted to memory system 410. For example, host system 405 can transmit the first access command to memory system 410. In some cases, the first access command can be a start command, a read command, or a write command. The first access command can be an instance of a UPIU memory access (UMA) command. For example, the first access command can be a UMA_OPEN command, which can be an instance of a read or write type command. The UMA_OPEN command can open a session (e.g., data transfer between memory system 410 and host system 405) and can be used by memory system 410 for tunneled access to host system 405. For example, the UMA_OPEN command can implement access to a portion of volatile memory at host system 405.

[0080] In some cases, the first access command may be a UMA_SUSPEND command, which may be an instance of a write command. The UMA_SUSPEND command can be used to request memory system 410 to close (e.g., complete) an unprocessed command. For example, the UMA_SUSPEND command may trigger memory system 410 to perform one or more access operations associated with a previously received command. In some cases, the UMA_SUSPEND command may be replaced by a flag interface or abort task request included in another command. In some cases, the start command may be an instance of a UIC command. Host system 405 may allocate a portion of memory associated with the access command. For example, host system 405 may allocate a PRDT (e.g., a hash table of memory resources) at a portion of volatile memory. In some cases, the PRDT may be located at host system 405 or at a portion of volatile memory at memory system 410.

[0081] At 420, a second access command may be transmitted to memory system 410. For example, host system 405 may transmit the second access command to memory system 410. In some cases, the second access command may be a read command or a write command. For example, the second access command may be a UMA_OPEN command, which may be an instance of a read or write type command. In some instances, the size of the data associated with each of the first and second access commands may be a maximum allowable size (e.g., 2GB), such as the maximum allowable size according to industry standard specifications (e.g., UFS specification or NVMe specification).

[0082] Host system 405 may allocate a portion of memory associated with the second access command. In some cases, host system 405 may allocate the same portion of memory as allocated for the first access command. That is, the first and second access commands may address the same memory location. For example, host system 405 may allocate the PRDT at the same portion of volatile memory located in memory system 410 or host system 405.

[0083] At point 425, a ready status indicator can be transmitted to host system 405. For example, memory system 410 can transmit a ready status indicator to host system 405. The ready status indicator may be as shown in the reference. Figure 3 Examples of described RTT messages. In some instances, host system 405 may store the state of memory system 410 based on a ready state indicator. In some instances, an RTT message may be transmitted in response to a pair of access commands (e.g., a first access command received at 415 and a second access command received at 420). In some cases, the same PRDT associated with both the first and second access commands may enable memory system 410 to transmit a single RTT message for both access commands, rather than transmitting an RTT message for each access command, thereby reducing latency.

[0084] In some instances, at 430, memory system 410 may perform one or more access operations. For example, memory system 410 may perform an access operation at 425 after indicating it is ready to receive data via an RTT message. In some instances, an access operation may be performed at 415 in response to receiving a first access command or at 420 in response to receiving a second access command. In some instances, memory system 410 may perform more than one access operation at 430 (e.g., an access operation at 425 for each access command received before the transmission ready status indicator).

[0085] In some instances, at 435, a third access command can be transmitted to memory system 410. For example, host system 405 can transmit a third access command to memory system 410. In some cases, the third access command can be a read command or a write command. For example, the third access command can be a UMA_OPEN command, which can be an instance of a read or write type command. In some instances, the third access command can be a UMA_SUSPEND command, which can be an instance of a write command. In some cases, the third access command can be a UMA_CLOSE command, which can be an instance of a write command. The UMA_CLOSE command can be used to request memory system 410 to release space in volatile memory (e.g., DRAM, SRAM) by transmitting some information to non-volatile memory (e.g., NAND). For example, the UMA_CLOSE command can be used to ensure that contiguous space exists for future access commands in volatile memory. Host system 405 can allocate a portion of the memory associated with the second access command. In some cases, host system 405 may allocate the same portion of memory as allocated for the first access command and the second access command. For example, host system 405 may allocate the PRDT in the same portion of volatile memory located in memory system 410 or host system 405.

[0086] In some instances, at 440, a certain amount of information can be transferred to memory system 410. For example, host system 405 can transfer said certain amount of information to memory system 410. The information may be a list of memory resources associated with a first, second, or third access command. For example, in some cases, the PRDT associated with the access command may be located in volatile memory at host system 405. In such cases, before the host system may lose power, it can transfer the information at the PRDT to non-volatile memory at memory system 410. For example, the host system can transfer information to a memory device, such as referenced... Figure 3 As described. In such cases, the third access command can be the UMA_CLOSE command, which can trigger the transfer of information to non-volatile memory.

[0087] In some instances, at 445, the memory system 410 may monitor information received from the host system 405. For example, the memory system 410 may receive information as part of a first, second, or third access command. In some cases, the memory system 410 may receive information at 440 when the host system 405 transfers information to non-volatile memory. In some cases, the memory system 410 may have dedicated hardware for tracking the amount of information received. The memory system 410 may monitor the received information to determine whether the amount meets a threshold. In some cases, the memory system 410 may determine that the host system 405 may anticipate performing a data transfer or access operation based on the monitoring. For example, the history of received access commands and other information may indicate a pattern of access operations to be performed.

[0088] In some instances, at 450, memory system 410 may perform an access operation in response to monitoring received information at 445. For example, memory system 410 may perform an access operation based on a history of information received from host system 405 without receiving an explicit command to do so. That is, memory system 410 may anticipate when host system 405 may anticipate performing an access operation. The access operation may be an instance of a read or write command. In some instances, the access operation may be an instance of the UMA_OPEN command, UMA_SUSPEND command, or UMA_CLOSE command as discussed herein.

[0089] Figure 5 A block diagram 500 illustrates a memory device 520 supporting memory device access technology according to an example disclosed herein. The memory device 520 may be referenced. Figure 1-4 Examples of various aspects of the described memory device. Memory device 520 or its various components may be examples of components for performing various aspects of the memory device access techniques described herein. For example, memory device 520 may include receiving component 525, transmitting component 530, monitoring component 535, access operation component 540, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0090] The receiving component 525 may be configured or otherwise supported to include means for receiving a first command to perform a first access operation. In some instances, the receiving component 525 may be configured or otherwise supported to include means for receiving a second command to perform a second access operation before transmitting a response to the first command. The transmitting component 530 may be configured or otherwise supported to include means for transmitting an indication of a ready state for receiving data from the memory device in response to the first and second commands.

[0091] In some instances, the first command includes a read command and the second command includes a write command.

[0092] In some instances, the receiving component 525 may be configured or otherwise supported for receiving a third command to perform a third access operation, wherein the third command includes a write command.

[0093] In some instances, receiving component 525 may be configured or otherwise supported for receiving a list of memory resources, at least in part, based on receiving a third command.

[0094] In some instances, receiving component 525 may be configured or otherwise supported to support means for receiving multiple commands, each of which includes a read command or a write command. In some instances, transmitting component 530 may be configured or otherwise supported to support means for transmitting a corresponding indication of the readiness state of the memory device for receiving data in response to each pair of commands.

[0095] In some instances, receiving component 525 may be configured or otherwise supported as a component for receiving a certain amount of data, at least in part, based on a transmission instruction.

[0096] In some instances, monitoring component 535 may be configured or otherwise supported to support components for monitoring a received quantity of data. In some instances, access operation component 540 may be configured or otherwise supported to support components for performing access operations based at least in part on a quantity of data satisfying a threshold.

[0097] In some instances, the first and second commands are associated with logical addresses outside the memory device.

[0098] In some instances, the first command and the second command are associated with the same memory address.

[0099] In some instances, a first command and a second command are executed based on either a first data mode or a second data mode. In some instances, the first data mode and the second data mode are associated with a reserved portion of the buffer.

[0100] In some instances, each of the first and second commands includes one or more attributes, one or more flags, or any combination thereof associated with the configuration of the volatile memory.

[0101] In some instances, the indication of readiness status includes the status of the memory device.

[0102] Figure 6 A block diagram 600 illustrates a host device 620 supporting memory device access technology according to an example disclosed herein. The host device 620 may be as described in the reference... Figures 1 to 4 Examples of various aspects of the described host device. Host device 620 or its various components may be examples of components for performing various aspects of the memory device access techniques described herein. For example, host device 620 may include a transmission component 625, a storage component 630, a receiving component 635, a command performance component 640, a data buffer component 645, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0103] The transmission component 625 may be configured or otherwise support means for transmitting a first command performing a first access operation to the memory device. The storage component 630 may be configured or otherwise support means for storing first information associated with the first command in a memory resource list. In some instances, the transmission component 625 may be configured or otherwise support means for transmitting a second command performing a second access operation to the memory device. In some instances, the storage component 630 may be configured or otherwise support means for storing second information associated with the second command in a memory resource list. The receiving component 635 may be configured or otherwise support means for receiving an indication at the host device of a ready state for receiving data from the memory device in response to the first and second commands.

[0104] In some instances, the list of memory resources is contained in a physical area description table located in a portion of volatile memory at the host device.

[0105] In some instances, the first command includes a read command and the second command includes a write command.

[0106] In some instances, the transfer component 625 may be configured or otherwise support means for transferring a third command performing a third access operation to a memory device, wherein the third command includes a write command. In some instances, the storage component 630 may be configured or otherwise support means for storing third information associated with the third command in a memory resource list.

[0107] In some instances, the transfer component 625 may be configured or otherwise support a means for transferring a list of memory resources to a memory device, at least in part, based on a third transfer command.

[0108] In some instances, the transmission component 625 may be configured or otherwise supported to support means for transmitting a plurality of commands to a memory device, wherein each of the plurality of commands includes a read command or a write command. In some instances, the receiving component 635 may be configured or otherwise supported to support means for receiving an indication of a ready state for receiving data on the memory device in response to each pair of commands.

[0109] In some instances, the transmission component 625 may be configured or otherwise support a means for transmitting a quantity of data to a memory device, at least in part based on an indication of a ready state for received data.

[0110] In some instances, the first and second commands are associated with logical addresses outside the memory device.

[0111] In some instances, the first command and the second command are associated with the same address in the memory at the host device.

[0112] In some instances, a first command and a second command are executed based on either a first data mode or a second data mode. In some instances, the first data mode and the second data mode are associated with a reserved portion of the buffer.

[0113] In some instances, each of the first and second commands includes one or more attributes, one or more flags, or any combination thereof associated with the configuration of volatile memory at the host device.

[0114] In some instances, the indication of readiness status includes the status of the memory device.

[0115] Figure 7 A flowchart illustrating a method 700 supporting memory device access technology according to an example disclosed herein is shown. The operation of method 700 can be implemented by a memory device or its components as described herein. For example, it can be implemented by, as referenced... Figures 1 to 5 The described memory device performs the operations of method 700. In some instances, the memory device may execute an instruction set to control the functional elements of the device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0116] At 705, the method may include receiving a first command to perform a first access operation. The operation at 705 may be performed according to examples disclosed herein. In some instances, aspects of the operation at 705 may be as described in references... Figure 5 The described receiving component 525 is used to perform this action.

[0117] At 710, the method may include receiving a second command to perform a second access operation before transmitting a response to the first command. The operation at 710 may be performed according to examples as disclosed herein. In some instances, aspects of the operation at 710 may be as described in references... Figure 5 The described receiving component 525 is used to perform this action.

[0118] At 715, the method may include transmitting an indication of a ready state for the memory device to receive data in response to a first command and a second command. The operation of 715 may be performed according to examples as disclosed herein. In some instances, aspects of the operation of 715 may be as described in references... Figure 5 The described transmission component 530 is executed.

[0119] In some instances, the device as described herein may perform one or more methods, such as method 700. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) or any combination thereof for performing aspects of this disclosure:

[0120] Aspect 1: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: receiving a first command to perform a first access operation; receiving a second command to perform a second access operation prior to transmitting a response to the first command; and transmitting an indication of a ready state for receiving data in response to the first command and the second command.

[0121] Aspect 2: The method, device, or non-transitory computer-readable medium according to aspect 1, wherein the first command includes a read command and the second command includes a write command.

[0122] Aspect 3: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 2 further includes an operation, feature, circuit system, logic, component, or instruction, or any combination thereof, for receiving a third command to perform a third access operation, wherein the third command includes a write command.

[0123] Aspect 4: The method, apparatus, or non-transitory computer-readable medium according to aspect 3 further includes features, circuitry, logic, components, or instructions, or any combination thereof, for receiving a list of memory resources at least in part based on receiving the third command.

[0124] Aspect 5: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 4 further includes operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: receiving a plurality of commands, each of which includes a read command or a write command; and, in response to each pair of the plurality of commands, transmitting a corresponding indication of the ready state for receiving data by the memory device.

[0125] Aspect 6: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 5 further includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for receiving a certain amount of data at least in part based on the transmission of the instruction.

[0126] Aspect 7: The method, apparatus, or non-transitory computer-readable medium according to aspect 6 further includes features, circuitry, logic, components, or instructions, or any combination thereof, for: monitoring the received amount of data and performing an access operation based at least in part on the amount of data satisfying a threshold.

[0127] Aspect 8: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 7, wherein the first command and the second command are associated with a logical address outside the memory device.

[0128] Aspect 9: A method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 8, wherein the first command and the second command are associated with the same address of memory.

[0129] Aspect 10: A method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 9, wherein the first command and the second command are executed according to a first data mode or a second data mode; and the first data mode and the second data mode are associated with a reserved portion of a buffer.

[0130] Aspect 11: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 10, wherein each of the first command and the second command includes one or more attributes, one or more flags, or any combination thereof associated with the configuration of the volatile memory.

[0131] Aspect 12: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 11, wherein the indication of the ready state includes the state of the memory device.

[0132] Figure 8A flowchart illustrating a method 800 supporting memory device access technology according to an example disclosed herein is shown. The operation of method 800 can be implemented by a host device or its components as described herein. For example, it can be implemented by, as referenced... Figures 1 to 4 The host device described in section 6 performs the operation of method 800. In some instances, the host device may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively, the host device may use dedicated hardware to perform aspects of the described functions.

[0133] At 805, the method may include transmitting a first command to a memory device to perform a first access operation. The operation at 805 may be performed according to examples disclosed herein. In some instances, aspects of the operation at 805 may be described by reference to... Figure 6 The described transmission component 625 is used to perform this.

[0134] At 810, the method may include storing first information associated with the first command in a list of memory resources. The operation of 810 may be performed according to examples disclosed herein. In some instances, aspects of the operation of 810 may be as described in references... Figure 6 The described storage component 630 is executed.

[0135] At point 815, the method may include transmitting a second command to the memory device to perform a second access operation. The operation at point 815 may be performed according to examples disclosed herein. In some instances, aspects of the operation at point 815 may be described by reference to... Figure 6 The described transmission component 625 is used to perform this.

[0136] At 820, the method may include storing second information associated with the second command in a list of memory resources. The operation of 820 may be performed according to examples disclosed herein. In some instances, aspects of the operation of 820 may be as described in references... Figure 6 The described storage component 630 is executed.

[0137] At 825, the method may include receiving, at the host device, an indication of a ready state for receiving data from the memory device in response to a first command and a second command. Operation of 825 may be performed according to examples as disclosed herein. In some instances, aspects of operation of 825 may be as described in references... Figure 6 The described receiving component 635 is used to perform this action.

[0138] In some instances, the device as described herein may perform one or more methods, such as method 800. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) or any combination thereof for performing aspects of this disclosure:

[0139] Aspect 13: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: transmitting a first command to a memory device to perform a first access operation; storing first information associated with the first command in a memory resource list; transmitting a second command to the memory device to perform a second access operation; storing second information associated with the second command in the memory resource list; and receiving an indication of a ready state for receiving data from the memory device at a host device in response to the first command and the second command.

[0140] Aspect 14: The method, apparatus, or non-transitory computer-readable medium according to aspect 13, wherein the list of memory resources is contained in a physical area description table located in a portion of volatile memory at the host device.

[0141] Aspect 15: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 13 to 14, wherein the first command comprises a read command and the second command comprises a write command.

[0142] Aspect 16: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 13 to 15 further comprises an operation, feature, circuit system, logic, component, or instruction, or any combination thereof, for: transmitting a third command to the memory device to perform a third access operation, wherein the third command includes a write command; and storing third information associated with the third command in the memory resource list.

[0143] Aspect 17: The method, apparatus, or non-transitory computer-readable medium according to aspect 16 further includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for transmitting the memory resource list to the memory device, at least in part based on the transmission of the third command.

[0144] Aspect 18: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 13 to 17 further comprises an operation, feature, circuit system, logic, component, or instruction, or any combination thereof, for: transmitting a plurality of commands to the memory device, wherein each of the plurality of commands comprises a read command or a write command; and receiving, in response to each pair of the plurality of commands, an indication of a ready state for the memory device to receive data.

[0145] Aspect 19: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 13 to 18 further comprises an operation, feature, circuit system, logic, component, or instruction, or any combination thereof, for transmitting a quantity of data to the memory device, at least in part based on receiving the indication of the ready state of the received data.

[0146] Aspect 20: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 13 to 19, wherein the first command and the second command are associated with a logical address outside the memory device.

[0147] Aspect 21: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 13 to 20, wherein the first command and the second command are associated with the same address of memory at the host device.

[0148] Aspect 22: A method, apparatus or non-transitory computer-readable medium according to any one of aspects 13 to 21, wherein the first command and the second command are executed according to a first data mode or a second data mode; and the first data mode and the second data mode are associated with a reserved portion of a buffer.

[0149] Aspect 23: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 13 to 22, wherein each of the first command and the second command includes one or more attributes, one or more flags, or any combination thereof associated with the configuration of volatile memory at the host device.

[0150] Aspect 24: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 13 to 23, wherein the indication of the ready state includes the state of the memory device.

[0151] It should be noted that the methods described above describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described may be combined.

[0152] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof, can be used to represent data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description. Some diagrams may illustrate signaling as a single signal; however, signals may represent buses of signals, which may have various bit widths.

[0153] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of electrons between them. Components are considered to be in electronic communication with each other (or in conductive contact, connected, or coupled) if any conductive path exists between them that can support the flow of signals at any given time. At any given time, the conductive path between components that are electronically connected (or in conductive contact, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the signal flow between connected components for a period of time.

[0154] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via conductive paths, while in a closed-circuit relationship, signals can travel between components via conductive paths. If a component, such as a controller, couples other components together, then the component initially allows signals to flow between other components via conductive paths that were previously not permitted.

[0155] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between them are isolated from each other when the switch is open. If a controller isolates two components, it achieves the following change: preventing signals from flowing between the components using previously permitted conductive paths.

[0156] As used herein, the term "layer" or "level" refers to a layer or sheet of geometry (e.g., relative to a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or level may be a three-dimensional structure in which two dimensions are greater than the third, such as a thin film. A layer or level may contain different elements, components, and / or materials. In some instances, a layer or level may consist of two or more sublayers or sublevels.

[0157] As used in this article, the term “generally” means that the modified feature (e.g., a verb or adjective modified by the term “generally”) does not have to be absolute but must be close enough to obtain the advantage of the feature.

[0158] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, the terms “if,” “when,” “based on,” or “at least partially based on” are used to describe a connection between conditional actions, conditional processes, or parts of a process.

[0159] The term "in response to" can refer to a condition or action that occurs at least partially (if not completely) as a result of a prior condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least partially as a result of the occurrence of the prior condition or action (whether directly after the first condition or action or after one or more other intermediate conditions or actions following the first condition or action).

[0160] Additionally, the terms "directly in response to" or "directly responding to" can refer to a condition or action occurring as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as "based on," "at least in part based on," or "in response to" a certain other step, action, event, or condition may additionally or alternatively (e.g., in alternative instances) "directly in response to" or "directly responding to" such other condition or action.

[0161] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0162] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, a drain, and a gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped, for example, degenerate, semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be called a p-type FET. The channel may be capped by an insulating gate oxide. The conductivity of the channel can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0163] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "advantageous" over other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0164] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a hyphen following the reference numeral and a second numeral used to differentiate between similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0165] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed implementations such that portions of the functions are implemented in different physical locations.

[0166] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or executed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components, or any combination thereof. A general-purpose processor may be a microprocessor; however, alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0167] As used herein, the word "or," as used in the claims, such as in a list of items (e.g., a list of items followed by phrases such as "at least one of" or "one or more of"), indicates a list containing endpoints such that a list of at least one of, for example, A, B, or C, means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0168] Computer-readable media includes both non-transitory computer-readable storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), compressed optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, these technologies are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0169] The description provided herein enables those skilled in the art to make or use this disclosure. Those skilled in the art will appreciate the various modifications that can be made to this disclosure, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: A controller, associated with a memory device, wherein the controller is configured to cause the device to: Receive the first command to execute the first access operation; Before transmitting a response to the first command, a second command to perform a second access operation is received, wherein the first command and the second command are associated with the same address in the memory; and In response to the first command and the second command, a single indication of the readiness state of the memory device to receive data is transmitted.

2. The device of claim 1, wherein the first command includes a read command and the second command includes a write command.

3. The device of claim 1, wherein the controller is further configured to cause the device to: Receive a third command to perform a third access operation, wherein the third command includes a write command.

4. The device of claim 3, wherein the controller is further configured to cause the device to: The list of memory resources is received at least in part based on the receipt of the third command.

5. The device of claim 1, wherein the controller is further configured to cause the device to: Receive multiple commands, each of which includes a read command or a write command; and In response to each pair of commands, a corresponding indication of the ready state for receiving data from the memory device is transmitted.

6. The device of claim 1, wherein the controller is further configured to cause the device to: A certain amount of data is received, at least in part, based on the transmission of the single instruction.

7. The device of claim 6, wherein the controller is further configured to cause the device to: Monitor the received amount of data; and Access operations are performed at least in part based on the fact that a certain amount of data meets a threshold.

8. The device of claim 1, wherein the first command and the second command are associated with a logical address outside the memory device.

9. The device of claim 1, wherein the first command and the second command are associated with the same Physical Region Description Table (PRDT).

10. The device according to claim 1, wherein: Execute the first command and the second command according to the first data mode or the second data mode; and The first data mode and the second data mode are associated with the reserved portion of the buffer.

11. The device of claim 1, wherein each of the first command and the second command includes one or more attributes, one or more flags, or any combination thereof associated with the configuration of the memory.

12. The device of claim 1, wherein the single indication of the ready state includes the state of the memory device.

13. An apparatus comprising: A controller associated with a host device, wherein the controller is configured to cause the device to: The first command to perform the first access operation is transmitted to the memory device; Store the first information associated with the first command in the memory resource list; The second command to perform the second access operation is transmitted to the memory device; The second information associated with the second command is stored in the memory resource list, wherein the first command and the second command are associated with the same address in the memory at the host device; and In response to the first command and the second command, an indication of the ready state for receiving data from the memory device is received at the host device.

14. The device of claim 13, wherein the list of memory resources is contained in a physical area description table located in a portion of volatile memory at the host device.

15. The device of claim 13, wherein the first command includes a read command and the second command includes a write command.

16. The device of claim 13, wherein the controller is further configured to cause the device to: A third command to perform a third access operation is transmitted to the memory device, wherein the third command includes a write command; and The third information associated with the third command is stored in the memory resource list.

17. The device of claim 16, wherein the controller is further configured to cause the device to: The list of memory resources is transferred to the memory device, at least in part, based on the transmission of the third command.

18. The device of claim 13, wherein the controller is further configured to cause the device to: Multiple commands are transmitted to the memory device, wherein each of the multiple commands includes a read command or a write command; and In response to each pair of the plurality of commands, an indication of the ready state for receiving data from the memory device is received.

19. The device of claim 13, wherein the controller is further configured to cause the device to: A certain amount of data is transferred to the memory device, at least in part based on the received indication of the readiness state of the received data.

20. The device of claim 13, wherein the first command and the second command are associated with a logical address outside the memory device.

21. The device of claim 13, wherein the first command and the second command are associated with the same Physical Area Description Table (PRDT) at the host device.

22. The device according to claim 13, wherein: Execute the first command and the second command according to the first data mode or the second data mode; and The first data mode and the second data mode are associated with the reserved portion of the buffer.

23. The device of claim 13, wherein each of the first command and the second command includes one or more attributes, one or more flags, or any combination thereof associated with the configuration of the memory at the host device.

24. The device of claim 13, wherein the indication of the ready state includes the state of the memory device.

25. A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor to: Receive the first command to execute the first access operation; Before transmitting a response to the first command, a second command to perform a second access operation is received, wherein the first command and the second command are associated with the same address in the memory; and In response to the first command and the second command, a single indication of the readiness state of the memory device to receive data is transmitted.

Images