Puf module and mram integrated with puf functionality

Abstract

The application provides a PUF module and an MRAM integrated with a PUF function, the PUF module comprising a PUF data array and a PUF data reading circuit. The PUF data array is composed of a plurality of PUF data units, each PUF data unit containing a magnetic tunnel junction, and the magnetic tunnel junction in each PUF data unit can be randomly formed into one of three or four logic states. The three or four logic states include a parallel state and an anti-parallel state, and further include a short circuit state or / and an open circuit state. The PUF data reading circuit is used to read the logic state of each magnetic tunnel junction in the PUF data array to form PUF data. The application is beneficial to improving the PUF safety factor and facilitating chip integration by saving the area occupied by the PUF data unit.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a PUF module and an MRAM with integrated PUF functionality. Background Technology

[0002] While the Internet of Things (IoT) brings convenience to our lives, it also poses potential data security risks. Attacks targeting the IoT can even spread through devices to real-world applications, causing unimaginable damage. AIoT (Artificial Intelligence of Things) applications increasingly demand security attributes. However, the current common solution of using security chips + Nor Flash (non-volatile flash memory) suffers from drawbacks such as high cost and space constraints. PUF (Physically Unclonable Function) + novel memory chips is expected to become a mainstream solution for addressing the storage and security issues of smart devices. PUF utilizes the process variations in semiconductor manufacturing to generate a unique function for each chip, achieving one-to-one encryption, often referred to as a "chip fingerprint." PUF uses challenge-response pairs (CRPs), which are easy to evaluate, difficult to predict, and unique within the device. Currently, PUFs are typically implemented using integrated circuits and are commonly used in applications with high security requirements.

[0003] Currently, those skilled in the art are developing PUF chips based on ReRAM (Resistive RAM). ReRAM has the characteristics of high on / off ratio, simple manufacturing process (low cost), large range of random configuration distribution, and configuration randomness even after repeated writing, making it suitable for simple PUF chips. However, in terms of reliability, especially erase / write cycles, current technology makes it difficult to enter the high erase / write cycle market. Therefore, PUF chips are a better choice for ReRAM to enter the market early.

[0004] Those skilled in the art are also developing PUF chips based on MRAM (Magnetoresistive Random Access Memory). MRAM, as a novel type of memory, utilizes the giant magnetoresistance effect of the tunnel layer—the difference in high and low resistance states when the magnetic tunnel junction is in a parallel or antiparallel state—to store information. Compared to ReRAM, MRAM offers advantages such as higher reliability, high-speed access, unlimited read / write cycles, and low power consumption. An increasing number of high-speed, non-volatile applications are looking to leverage MRAM to improve system performance. Some users, in addition to using MRAM for storage, also require PUF modules or chips for authentication or hardware matching.

[0005] However, in existing PUF chips based on MRAM memory, each bit can only be randomly flipped to either a parallel or antiparallel state; that is, each bit can only be randomly flipped to one of two logical states. When generating PUF data, efforts should be made to ensure that the probability of each bit being randomly flipped to a parallel or antiparallel state is equal, thereby maximizing the Hamming distance. However, to increase the randomness of PUF data, the number of bits needs to be further increased, resulting in the PUF chip occupying more area, which is detrimental to the integration of MRAM memory. Summary of the Invention

[0006] This invention provides a PUF module and an MRAM with integrated PUF function, which randomly generates more types of PUF data, increases the Hamming distance between PUF chips, and facilitates chip integration.

[0007] In a first aspect, the present invention provides a PUF module, comprising a PUF data array and a PUF data read circuit. The PUF data array consists of multiple PUF data units, each PUF data unit containing a magnetic tunnel junction, and the magnetic tunnel junction in each PUF data unit can be randomly configured into one of three or four logic states. The PUF data read circuit is used to read the logic state of each magnetic tunnel junction in the PUF data array to form PUF data.

[0008] In the above-described scheme, by allowing the magnetic tunnel junction in each PUF data unit to be randomly formed into one of three or four logic states, the number of logic states that can be randomly formed in each PUF data unit is increased. Simultaneously, the distribution of the magnetic tunnel junctions in the added one or two logic states is uncontrollable, exhibiting complete randomness, thus increasing the inter-chip Hamming distance and the PUF security factor. Compared to the prior art where each bit has only two logic states, the scheme of this application can randomly form more types of PUF data with the same PUF data unit, increasing the inter-chip Hamming distance and improving the PUF security factor. Correspondingly, in applications requiring the same Hamming distance, the scheme of this application can use fewer PUF data units compared to prior art, thereby saving the area occupied by the PUF data units and facilitating chip integration. Furthermore, it overcomes the disadvantage of conventional MRAM having a lower switching ratio than RRAM and PCRAM, preventing its use for polymorphism.

[0009] In one specific implementation, these three or four logic states include parallel and antiparallel states, as well as short-circuit and / or open-circuit states. That is, these three or four logic states must include at least one of parallel and antiparallel states, and at least one of short-circuit and open-circuit states. This makes the distribution of the magnetic tunnel junctions in the added short-circuit and / or open-circuit states uncontrollable, exhibiting complete randomness, increasing the inter-chip Hamming distance, and increasing the PUF security factor. Furthermore, compared to the existing technology which only uses parallel and antiparallel states, the addition of at least one of short-circuit and open-circuit states not only facilitates the randomization of each PUF data unit into a short-circuit or open-circuit state, satisfying the randomness requirement, but also allows for a significant difference in resistance values ​​between the magnetic tunnel junctions in the short-circuit, parallel, antiparallel, or open-circuit states. This facilitates the PUF data read circuit to quickly and accurately read the logic state of each magnetic tunnel junction in the PUF data array, forming PUF data.

[0010] In one specific implementation, these three or four logic states include a short-circuit state. The PUF module also includes a breakdown circuit, which outputs a breakdown voltage of a first set value to the PUF data array to randomly break down some magnetic tunnel junctions in the PUF data array into a short-circuit state. Utilizing the possibility of inconsistent breakdown voltages (VBDs) between the magnetic tunnel junctions of different PUF data cells due to manufacturing process fluctuations, the added breakdown circuit randomly breaks down some magnetic tunnel junctions in the PUF data array into a short-circuit state, satisfying the randomness requirement and facilitating control of the breakdown probability.

[0011] In one specific implementation, the three or four logic states include a short-circuit state. Some magnetic tunnel junctions in the PUF data array are randomly fabricated into short-circuit states during fabrication. This utilizes the process randomness in PUF module fabrication to randomly fabricate some magnetic tunnel junctions in the PUF data array into short-circuit states, satisfying the randomness requirement and facilitating control over the proportion of short-circuit magnetic tunnel junctions.

[0012] In one specific implementation, the spacing between any two adjacent magnetic tunnel junctions in the same column or row of the PUF data array is within a set spacing range. This allows for the random distribution of metal redeposition material on the sidewalls of each magnetic tunnel junction during fabrication, randomly creating short-circuit states for some of the magnetic tunnel junctions in the PUF data array. By controlling the spacing between two adjacent magnetic tunnel junctions in the same row or column within a smaller set spacing range under the same physical dimensions, it is easier to randomly distribute the generated metal redeposition material on the sidewalls of each magnetic tunnel junction, randomly creating short-circuit states for some of the magnetic tunnel junctions. This not only satisfies the randomness requirement but also facilitates the control of the proportion of short-circuit magnetic tunnel junctions.

[0013] In one specific implementation, the critical size of each magnetic tunnel junction in the PUF data array is within a first predetermined critical size range. This allows for the random distribution of metal redeposition material on the sidewalls of each magnetic tunnel junction during fabrication, randomly creating short-circuit states in some of the magnetic tunnel junctions. By controlling the critical size of each magnetic tunnel junction within a smaller first predetermined critical size range while maintaining other physical dimensions, it is easier to randomly distribute the generated metal redeposition material on the sidewalls of each magnetic tunnel junction, randomly creating short-circuit states in some of the magnetic tunnel junctions. This not only satisfies the randomness requirement but also facilitates control over the proportion of short-circuit magnetic tunnel junctions.

[0014] In one specific implementation, the bottom electrode connected to each magnetic tunnel junction in the PUF data array is within a second predetermined critical size range. This allows for the randomization of some magnetic tunnel junctions in the PUF data array into a short-circuit state by the metal redeposition material randomly distributed on the sidewalls of each magnetic tunnel junction during fabrication. By controlling the critical size of the bottom electrode connected to each magnetic tunnel junction within a larger second predetermined critical size range while maintaining other physical dimensions, more metal redeposition material can be generated during the etching process to form the magnetic tunnel junctions. This makes it easier to randomly distribute the large amount of generated metal redeposition material on the sidewalls of each magnetic tunnel junction, randomly causing some magnetic tunnel junctions to form a short-circuit state. This not only satisfies the randomness requirement but also facilitates the control of the proportion of short-circuit magnetic tunnel junctions.

[0015] In one specific implementation, the magnetic tunnel junction in each PUF data unit can be randomly configured into a parallel state, an antiparallel state, or a short-circuit state. The PUF module also includes a PUF data write circuit, which outputs a write voltage of a second set voltage value to the PUF data array to randomly write the remaining magnetic tunnel junctions in the PUF data array into a parallel state or an antiparallel state, thereby randomly configuring each magnetic tunnel junction in the entire PUF data array into one of the following logic states: parallel state, antiparallel state, or short-circuit state.

[0016] In one specific implementation, the PUF module further includes a failure control circuit. The failure control circuit is used to disable the write operation function of the PUF data writing circuit after the PUF data writing circuit randomly writes the remaining magnetic tunnel junctions in the PUF data array into a parallel state or an antiparallel state, so that the PUF data writing circuit only performs a write operation to the PUF data array once, ensuring that the same PUF data is read out in the PUF module in the future.

[0017] In one specific implementation, the proportion of the number of magnetic tunnel junctions in the short-circuit state in the PUF data array to the total number of magnetic tunnel junctions in the PUF data array is α, where 0 < α < 67%, thereby increasing the Hamming distance of the PUF data formed by the PUF data array.

[0018] In one specific implementation, the PUF data read circuit obtains the resistance value of each magnetic tunnel junction in the PUF data array and reads the logic state of each magnetic tunnel junction, so as to accurately and quickly read the logic state of each magnetic tunnel junction.

[0019] In one specific implementation, the magnetic tunnel junctions in each PUF data cell can be randomly configured into parallel, antiparallel, or short-circuited states. The PUF data read circuit includes a first PUF data read circuit and a second PUF data read circuit. The first PUF data read circuit reads all magnetic tunnel junctions in the PUF data array that are in the short-circuited state; the second PUF data read circuit reads all magnetic tunnel junctions in the PUF data array that are in the parallel or antiparallel state. This simplifies the configuration of the PUF data read circuit and facilitates accurate and rapid reading of the number and location of magnetic tunnel junctions in the PUF data array that are in the parallel, antiparallel, and short-circuited states, respectively.

[0020] Secondly, this invention also provides an MRAM with integrated PUF functionality, comprising a storage region and a PUF region. The storage region contains multiple MRAM storage cells; the PUF region contains any of the aforementioned PUF modules. By allowing the magnetic tunnel junctions in each PUF data cell to be randomly formed into one of three or four logic states, the number of logic states that can be randomly formed for each PUF data cell is increased. Simultaneously, the distribution of the one or two logic states of the magnetic tunnel junctions is uncontrollable, exhibiting complete randomness, thereby increasing the inter-chip Hamming distance and the PUF security factor. Compared to the prior art where each bit has only two logic states, the solution of this application can randomly form more types of PUF data with the same PUF data cell, increasing the inter-chip Hamming distance and improving the PUF security factor. Correspondingly, in applications requiring the same Hamming distance, the solution of this application can use fewer PUF data cells compared to the prior art, thereby saving the area occupied by the PUF data cells and facilitating chip integration. Furthermore, it overcomes the disadvantages of conventional MRAM compared to RRAM and PCRAM, namely its lower on / off ratio and inability to be used for polymorphism. By simultaneously implementing MRAM and PUF functions in a single chip, the introduction of one or two logic states does not affect the determinism and non-cloning properties of other MRAM memory areas. In other words, the PUF region and the memory region are independent of each other (the addition of one or two logic states to the PUF region does not affect the yield of the memory region), ensuring process compatibility. This allows MRAM to not only have normal memory functions but also PUF functionality, reducing system costs.

[0021] In one specific implementation, three or four logic states include a short-circuit state. Multiple MRAM memory cells are arrayed in the storage region, each MRAM cell containing a magnetic tunnel junction. The spacing between any two adjacent magnetic tunnel junctions in the same column or row of the PUF data array is smaller than the spacing between any two adjacent magnetic tunnel junctions in the same column or row of the storage region. When designing the magnetic tunnel junction array for the PUF region, under the condition that other physical dimensions are the same, designing the spacing between two adjacent magnetic tunnel junctions in the same row or column of the PUF region to be smaller than the spacing between two adjacent magnetic tunnel junctions in the same row or column of the storage region makes it easier to randomly distribute the generated metal redeposited material on the sidewalls of each magnetic tunnel junction, randomly causing some magnetic tunnel junctions to form a short-circuit state. This not only satisfies the randomness requirement but also facilitates control over the proportion of magnetic tunnel junctions in the short-circuit state.

[0022] In one specific implementation, three or four logic states include a short-circuit state. Multiple MRAM memory cells are arrayed in the storage region, each MRAM memory cell containing a magnetic tunnel junction. The critical size of each magnetic tunnel junction in the PUF data array is smaller than the critical size of each magnetic tunnel junction in the storage region. When designing the magnetic tunnel junction array for the PUF region, under the condition that other physical dimensions are the same, designing the critical size of each magnetic tunnel junction to be smaller than the critical size of each magnetic tunnel junction in the storage region makes it easier to randomly distribute the generated metal redeposited material on the sidewalls of each magnetic tunnel junction, randomly causing some magnetic tunnel junctions to form a short-circuit state. This not only satisfies the randomness requirement but also facilitates the control of the proportion of magnetic tunnel junctions in the short-circuit state.

[0023] In one specific implementation, three or four logic states include a short-circuit state. Multiple MRAM memory cells are arrayed in the storage region, each MRAM memory cell containing a magnetic tunnel junction. The critical size of the bottom electrode connected to each magnetic tunnel junction in the PUF data array is smaller than the critical size of the bottom electrode connected to each magnetic tunnel junction in the storage region. When designing the magnetic tunnel junction array for the PUF region, under the condition that other physical dimensions are the same, the critical size of the bottom electrode connected to each magnetic tunnel junction is designed to be larger than the critical size of the bottom electrode connected to each magnetic tunnel junction in the storage region. During the etching process to form the magnetic tunnel junctions, more metal redeposited material can be generated, making it easier to randomly distribute the generated large amount of metal redeposited material on the sidewalls of each magnetic tunnel junction, randomly causing some magnetic tunnel junctions to form short-circuit states. This not only satisfies the randomness requirement but also facilitates control over the proportion of short-circuit magnetic tunnel junctions. Attached Figure Description

[0024] Figure 1 This is a partial structural diagram of a PUF module provided in an embodiment of the present invention;

[0025] Figure 2 A schematic diagram showing the resistance distribution of a magnetic tunnel junction in short-circuit, parallel, and antiparallel states, respectively, according to an embodiment of the present invention.

[0026] Figure 3 A schematic diagram of an MRAM with integrated PUF function provided in an embodiment of the present invention;

[0027] Figure 4 A logic diagram of a PUF data read circuit provided in an embodiment of the present invention;

[0028] Figure 5 A flowchart illustrating a PUF data read circuit reading a PUF data array, provided as an embodiment of the present invention;

[0029] Figure 6 A cross-sectional view of the distribution of magnetic tunnel junctions in a PUF data array provided in an embodiment of the present invention;

[0030] Figure 7 This is a cross-sectional view of the distribution of magnetic tunnel junctions in another PUF data array provided in an embodiment of the present invention;

[0031] Figure 8 A comparison diagram of Hamming distance between PUF data generated by the PUF data array provided in this embodiment of the invention and PUF data generated by prior art.

[0032] Figure 9 The graph shows the average Hamming distance increasing from 0.5 to nearly 1 as the number of logic states changes from 2 to 100.

[0033] Figure 10 The Hamming distance distribution is shown for cases with 2, 3, 4, and 5 logic states.

[0034] Figure 11 The normalized Hamming distance distribution between PUF slices under different third-state probabilities when the number of logic states is 3, as provided in the embodiments of the present invention;

[0035] Figure 12 A cross-sectional view showing the distribution of magnetic tunnel junction spacing in the storage region of an MRAM with integrated PUF function provided in an embodiment of the present invention;

[0036] Figure 13 A cross-sectional view showing the distribution of critical dimensions of the magnetic tunnel junction in the storage region of an MRAM with integrated PUF function, provided in an embodiment of the present invention.

[0037] Figure label:

[0038] 10-PUF Data Unit 11-Magnetic Tunnel Junction

[0039] 12-MOSFET 13-PUF data read circuit

[0040] 21-PUF area 22-Storage area 23-Control circuit Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] To facilitate understanding of the PUF module provided in this embodiment of the invention, the application scenarios of the PUF module provided in this embodiment of the invention will be described first. This PUF module is applied in scenarios such as, but not limited to, the Internet of Things (IoT) to generate PUF data. The PUF module will now be described in detail with reference to the accompanying drawings.

[0043] refer to Figure 1 and Figure 4 The PUF module provided in this embodiment of the invention includes a PUF data array and a PUF data read circuit 13. The PUF data array consists of multiple PUF data units 10, each PUF data unit 10 containing a magnetic tunnel junction 11. The magnetic tunnel junction 11 in each PUF data unit 10 can be randomly configured into one of three or four logical states. These three or four logical states include a parallel state (P state) and an antiparallel state (AP state), as well as a short-circuit state and / or an open-circuit state. The PUF data read circuit 13 is used to read the logical state of each magnetic tunnel junction 11 in the PUF data array to form PUF data.

[0044] In the above scheme, by enabling the magnetic tunnel junction 11 in each PUF data unit 10 to be randomly formed into one of three or four logic states, the number of logic states that each PUF data unit 10 can be randomly formed is increased. Simultaneously, the distribution position of the magnetic tunnel junction 11 with one or two logic states is uncontrollable, exhibiting complete randomness, thus increasing the inter-chip Hamming distance and the PUF security factor. Compared to the prior art where each bit has only two logic states, the scheme of this application, with the same PUF data unit 10, can randomly form more types of PUF data, increasing the inter-chip Hamming distance and improving the PUF security factor. Correspondingly, in applications requiring the same Hamming distance, the scheme of this application, compared to the prior art, can use fewer PUF data units 10, thereby saving the area occupied by the PUF data units 10 and facilitating chip integration. Furthermore, it overcomes the disadvantage of conventional MRAM having a lower switching ratio than RRAM and PCRAM, preventing its use for polymorphism. The following is a detailed description of the above structures in conjunction with the accompanying drawings.

[0045] When setting up a PUF data array, refer to Figure 1 A PUF data array is formed by arranging multiple PUF data units 10 in an array. Each PUF data unit 10 contains a magnetic tunnel junction 11 and may also contain a MOS transistor 12, or other circuit structures, to achieve the switching of the magnetic tunnel junction 11 in parallel or antiparallel states. For example, refer to... Figure 1It can also set word lines (WL), bit lines (BL), power lines (SL), etc., and can also integrate a function for output write voltage (V). W The write circuit for outputting the read voltage (V) R The PUF data unit 10 includes read circuits, etc. Specifically, each PUF data unit 10 can be configured using the storage cell configuration of MRAM, meaning each PUF data unit 10 is formed based on an MRAM storage cell. This MRAM storage cell can specifically be an SOT-MRAM storage cell or a VCMA storage cell. In a more preferred embodiment, each PUF data unit 10 can be an STT-MRAM storage cell. The PUF data array is fabricated using the mature STT-MRAM process, resulting in low power consumption and high reliability.

[0046] Furthermore, the magnetic tunnel junction 11 in each PUF data unit 10 can be randomly formed into one of three or four logical states. When determining these three or four logical states, reference is made to... Figure 1 and Figure 2 These three or four logic states include parallel and antiparallel states, and the added one or two logic states can be short-circuit and / or open-circuit states. That is, these three or four logic states must include parallel and antiparallel states, and may also include at least one of short-circuit and open-circuit states, making the distribution position of the added short-circuit and / or open-circuit states of the magnetic tunnel junction 11 uncontrollable and completely random, increasing the inter-chip Hamming distance and the PUF security factor. Furthermore, compared to the parallel and antiparallel states used in the prior art, these three or four logic states only add at least one of short-circuit and open-circuit states, which not only facilitates randomly forming each PUF data unit 10 into a short-circuit or open-circuit state to meet the randomness requirement, but also allows the resistance values ​​of the magnetic tunnel junction 11 in the short-circuit, parallel, antiparallel, or open-circuit states to differ significantly, facilitating the PUF data read circuit 13 to quickly and accurately read the logic state of each magnetic tunnel junction 11 in the PUF data array, forming PUF data.

[0047] like Figure 2 The first configuration represents the parallel state, the second configuration represents the antiparallel state, and the third configuration represents the short-circuit state. The specific location of the added short-circuit or / and open-circuit states of the magnetic tunnel junction 11 is uncontrollable and completely random, but the probability of each magnetic tunnel junction 11 being formed into a certain logic state can be controlled. The short-circuit state refers to the loss of insulation function of the insulating layer in the magnetic tunnel junction 11, thus causing a short circuit between the free layer and the reference layer of the magnetic tunnel junction 11, i.e., the magnetic tunnel junction 11 is in the Short state, and the resistance value of the magnetic tunnel junction 11 suddenly decreases, such as... Figure 2The resistance of the magnetic tunnel junction 11 in the short-circuit state is much smaller than that in the parallel state. The open-circuit state refers to a sudden increase in the insulation effect of the insulating layer in the magnetic tunnel junction 11, causing an open circuit between the free layer and the reference layer, i.e., the magnetic tunnel junction 11 is in the Open state. The resistance of the magnetic tunnel junction 11 increases suddenly, making its resistance much greater than that of the anti-parallel state. This ensures that the resistance values ​​of the magnetic tunnel junctions 11 in different logic states are within a completely non-overlapping distribution range. This facilitates the PUF data read circuit 13 in acquiring the resistance value of each magnetic tunnel junction 11 in the PUF data array and reading the logic state of each magnetic tunnel junction 11, enabling accurate and rapid reading of the logic state of each magnetic tunnel junction 11. It should be understood that, in addition to reading the resistance value of the magnetic tunnel junction 11 to obtain the logic state of the magnetic tunnel junction 11, the PUF data read circuit 13 can also use other methods to read whether the magnetic tunnel junction 11 is in a parallel state, antiparallel state, short-circuit state, or open-circuit state.

[0048] Specifically, the magnetic tunnel junctions 11 in each PUF data unit 10 can be randomly configured into one of three logical states: parallel, antiparallel, and short-circuit. That is, some magnetic tunnel junctions 11 in the PUF data array are randomly configured as parallel, some as antiparallel, and the remaining as short-circuit. Alternatively, these three logical states can also be parallel, antiparallel, and open-circuit. In other words, some magnetic tunnel junctions 11 in the PUF data array are randomly configured as parallel, some as antiparallel, and the remaining as open-circuit. The magnetic tunnel junction 11 in each PUF data unit 10 can also be randomly formed into one of four logical states: parallel state, antiparallel state, short-circuit state, and open-circuit state. That is, some magnetic tunnel junctions 11 in the PUF data array are randomly formed into a parallel state, some into an antiparallel state, some into an open-circuit state, and the remaining magnetic tunnel junctions 11 into a short-circuit state. The time when the magnetic tunnel junction 11 of each PUF data unit 10 in the PUF data array is randomly formed into one of the three or four logical states can be completed by any process before application, such as preparation and testing.

[0049] For example, the magnetic tunnel junction 11 in each PUF data unit 10 can be randomly formed into three or four logical states, which necessarily include parallel state, antiparallel state, and short-circuit state. That is, when the magnetic tunnel junction 11 is randomly formed into three logical states, these three logical states are parallel state, antiparallel state, and short-circuit state; when the magnetic tunnel junction 11 is randomly formed into four logical states, these four logical states are parallel state, antiparallel state, short-circuit state, and open-circuit state.

[0050] At this point, when randomly forming some magnetic tunnel junctions 11 in the PUF data array into a short-circuit state, this can be achieved through a breakdown circuit, which is completed during the testing and other process stages after the PUF data array is fabricated. The breakdown circuit outputs a first-set breakdown voltage to the PUF data array to randomly break down some of the magnetic tunnel junctions 11 in the PUF data array into a short-circuit state. This first-set breakdown voltage needs to be sufficiently large to ensure that at least one magnetic tunnel junction 11 in the PUF data array is broken down into a short-circuit state, but it also needs to be large enough to prevent all magnetic tunnel junctions 11 in the PUF data array from being broken down. Therefore, by adjusting the first-set voltage, the proportion of magnetic tunnel junctions 11 in the PUF data array that are broken down can be controlled, thereby controlling the breakdown probability. The above method utilizes the inconsistency in breakdown voltage between the magnetic tunnel junctions 11 of different PUF data units 10 that may exist due to fluctuations in the manufacturing process. By adding a breakdown circuit, some magnetic tunnel junctions 11 in the PUF data array are randomly broken down into a short-circuit state, which not only meets the randomness requirement, but also makes it easier to control the breakdown probability.

[0051] Of course, the method of randomly forming some magnetic tunnel junctions 11 in the PUF data array into short-circuit states is not limited to the breakdown circuit method shown above. Other methods can also be used. For example, it can be achieved during the fabrication of the PUF data array. That is, some magnetic tunnel junctions 11 in the PUF data array are randomly formed into short-circuit states during fabrication. Specifically, refer to... Figure 6 , Figure 7 , Figure 12 and Figure 13 The fabrication process of the PUF data array also includes the magnetic tunnel junction 11, upper and lower contact electrodes, vias, and upper and lower metal interconnects (M). X and M X+1The fabrication of the upper and lower metal interconnects is shown separately. The proportion of short-circuit magnetic tunnel junctions 11 can be controlled and made completely random by adjusting the pitch of the magnetic tunnel junction array 11 in the PUF data array, or by adjusting the design rules such as the bottom electrode (BE), bottom via (BV), and critical dimensions of the magnetic tunnel junction 11. This utilizes the randomness of the fabrication process in the PUF module to randomly fabricate some of the magnetic tunnel junctions 11 in the PUF data array into a short-circuit state, which not only meets the randomness requirement but also facilitates control over the proportion of short-circuit magnetic tunnel junctions 11.

[0052] For example, refer to Figure 6 This process can reduce the pitch (Pitch2) of any two adjacent magnetic tunnel junctions 11 in the same row or column of the PUF data array to a set pitch range. This fabrication method is exactly the opposite of the process requirements for fabricating the magnetic tunnel junctions 11 of the storage region 22 of MRAM. (Reference) Figure 12 During the normal fabrication of the magnetic tunnel junctions 11 in the storage region 22 of the MRAM, it is necessary to avoid metal redeposition during processes such as etching the metal hard mask due to excessively small pitch (Pitch1) between any two adjacent magnetic tunnel junctions 11 in the same row or column. This would cause the redeposited metal material to be distributed on the sidewalls of the magnetic tunnel junctions 11, resulting in a short circuit. In this embodiment, it is necessary to reduce the pitch between any two adjacent magnetic tunnel junctions 11 in the same row or column of the PUF data array to a set pitch range. This allows the metal redeposited material that occurs during the fabrication of the PUF data array to be randomly distributed on the sidewalls of each magnetic tunnel junction 11, thereby randomly creating a short-circuit state for some of the magnetic tunnel junctions 11 in the PUF data array. The above method, by controlling the spacing between two adjacent magnetic tunnel junctions 11 in the same row or column within a small set spacing range under the condition that other physical dimensions are the same, makes it easier to randomly distribute the generated metal redeposited material on the sidewall of each magnetic tunnel junction 11, and randomly make some magnetic tunnel junctions 11 form a short-circuit state. This not only satisfies the randomness requirement, but also makes it easier to control the proportion of short-circuit magnetic tunnel junctions 11.

[0053] Other fabrication processes can also be used to randomly form some of the magnetic tunnel junctions 11 in the PUF data array into short-circuit states. For example, refer to... Figure 7 This process can reduce the critical size (CD2) of each magnetic tunnel junction 11 in the PUF data array to a first predetermined critical size range. This fabrication method is exactly the opposite of the process requirements for fabricating the magnetic tunnel junction 11 of the normal MRAM storage region 22. (Reference) Figure 13During the normal fabrication of the magnetic tunnel junction 11 in the storage region 22 of the MRAM, it is necessary to avoid metal redeposition during processes such as etching the metal hard mask due to an excessively small critical size (CD1) of the magnetic tunnel junction 11. This would cause the redeposited metal material to be distributed on the sidewalls of the magnetic tunnel junction 11, resulting in a short circuit. In this embodiment, it is necessary to reduce the critical size of each magnetic tunnel junction 11 in the PUF data array to a first set critical size range. This allows the metal redeposited material that occurs during the fabrication of the PUF data array to be randomly distributed on the sidewalls of each magnetic tunnel junction 11, thereby randomly creating a short-circuit state for some of the magnetic tunnel junctions 11 in the PUF data array. The above method, by controlling the critical size of each magnetic tunnel junction 11 within a smaller first set critical size range under the condition that other physical dimensions are the same, makes it easier to randomly distribute the generated metal redeposited material on the sidewall of each magnetic tunnel junction 11, and randomly make some magnetic tunnel junctions 11 form a short-circuit state. This not only satisfies the randomness requirement, but also makes it easier to control the proportion of magnetic tunnel junctions 11 in the short-circuit state.

[0054] In another implementation, the bottom electrode connected to each magnetic tunnel junction in the PUF data array can be enlarged to a second predetermined critical size range. This fabrication method is exactly the opposite of the process requirements for fabricating the magnetic tunnel junction 11 of the storage region 22 of MRAM. During the normal fabrication of the magnetic tunnel junction 11 of the storage region 22 of MRAM, it is necessary to avoid excessively large critical sizes of the bottom electrodes connected to the magnetic tunnel junction 11, which could lead to more severe metal redeposition during processes such as etching the metal hard mask. This would cause a large amount of redepositioned metal material to be distributed on the sidewalls of the magnetic tunnel junction 11, resulting in a short circuit. In this embodiment, it is necessary to increase the critical size of the bottom electrode connected to each magnetic tunnel junction 11 in the PUF data array to a second predetermined critical size range. This results in a large amount of metal redeposition during the fabrication of the PUF data array, allowing a large amount of redepositioned metal material to be randomly distributed on the sidewalls of each magnetic tunnel junction 11, thereby randomly creating a short-circuit state for some of the magnetic tunnel junctions 11 in the PUF data array. The above method, under the condition that other physical dimensions are the same, controls the critical size of the bottom electrode connected to each magnetic tunnel junction 11 within a larger second set critical size range. During the etching process to form the magnetic tunnel junction 11, more metal redeposited material can be generated, and it is easier to make the generated large amount of metal redeposited material randomly distributed on the sidewall of each magnetic tunnel junction 11. This randomly makes some magnetic tunnel junctions 11 form a short-circuit state, which not only meets the randomness requirement, but also makes it easier to control the proportion of short-circuit magnetic tunnel junctions 11.

[0055] The metal redeposition material generated during the etching process of the magnetic tunnel junction 11 can be produced by a hard mask, a metal thin film of the magnetic tunnel junction 11, or a bottom electrode. In the patterning process of the magnetic tunnel junction 11, the etching process involves etching more than a dozen complex metal thin film stack structures. During the fabrication of the magnetic tunnel junction 11, the selected fabrication process can include ion beam etching (IBE) and reactive ion etching (RIE). The etching process can include etching of the magnetic tunnel junction 11, the hard mask (HM), and can also include etching over the bottom electrode. That is, the methods used for etching the magnetic tunnel junction 11 (especially at close pitch) mainly include the ion beam etching and reactive ion etching shown above. Reactive ion etching (RIE) can cause significant damage to the magnetic tunnel junction 11. Etching damage to the transition metals (pinned layers, free layers) and even the bottom and top electrodes can alter parameters such as the tunnel magnetoresistance ratio (TMR) and energy barrier (Eb) of the magnetic tunnel junction 11, leading to performance degradation. Another method for etching the magnetic tunnel junction 11 involves ion beam etching. Ion beam etching can be used to etch materials that do not readily respond to chemical etching. It guides a charged particle ion beam to the target material to etch it. This process can avoid or reduce most of the etching damage in reactive ion etching. However, this physical sputtering etching inevitably produces some metallic byproducts that adhere to the sidewalls of the magnetic tunnel junction 11, especially when penetrating the tunnel layer, causing short circuits. In addition, since the lower metal buffer layer of the magnetic tunnel junction 11 and the upper metal hard mask of the magnetic tunnel junction 11 often serve as the lower and upper electrodes of the magnetic tunnel junction 11, they are also the source of metal redeposition material; changes in the etching angle and the pitch between bits of the magnetic tunnel junction 11 will also cause metal redeposition to varying degrees.

[0056] When determining the material thickness of each structure related to the magnetic tunnel junction 11, the thickness of the hard mask of the magnetic tunnel junction 11 can be designed to be 30–60 nm, and the material of the hard mask can be one or more of TaN, Ta, Ti, and TiN. The thickness of the bottom electrode metal layer can be 5 nm–80 nm, and the thickness of the top electrode metal layer can be 20 nm–100 nm. The materials of the bottom electrode and the top electrode can be TaN, Ta, Ti, TiN, Co, W, Al, WN, Ru, or combinations thereof. The total thickness of the multilayer film used to fabricate the magnetic tunnel junction 11 can be 5 nm–40 nm. The multilayer film used to fabricate the magnetic tunnel junction 11 can be a stacked structure of a reference layer, a barrier layer, and a free layer from bottom to top, wherein the reference layer has magnetic polarization invariance, and the barrier layer is a non-magnetic metal oxide.

[0057] It should be understood that the way some magnetic tunnel junctions 11 in the PUF data array are made into a short-circuit state is not limited to the single implementation method mentioned above, but can also be a combination of the above multiple implementation methods.

[0058] Furthermore, during the process of randomly forming some magnetic tunnel junctions 11 in the PUF data array into a short-circuit state, the proportion α of the number of magnetic tunnel junctions 11 in the short-circuit state relative to the total number of magnetic tunnel junctions 11 in the PUF data array can be controlled, i.e., the magnitude of α can be controlled. If each magnetic tunnel junction 11 in the PUF data array can only be randomly formed into one of the three logical states: parallel state, antiparallel state, and short-circuit state, then α can be controlled within the following range: 0 < α < 67%. Specifically, α can be any value between 0 and 67%, such as 1%, 10%, 20%, 30%, 40%, 50%, 60%, 65%, 66.7%, etc. Figure 11 To illustrate the Hamming distance of the proportion α of the third state as a short-circuit state at different values, combined with... Figure 7 It can be seen that when α is 0 < α < 67%, the Hamming distance is greater than the Hamming distance when there are only two logic states, thus improving the Hamming distance of the PUF data formed by the PUF data array. Similarly, if each magnetic tunnel junction 11 in the PUF data array can be randomly formed into one of the logic states of parallel, antiparallel, and open circuit, the proportion of the number of magnetic tunnel junctions 11 in the open circuit state in the PUF data array to the total number of magnetic tunnel junctions 11 in the PUF data array can be controlled between 0% and 67%.

[0059] When it is necessary to randomly form some of the magnetic tunnel junctions 11 in the PUF data array into an open circuit state, the same method of adjusting the fabrication process can be used to randomly form some of the magnetic tunnel junctions 11 in the PUF data array into an open circuit state.

[0060] If it is only necessary to randomly form the magnetic tunnel junction 11 in each PUF data unit 10 into a parallel state, an antiparallel state, or a short-circuit state, then a write circuit can be used to perform a write operation, randomly writing the remaining magnetic tunnel junctions 11 in the PUF data array into a parallel state or an antiparallel state. Specifically, a PUF data write circuit can be configured to output a write voltage of a second set value to the PUF data array, randomly writing the remaining magnetic tunnel junctions 11 in the PUF data array into a parallel state or an antiparallel state. That is, by adjusting the write voltage of the second set value, each remaining magnetic tunnel junction 11 in the PUF data array is randomly flipped into a parallel state or an antiparallel state, thereby randomly forming each magnetic tunnel junction 11 in the entire PUF data array into one of the following logic states: parallel, antiparallel, or short-circuit. The specific operation process can be as follows: First, the entire PUF data array is magnetically initialized so that all the remaining magnetic tunnel junctions 11 in the PUF data array are in a parallel or antiparallel state. Then, the PUF data writing circuit applies a write voltage of the second set voltage value to randomly write the remaining magnetic tunnel junctions 11 in the PUF data array into a parallel or antiparallel state.

[0061] Additionally, a failure control circuit 23 can be added to the PUF module. After the PUF data write circuit randomly writes the remaining magnetic tunnel junctions 11 in the PUF data array into a parallel or antiparallel state, the failure control circuit 23 disables the write operation function of the PUF data write circuit, ensuring that the PUF data write circuit performs only one write operation to the PUF data array, guaranteeing that the same PUF data is read from the PUF module subsequently. This failure control circuit 23 can be implemented using an Efuse circuit associated with the write current to simplify the implementation.

[0062] When configuring the PUF data read circuit 13, refer to... Figure 4 and Figure 5 The logic state of each magnetic tunnel junction 11 in each PUF data array can be determined by integrating a specific reference circuit to determine its resistance state. Specifically, the resistance value of a magnetic tunnel junction 11 in a short-circuit state is significantly lower than that of a magnetic tunnel junction 11 in a parallel or anti-parallel state, which can be used by a simple readout circuit to confirm whether the magnetic tunnel junction 11 is in a short-circuit state. When the magnetic tunnel junctions 11 in each PUF data cell 10 can be randomly formed into parallel, anti-parallel, or short-circuit states, the PUF data read circuit 13 may include a first PUF data read circuit and a second PUF data read circuit. Figure 4 The MTJInput module acquires the sampled signal from each magnetic tunnel junction 11. The first PUF data read circuit reads all magnetic tunnel junctions 11 in the short-circuit state in the PUF data array, such as... Figure 4 Ref 1Input is used as a reference signal. For example, the reference resistor used in the first PUF data read circuit can be 300 ohms, and a resistor such as... Figure 2 Vref 2 serves as the reference voltage corresponding to the reference resistor. The second PUF data read circuit is used to read all magnetic tunnel junctions 11 in the PUF data array that are in parallel or antiparallel states, such as... Figure 4 The Ref 2Input is used as a reference signal. For example, the reference resistor used in the second PUF data read circuit can be 3K to 4K ohms, and can be used as follows: Figure 2 Vref 1 in the reference resistor is used as the reference voltage. Specifically, the first PUF data read circuit and the second PUF data read circuit can be implemented in parallel or serially. This simplifies the setup of the PUF data read circuit 13 and facilitates accurate and rapid reading of the number and position of the magnetic tunnel junctions 11 in the PUF data array, which are in parallel, antiparallel, and short-circuit states, respectively. For example... Figure 3 The diagram illustrates the logic states of each magnetic tunnel junction 11 in a PUF data array. Based on the logic states of the different magnetic tunnel junctions 11 in the PUF data array, the PUF data read circuit 13 outputs a PUF response, generating PUF data. (Reference) Figure 4 The binary symbol "11" can be used to represent that the magnetic tunnel junction 11 is in an antiparallel state, the binary symbol "01" can be used to represent that the magnetic tunnel junction 11 is in a parallel state, and the binary symbol "10" can be used to represent that the magnetic tunnel junction 11 is in an open-circuit state. Figure 4 In the X), the binary "00" indicates that the magnetic tunnel junction 11 is in a short-circuit state. Figure 4 The Short state in the PUF data array is combined to form PUF data.

[0063] By enabling the magnetic tunnel junction 11 in each PUF data unit 10 to be randomly formed into one of three or four logic states, the number of logic states that can be randomly formed in each PUF data unit 10 is increased. Simultaneously, the distribution of the magnetic tunnel junction 11 in the added one or two logic states is uncontrollable, exhibiting complete randomness, thus increasing the inter-chip Hamming distance and the PUF security factor. Compared to the prior art where each bit has only two logic states, the solution of this application can randomly form more types of PUF data with the same PUF data unit 10, increasing the inter-chip Hamming distance and improving the PUF security factor. Correspondingly, in applications requiring the same Hamming distance, the solution of this application can use fewer PUF data units 10 compared to the prior art, thereby saving the area occupied by the PUF data units 10 and facilitating chip integration. Figure 8 The Matlab simulation comparison charts shown demonstrate that, compared to an MRAM PUF with only two logic states (parallel and antiparallel), introducing a certain proportion of a third logic state has the advantage of increasing the Hamming distance, i.e., improving the PUF's security factor. Specifically, with only two logic states (P and AP states): when the probabilities of writing to the P state and AP state are equal, the inter-chip Hamming distance is the largest, at 50% (ideal state). After introducing the third logic state: based on symmetry and probability calculations, when the probabilities of the P state, AP state, and the third logic state are equal (all 1 / 3), the inter-chip Hamming distance is the largest, at 66.7%. That is, after inputting a specific stimulus to two different PUF entities, adding an additional data logic state increases the distance between the two resulting responses, thus improving the security factor. Figure 9 and Figure 10 As shown, with the increase in the number of randomly generated logic states for each magnetic tunnel junction 11, the probability of different corresponding elements in different arrays increases, and therefore the Hamming distance also increases. However, when the number of logic states is infinite, the probability of corresponding elements being the same is 0, and the Hamming distance is 1. Thus, through... Figure 9 and Figure 10 This also corroborates that, compared to the existing two-logic-state approach, adding one or two additional logic states can improve the Hamming distance and increase the security factor.

[0064] In a preferred embodiment, compared to the parallel and antiparallel states used only in the prior art, the addition of at least one logic state—short-circuit or open-circuit—not only facilitates the randomization of each PUF data unit 10 into a short-circuit or open-circuit state, satisfying the randomness requirement, but also allows the PUF data read circuit 13 to quickly and accurately read the logic state of each magnetic tunnel junction 11 in the PUF data array, forming PUF data, as the resistance values ​​of the magnetic tunnel junction 11 differ significantly when it is in the short-circuit, parallel, antiparallel, or open-circuit state. Furthermore, it overcomes the disadvantage of conventional MRAM having a lower switching ratio than RRAM and PCRAM, preventing its use in multi-state applications.

[0065] In addition, embodiments of the present invention also provide an MRAM with integrated PUF functionality, see reference. Figure 1 , Figure 3 and Figure 4The MRAM includes a storage region 22 and a PUF region 21. Storage region 22 contains multiple MRAM memory cells, which can be arranged in an array. Each MRAM memory cell also contains a magnetic tunnel junction 11. PUF region 21 contains any of the aforementioned PUF modules; that is, storage region 22 and PUF region 21 are two independent regions on a single chip. The PUF data cells 10 in PUF region 21 are compatible with the fabrication process of the MRAM memory cells in storage region 22, meaning they can be fabricated simultaneously without interference. As described above regarding the PUF module, the PUF data array consists of multiple PUF data cells 10. The structure of each PUF data cell 10 is consistent with the structure of each MRAM memory cell in storage region 22, mainly including a bottom metal line (Mx), a bottom via (BV), a bottom electrode (BE), a magnetic tunnel junction 11, a hard mask (HM), a top electrode (TE), a top via (TV), and a top metal line (TM). Of course, a control circuit 23 can also be integrated into the MRAM. This control circuit 23 may include the PUF data read circuit 13, PUF data write circuit, failure control circuit 23, etc. shown above.

[0066] By enabling the magnetic tunnel junction 11 in each PUF data unit 10 to be randomly formed into one of three or four logic states, the number of logic states that can be randomly formed in each PUF data unit 10 is increased. Simultaneously, the distribution of the magnetic tunnel junction 11 in one or two logic states is uncontrollable, exhibiting complete randomness, thus increasing the inter-chip Hamming distance and the PUF security factor. Compared to the prior art where each bit has only two logic states, the solution of this application can randomly form more types of PUF data with the same PUF data unit 10, increasing the inter-chip Hamming distance and improving the PUF security factor. Correspondingly, in applications requiring the same Hamming distance, the solution of this application can use fewer PUF data units 10 compared to the prior art, thereby saving the area occupied by the PUF data units 10 and facilitating chip integration. Furthermore, it overcomes the disadvantage of conventional MRAM having a lower on / off ratio than RRAM and PCRAM, preventing its use for polymorphism.

[0067] Among them, when three or four logic states include a short-circuit state, refer to Figure 6 and Figure 12When designing the PUF and MRAM regions, the spacing between any two adjacent magnetic tunnel junctions 11 in the same column or row of the PUF data array can be designed to be smaller than the spacing between any two adjacent magnetic tunnel junctions 11 in the same column or row of the storage region 22. When designing the magnetic tunnel junction 11 array for the PUF region, under the condition that other physical dimensions are the same, designing the spacing between two adjacent magnetic tunnel junctions 11 in the same row or column of the PUF region to be smaller than the spacing between two adjacent magnetic tunnel junctions 11 in the same row or column of the storage region 22 makes it easier to randomly distribute the generated metal redeposited material on the sidewalls of each magnetic tunnel junction 11, randomly causing some magnetic tunnel junctions 11 to form short-circuit states. This not only satisfies the randomness requirement but also facilitates control over the proportion of short-circuit magnetic tunnel junctions 11. For details, please refer to the aforementioned description of the PUF module section; it will not be repeated here.

[0068] Of course, besides these methods, other design approaches can be used to achieve the short-circuit state during the design and fabrication process. For example, refer to... Figure 7 and Figure 13 Furthermore, the critical size of each magnetic tunnel junction 11 in the PUF data array can be designed to be smaller than the critical size of each magnetic tunnel junction 11 in the storage region 22. When designing the array of magnetic tunnel junctions 11 in the PUF region, under the condition that other physical dimensions are the same, designing the critical size of each magnetic tunnel junction 11 to be smaller than the critical size of each magnetic tunnel junction 11 in the storage region 22 makes it easier to randomly distribute the generated metal redeposited material on the sidewalls of each magnetic tunnel junction 11, and randomly make some magnetic tunnel junctions 11 form a short-circuit state. This not only meets the randomness requirement, but also makes it easier to control the proportion of magnetic tunnel junctions 11 in the short-circuit state. For details, please refer to the description of the PUF module section above, which will not be repeated here.

[0069] Alternatively, the critical size of the bottom electrode connected to each magnetic tunnel junction 11 in the PUF data array can be designed to be smaller than the critical size of the bottom electrode connected to each magnetic tunnel junction 11 in the storage region 22. When designing the array of magnetic tunnel junctions 11 in the PUF region, under the condition that other physical dimensions are the same, the critical size of the bottom electrode connected to each magnetic tunnel junction 11 can be designed to be larger than the critical size of the bottom electrode connected to each magnetic tunnel junction 11 in the storage region 22. During the etching process to form the magnetic tunnel junctions 11, more metal redeposited material can be generated, and it is easier to make the generated large amount of metal redeposited material randomly distributed on the sidewall of each magnetic tunnel junction 11, randomly causing some magnetic tunnel junctions 11 to form a short-circuit state. This not only meets the randomness requirement, but also makes it easier to control the proportion of short-circuit magnetic tunnel junctions 11. For details, please refer to the description of the PUF module section above, which will not be repeated here.

[0070] By implementing MRAM and PUF functions simultaneously in a single chip, the introduction of one or two logic states (in a preferred embodiment, the added logic states can be short-circuit and / or open-circuit states) does not affect the determinism and unclonability of other MRAM memory areas themselves. Specifically, refer to... Figure 3 The diagram illustrates a PUF data region where each magnetic tunnel junction 11 in the PUF data array can be randomly configured as logic "0", "1", and "S" as a third logic state. However, each magnetic tunnel junction 11 in the storage region 22 can be repeatedly flipped to logic state "0" or "1", and logic state "S" does not exist. That is, the PUF region 21 and the storage region 22 do not affect each other (in a more preferred embodiment, newly added short-circuit states and / or open-circuit states in the PUF region 21 do not affect the yield of the storage region 22), ensuring process compatibility. This allows the MRAM to not only have normal storage functionality but also PUF functionality, reducing system costs.

[0071] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A PUF device, characterized in that, include: A PUF data array consisting of multiple PUF data units; wherein each PUF data unit contains a magnetic tunnel junction, and the magnetic tunnel junction in each PUF data unit can be randomly formed into one of three logic states; wherein the magnetic tunnel junction in each PUF data unit can be randomly formed into a parallel state, an antiparallel state, or a short-circuit state. The PUF data read circuit is used to read the logic state of each magnetic tunnel junction in the PUF data array to form PUF data; In this embodiment, some magnetic tunnel junctions in the PUF data array are randomly short-circuited during fabrication; or, the PUF device further includes a breakdown circuit for outputting a breakdown voltage of a first set voltage value to the PUF data array to randomly break down some magnetic tunnel junctions in the PUF data array into a short-circuit state. The PUF device further includes: a PUF data writing circuit, used to output a writing voltage of a second set voltage value to the PUF data array, so as to randomly write the remaining magnetic tunnel junctions in the PUF data array into a parallel state or an antiparallel state. The PUF device also includes: A failure control circuit is used to disable the write operation function of the PUF data write circuit after the PUF data write circuit randomly writes the remaining magnetic tunnel junctions in the PUF data array into a parallel state or an antiparallel state.

2. The PUF device as described in claim 1, characterized in that, The spacing between any two adjacent magnetic tunnel junctions in the same column or row of the PUF data array is within a set spacing range, so that by randomly distributing metal redeposited material on the sidewalls of each magnetic tunnel junction during preparation, some magnetic tunnel junctions in the PUF data array are randomly made into a short-circuit state.

3. The PUF device as described in claim 1, characterized in that, The critical size of each magnetic tunnel junction in the PUF data array is within a first set critical size range, so that by randomly distributing metal redeposited material on the sidewalls of each magnetic tunnel junction during preparation, some magnetic tunnel junctions in the PUF data array are randomly made into a short-circuit state.

4. The PUF device as described in claim 1, characterized in that, The bottom electrode connected to each magnetic tunnel junction in the PUF data array is within a second set critical size range, so that by randomly depositing metal redeposition material on the sidewalls of each magnetic tunnel junction during fabrication, a portion of the magnetic tunnel junctions in the PUF data array are randomly made into a short-circuit state.

5. The PUF device according to any one of claims 1 to 4, characterized in that, The proportion of the number of magnetic tunnel junctions in the short-circuit state in the PUF data array to the total number of magnetic tunnel junctions in the PUF data array is α. Where 0 < α < 67%.

6. The PUF device as claimed in claim 1, characterized in that, The PUF data read circuit obtains the resistance value of each magnetic tunnel junction in the PUF data array and reads the logic state of each magnetic tunnel junction.

7. The PUF device as described in claim 6, characterized in that, The PUF data read circuit includes: The first PUF data read circuit is used to read all magnetic tunnel junctions in the short-circuit state in the PUF data array; The second PUF data read circuit is used to read all magnetic tunnel junctions in the PUF data array that are in a parallel or antiparallel state.

8. An MRAM with integrated PUF function, characterized in that, include: A storage area formed by multiple MRAM storage cells; The PUF region is formed with the PUF device as described in any one of claims 1 to 7.

9. The MRAM as claimed in claim 8, characterized in that, The three logical states include the short-circuit state; The storage region contains an array of multiple MRAM memory cells arranged in an array, each MRAM memory cell containing a magnetic tunnel junction; Furthermore, the spacing between any two adjacent magnetic tunnel junctions in the same column or row of the PUF data array is smaller than the spacing between any two adjacent magnetic tunnel junctions in the same column or row of the storage area.

10. The MRAM as claimed in claim 8, characterized in that, The three logical states include the short-circuit state; The storage region contains an array of multiple MRAM memory cells arranged in an array, each MRAM memory cell containing a magnetic tunnel junction; Furthermore, the critical size of each magnetic tunnel junction in the PUF data array is smaller than the critical size of each magnetic tunnel junction in the storage region.

11. The MRAM as claimed in claim 8, characterized in that, The three logical states include the short-circuit state; The storage region contains an array of multiple MRAM memory cells arranged in an array, each MRAM memory cell containing a magnetic tunnel junction; Furthermore, the critical size of the bottom electrode connected to each magnetic tunnel junction in the PUF data array is smaller than the critical size of the bottom electrode connected to each magnetic tunnel junction in the storage region.

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