Semiconductor device and method of forming the same

Abstract

Semiconductor devices and methods of forming semiconductor devices are disclosed. In some embodiments, a method of generating a cell in a layout includes selecting a cell from a library of standard cells, the components of the cell defining active circuitry; identifying a dummy device within the cell, the dummy device not connected to the active circuitry within the cell; and connecting the dummy device to a target node of the active circuitry.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and more particularly to semiconductor devices and methods of forming the same. Background Technology

[0002] The integrated circuit (IC) industry produces a variety of analog and digital semiconductor devices to solve problems in different fields. Advances in semiconductor process technology nodes include progressively smaller component sizes and tighter spacing, leading to progressively higher transistor densities. ICs are becoming increasingly smaller.

[0003] In the context of semiconductor device manufacturing, design rules are geometric constraints imposed on circuit board, semiconductor device, and / or IC designers to ensure that the IC design functions correctly and reliably and is manufactured with acceptable yield. Design rules are developed by process engineers based on the corresponding semiconductor process technology node. One type of electronic design automation (EDA) used to ensure that designers do not violate design rules is called design rule checking (DRC). DRC is a step in the physical verification sign-off / approval process for a given design. Physical verification sign-off / approval also includes LVS (layout vs. schematic) checks, XOR (logic) checks, electrical rule checks (ERC), or antenna checks (collecting charge from electromagnetic fields), etc. Summary of the Invention

[0004] In one aspect, embodiments of this application provide a method for generating cells in a layout diagram, the method comprising: selecting cells from a standard cell library, wherein the components of the cells define active circuitry; identifying dummy devices within the cells, the dummy devices not connected to the active circuitry within the cells; and connecting the dummy devices to a target node of the active circuitry.

[0005] In another aspect, embodiments of this application provide a semiconductor device comprising: a cell region configured as a functional circuit, the cell region including: an active transistor arranged in a rectangular region, a first portion of the active transistor being configured to receive data at a data input node of the cell region and to receive a clock at a timing input node of the cell region, and a second portion of the active transistor being configured to generate an output signal at an output node of the cell region; and one or more capacitor configuration transistors arranged in the rectangular region, the terminals of the one or more capacitor configuration transistors being connected to a target node of the functional circuit.

[0006] In another aspect, embodiments of this application provide a method for forming a semiconductor device, the method comprising: forming an active region, including doping a region of a substrate; forming a source / drain S / D region, the forming comprising doping a first region of the active region, the S / D region representing a first transistor assembly, wherein a second region of the active region between corresponding S / D regions is a channel region, the channel region representing a second transistor assembly; forming a metal-to-S / D contact structure, the metal-to-S / D contact structure above corresponding S / D regions in the S / D region, the metal-to-S / D contact structure representing a third transistor assembly; forming a gate line above corresponding channel regions in the channel region, the gate line representing a fourth transistor assembly; and forming the active region, forming the S / D region, forming the metal-to-S / D contact structure, and forming the gate line to obtain the first... A first set of transistor components connected to a fourth transistor component as corresponding active transistors defining a functional circuit, and a second set of transistor components connected to the fourth transistor component as one or more corresponding capacitor configuration transistors; the transistor components of the first set and the transistor components of the second set are assembled within a cell region having a rectangular area; and metallization is formed to interconnect the active transistors and the one or more capacitor configuration transistors, such that: a first portion of the active transistor is configured to receive data at a data input node of the cell region and receive a clock at a timing input node of the cell region; a second portion of the active transistor is configured to generate an output signal at an output node of the cell region; and terminals of the one or more capacitor configuration transistors are connected to a target node of the functional circuit. Attached Figure Description

[0007] One or more embodiments are shown in the accompanying drawings by way of example and not limitation, wherein elements having the same reference numerals denote the same elements throughout the text. Unless otherwise disclosed, the drawings are not necessarily drawn to scale.

[0008] Figure 1 This is a block diagram of a semiconductor device according to some embodiments.

[0009] Figure 2A , 2B 2C and 2D are corresponding layout diagrams of semiconductor devices according to some embodiments.

[0010] Figure 3A This is a schematic diagram of a capacitor-configured transistor according to some embodiments.

[0011] Figure 3B This is a schematic diagram of a dummy transistor according to some embodiments.

[0012] Figure 4A , 4B 4C, 4D, 4E and 4F are corresponding schematic diagrams of semiconductor devices according to some embodiments.

[0013] Figure 5A , 5B 5C, 5D, 5E and 5F are corresponding layout diagrams of semiconductor devices according to some embodiments.

[0014] Figure 5G This is a cross-section based on some embodiments.

[0015] Figure 6A This is a flowchart of a method for generating a layout diagram according to some embodiments.

[0016] Figure 6B This is a flowchart of a method for manufacturing a semiconductor device according to some embodiments.

[0017] Figure 7 This is a flowchart of a method for manufacturing a semiconductor device according to some embodiments.

[0018] Figure 8 This is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0019] Figure 9 This is a block diagram of an integrated circuit (IC) manufacturing system and the associated IC manufacturing process according to some embodiments. Detailed Implementation

[0020] The following disclosure presents numerous different embodiments or examples of various features for implementing this subject matter. Examples of components, materials, values, steps, operations, or arrangements are described below to simplify this disclosure. Of course, these are merely exemplary and not limiting. Other components, values, operations, materials, or arrangements may also be contemplated. For example, in the following description, embodiments in which a first feature is formed on or includes a second feature, wherein the first and second features are formed in direct contact, and embodiments in which an additional feature is formed between the first and second features such that the first and second features are in indirect contact. Furthermore, reference numerals and / or letters are repeated in various examples in this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0021] Furthermore, spatially related terms used herein, such as “below,” “under,” “below,” “above,” “on,” etc., are for descriptive purposes to describe the relationship between one element or feature and another (or other) element or feature as shown in the figures. In addition to the orientations shown in the figures, these spatially related terms are intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatially related descriptors used herein should be interpreted accordingly. In some embodiments, the term standard cell structure refers to a standardized building block included in a library of various standard cell structures. In some embodiments, various standard cell structures are selected from their libraries and used as components in layout diagrams representing circuits.

[0022] In some embodiments, a system and method are disclosed that reduce hold-slack violations in a given trigger design. According to another method, for a given trigger design suffering hold-slack violations in scenarios at larger timescales (i.e., equal to or greater than about 5 picoseconds), modifications are made to the given trigger design that avoid hold-slack violations but increase the cell area / occupancy of the modified trigger design relative to the given trigger design's footprint. In contrast, in some embodiments, modifications to the given trigger design are disclosed for a given trigger design suffering hold-slack violations that correspondingly reduce the hold-slack time and thereby avoid hold-slack violations without increasing the cell area / occupancy of the given trigger design. Furthermore, in some embodiments, a system and method are disclosed that reduces hold-slack violations in a given trigger design in scenarios at smaller timescales (i.e., less than about 5 picoseconds).

[0023] In some embodiments, a method for modifying a cell in a layout to reduce hold time margin violations of the cell's active circuitry includes: identifying dummy devices within the cell that are not connected to the active circuitry within the cell; and repurposing the dummy device, which is a passive device, to a target node of the active circuitry, thereby reducing the hold time margin violation of the active circuitry. In some embodiments, such a method of repurposing an unconnected dummy (DD) device within a cell to a connected passive (CP) device is referred to as the DD2CP method. According to another method known as cell padding (which is typically applied to transistors with a fin-FET architecture), for a given circuit design that suffers hold time margin violations in scenarios with larger timescales (i.e., equal to or greater than about 5 picoseconds), adding isolated dummy gates and / or dummy transistors to the given circuit design can mitigate the hold time margin violations of the given circuit design. However, due to the addition of isolated dummy gates and / or dummy devices, these other methods correspondingly suffer from an increase in the footprint of the modified circuitry relative to the footprint of the given circuitry. In contrast, at least some embodiments involve the DD2CP method, which repurposes existing, though unconnected, dummy devices within a given circuit design (e.g., flip-flops) as connected passive devices to mitigate time margin violations. In some embodiments, such mitigation of time margin violations via the DD2CP method without increasing footprint is applicable not only to scenarios with larger time scales but also to scenarios with smaller time scales (i.e., less than about 5 picoseconds).

[0024] In some embodiments, identifying a dummy device includes identifying a transistor with a short-circuit configuration (short-circuit transistor) as a dummy device, the short-circuit transistor including a gate pattern, a first source / drain (S / D) region, and a second S / D region, the gate pattern, the first source / drain (S / D) region, and the second S / D region being connected together. In such embodiments, the method further includes converting the short-circuit transistor into a transistor with a capacitor configuration (capacitor-configured transistor); and connecting the dummy device to a target node includes using the capacitor-configured transistor as a dummy device. In such embodiments, converting the short-circuit transistor includes: removing one or more first conductive segment patterns that connect the gate pattern of the short-circuit transistor to each of the first S / D region and the second S / D region of the short-circuit transistor; and generating a second conductive segment pattern that connects a data input line pattern of an active circuit to the gate pattern of the short-circuit transistor. In such an embodiment, removing one or more first conductive segment patterns not only causes the gate pattern to be disconnected from each of the first S / D region and the second S / D region, but also causes the first S / D region and the second S / D region to be disconnected from each other; and modifying the short-circuit transistor also includes generating a third conductive segment pattern that connects the first S / D region and the second S / D region together.

[0025] In some embodiments, the target node is an input node of an active circuit; and connecting the dummy device further includes connecting the dummy device in parallel with the input node of the active circuit. In some embodiments, the target node is an output node of an input transistor of an active circuit; and connecting the dummy device further includes connecting the dummy device to the output node of the input transistor of the active circuit. In some embodiments, the target node is an output node of an active circuit; and connecting the dummy device further includes connecting the dummy device to the output node of the active circuit. In some embodiments, the active circuit is a scan-inserted D flip-flop (SDFQ), which includes a D flip-flop (FF) and a multiplexer connected in series at an internal node of the SDFQ; the target node is an internal node of the SDFQ; and connecting the dummy device further includes connecting the dummy device to the internal node. In some embodiments, time margin violations include hold-type time margin violations and setup-type time margin violations; identifying and connecting the dummy device aims to reduce hold-type time margin violations; and the method further includes modifying the frequency of the active circuit to reduce setup-type time margin violations.

[0026] In some embodiments, modifying a dummy device is performed as part of an Engineering Change Order (ECO). In chip design, an ECO is the process of directly inserting changes into the netlist after it has been processed by automated tools. ECOs are typically performed before the chip mask is fabricated to save time by avoiding the need for a full suite of ASIC logic synthesis, technology mapping, placement, routing, layout extraction, and timing verification. EDA tools are often built with step-by-step operating modes to facilitate this type of ECO.

[0027] Related terminology includes the following. Sequential logic refers to clock-controlled logic or synchronous logic. In a synchronous circuit, an electronic oscillator, called a clock (or clock generator), generates a repetitive pulse sequence, i.e., a clock signal, which is distributed to all memory elements in the circuit. The basic memory element in sequential logic is the flip-flop. The output of each flip-flop changes only when triggered by a clock pulse, so changes in the logic signals throughout the circuit begin simultaneously, at regular intervals, and are synchronized by the clock. At any given time, the outputs of all memory elements (flip-flops) in the circuit (which represent the binary data contained in the circuit) are called the state of the circuit. The state of a synchronous circuit changes only under the influence of a clock pulse. In each cycle, the next state is determined by the current state and the value of the input signal when the clock pulse occurs.

[0028] When input data changes the state, the propagation delay is the finite amount of time required for a logic gate to perform its operation on the changed input data. One condition for efficient operation is that the interval between clock pulses must be long enough for all logic gates to have time to respond to changes in the input data and for their respective outputs to stabilize to stable logic values ​​before the next clock pulse arrives. Generally, when this condition is met, the circuit is stable and reliable.

[0029] Setup time is the shortest time a signal must remain stable before the rising edge of the clock. Insufficient setup time risks misinterpreting the signal's logical state. More specifically, insufficient setup time risks the signal failing to stabilize to either the first voltage range (clearly representing logic zero) or the third voltage range (clearly representing logic one), instead remaining in the intermediate second voltage range (clearly representing neither logic zero nor logic one). This leads to the possibility that a misinterpretation of the signal's logical state will be input into a register (i.e., latched). Setup slack is the time difference between when a signal becomes active and its setup time. In other words, a positive setup slack means the signal becomes active earlier than the required setup time. A negative setup slack means the signal becomes active after the required setup time. While a large positive setup slack typically prevents misinterpretation of the signal state, it is undesirable because a significant portion of a large positive setup slack represents avoidable delays. Therefore, in general, the goal of establishing a time margin is to have a positive number close to zero.

[0030] Hold time is the shortest time a signal must remain stable after the rising edge of the clock. If the hold time is not met, there is a risk that an incorrect interpretation of the signal's logical state will be input into a register (i.e., latched). Hold-slack is the time difference between when the signal becomes active and the hold time. In other words, when the hold-slack is positive, the signal remains active for a longer period than the required hold time. When the hold-slack is negative, the signal remains active for a shorter period than the required hold time. Generally, while a large positive hold-slack avoids incorrect interpretation of the signal state, a large positive hold-slack is undesirable because a significant portion of a large positive hold-slack represents avoidable delays. Therefore, generally, the target for hold-slack is a positive number close to zero.

[0031] Hold-up time margin fixes or adjustments are typically performed before tape-out (the final result of the design process for a semiconductor device or printed circuit board before it is sent for manufacturing). As technology nodes advance and semiconductor device sizes shrink accordingly, hold-up fixes become more difficult because semiconductor devices include a greater number of bends and additional patterns. Other methods are incorporated into standard cells (e.g., buffer cells and delay cells) to perform hold-up fixes. While these other methods for hold-up fixes may be effective in scenarios with larger time scales (i.e., hold-up time margin violations equal to or greater than about 5 picoseconds), they are not effective for hold-up time margin violations in scenarios with smaller time scales (i.e., hold-up time margin violations less than about 5 picoseconds). In some embodiments, again in scenarios with smaller time scales (i.e., less than about 5 picoseconds), a system and method are disclosed that reduce hold-up time margin violations in a given circuit design (e.g., a flip-flop design).

[0032] Holding time margin violations are most often diagnosed or discovered during static timing analysis (STA), which is part of the EDA process. Compared to the time-consuming and computationally expensive process of fully simulating the entire logic operation of a circuit design, STA represents the circuit design as a set of timing paths, calculates the corresponding signal propagation delays along these paths, and checks for violations of timing constraints. Traditionally, high-performance integrated circuits are characterized by the clock frequency at which they operate. Measurements of a circuit's ability to operate at a specified speed are performed by measuring circuit delays in multiple steps during the design process. Holding time margin violations can be prevalent in smaller timescales (i.e., less than approximately 5 picoseconds). For example, in smaller timescale scenarios, holding time margin violations account for nearly 50% of all design rule violations in some static random access memory (SRAM) designs.

[0033] As discussed above, other methods have incorporated isolated dummy gates to perform hold repair in scenarios with larger timescales (i.e., hold time margin violations equal to or greater than approximately 5 picoseconds). However, the timing effects from the layout-dependent effect (LDE) are becoming increasingly significant at advanced technology nodes. Isolated dummy gates affect flip-flop performance because their influence on the transistor voltage threshold (Vt) introduces timing uncertainties. Changes in Vt not only cause mismatch effects but also significant performance variations.

[0034] As discussed above, typically for Fin-FET architectures, other methods have been incorporated into cell filling to mitigate timing uncertainties in larger timescales (i.e., hold margin violations greater than approximately 5 picoseconds). Typically, cells are filled by expanding the cell footprint by adding dummy devices on both sides of the active circuitry. For example, double-contact polypitch (CPP) dummy devices are added to each of the right and left sides of the device under test (DUT) (e.g., sequential logic circuitry). However, at smaller timescales in advanced technology nodes where hold margin violations are less than approximately 5 picoseconds, each additional dummy device added worsens (i.e., increases) both hold and setup times. Therefore, for smaller timescales, cell filling techniques are not effective for mitigating hold margin violations. For advanced technology nodes, the use of dummy devices does not provide a realistically viable solution for time margin repair. In some embodiments, again in a context of a smaller time scale (i.e., less than about 5 picoseconds), a system and method are disclosed that reduce hold time margin violations in a given circuit design (e.g., a flip-flop design).

[0035] Figure 1 This is a block diagram of a semiconductor device 100 according to some embodiments.

[0036] Semiconductor device 100 includes cell region 102, which includes a left boundary 103 (1), an upper / top cell boundary 103 (2), a right boundary 103 (3), and a lower / bottom cell boundary 103 (4). Generally, the boundaries of cell regions in a semiconductor device are identified in a variety of ways, and some examples are given below. In some embodiments where the long axis of the active region extends in a first direction, for example, parallel to the X-axis, the left boundary of the cell region generally corresponds to a first imaginary line aligning the left end of a first subset of active regions, which includes most of the active regions aligned, and the right boundary of the cell region generally corresponds to a second imaginary line aligning the right end of a second subset of active regions, which includes most of the active regions aligned. In some embodiments where the long axis of the active region extends parallel to a first direction (e.g., the X-axis) and the long axis of the gate segment extends parallel to a second direction perpendicular to the first direction (e.g., the Y-axis), the left and / or right boundaries of the cell region generally correspond to instances of gate segments that have been replaced by isolated dummy gates (discussed below). In some embodiments where the long axis of the active region and the long axis of the power rail extend in a first direction (e.g., the X-axis), the upper / top boundary and / or lower / bottom boundary of the cell region roughly correspond to an instance of the power rail.

[0037] Cell region 102 includes a first set of transistor components 112 and a second set of transistor components 114. In some embodiments, cell region 102 includes sequential logic circuitry. In some embodiments, cell region 102 includes a flip-flop. In some embodiments, cell region 102 includes a D flip-flop. In some embodiments, cell region 102 includes a scan insertion D flip-flop (SDFQ).

[0038] The first set of transistor components 112 is connected as corresponding active transistors defining functional circuitry. The second set of transistor components 114 is connected as one or more corresponding capacitor-configured transistors. Cell region 102 is a rectangular area having a minimum size sufficient to accommodate transistor components. In some embodiments, according to certain examples, cell region 102 is a shape other than a rectangle, such as a square, ellipse, circle, or any other shape. In some embodiments, one or more active transistors are configured at the data input node of cell region 102 (see [link to documentation]). Figures 4A-4F Data is received at the location ) and at the timing input node in cell 102 (see Figures 4A-4F The clock buffer is received at the output node of cell region 102 (see [link to relevant documentation]). In some embodiments, one or more active transistors are configured to receive the clock buffer at the output node of cell region 102 (see [link to relevant documentation]). Figures 4A-4F An output signal is generated at (). This functional circuit represents a modified version of a given circuit design that has suffered a hold violation. Modifications made to reduce hold violations of the functional circuit include configuring the terminals corresponding to the transistors of one or more capacitors in the second set with the target node of the functional circuit (see...). Figures 4A-4F The connection between the cells. In some embodiments, the target node is the input node of cell region 102. In some embodiments, the target node is the output node of cell region. In some embodiments, the target node is an internal node of D flip-flop (see...). Figures 4A-4F In some embodiments, the target node is the output node of the input transistor of an active circuit.

[0039] Cell boundaries 103(1)-103(4) are imaginary boundaries of cell region 102. In some embodiments, cell boundaries 103(1)-103(4) are actually represented by corresponding features of cell region 102. In some embodiments, cell boundaries 103(1)-103(4) are boundaries set by other cell regions (not shown) adjacent to cell region 102.

[0040] Figure 2A-2D It is a layout diagram of corresponding cells 212A-212D in a representative cell region of a semiconductor device according to some embodiments.

[0041] Figure 2B and Figure 2A The comparison between them and Figure 2D and Figure 2C The comparison helps to illustrate a method, according to some embodiments, for repurposing unconnected dummy (again, DD) devices within a cell as connected passive (again, CP) devices, namely the DD2CP method.

[0042] Generally, a layout diagram represents a semiconductor device. The graphics in the layout diagram represent corresponding components within the semiconductor device. The layout diagram itself is a top view. The graphics in the layout diagram are two-dimensional about, for example, the X and Y axes. The semiconductor device represented is three-dimensional. Typically, about the Z-axis, the semiconductor device is organized as a stack of layers, with corresponding structures within these layers; that is, corresponding structures belong to these layers. Therefore, more specifically, each graphic in the layout diagram represents a component in a corresponding layer of the corresponding semiconductor device. Typically, the layout diagram represents the relative depth of the graphics and layers, i.e., their position about the Z-axis, by superimposing a second graphic on a first graphic such that the second graphic at least partially overlaps the first graphic.

[0043] Layout diagrams vary in the amount of detail they represent. In some cases, such as for simplification, selected layers of the layout diagram are combined / abstracted into a single layer. Alternatively and / or additionally, in some cases, such as for the sake of simplicity, not all layers of the corresponding semiconductor device are shown; that is, selected layers of the layout diagram are omitted. Figure 2A-2D Examples of layout diagrams where selected layers have been grouped / abstracted and selected layers have been omitted are described below.

[0044] In some embodiments, Figure 2A-2D Each of the corresponding cells 212A-212D is an example of a cell region 102 of a semiconductor device 100. Cells 212A-212D include cell boundaries 203(1), 203(2), 203(3) and 203(4), which correspond to cell boundaries 103(1)-103(4) of the cell region 102 of the semiconductor device 100.

[0045] exist Figure 2A-2D In the transistor layer, the corresponding units 212A-212B include active device regions 202(1)-202(18), dummy positive channel metal-oxide-semiconductor (PMOS) regions 204(1)-204(2), and dummy negative channel metal-oxide-semiconductor (NMOS) regions 206(1)-206(2). Figure 2C-2DIn the corresponding units 212C-212D, there are also dummy PMOS regions 204(11)-204(14) and dummy NMOS regions 206(11)-206(14). Each of the active device regions 202(1)-202(18) represents an active transistor, such that the combination of active regions 202(1)-202(18) represents, for example, an active transistor formed by the transistor assembly 112 of the first set (see See Figure 1 (The discussion). The active transistors defined by active device areas 202(1)-202(18) define the functional circuits (see the discussion). Figures 4A-4F ). Depending on the functional circuit defined by the active transistors represented by the active device regions 202(1)-202(18), the active device regions 202(1)-202(18) are respectively PMOS or NMOS regions. In some embodiments, the active device regions 202(1)-202(9) are PMOS device regions and the active device regions 202(10)-202(18) are NMOS device regions. Each of the dummy PMOS regions 204(1)-204(2) and the dummy NMOS regions 206(1)-206(2) represents a dummy transistor device, such that the combination of the dummy PMOS regions 204(1)-204(2) and the dummy NMOS regions 206(1)-206(2) represents, for example, a dummy transistor formed by 114 of the transistor assembly of the second set (see Figure 1 (Discussion).

[0046] exist Figure 2A-2D In each of these, for simplicity, a transistor layer is an example of multiple layers combined / abstracted into a single layer. In some embodiments, regarding the basis including Figure 2A-2C The semiconductor device of the corresponding units 212A-212C in larger figures, the transistor layer includes: a sublayer (not shown) corresponding to the substrate forming the active region (not shown), wherein source / drain (S / D) regions (not shown) are correspondingly formed in the active region; an MD sublayer (not shown) including a gate segment (not shown) and a metal-to-source / drain (MD) contact structure (not shown), the latter for coupling the S / D region in the active region to the corresponding VD / VG structure (…). Figure 2B and 2D ); and a VD / VG sublayer (not shown), which includes a VD / VG structure ( Figure 2B-2C The VD / VG structure includes a via-to-source / drain (VD) structure (not shown) and a via-to-gate (VG) structure (not shown). The via-to-source / drain (VD) structure is used to connect the MD contact structure to the corresponding M_1st segment in the first metallized layer (M_1st layer) (not shown). Figure 2B and 2DThe via-gate (VG) structure is used to connect the gate segment to the corresponding M_1st segment.

[0047] The active transistor represented by active regions 202(1)-202(18) defines the active transistor. Figure 2A-2D The functional circuits in it are made of Figure 2A Each dummy transistor represented by dummy PMOS regions 204(1)-204(2) and NMOS regions 206(1)-206(2) is not connected to the functional circuitry of cell 212A. The dummy transistors represented by dummy PMOS regions 204(1)-204(2) and NMOS regions 206(1)-206(2) are examples of DD devices that have undergone in-cell repurposing according to the DD2CP method.

[0048] In some embodiments, the dummy transistors represented by one or more of the dummy PMOS regions 204(1)-204(2) and / or NMOS regions 206(1)-206(2) have a capacitor configuration; however, the dummy transistors are not associated with capacitors. Figure 2A The functional circuit connection of unit 212A. In some embodiments, the dummy transistor represented by one or more of dummy PMOS 204(1) and 204(2) and / or NMOS regions 206(1) and 206(2) has a short-circuit configuration, wherein the gate, drain and source are connected together ( Figure 3B ); Short-circuit configuration prevents dummy transistors from conducting current.

[0049] In some embodiments, the functional circuits defined by units 212A-212D are corresponding sequential logic devices. In some embodiments, the functional units defined by units 212A-212D define corresponding flip-flop units.

[0050] Figure 2A-2D The following assumptions are made regarding the active regions (e.g., 202(1)), the dummy PMOS regions (e.g., 204(1)), and the dummy NMOS regions 206(1): they have the same width (about the X-axis) and height (about the Y-axis) and therefore the same area (referred to herein as unit area); and they are uniformly spaced about each of the X and Y axes (having uniform spacing). Thus, in some embodiments and in terms of unit area, cell 212A is described as having an area of ​​11 units wide and 2 units high.

[0051] about Figure 2AIn some embodiments, one aspect of the in-cell repurposing according to the DD2CP method is subjecting cell 212A to time margin violation analysis (e.g., static timing analysis (STA)) to determine whether any time margin violations are diagnosed or discovered. STA is a simulation method that calculates the desired timing of a synchronous digital circuit without simulating the entire circuit. In response to the STA result for cell 212A indicating no time margin violation and otherwise indicating an acceptable time margin time (e.g., not an excessive time margin time), cell 212A is considered ready to proceed to the next stage of circuit design development. However, in response to the STA result for cell 212A indicating a hold time margin violation, the design engineer considers modifications to cell 212A as a mitigation of the hold time margin, i.e., considers hold repair. An example of subjecting cell 212A to hold time margin mitigation (i.e., subjecting cell 212A to hold repair) is subjecting cell 212A to in-cell repurposing according to the DD2CP method.

[0052] about Figure 2B Unit 212B illustrates the result of subjecting unit 212A to a reduced holding time margin (i.e., subjecting unit 212A to holding repair). More specifically, unit 212B illustrates the result of subjecting unit 212A to a readjustment of its intra-unit use according to the DD2CP method. Figure 2B Assuming by Figure 2A Each of the dummy PMOS regions 204(1)-204(2) and NMOS dummy regions 206(1)-206(2) of cell 212A represents a dummy transistor with a capacitor configuration, however, the dummy transistor is not connected to the functional circuit defined by the transistor represented by the active device regions 202(1)-202(18).

[0053] exist Figure 2B In this context, a first mitigation connection path has been established, which connects a terminal of each of the capacitor-configured dummy transistors represented by each of the dummy PMOS regions 204(1) and NMOS dummy regions 206(1) to node 218, which is shared by transistors represented by active device regions 202(3) and 202(12). The first mitigation connection path includes a corresponding M_1st segment, a corresponding VIA_1st via in the first layer interconnect (VIA_1st layer) (not shown), and a corresponding M_2nd segment in the second layer metallization (M_2nd layer) (not shown). The first mitigation connection path is a first hold repair. In some embodiments where cell 212B defines SDFQ, node 218 has a signal m1_ax ( Figures 4A-4EIn some embodiments where the SDFQ is defined in unit 212B, the signal m1_ax is the input signal to the D flip-flop (FF) of the SDFQ.

[0054] In addition, Figure 2B In this context, a second mitigation connection path has been established, which connects a terminal of each of the dummy transistors configured with capacitors represented by each of the dummy PMOS regions 204 (2) and NMOS dummy regions 206 (2) to node 264, which is shared by transistors represented by active device regions 202 (7) and 202 (16). The second mitigation connection path includes a corresponding M_1st segment, a corresponding VIA_1st via, and a corresponding M_2nd segment. The second mitigation connection path is a second hold repair. In some embodiments where SDFQ is defined in cell 212B, node 264 has a signal Q ( Figures 4A-4E ).

[0055] about Figure 2B In terms of space occupied, the first and second retaining repairs do not increase the space occupied by cell 212B compared to cell 212A. Cell 212B has a space occupied by 11 cell widths and 2 cell heights, which is the same as cell 212A.

[0056] In some embodiments where one or more dummy transistors, represented by dummy PMOS regions 204(1) and 204(2) and dummy NMOS regions 206(1) and 206(2) respectively, have short-circuit configurations, each short-circuit configuration is converted to a capacitor configuration before establishing a first and a second mitigating connection path.

[0057] Figure 2C yes Figure 2A One version of it assumes that the transistor represented by active regions 202(1)-202(18), dummy PMOS regions 204(1)-204(2) and dummy NMOS 206(1)-206(2) has a fin-FET architecture; and that the functional circuit of cell 212A defined by the active transistor represented by active regions 202(1)-202(18) has a hold time margin violation.

[0058] exist Figure 2C In this process, virtual PMOS regions 204(11)-204(12) and virtual NMOS regions 206(11)-206(12) are added at the left boundary 203(1) of adjacent cell 212A, and virtual PMOS regions 204(13)-204(14) and virtual NMOS regions 206(13)-206(14) are added at the right boundary 203(3) of adjacent cell 212A. Cell filling technology has been applied to this process. Figure 2A Unit 212A, thereby generating Figure 2C Unit 212C. Figure 2C Suppose that cell-filling techniques have resolved hold-up time margin violations in scenarios with larger time scales (i.e., equal to or greater than approximately 5 picoseconds), but have not resolved hold-up time margin violations in scenarios with smaller time scales (i.e., less than approximately 5 picoseconds). To resolve hold-up time margin violations in scenarios with smaller time scales, Figure 2C The cell 212C suffers from reduced holding time margin, i.e., it suffers from readjustment of in-cell usage according to the DD2CP method.

[0059] about Figure 2D Cell 212D illustrates the result of subjecting cell 212C to a reduced holding time margin (i.e., subjecting cell 212C to holding repair). More specifically, cell 212D illustrates the result of subjecting cell 212C to a readjustment of its intra-cell use according to the DD2CP method. Figure 2D Assuming by Figure 2C The dummy transistors represented by each of the dummy PMOS regions 204(1)-204(2) and 204(11)-204(14) and the NMOS dummy regions 206(1)-206(2) and 206(11)-206(14) of cell 212C have a capacitor configuration, however, the dummy transistors are not connected to the functional circuits defined by the transistors represented by the active device regions 202(1)-202(18).

[0060] exist Figure 2D In the middle, the first lightened connection path has been established, which is connected with... Figure 2B The first mitigation path in unit 212B is the same. Additionally, a second mitigation connection path has been established, which is... Figure 2B The extension of the second mitigation path in cell 212B. More specifically, the second mitigation path of cell 212D additionally connects one terminal of each of the dummy transistors in the capacitor configuration represented by each of the dummy PMOS regions 204(13)-204(14) and NMOS dummy regions 206(13)-206(14) to node 264.

[0061] In addition, Figure 2DIn this context, a third mitigation connection path has been established, which connects a terminal of each of the dummy transistors in the capacitor configuration represented by each of the dummy PMOS regions 204(11)-204(12) and NMOS dummy regions 206(11) and 206(12) to node 214, which is shared by the transistors represented by active device regions 202(1) and 202(2). The third mitigation connection path includes a corresponding M_1st segment, a corresponding VIA_1st via, and a corresponding M_2nd segment. The third mitigation connection path is a third hold repair. In some embodiments where cell 212D defines SDFQ, node 214 has signal D ( Figures 4A-4E ).

[0062] about Figure 2D In terms of space occupied, compared with Figure 2C Compared to cell 212C, the first holding repair, the second holding repair, and the third holding repair do not increase the space occupied by cell 212D. Cell 212D has a space occupied by 15 cell widths and 2 cell heights, which is the same as cell 212C.

[0063] In some embodiments where one or more dummy transistors, represented by dummy PMOS regions 204(11) and 204(12) and dummy NMOS regions 206(11) and 206(12) respectively, have short-circuit configurations, each short-circuit configuration is converted to a capacitor configuration before establishing a first, second, and third mitigation connection path.

[0064] Figure 3A This is a schematic diagram of a capacitor-configured transistor 300A according to some embodiments.

[0065] In some embodiments, the capacitor configuration transistor 300A is... Figure 2A-2D The virtual PMOS regions 204(1)-204(2) and virtual NMOS regions 206(1)-206(2) and Figure 2C-2D Examples of one or more capacitor configuration transistors represented by dummy PMOS regions 204(11)-204(14) and dummy NMOS regions 206(11)-206(14). Capacitor configuration transistor 300A includes: a gate 320A representing a first capacitor plate; and a first source / drain (S / D) 322A and a second S / D 324A, which are connected together via conductor 326A and represent a second capacitor plate. In some embodiments, a body bias (body bias) terminal of transistor 300A is also connected to conductor 326A. In some embodiments, the first capacitor plate is connected to a node of a functional circuit, while the second capacitor plate remains floating. In some embodiments, the second capacitor plate is connected to a node of a functional circuit, while the first capacitor plate remains floating.

[0066] Figure 3B This is a schematic diagram of a short-circuit transistor 300B according to some embodiments.

[0067] In some embodiments, the short-circuit transistor 300B is... Figure 2A-2D The virtual PMOS regions 204(1)-204(2) and virtual PMOS regions 206(1)-206(2) in the middle and Figure 2C-2D Examples of one or more short-circuit transistors represented by dummy PMOS regions 204(11)-204(14) and dummy PMOS regions 206(11)-206(14). Short-circuit transistor 300B includes a gate 320B, a first source / drain (S / D) 322B, and a second S / D 324B. The first S / D 322B and the second S / D 324B are connected together via conductor 326B(1). The first S / D 322B and the gate 320B are connected together via conductor 326B(2). The gate 320B and the second S / D 324B are connected together via conductor 326B(3). In some embodiments, the body bias (body bias) terminal of transistor 300B is also connected to conductor 326B(1).

[0068] Figure 4A This is a schematic diagram of circuit 400 according to some embodiments.

[0069] Figure 4B , 4C 4D, 4E and 4F are corresponding schematic diagrams of the corresponding circuits 402B, 402C, 402D and 402E according to some embodiments.

[0070] In some embodiments, circuit 400 is composed of Figure 1 Examples of functional circuits defined by transistor components 112 and 114. In some embodiments, circuit 400 is composed of... Figure 2B The active regions 202(1)-202(18), PMOS regions 204(1)-204(2) and NMOS regions 206(1)-206(2) or Figure 2D Examples of functional circuits defined by transistors represented by the active regions 202(1)-202(18), PMOS regions 204(1)-204(2) and 204(11)-204(14) and NMOS regions 206(1)-206(2) and 206(11)-206(14).

[0071] exist Figure 4AIn this circuit, circuit 400 is a scan-insertion D flip-flop (SDFQ). Semiconductor circuit 400 includes a multiplexer 402A, a D flip-flop 404, a clock buffer 401, a scan buffer 403, a first pair of uncoupled capacitor-configured transistors 405, and a second pair of capacitor-configured transistors 407. In some embodiments, either pair 405 or pair 407 is not included in SDFQ 400.

[0072] SDFQ 400 is the result of repurposing the original SDFQ (not shown) within its cell according to the DD2CP method. More specifically, including the corresponding capacitor configuration transistor pairs 405 and 407 in the SDFQ is the result of repurposing the original SDFQ (not shown) within its cell according to the DD2CP method.

[0073] exist Figure 4A In this configuration, capacitor configuration transistor pair 405 includes capacitor configuration transistors P51 and N51. One capacitor plate of each of capacitor configuration transistors P51 and N51 is connected to input node 406(0) of SDFQ 400, which receives the input signal D. More specifically, each of the gate terminal 406(3) of capacitor configuration transistor P51 and the gate terminal 406(4) of capacitor configuration transistor N61 is connected to input node 406(0) of SDFQ 400. Furthermore, as described below, the gate terminal 406(1) of transistor P13 and the gate terminal 406(2) of transistor N15 are also connected to input node 406(0).

[0074] The capacitor configuration transistor pair 405 indicates that a first hold repair has been applied to the SDFQ 400. The capacitor configuration transistor pair 405 influences the hold time margin of the SDFQ 400 by altering the data path of the input data signal at input node 406(0), e.g., by increasing the capacitance at input node 406(0). In some embodiments, assuming the input signal has a current state representing a logic value of 1 and a previous state representing a logic value of 0, as the input signal stabilizes to the current state at input node 406(0), the input signal first charges capacitor configuration transistors P51 and N51 (which have been discharged by the previous state of the input signal). This charging takes a small amount of time but still delays the stabilization of the data signal by a sufficient amount to helpfully influence the hold time margin of the SDFQ 400. In some embodiments, assuming the input signal has a current state representing a logic value of 0 and a previous state representing a logic value of 1, as the input signal stabilizes to the current state at input node 406(0), the input signal first discharges capacitors configuring transistors P51 and N51 (P51 and N51 have been charged by the previous state of the data signal). This discharge takes a small amount of time, but still delays the stabilization of the input signal by a sufficient amount to helpfully affect the hold time margin of the SDFQ 400.

[0075] exist Figure 4A In this configuration, capacitor configuration transistor pair 407 includes capacitor configuration transistors P61 and N61. One capacitor plate of each of capacitor configuration transistors P61 and N61 is connected to output node 464. More specifically, the gate terminal of each of capacitor configuration transistors P61 and N61 is connected to output node 464. For discussion and efficiency purposes, devices referred to as Pxx transistors are PMOS devices, while devices referred to as Nxx transistors are NMOS transistors.

[0076] The capacitor configuration transistor pair 407 indicates that a second hold repair has been applied to the SDFQ 400. The capacitor configuration transistor pair 407 influences the hold time margin of the SDFQ 400 by altering the data path of the output data signal at output node 464 (e.g., by increasing the capacitance at output node 464). In some embodiments, assuming the data signal has a current state representing a logic value of 1 and a previous state representing a logic value of 0, as the data signal stabilizes to the current state at output node 464, the data signal first charges capacitor configuration transistors P61 and N61 (P61 and N61 have been discharged by the previous state of the data signal). This charging takes a small amount of time but still delays the stabilization of the data signal by a sufficient amount to helpfully influence the hold time margin of the SDFQ 400. In some embodiments, assuming the data signal has a current state representing a logic value of 0 and a previous state representing a logic value of 1, as the data signal stabilizes to the current state at output node 464, the data signal first discharges capacitor configuration transistors P61 and N61 (P61 and N61 have been charged by the previous state of the data signal). The discharge takes a small amount of time, but still delays the stabilization of the data signal by a sufficient amount, thus affecting the hold time margin of the SDFQ 400 in a helpful way.

[0077] exist Figure 4A In this configuration, scan buffer 403 receives a scan / test enable (SE) signal, which selects between normal operation with respect to the input signal D or scan operation with respect to the scan input (SI) signal. Scan buffer 403 is an inverter comprising transistors P41 and N41 connected in series. Transistor P41 is connected between nodes 480 and 482, each having a first reference voltage (e.g., VDD). Transistor N41 is connected between node 482 and node 484, each having a second reference voltage (e.g., VSS). The gate terminals of each of transistors P41 and N41 are connected together and configured to receive the signal SE. Node 482 has a signal seb, which is the inverted signal of signal SE.

[0078] exist Figure 4A In this configuration, clock buffer 401 includes a pair of inverters. The first inverter includes transistors P31 and N31 connected in series. Transistor P31 is connected between nodes 468 and 472, which have a voltage VDD. Transistor N31 is connected between node 472 and node 476, which has a voltage VSS. The gate terminals of each of transistors P31 and N31 are connected together and configured to receive a clock signal CP. Node 472 represents the output node of the first inverter and has a clock signal clkb, which represents the inverted signal of signal CP. Each of signals SE and seb is routed to and used by multiplexer 402A.

[0079] The second inverter includes transistors P32 and N32 connected in series. Transistor P32 is connected between nodes 470 and 474, which have a voltage VDD. Transistor N32 is connected between node 474 and node 478, which has a voltage VSS. The gate terminals of each of transistors P32 and N32 are connected together and connected to node 472, and are therefore configured to receive a clock signal clkb. Node 474 represents the output node of the second inverter and has a clock signal clkbb, which represents the inverted signal clkb. Each of signals clkb and clkbb is routed to and used by each of multiplexer 402 and D flip-flop 404.

[0080] exist Figure 4A In this multiplexer 402A, transistors P11-P15 and N11-N15 are included. Transistor P11 is connected between nodes 408 and 412, which have a voltage VDD. The gate terminal of transistor P11 receives signal SI. Transistor P12 is connected between nodes 412 and 416. The gate terminal of transistor P12 receives signal seb. Transistor P13 is connected between nodes 410 and 414, which have a voltage VDD. The gate terminal 406 (1) of transistor P13 receives input signal D. Transistor P14 is connected between nodes 414 and 416. The gate terminal of transistor P14 receives signal SE. Transistor P15 is connected between node 416 and node 418, which has a signal m1_ax. The gate terminal of transistor P15 receives signal clkbb. Transistor N11 is connected between nodes 418 and 420. The gate terminal of transistor N11 receives signal clkb. Transistor N12 is connected between nodes 420 and 422. The gate terminal of transistor N12 receives signal SE. Transistor N13 is connected between node 422 and node 426 with voltage VSS. The gate terminal of transistor N13 receives signal SI. Transistor N14 is connected between nodes 420 and 424. The gate terminal of transistor N14 receives signal seb. Transistor N15 is connected between node 424 and node 428 with voltage VSS. The gate terminal 406(2) of transistor N15 receives input signal D.

[0081] exist Figure 4AIn this configuration, the D flip-flop 404 includes a first non-sleeping (NS) inverter, a second non-sleeping (NS) inverter, a third non-sleeping (NS) inverter, a transmission gate, and a first sleep inverter and a second sleep inverter. The first NS inverter includes transistors P21 and N21. Transistor P21 is connected between nodes 432 and 434, which have a voltage VDD. Transistor N21 is located between node 434 and node 436, which has a voltage VSS. The gate terminals of transistors P21 and N21 are connected together and connected to node 418, thus being configured to receive the signal m1_ax. Thus, signal m1_ax represents the input signal of the D flip-flop 404. Node 434 represents the output node of the first NS inverter and has a signal m1_b, which represents the inverted signal m1_ax.

[0082] In D flip-flop 404, the first sleep inverter includes transistors P22-P23 and N22-N23. Transistor P22 is connected between nodes 438 and 440, which have a voltage VDD. Transistor P23 is connected between nodes 440 and 418. The gate terminal of transistor P23 receives the signal clkb. Transistor N22 is connected between nodes 418 and 442. The gate terminal of transistor N22 receives the signal clkbb. Transistor N23 is connected between node 442 and node 444, which has a voltage VSS. The gate terminal of transistor N22 receives the signal clkbb. Due to transistors P23 and N22, the first sleep inverter can enter sleep mode. The gate terminals of transistors P22 and N23 are connected together and connected to node 434. Therefore, the first sleep inverter feeds back the inverted version of the signal m1_b (from node 434) to node 418.

[0083] exist Figure 4A In this configuration, the transmission gates include transistors P24 and N24. Transistors P24 and N24 are connected in parallel between nodes 434 and 446. The gate of transistor P24 receives the signal clkb. The gate terminal of transistor N24 receives the signal clkbb. Node 446 has the signal s1_a.

[0084] In the D flip-flop 404, the second NS inverter includes transistors P25 and N25. Transistor P25 is connected between nodes 456 and 458, which have a voltage VDD. Transistor N25 is connected between node 458 and node 460, which has a voltage VSS. The gate terminals of transistors P25 and N25 are connected together and connected to node 446, thus being configured to receive the signal s1_a. Node 458 represents the output node of the second NS inverter and has a signal s1_bx, which represents the inverted signal of signal s1_a.

[0085] exist Figure 4A In this circuit, the second sleep inverter includes transistors P26-P27 and N26-N27. Transistor P26 is connected between nodes 448 and 450, which have a voltage VDD. Transistor P27 is connected between nodes 450 and 446. The gate terminal of transistor P27 receives the signal clkbb. Transistor N26 is connected between nodes 446 and 452. Transistor N27 is connected between node 452 and node 454, which has a voltage VSS. The gate terminal of transistor N26 receives the signal clkb. Due to transistors P27 and N26, the second sleep inverter can enter sleep mode. The gate terminals of transistors P22 and N23 are connected together and connected to node 458. Therefore, the second sleep inverter feeds back the inverted version of the signal s1_bx (from node 458) to node 446.

[0086] In the D flip-flop 404, the third NS inverter includes transistors P28 and N28. Transistor P28 is connected between nodes 462 and 464, which have a voltage VDD. Transistor N28 is connected between node 464 and node 466, which has a voltage VSS. The gate terminals of transistors P28 and N28 are connected together and connected to node 458, and are therefore configured to receive the signal s1_bx. Node 464 represents the output node of the third NS inverter, and therefore the output node of the D flip-flop 404. Furthermore, node 464 also represents the output node of the SDFQ 400. Node 464 has a signal Q, which represents the inverted signal of signal s1_bx.

[0087] exist Figure 4BIn this embodiment, multiplexer 402B is a first alternative version of multiplexer 402A. Thus, multiplexer 402B is included in a corresponding first alternative version (not shown) of SDFQ 400. Specifically, multiplexer 402B also includes a pair 409 of capacitor configuration transistors P71 and N71. One capacitor plate of each of capacitor configuration transistors P71 and N71 is connected to node 418. More specifically, the gate terminal of each of capacitor configuration transistors P71 and N71 is connected to node 418. The capacitor configuration transistors P71 and N71 together in the pair 409 affect the hold time margin of the first alternative version of SDFQ 400 by changing the data path of the signal m1_ax at input node 418 (e.g., by increasing the capacitance at node 418). This change to the data path, though slight, still delays the stabilization of signal m1_ax by a sufficient amount to helpfully affect the hold time margin of the first alternative version of SDFQ 400. The first alternative version of SDFQ 400 is the result of repurposing the original SDFQ (not shown) for in-cell use according to the DD2CP method. More specifically, the pair 409 including capacitor configuration transistors P71 and N71 in the first alternative version of SDFQ 400 is the result of repurposing the original SDFQ (not shown) for in-cell use according to the DD2CP method. In some embodiments, either pair 405 or pair 407 is not included in the first alternative version of SDFQ 400.

[0088] exist Figure 4CIn this context, multiplexer 402C is a second alternative version of multiplexer 402A. Thus, multiplexer 402C is included in a corresponding second alternative version (not shown) of SDFQ 400. Specifically, multiplexer 402C also includes capacitor configuration transistors P81 and N81. One capacitor plate of capacitor configuration transistor P81 is connected to node 414. One capacitor plate of capacitor configuration transistor N81 is connected to node 424. More specifically, the gate terminals of capacitor configuration transistors P81 and N81 are respectively connected to nodes 414 and 424. Capacitor configuration transistors P81 and N81 accordingly affect the hold time margin of the second alternative version of SDFQ 400 by changing the data paths that respectively include nodes 414 and 424 (e.g., by increasing the corresponding capacitance at nodes 414 and 424). Although these changes to the corresponding data paths are minor, they still delay the stabilization of the corresponding signals on nodes 414 and 424 by a sufficient amount to affect the hold-up time margin of the second alternative version of SDFQ 400 in a helpful manner. The second alternative version of SDFQ 400 is the result of repurposing the original SDFQ (not shown) according to the DD2CP method for its in-cell usage. More specifically, the inclusion of capacitor configuration transistors P81 and N81 in the second alternative version of SDFQ 400 is the result of repurposing the original SDFQ (not shown) according to the DD2CP method for its in-cell usage. In some embodiments, either pair 405 or pair 407 is not included in the second alternative version of SDFQ 400. In some embodiments, Figure 4B The 402B multiplexer includes the 409. Figure 4C In the 402C multiplexer.

[0089] exist Figure 4D In this context, multiplexer 402D is a version of multiplexer 402C, making it a third alternative to multiplexer 402A. Thus, multiplexer 402D is included in the corresponding third alternative (not shown) of SDFQ 400. The difference between multiplexer 402D and multiplexer 402C is that multiplexer 402D also includes a connection 490 between the gate terminals of corresponding capacitors configuring transistors P81 and N81. Thus, nodes 414 and 424 are connected together in multiplexer 402D, whereas nodes 414 and 424 are not connected in multiplexer 402C. In some embodiments, either pair 405 or pair 407 is not included in the third alternative of SDFQ 400. In some embodiments, Figure 4B The 402B multiplexer includes the 409. Figure 4D In the 402D multiplexer.

[0090] exist Figure 4E In this context, multiplexer 402E is a fourth alternative version of multiplexer 402A. Thus, multiplexer 402E is included in a corresponding fourth alternative version (not shown) of SDFQ 400. Specifically, multiplexer 402E also includes capacitor configuration transistors P91 and N91. One capacitor plate of capacitor configuration transistor P91 is connected to the gate terminal 406(1) of transistor P13. One capacitor plate of capacitor configuration transistor N81 is connected to the gate terminal 406(2) of transistor N15. More specifically, the gate terminals of capacitor configuration transistors P91 and N91 are respectively connected to the gate terminals 406(1) of the respective transistors P13 and N15. The capacitor configuration transistors P91 and N91 affect the hold time margin of the fourth alternative version of the SDFQ 400 by changing the data path, which correspondingly includes the gate terminal 406(1) of the corresponding transistor P13 and the gate terminal 406(2) of N15 (e.g., by increasing the capacitance at the gate terminals 406(1) and 406(2) of the corresponding transistors P13 and N15). These changes to the corresponding data paths, though minor, still delay the stabilization of the signals at the gate terminals 406(1) of the corresponding transistors P13 and N15 by a sufficient amount, thereby helpfully affecting the hold time margin of the fourth alternative version of the SDFQ 400. The fourth alternative version of the SDFQ 400 is the result of reconfiguring the original SDFQ (not shown) for in-cell use according to the DD2CP method. More specifically, the inclusion of capacitor configuration transistors P91 and N91 in the fourth alternative version of SDFQ 400 is a result of repurposing the original SDFQ (not shown) for in-cell use according to the DD2CP method. In some embodiments, either pair 405 or pair 407 is not included in the fourth alternative version of SDFQ 400. In some embodiments, Figure 4B The 402B multiplexer includes the 409. Figure 4E In the 402E multiplexer.

[0091] exist Figure 4FIn this context, multiplexer 402F is a version of multiplexer 402E, and it also makes multiplexer 402F the fifth alternative version of multiplexer 402A. Thus, multiplexer 402F is included in the corresponding fifth alternative version (not shown) of SDFQ 400. The difference between multiplexer 402F and multiplexer 402E is that multiplexer 402F also includes a connection 492 between the gate terminals of the respective capacitor-configured transistors P91 and N91. Thus, the gate terminals 406(1) of the respective transistors P13 and N15 are connected together in multiplexer 402F, whereas the gate terminals 406(1) of the respective transistors P13 and N15 are not connected in multiplexer 402C. In some embodiments, either 405 or 407 is not included in the fifth alternative version of SDFQ 400. In some embodiments, Figure 4B The 402B multiplexer is included in the 409. Figure 4F In the 402F multiplexer.

[0092] Figure 5A , 5B 5C, 5D, 5E and 5F are layout diagrams representing corresponding cells 500A, 500B, 500C, 500D, 500E and 500F of corresponding cell regions in a semiconductor device according to some embodiments. Figure 5G This is a cross-section based on some embodiments.

[0093] Units 500A-500F and Figures 4A-4F The relationship is as follows. Figure 5A The 500A unit uses a planar transistor architecture, which is similar to... Figure 4C The multiplexer 402C is represented as a second alternative version (not shown) to the SDFQ 400. Figure 5B The 500B cell uses a Fin-FET architecture, which is similar to... Figure 4D The multiplexer 402D is a representation of the third alternative version (not shown) of the SDFQ 400 corresponding to it. Figure 5C The 500C cell uses a planar transistor architecture, which is similar to... Figure 4B The multiplexer 402B is represented by a second alternative version (not shown) of the SDFQ 400 corresponding to it. Figure 5D The 500D cell uses a Fin-FET architecture, which is similar to... Figure 4B The multiplexer 402B is represented by a second alternative version (not shown) of the SDFQ 400 corresponding to it. Figure 5E The 500E cell uses a planar transistor architecture, which is similar to... Figure 4EThe multiplexer 402E is a representation of the fourth alternative version (not shown) of the SDFQ 400 corresponding to it. Figure 5F The 500F cell uses a Fin-FET architecture, which is similar to... Figure 4F The multiplexer 402F is represented as the fifth alternative version (not shown) to the SDFQ 400.

[0094] The cell region 102 of the semiconductor device 100 is an example of a cell region in the semiconductor device obtained from a larger layout drawing that correspondingly includes cells 500A, 500B, 500C, 500D, 500E, and 500F. Each of cells 500A, 500B, 500C, 500D, 500E, or 500F includes cell boundaries 503(1), 503(2), 503(3), and 503(4), which correspond to cell boundaries 103(1)-103(4) of the cell region 102 of the semiconductor device 100. For the sake of simplicity, in Figure 5A , 5B Repeated reference numerals have been omitted in figures 5C, 5D, 5E, and 5F. Figure 5A , 5B The differences between 5C, 5D, 5E and 5F are pointed out; variations in elements are indicated by different reference numerals.

[0095] Figure 5A , 5C The corresponding units 500A, 500C and 500E of 5E adopt the corresponding planar transistor architecture. Figure 5B , 5D The corresponding cells 500B, 500D, and 500F of 5F employ the corresponding fin-FET architecture. Each of cells 500A, 500B, 500C, 500D, 500E, or 500F includes a substrate region 520, which is located in a first layer or substrate layer, or in a sublayer of a transistor layer.

[0096] Generally, a layout diagram represents a three-dimensional semiconductor device. The graphics in the layout diagram represent corresponding components within the semiconductor device. The layout diagram itself is a top view. The graphics in the layout diagram are two-dimensional. More specifically, each graphic in the layout diagram represents a component in a corresponding layer of the corresponding semiconductor device. Typically, a layout diagram represents relative depth by superimposing a second graphic on a first graphic such that the second graphic at least partially overlaps with the first graphic.

[0097] In a more formal naming context, Figure 4A SDFQ 400 or with Figure 4B-4F The elements in the corresponding SDFQ 400 first to fifth optional versions (not shown) etc. are... Figures 5A-5FThe corresponding patterned (also called graphic) representation in the corresponding layout diagram. For the sake of simplicity in discussion, i.e. for ease of discussion, Figures 5A-5F Some elements in the layout diagram are just like they are Figures 4A-4F The corresponding structure (rather than the pattern / graphic itself) is mentioned.

[0098] exist Figure 5A In the diagram, active region (AR) patterns 522(1) and 522(2) extend parallel to the X-axis and have a width about the X-axis. AR patterns 522(1) and 522(2) are in the second layer or in the AR layer, or in a sublayer of the transistor layer, etc. AR pattern 522(2) represents an n-type AR and AR pattern 522(1) represents a p-type AR. Gate pattern 544 extends parallel to the Y-axis and has a width along the X-axis. Gate pattern 544 is in the third layer or the gate layer, or in the MD sublayer of the transistor layer, etc. Contact pattern 526 or VD / / VG pattern is in the fourth layer or in the VD / VG sublayer of the transistor layer, etc. Conductive segments 528(1)A, 528(2)A and 528(3)A are M_1st segments, which correspond to the conductors included in the first (1st) metallization layer (M_1st layer) in a semiconductor device based on a correspondingly larger layout including SDFQ 500A. In some embodiments, depending on the numbering convention of the corresponding process node used to manufacture this semiconductor device, the M_1st layer is either metallization layer zero (M0) or metallization layer one (M1). Discontinuity 530 indicates a pattern omitted for the sake of simplicity in description and discussion.

[0099] In the SDFQ 500A, the gate patterns originally shared by transistors P14 and N15, P12 and N12, and P15 and N11 are designated to be cut / divided by the corresponding cut gate (CG) patterns. The gate pattern receive signals are: D for transistors P13 and N15; SE for transistor P14; seb for transistor N14; seb for transistor P12; SE for transistor N12; SI for transistors P11 and N13; clkbb for transistor P15; and clkb for transistor N11.

[0100] exist Figure 5AIn the diagram, segment M_1st 528(1)A connects the S / D region shared by transistors P13 and P14 to the gate pattern of transistor P81 via the corresponding VGD pattern 526 and the MD contact pattern (not shown) (regarding the S / D region). S_1st segment 528(2)A connects the S / D region shared by transistors N15 and N14 to the gate pattern of transistor N81 via the corresponding VGD pattern 526 and the MD contact pattern (not shown) (regarding the S / D region). S_1st segment 528(3)A connects the S / D region of transistor P28 to the S / D region of transistor N28 and to the gate patterns of each of transistors P61 and N61 via the corresponding VGD pattern 526 and the corresponding MD contact pattern (not shown) (regarding the S / D region). S_1st segment 528(3)A is designated to have a signal Q.

[0101] In SDFQ 500A, M_1st segment 528(4)A connects the first and second S / D regions of transistor P81 and transistor P61 via corresponding VGD pattern 526 and MD contact pattern (not shown), wherein the second S / D region of transistor P81 is the same as the first S / D region of transistor P61. M_1st segment 528(5)A connects the first and second S / D regions of transistor N81 via corresponding VGD pattern 526 and MD contact pattern (not shown). M_1st segment 528(6)A connects the first and second S / D regions of transistor N61 via corresponding VGD pattern 526 and MD contact pattern (not shown).

[0102] Figure 5G The cell region 500G corresponds to Figure 5A Unit 500A. Specifically, Figure 5G The cell region 500G corresponds to Figure 5A The cross-section line shown is 5G-5G'. In... Figure 5G In the diagram, AR 522(1) is shown as divided into three parts: 522(1)(1), 522(1)(2), and 522(1)(3). Relative to... Figure 5A , Figure 5G It also includes a metal-to-source / drain (MD) contact structure 525. Figure 5G The capacitor configuration transistors P61 and P81 are shown, etc.

[0103] exist Figure 5BIn this context, the gate patterns originally shared by transistors P14 and N15, P12 and N12, and P15 and N11 are designated to be cut / divided by the corresponding cut gate (CG) patterns. The gate patterns of transistors P13 and N13 receive signal D. The gate pattern of transistor P14 receives signal SE. The gate pattern of transistor N14 receives signal seb. The gate pattern of transistor P12 receives signal seb. The gate pattern of transistor N12 receives signal SE. The gate pattern of transistors P11 and N13 receives signal SI. The gate pattern of transistor P15 receives signal clkbb. The gate pattern of transistor N11 receives signal clkb. The M_1st segment 528(1)B connects the S / D region shared by transistors P13 and P14 to the gate patterns of transistors P81 and N91 via the corresponding VGD pattern 526 and the MD contact pattern (not shown) (regarding the S / D region).

[0104] In SDFQ 500B, M_1st segment 528(2)B connects the S / D region shared by transistors N15 and N14 to the gate patterns of each of transistors P81 and N81 via the corresponding VGD pattern 526 and the MD contact pattern (not shown) (regarding the S / D region). M_1st segment 528(3)B connects the S / D region of transistor P28 to the S / D region of transistor N28 and to the gate patterns of each of transistors P61 and N61 via the corresponding VGD pattern 526 and the MD contact pattern (not shown) (regarding the S / D region). M_1st segment 528(3)B is designated to have a signal Q. The gate pattern between (A) the gate patterns of transistors P13 and N15 and (B) the gate patterns of transistors P81 and N81 is designated as the isolated dummy gate (IDG).

[0105] exist Figure 5B In the diagram, segment M_1st 528(7)B connects the first S / D region, second S / D region, and third S / D region of transistor P61 via the corresponding VGD pattern 526 and MD contact pattern (not shown). Segment M_1st 528(8)B connects the first S / D region, second S / D region, and third S / D region of transistor N61 via the corresponding VGD pattern 526 and MD contact pattern (not shown). Segment M_1st 528(9)B connects the first S / D region, second S / D region, and third S / D region of transistor P81 via the corresponding VGD pattern 526 and MD contact pattern (not shown). Segment M_1st 528(10)B connects the first S / D region, second S / D region, and third S / D region of transistor N81 via the corresponding VGD pattern 526 and MD contact pattern (not shown).

[0106] In SDFQ 500B, the gate pattern between (A) transistors P15 and N11 and the gate pattern between (B) interrupt 530 is designated as an isolated dummy gate (IDG). The gate pattern between (A) transistors P11 and N13 and the gate pattern between (B) transistors P15 and N11 is designated as an isolated dummy gate (IDG).

[0107] In some embodiments, the isolation dummy gate is a dielectric structure comprising one or more dielectric materials and serving as an electrical isolation structure. Therefore, the isolation dummy gate is not a conductive structure and is not used as an active gate, for example, in a transistor. The isolation dummy gate comprises one or more dielectric materials and serves as an electrical isolation structure. In some embodiments, the isolation dummy gate is based on a gate structure as a precursor. In some embodiments, the dummy gate structure comprises a gate conductor, a gate insulating layer, or (optionally) one or more spacers, etc. In some embodiments, the isolation dummy gate is formed by: first forming a gate structure (e.g., a dummy gate structure); sacrificing / removing (e.g., etching) the gate conductor of the gate structure to form a trench; (optionally) removing a portion of the substrate previously beneath the gate conductor to deepen the trench; and then filling the trench with one or more dielectric materials such that the physical dimensions of the resulting electrical isolation structure (i.e., the isolation dummy gate) are similar to the dimensions of the sacrificed dummy gate conductor (i.e., the gate conductor or a combination of the gate conductor and the portion of the substrate). In some embodiments, the isolation dummy gate is a dielectric feature and serves as an isolation feature, comprising one or more dielectric materials (e.g., oxides, nitrides, oxynitrides, or other suitable materials). In some embodiments, the isolation dummy gate is continuous polysilicon on an oxide diffusion (OD) edge structure and is referred to as a CPODE structure.

[0108] about Figure 5C Note the relative Figure 5A The difference. M_1st segment 528(4)C connects the first S / D region and the second S / D region of transistor P71 and the first S / D region and the second S / D region of transistor P61 through the corresponding VGD pattern 526 and MD contact pattern (not shown), wherein the second S / D region of transistor P71 is the same as the first S / D region of transistor P61. M_1st segment 528(5)C connects the first S / D region and the second S / D region of transistor N71 through the corresponding VGD pattern 526 and MD contact pattern (not shown). Figure 5C It also includes section 528(7)C of M_1st, but omits... Figure 5AThe M_1st segments 528(1)A and 528(2)A. The M_1st segment 528(7)C connects the S / D region of transistor P15 to the S / D region of transistor N11 and to the gate pattern of transistor N71 and the gate pattern of transistor P71 via the corresponding VGD pattern 526 and the MD contact pattern (not shown) (regarding the S / D region). The M_1st segment 528(7)C is designated to have the signal m1_ax.

[0109] about Figure 5D Note the relative Figure 5B The differences. In Figure 5D In the SDFQ 500D, the M_1st segment 528(7)D is also included, but the ellipsis is omitted. Figure 5B M_1st segments 528(1)B and 528(2)B. M_1st segment 528(7)D connects the gate patterns of each of transistors P71 and N71 to the S / D region of transistor P15 and to the S / D region of transistor N11 via the corresponding VGD pattern 526 and the MD contact pattern (not shown) (regarding the S / D region). The gate pattern between the gate patterns of transistors (A) P13 and N15 and (B) P71 and N71 is designated as an isolated dummy gate (IDG). Figure 5D In the middle, segment M_1st 528 (9)D connects the first S / D region, the second S / D region, and the third S / D region of transistor P71 through the corresponding VGD pattern 526 and MD contact pattern (not shown). Segment M_1st 528 (10)D connects the first S / D region, the second S / D region, and the third S / D region of transistor N71 through the corresponding VGD pattern 526 and MD contact pattern (not shown).

[0110] about Figure 5E Note the relative Figure 5C The difference. M_1st segment 528(4)E connects the first S / D region and the second S / D region of transistor P91 and the first S / D region and the second S / D region of transistor P61 through the corresponding VGD pattern 526 and MD contact pattern (not shown), wherein the second S / D region of transistor P91 is the same as the first S / D region of transistor P61. M_1st segment 528(5)E connects the first S / D region and the second S / D region of transistor N91 through the corresponding VGD pattern 526 and MD contact pattern (not shown). Figure 5E It also includes section 528(8)E of M_1st, but omits... Figure 5CM_1st segment 528 (7) C. M_1st segment 528 (8) E connects the gate patterns of transistors P13 and N15 to the gate pattern of transistor N91 and to the gate pattern of transistor P91 via the corresponding VGD pattern 526 and the corresponding MD contact pattern (not shown) (with respect to the S / D area).

[0111] about Figure 5F Note the relative Figure 5D The differences. In Figure 5F In SDFQ 500F, the M_1st segment 528(8)F is also included, but the ellipsis is omitted. Figure 5D M_1st segment 528(7)D. M_1st segment 528(8)F connects the gate pattern of each of transistors P91 and N91 to the gate electrode of each of transistors P13 and N15 via the corresponding VGD pattern 526. Figure 5F In the middle, segment M_1st 528 (9)F connects the first S / D region, the second S / D region, and the third S / D region of transistor P91 through the corresponding VGD pattern 526 and MD contact pattern (not shown). Segment M_1st 528 (10)F connects the first S / D region, the second S / D region, and the third S / D region of transistor N91 through the corresponding VGD pattern 526 and MD contact pattern (not shown).

[0112] Figure 6A This is a flowchart of a method 600 for generating a layout diagram according to some embodiments.

[0113] Method 600 includes blocks 602-610. In Figure 6A At block 602, identify the cell with a time margin violation in the layout diagram. An example of a cell with a time margin violation is... Figure 2A Unit 212A, etc. The process proceeds from block 602 to block 604.

[0114] Alternatively, Figure 6A The process begins at block 603. In block 603, a cell is selected from the standard cell library. An example of this cell is... Figure 2A Examples include unit 212A in the standard unit library. Figure 8 The standard cell library 820, etc. The process proceeds from block 603 to block 604.

[0115] In block 604, dummy devices are identified that reside within a cell and are not connected to an active circuit defined by the cell. Examples of dummy devices not connected to an active circuit include those defined by... Figure 2A The virtual transistors are represented by virtual PMOS regions 204(1)-204(2) or virtual NMOS regions 206(1)-206(2). The flow proceeds from block 604 to block 606.

[0116] Blocks 606-610 are executed iteratively for each identified dummy device. At block 606, which serves as a decision block, it is determined whether the dummy device is configured as a capacitor-configured transistor. An example of a dummy device with a capacitor configuration is... Figure 3A The dummy device is configured as a capacitor configuration transistor 300A. In response to the dummy device not being a capacitor configuration transistor (the "No" branch of block 606), the process proceeds to block 608. In response to the dummy device being configured as a capacitor configuration transistor (the "Yes" branch of block 606), the process proceeds to block 610.

[0117] In block 608, a dummy device with a non-capacitor configuration is reconfigured to a capacitor configuration. An example of a dummy device with a non-capacitor configuration is a dummy device with a short-circuit configuration, such as... Figure 3B The short-circuit transistor 300B, etc. Figure 2B The example of converting a short-circuit transistor into a capacitor-configured transistor is discussed in the context of this paper. The flow proceeds from block 608 to block 610.

[0118] In block 610, a dummy device is connected to one or more target nodes of an active circuit, thereby reallocating the purpose of the dummy device within the cell. Therefore, block 610 is an example of the DD2CP method. Examples of connecting a dummy device to a target node include: Figure 4B The capacitor configuration transistors P71 and N71 have their gate terminals connected to the connection at node 418. Figure 4C The corresponding capacitors are configured such that the gate terminals of transistors P81 and N81 are connected to the corresponding nodes 414 and 424, etc.

[0119] Figure 6B This is a flowchart of a method 614 for manufacturing a semiconductor device according to some embodiments.

[0120] According to some embodiments, method 614 can, for example, use EDA system 800 ( Figure 8 (discussed below) and Integrated Circuit (IC) Manufacturing System 900 ( Figure 9 (This will be discussed below) to achieve this. Examples of semiconductor devices that can be manufactured according to method 614 include those with... Figure 2A , 2B Semiconductor devices 212A, 212B, 212C, 400, 402B, 402C, 402D, 402E and 402F corresponding to 2C, 4A, 4B, 4C, 4D, 4E and 4F, or semiconductor devices corresponding to the various layout diagrams disclosed herein.

[0121] exist Figure 6BIn this method, 614 includes blocks 616-618. In block 616, a layout diagram is generated, which includes one or more layout diagrams disclosed herein, for example, according to... Figure 6A The layout diagram obtained by method 600, and the corresponding Figure 2A , 2B Layout diagrams of semiconductor devices 212A, 212B, 212C, 400, 402B, 402C, 402D, 402E, and 402F, 2C, 4A, 4B, 4C, 4D, 4E, and 4F, etc. According to some embodiments, block 616 can, for example, use an EDA system 800 (… Figure 8 (This will be discussed below) to achieve this.

[0122] More specifically, block 616 includes generating a pattern corresponding to the structure in the semiconductor diagram to be represented. For example, if the generated layout corresponds to cell region 212A, block 616 includes generating a pattern corresponding to the structure to be included in cell region 212A. The flow proceeds from block 616 to block 618.

[0123] At block 618, based on the layout diagram, at least one of the following is performed: (A) one or more photolithographic exposures; or (B) fabrication of one or more semiconductor masks; or (C) fabrication of one or more components in a layer of a semiconductor device. See below for details. Figure 9 Discussion of IC manufacturing system 900 in China.

[0124] Figure 7 This is a flowchart of a method 700 for manufacturing a semiconductor device according to some embodiments.

[0125] Method 700 includes blocks 702-712. In block 702, a transistor assembly is formed. Examples of transistor assemblies include gate structures or active regions including one or more source / drain (S / D) regions. Examples of patterns in a layout drawing corresponding to such a transistor assembly include... Figure 5A The gate patterns in the diagram are 544, AR 522(1), and AR 522(2), etc. In some embodiments, forming a transistor device includes: forming a substrate (e.g., 520); forming an active region (e.g., 522(1)(1)-522(1)(3)), which includes doping a region of the substrate; forming a source / drain (S / D) region ( Figure 5G This includes doping a first region of the active region, the S / D region representing a first transistor assembly, and a second region of the active region between the corresponding S / D regions representing a channel region representing a second transistor assembly. Figure 5G ); forming a metal-to-semiconductor (MD) contact structure, the MD contact structure being above a corresponding S / D region in the S / D region, the MD contact structure representing a third transistor assembly; and forming a gate line ( Figure 5G The gate line is above the corresponding channel region in the channel region, and the gate line represents the fourth transistor assembly. Block 702 includes block 704.

[0126] In block 704, transistor assemblies are arranged to be assembled within a cell region. Examples of transistor assemblies arranged within a cell region include transistors P11-P15, P28, P61, P81, N11-N15, N28, N61, and N81, as well as transistors (not shown) arranged in interruption 530 within cell 500A, which is defined by cell boundaries 503(1)-503(4), etc. The flow exits block 702 from block 704 and proceeds to block 706.

[0127] exist Figure 7 In block 706, transistor assemblies are connected to form corresponding active transistors. Examples of connecting transistor assemblies to form corresponding active transistors include: forming with... Figures 5A-5F Gate conductors corresponding to the gate pattern, or formed with Figures 5A-5F The M_1st pattern corresponds to the M_1st segment, etc. Block 706 includes blocks 708, 710, and 712. The flow proceeds from block 706 to block 708.

[0128] In block 708, an active transistor is configured to receive data at the data input node. Examples of active transistors configured to receive data at the data input node include those connected to... Figure 4A Transistors P13 and N15, etc., in input node 406(0). The process proceeds from block 708 to block 710.

[0129] In block 710, an active transistor is configured to generate an output signal. Examples of active transistors configured to generate an output signal include those connected to... Figure 4A The output node 464 contains active transistors P28 and N28, etc. The process proceeds from block 710 to block 712.

[0130] In block 712, the terminals of the capacitor configuration transistor are connected to the target node. Examples of terminals of the capacitor configuration transistor connected to the target node include: connected to... Figure 4B The capacitor at node 418 is configured to connect to the gate terminal of each of transistors P71 and N71, or accordingly connected to... Figure 4C The capacitors at nodes 414 and 424 are configured with the gate terminals of transistors P81 and N81, etc.

[0131] Figure 8 This is a block diagram of an electronic design automation (EDA) system 800 according to some embodiments.

[0132] In some embodiments, EDA system 800 includes an APR system. According to some embodiments, EDA system 800 is used for implementation, for example. Figure 7 The flowchart 700 describes a method for generating instance-modified dummy transistor structures 500A, 500B, 500C, 500D, 500E, or 500F, or other suitable structures within the expected scope of the disclosure.

[0133] In some embodiments, the EDA system 800 is a general-purpose computing device including a hardware processor 802 and a non-transitory computer-readable storage medium 804. The storage medium 804 is encoded with (i.e., stores) computer program code 806 (i.e., a set of executable instructions). Execution of the instructions 806 by the hardware processor 802 (at least partially) represents an EDA tool, which, according to one or more embodiments, is implemented as follows: Figure 6A , 6B The method of 7 (the process and / or method described below) is a part or all of the method. Storage medium 804 is storage layout diagram 816, which includes layout diagrams of individual cells 500A, 500B, 500C, 500D, 500E and 500F, as well as other similar layout diagrams within the scope of this disclosure.

[0134] Processor 802 is electrically coupled to computer-readable storage medium 804 via bus 808. Processor 802 is also electrically coupled to I / O interface 810 via bus 808. Network interface 812 is also electrically connected to processor 802 via bus 808. Network interface 812 is connected to network 814, enabling processor 802 and computer-readable storage medium 804 to be connected to external components via network 814. Processor 802 is configured to execute computer program code 806 encoded in computer-readable storage medium 804 so that system 800 can be used to perform some or all of the described processes and / or methods. In one or more embodiments, processor 802 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0135] In one or more embodiments, the computer-readable storage medium 804 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 804 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 804 includes a compact disc read-only memory (CD-ROM), an optical disc read / write (CD-R / W), and / or a digital video optical disc (DVD).

[0136] In one or more embodiments, storage medium 804 stores computer program code 806 configured to cause system 800 (where such execution (at least partially) represents an EDA tool) to perform some or all of the described processes and / or methods. In one or more embodiments, storage medium 804 also stores information facilitating the execution of some or all of the described processes and / or methods. In one or more embodiments, storage medium 804 stores a standard cell library 820 including such standard cells as disclosed herein.

[0137] EDA system 800 includes an I / O interface 810. The I / O interface 810 is coupled to external circuitry. In one or more embodiments, the I / O interface 810 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 802.

[0138] EDA system 800 also includes a network interface 812 coupled to processor 802. Network interface 812 allows system 800 to communicate with a network 814 to which one or more other computer systems are connected. Network interface 812 includes a wireless network interface, such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the described processes and / or methods are implemented in two or more systems 800.

[0139] System 800 is configured to receive information via I / O interface 810. The information received via I / O interface 810 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 802. The information is transmitted to processor 802 via bus 808. EDA system 800 is configured to receive UI-related information via I / O interface 810. This information is stored as a user interface (UI) 818 on computer-readable medium 804.

[0140] In some embodiments, some or all of the described processes and / or methods are implemented as a standalone software application for processor execution. In some embodiments, some or all of the described processes and / or methods are implemented as a software application as part of an additional software application. In some embodiments, some or all of the described processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the described processes and / or methods is implemented as a software application as part of an EDA tool. In some embodiments, some or all of the described processes and / or methods are implemented as a software application used by an EDA system 800. In some embodiments, a layout diagram including standard cells is generated using a tool such as VIRTUOSO®, available from Cadence Design Systems, Inc., or other suitable layout generation tools.

[0141] In some embodiments, these processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage devices or memory units, such as one or more of the following: optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROM, RAM), memory cards, etc.

[0142] Figure 9 This is a block diagram of an integrated circuit (IC) manufacturing system 900 according to some embodiments and the associated IC manufacturing process.

[0143] exist Figure 6B Following block 616, based on the layout, manufacturing system 900 is used to manufacture at least one of the following: (A) one or more semiconductor masks, or (B) at least one component in the layer that forms the initial semiconductor integrated circuit. In some embodiments, in Figure 7 After block 702, based on the layout, at least one of the following is manufactured: (A) one or more semiconductor masks, or (B) at least one component in the layer that forms the initial semiconductor integrated circuit.

[0144] exist Figure 9In this IC manufacturing system 900, entities such as design room 920, mask room 930, and IC manufacturing plant / manufacturer (“fab”) 940 interact with each other in connection with the design, development, and manufacturing cycles and / or services related to the manufacture of IC devices 960. The entities in system 900 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design room 920, mask room 930, and IC manufacturing plant 940 are owned by a single, larger company. In some embodiments, two or more of design room 920, mask room 930, and IC manufacturing plant 940 coexist in public facilities and use public resources.

[0145] Design studio (or design team) 920 generates IC design layout 922. IC design layout 922 includes various geometric patterns designed for IC device 960. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute the various components of the IC device 960 to be manufactured. The various layers combine to form various IC features. For example, portions of IC design layout 922 include various IC features to be formed on a semiconductor substrate (e.g., a silicon wafer) and in various material layers disposed on the semiconductor substrate, such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads. Design studio 920 implements appropriate design procedures to form IC design layout 922. Design procedures include one or more of logic design, physical design, or placement and routing. IC design layout 922 is presented in one or more data files containing geometric pattern information. For example, IC design layout 922 is represented in GDSII file format or DFII file format.

[0146] Mask chamber 930 includes data preparation 932 and mask fabrication 934. Mask chamber 930 uses an IC design layout 922 to fabricate one or more masks for fabricating various layers of an IC device 960 according to the IC design layout 922. Mask chamber 930 performs mask data preparation 932, where the IC design layout 922 is converted into a representative data file (“RDF”). Mask data preparation 932 provides the RDF to mask fabrication 934. Mask fabrication 934 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (photomask) or semiconductor wafer. The design layout is manipulated by mask data preparation 932 to conform to the specific characteristics of the mask writer and / or the requirements of the IC fabrication plant 940. Figure 9In this embodiment, mask data preparation 932, mask manufacturing 934, and mask 945 are shown as separate elements. In some embodiments, mask data preparation 932 and mask manufacturing 934 are collectively referred to as mask data preparation.

[0147] In some embodiments, mask data preparation 932 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout 922. In some embodiments, mask data preparation 932 also includes resolution enhancement techniques (RET), such as off-axis illumination, subresolution auxiliary features, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, which treats OPC as an inverse imaging problem.

[0148] In some embodiments, mask data preparation 932 includes a mask rule checker (MRC) that uses a set of mask creation rules to check the IC design layout already processed in the OPC. This set of mask creation rules includes certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout to compensate for constraints during mask fabrication 934, and can undo some modifications performed by the OPC to satisfy the mask creation rules.

[0149] In some embodiments, mask data preparation 932 includes lithography process inspection (LPC), which simulates a process to be performed by IC fabrication plant 940 to manufacture IC device 960. The LPC simulates this process based on IC design layout 922 to manufacture a simulated manufactured device, such as IC device 960. Process parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, or combinations thereof. In some embodiments, after the simulated manufactured device is created by the LPC, if the pattern of the simulated device is insufficient to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 922.

[0150] For clarity, the above description of mask data preparation 932 has been simplified. In some embodiments, data preparation 932 includes additional features such as logic operations (LOPs) to modify the IC design layout according to manufacturing rules. Furthermore, the processes applied to IC design layout 922 during data preparation 932 can be performed in various different sequences.

[0151] After mask data preparation 932 and during mask fabrication 934, a mask 945 or a set of masks is fabricated based on a modified IC design layout. In some embodiments, an electron beam (e-beam) or multiple electron beams are used to form a pattern on the mask (photomask or photomask) based on the modified IC design layout. The mask is formed using various techniques. In some embodiments, a binary technique is used to form the mask. In some embodiments, the mask pattern includes opaque regions and transparent regions. A radiation beam (e.g., an ultraviolet (UV) beam) used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer is blocked by the opaque regions and transmits through the transparent regions. In one example, a binary mask includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque regions of the mask. In another example, a phase-shifting technique is used to form the mask. In a phase-shifting mask (PSM), various features in the pattern formed on the mask are configured to have an appropriate phase difference to improve resolution and imaging quality. In various examples, the phase-shifting mask is a decaying PSM or an alternating PSM. One or more masks generated by Mask Fabrication 934 are used in a variety of processes. For example, one or more such masks are used in ion implantation processes to form various doped regions in a semiconductor wafer, one or more such masks are used in etching processes to form various etched regions in a semiconductor wafer, and / or in other suitable processes.

[0152] IC manufacturing plant 940 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC manufacturing plant 940 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end manufacturing (front-end process (FEOL) manufacturing) of multiple IC products, a second manufacturing facility that can provide back-end manufacturing (back-end process (BEOL) manufacturing) for interconnection and packaging of IC products, and a third manufacturing facility that can provide other services to the foundry enterprise.

[0153] IC manufacturing plant 940 uses a mask (or multiple masks) manufactured by mask chamber 930 to manufacture IC device 960 using manufacturing tool 952. Therefore, IC manufacturing plant 940 uses IC design layout 922 at least indirectly to manufacture IC device 960. In some embodiments, semiconductor wafer 942 is manufactured by IC manufacturing plant 940 using a mask (or multiple masks) to form IC device 960. Semiconductor wafer 942 includes a silicon substrate or other suitable substrate having a layer of material formed thereon. Semiconductor wafer also includes one or more of various doped regions, dielectric features, multilevel interconnects, etc. (formed in subsequent manufacturing steps).

[0154] Regarding integrated circuit (IC) manufacturing systems (e.g., Figure 9 Details of the system (900) and the associated IC manufacturing process can be found in, for example, the following patent documents: U.S. Patent No. 9,256,709, granted February 9, 2016; U.S. Pre-Publication No. 20150278429, published October 1, 2015; U.S. Pre-Publication No. 20140040838, published February 6, 2014; and U.S. Patent No. 7,260,442, granted August 21, 2007, the entire contents of each of which are incorporated herein by reference.

[0155] In some embodiments, a method for generating cells in a layout diagram includes: selecting a cell from a standard cell library, wherein the components of the cell define active circuitry; identifying a dummy device within the cell that is not connected to active circuitry within the cell; and connecting the dummy device to a target node of the active circuitry.

[0156] In some embodiments, identifying a dummy device involves identifying a transistor with a short-circuit configuration (short-circuit transistor) as a dummy device. The short-circuit transistor includes a gate pattern, a first source / drain (S / D) region, and a second S / D region, which are connected together. The method further includes: modifying the short-circuit transistor into a transistor with a capacitor configuration (capacitor-configured transistor); and connecting the dummy device includes: using the capacitor-configured transistor as a dummy device. In some embodiments, modifying the short-circuit transistor includes: removing one or more first conductive segment patterns that connect the gate pattern of the short-circuit transistor to each of the first and second S / D regions of the short-circuit transistor; and generating a second conductive segment pattern that connects a data input line pattern of an active circuit to the gate pattern of the short-circuit transistor. In some embodiments, removing one or more first conductive segment patterns not only causes the gate pattern to be disconnected from each of the first S / D region and the second S / D region, but also causes the first S / D region and the second S / D region to be disconnected from each other; and modifying the short-circuit transistor further includes generating a third conductive segment pattern that connects the first S / D region and the second S / D region together. In some embodiments, modifying the dummy device is performed as part of an engineering change order.

[0157] In some embodiments, the target node is an input node of an active circuit; and connecting the dummy device further includes: connecting the dummy device in parallel with the input node of the active circuit. In some embodiments, the target node is an output node of an input transistor of an active circuit; and connecting the dummy device further includes: connecting the dummy device to the output node of the input transistor of the active circuit. In some embodiments, the target node is an output node of an active circuit; and connecting the dummy device further includes: connecting the dummy device to the output node of the active circuit. In some embodiments, the active circuit is a scan-inserted D flip-flop (SDFQ), which includes a D flip-flop (FF) and a multiplexer connected in series at an internal node of the SDFQ; the target node is an internal node of the SDFQ; and connecting the dummy device further includes: connecting the dummy device to the internal node. In some embodiments, the method further includes: identifying cells in a layout diagram with time margin violations, in some embodiments the time margin violations including hold-type time margin violations and build-up-type time margin violations; identifying and connecting the dummy device aims to reduce hold-type time margin violations; and the method further includes: modifying the frequency of the active circuit to reduce build-up-type time margin violations.

[0158] In some embodiments, a semiconductor device includes: a cell region configured as a functional circuit, the cell region including: an active transistor arranged to be mounted within a rectangular region, a first portion of the active transistor being correspondingly configured to receive data at a data input node of the cell region and to receive a clock at a timing input node of the cell region, and a second portion of the active transistor being configured to generate an output signal at an output node of the cell region; and one or more capacitor configuration transistors arranged within the rectangular region, the terminals of the one or more capacitor configuration transistors being connected to a target node of the functional circuit.

[0159] In some embodiments, the target node is a data input node of the cell area. In some embodiments, the target node is an output node of the cell area. In some embodiments, the functional circuit is a sequential logic circuit. In some embodiments, the semiconductor device is a scan-insertion D flip-flop (SDFQ), which includes a D flip-flop (FF) and a multiplexer connected in series at an internal node of the SDFQ; and the target node is the internal node of the SDFQ.

[0160] In some embodiments, a method of forming a semiconductor device includes: forming an active region, including doping a region of a substrate; forming a source / drain (S / D) region, including doping a first region of the active region, the S / D region representing a first transistor assembly, wherein a second region of the active region between corresponding S / D regions is a channel region, the channel region representing a second transistor assembly; forming metal-to-S / D (MD) contact structures, these MD contact structures being over corresponding S / D regions in the S / D region, these MD contact structures representing a third transistor assembly; forming gate lines, these gate lines being over corresponding channel regions in the channel region, these gate lines representing a fourth transistor assembly; forming the active region, forming the S / D region, forming the MD contact structures, and forming the gate lines to obtain a first set and a first crystal assemblies connected as corresponding active transistors defining functional circuitry of the first to fourth transistor assemblies. A second set of transistors, from the first set to the fourth set, is connected as one or more corresponding capacitor-configured transistors; the transistors of the first set and the second set are assembled within a cell region having a rectangular area; and metallization is formed to interconnect the active transistors and one or more capacitor-configured transistors, such that: a first portion of the active transistor is configured to receive data at the data input node of the cell region and to receive a clock at the timing input node of the cell region; a second portion of the active transistor is configured to generate an output signal at the output node of the cell region; and the terminals of the one or more capacitor-configured transistors are connected to the target node of the functional circuit.

[0161] In some embodiments, the target node is the data input node of the cell area. In some embodiments, the target node is the output node of the cell area. In some embodiments, the functional circuit is a sequential logic circuit. In some embodiments, the sequential logic circuit is a scan-insertion D flip-flop (SDFQ), which includes a D flip-flop (FF) and a multiplexer connected in series at an internal node of the SDFQ; the sequential logic circuit is a D FF; and the target node is the internal node of the SDFQ.

[0162] The following are some specific examples.

[0163] Example 1. A method for generating cells in a layout diagram, the method comprising: Select a cell from the standard cell library, wherein the components of the cell define active circuitry; Identify dummy devices within the unit, wherein the dummy devices are not connected to the active circuitry within the unit; and Connect the dummy device to the target node of the active circuit.

[0164] Example 2. According to the method described in Example 1, wherein: The dummy device is identified by identifying a short-circuit transistor as the dummy device. The short-circuit transistor is a transistor with a short-circuit configuration, including a gate pattern, a first source / drain S / D region, and a second S / D region, wherein the gate pattern, the first S / D region, and the second S / D region are connected together; and The method further includes: The short-circuit transistor is modified into a capacitor-configured transistor, which is a transistor with a capacitor configuration; and Connecting the virtual device includes: The capacitor is used to configure the transistor as the dummy device.

[0165] Example 3. The method according to Example 2, wherein modifying the short-circuit transistor includes: Remove one or more first conductive segment patterns, said one or more first conductive segment patterns connecting the gate pattern of the short-circuit transistor to each of the first S / D region and the second S / D region of the short-circuit transistor; and A second conductive segment pattern is generated, which connects the data input line pattern of the active circuit to the gate pattern of the short-circuit transistor.

[0166] Example 4. According to the method described in Example 3, wherein: Removing the one or more first conductive segment patterns not only causes the gate pattern to be disconnected from each of the first S / D region and the second S / D region, but also causes the first S / D region and the second S / D region to be disconnected from each other; and Modifying the short-circuit transistor also includes: A third conductive segment pattern is generated, which connects the first S / D region and the second S / D region together.

[0167] Example 5. The method described in Example 2, wherein the modification of the dummy device is performed as part of an engineering change order.

[0168] Example 6. According to the method described in Example 1, wherein: The target node is the input node of the active circuit; and Connecting the virtual device also includes: The dummy device is connected in parallel with the input node of the active circuit.

[0169] Example 7. According to the method described in Example 1, where: The target node is the output node of the input transistor of the active circuit; and Connecting the virtual device also includes: The dummy device is connected to the output node of the input transistor of the active circuit.

[0170] Example 8. According to the method described in Example 1, where: The target node is the output node of the active circuit; and Connecting the virtual device also includes: Connect the dummy device to the output node of the active circuit.

[0171] Example 9. According to the method described in Example 1, wherein: The active circuit is a scan-insertion D flip-flop, an SDFQ, which includes a multiplexer and a D flip-flop, and the multiplexer and the D flip-flop are connected in series at the internal nodes of the SDFQ. The target node is the internal node of the SDFQ; and Connecting the virtual device also includes: Connect the dummy device to the internal node.

[0172] Example 10. The method described in Example 1 further includes: Identify the units in the layout diagram that have time margin violations. in: The time margin violations include hold-type time margin violations and build-type time margin violations; Identifying and connecting the dummy device aims to reduce time margin violations of the hold type; and The method further includes: Modify the frequency of the active circuit to reduce the time margin violation of the setup type.

[0173] Example 11. A semiconductor device comprising: A unit area, configured as a functional circuit, includes: Active transistors, the active transistors being arranged and assembled within a rectangular region, The first portion of the active transistor is accordingly configured to receive data at the data input node of the cell region and to receive a clock at the timing input node of the cell region. The second portion of the active transistor is configured to generate an output signal at the output node of the cell region; and One or more capacitor configuration transistors are arranged within the rectangular area, and the terminals of the one or more capacitor configuration transistors are connected to the target node of the functional circuit.

[0174] Example 12. The semiconductor device according to Example 11, wherein the target node is the data input node of the cell region.

[0175] Example 13. The semiconductor device according to Example 11, wherein the target node is the output node of the cell region.

[0176] Example 14. The semiconductor device according to Example 11, wherein the functional circuit is a sequential logic circuit.

[0177] Example 15. The semiconductor device according to Example 14, wherein: The semiconductor device is a scan-insertion D flip-flop, an SDFQ, which includes a multiplexer and a D flip-flop, connected in series at an internal node of the SDFQ; and The target node is the internal node of the SDFQ.

[0178] Example 16. A method of forming a semiconductor device, the method comprising: Forming an active region includes doping a region of the substrate; Forming source / drain S / D regions, the formation including doping a first region of the active region, the S / D region representing a first transistor component, wherein a second region of the active region between the respective S / D regions is a channel region, the channel region representing a second transistor component; A metal-to-S / D contact structure is formed on a corresponding S / D region in the S / D region, and the metal-to-S / D contact structure represents a third transistor component. A gate line is formed above a corresponding channel region in the channel region, the gate line representing a fourth transistor assembly; The formation of the active region, the formation of the S / D region, the formation of the metal-to-S / D contact structure, and the formation of the gate line result in a first set of active transistors connected from the first transistor assembly to the fourth transistor assembly as corresponding active transistors defining a functional circuit, and a second set of active transistors connected from the first transistor assembly to the fourth transistor assembly as corresponding one or more capacitor configuration transistors. The transistor assemblies of the first set and the transistor assemblies of the second set are assembled within a cell region, the cell region having a rectangular area; and Metallization is formed to interconnect the active transistor and the one or more capacitors, such that: The first portion of the active transistor is configured to receive data at the data input node of the cell region and to receive a clock at the timing input node of the cell region; The second portion of the active transistor is configured to generate an output signal at the output node of the cell region; and The terminals of the one or more capacitors configured to connect to the target node of the functional circuit are connected.

[0179] Example 17. The method according to Example 16, wherein the target node is the data input node of the cell area.

[0180] Example 18. The method according to Example 16, wherein the target node is the output node of the cell region.

[0181] Example 19. The method according to Example 16, wherein the functional circuit is a sequential logic circuit.

[0182] Example 20. The method described in Example 19, wherein: The sequential logic circuit is a scan-insertion D flip-flop, an SDFQ, which includes a multiplexer and a D flip-flop, and the multiplexer and the D flip-flop are connected in series to the D flip-flop at the internal node of the SDFQ. The sequential logic circuit is the D flip-flop; and The target node is the internal node of the SDFQ. Those skilled in the art will readily recognize that one or more of the disclosed embodiments achieve one or more of the advantages described above. After reading the foregoing specification, those skilled in the art will be able to implement various variations, substitutions, and other embodiments as broadly disclosed herein. Therefore, the protection granted herein is intended to be limited only by the definitions contained in the appended claims and their equivalents.

Claims

1. A method for generating cells in a layout diagram, the method comprising: Select a cell from the standard cell library, wherein the components of the cell define active circuitry; Identify dummy devices within the unit, wherein the dummy devices are not connected to the active circuitry within the unit; and Connect the dummy device to the target node of the active circuit. in: The dummy device is identified by identifying a short-circuit transistor as the dummy device. The short-circuit transistor is a transistor with a short-circuit configuration, including a gate pattern, a first source / drain S / D region, and a second S / D region, wherein the gate pattern, the first S / D region, and the second S / D region are connected together; and The method further includes: The short-circuit transistor is modified into a capacitor-configured transistor, which is a transistor with a capacitor configuration; and Connecting the virtual device includes: The capacitor is used to configure the transistor as the dummy device.

2. The method according to claim 1, wherein, Modifying the short-circuit transistor includes: Remove one or more first conductive segment patterns, said one or more first conductive segment patterns connecting the gate pattern of the short-circuit transistor to each of the first S / D region and the second S / D region of the short-circuit transistor; and A second conductive segment pattern is generated, which connects the data input line pattern of the active circuit to the gate pattern of the short-circuit transistor.

3. The method according to claim 2, wherein: Removing the one or more first conductive segment patterns not only causes the gate pattern to be disconnected from each of the first S / D region and the second S / D region, but also causes the first S / D region and the second S / D region to be disconnected from each other; and Modifying the short-circuit transistor also includes: A third conductive segment pattern is generated, which connects the first S / D region and the second S / D region together.

4. The method according to claim 1, wherein, The modification of the dummy device was performed as part of an engineering change command.

5. The method according to claim 1, wherein: The target node is the input node of the active circuit; and Connecting the virtual device also includes: The dummy device is connected in parallel with the input node of the active circuit.

6. The method according to claim 1, wherein: The target node is the output node of the input transistor of the active circuit; and Connecting the virtual device also includes: The dummy device is connected to the output node of the input transistor of the active circuit.

7. The method according to claim 1, wherein: The target node is the output node of the active circuit; and Connecting the virtual device also includes: Connect the dummy device to the output node of the active circuit.

8. The method according to claim 1, wherein: The active circuit is a scan-insertion D flip-flop, an SDFQ, which includes a multiplexer and a D flip-flop, and the multiplexer and the D flip-flop are connected in series at the internal nodes of the SDFQ. The target node is the internal node of the SDFQ; as well as Connecting the virtual device also includes: Connect the dummy device to the internal node.

9. The method according to claim 1, further comprising: Identify the units in the layout diagram that have time margin violations. Wherein: the time margin violation includes hold-type time margin violation and establish-type time margin violation; Identifying and connecting the dummy device aims to reduce time margin violations of the hold type; and The method further includes: Modify the frequency of the active circuit to reduce the time margin violation of the setup type.

10. A semiconductor device, comprising: The unit area includes: Active transistors, the active transistors being arranged and assembled within a rectangular region, The first portion of the active transistor is accordingly configured to receive data at the data input node of the cell region and to receive a clock at the timing input node of the cell region. The second portion of the active transistor is configured to generate an output signal at the output node of the cell region; and One or more capacitor configuration transistors are arranged within the rectangular region, and the terminals of the one or more capacitor configuration transistors are connected to a target node of the cell region. The one or more capacitor configuration transistors are derived from short-circuit transistors, which are transistors with a short-circuit configuration including a gate pattern, a first source / drain S / D region, and a second S / D region, wherein the gate pattern, the first S / D region, and the second S / D region are connected together.

11. The semiconductor device according to claim 10, wherein, The target node is the data input node of the unit area.

12. The semiconductor device according to claim 10, wherein, The target node is the output node of the unit area.

13. The semiconductor device according to claim 10, wherein, The cell area is configured as a sequential logic circuit.

14. The semiconductor device according to claim 13, wherein: The semiconductor device is a scan-insertion D flip-flop, an SDFQ, which includes a multiplexer and a D flip-flop, connected in series at an internal node of the SDFQ; and The target node is the internal node of the SDFQ.

15. A method of forming a semiconductor device, the method comprising: Forming an active region includes doping a region of the substrate; Forming source / drain S / D regions, the formation including doping a first region of the active region, the S / D region representing a first transistor component, wherein a second region of the active region between the respective S / D regions is a channel region, the channel region representing a second transistor component; A metal-to-S / D contact structure is formed on a corresponding S / D region in the S / D region, and the metal-to-S / D contact structure represents a third transistor component. A gate line is formed above a corresponding channel region in the channel region, the gate line representing a fourth transistor assembly; The active region is formed, the S / D region is formed, the metal-to-S / D contact structure is formed, and the gate line is formed to obtain a first set of the first transistor assembly to the fourth transistor assembly connected as corresponding active transistors and a second set of the first transistor assembly to the fourth transistor assembly connected as corresponding one or more capacitor-configured transistors. The transistor assemblies of the first set and the transistor assemblies of the second set are assembled within a cell region, the cell region having a rectangular area; and Metallization is formed to interconnect the active transistor and the one or more capacitors, such that: The first portion of the active transistor is configured to receive data at the data input node of the cell region and to receive a clock at the timing input node of the cell region; The second portion of the active transistor is configured to generate an output signal at the output node of the cell region; and The terminals of the one or more capacitors configured to connect to the target node of the active transistor are connected.

16. The method according to claim 15, wherein, The target node is the data input node of the unit area.

17. The method according to claim 15, wherein, The target node is the output node of the unit area.

18. The method according to claim 15, wherein, The active transistor defines a sequential logic circuit.

19. The method of claim 18, wherein: The sequential logic circuit is a scan-insertion D flip-flop, SDFQ, which includes a multiplexer and a D flip-flop, and the multiplexer and the D flip-flop are connected in series to the D flip-flop at the internal node of the SDFQ. The sequential logic circuit is the D flip-flop; and The target node is the internal node of the SDFQ.

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