Integrated circuit reliability intelligence computing method and apparatus

Abstract

The application discloses a kind of integrated circuit reliability intelligent computing method and equipment, method includes the following steps: generating the failure characteristic parameter table of target integrated circuit and element basic failure rate, and store in basic element library;The failure characteristic parameter table includes the serial number of electronic component, component name, component minimum category, lower element list, upper element list;Electronic component upper and lower element list according to current direction;Using computer search algorithm to identify the failure ring in target integrated circuit diagram;According to rules, each electronic component in target integrated circuit is automatically judged by computer failure series-parallel structure, draw failure tree according to failure ring and stratification, each layer corresponds to a branch of failure tree;The failure rate of each branch of failure tree, the overall failure rate of failure tree and the reliability of target integrated circuit are calculated.The method of the application has high calculation efficiency, high calculation accuracy, and can calculate the reliability of circuit system composed of mass elements.

Description

Technical Field

[0001] This invention relates to the field of circuit testing technology, and in particular to an intelligent calculation method and device for integrated circuit reliability. Background Technology

[0002] Integrated circuits are widely used in all aspects of our daily lives, and their reliability level is directly related to people's health and property safety. Therefore, conducting high-reliability design of integrated circuits has become a general consensus in the industry. As one of the key links in reliability design, the research on reliability calculation methods for integrated circuits has been a key focus of the industry in recent years. However, with the continuous increase in circuit integration and scale, existing methods often have shortcomings in effectively balancing accuracy and speed when performing reliability calculations of circuit systems. For example, traditional minimal cut set method, minimal path set method, and state separation method can only solve the reliability calculation problem of circuit systems composed of a small number of components. When the circuit system contains tens of millions of components, traditional minimal cut set method, minimal path set method, and state separation method are all unusable.

[0003] Tianjin University has published an invention patent (publication number CN106547962A) for an integrated circuit interconnect reliability analysis method based on neural network parameter modeling. This method combines neural networks with interconnect reliability, models the input-output relationship of electromigration (EM) reliability using a neural network, trains the model using the neural network, and derives reliability results under various operating conditions after the model is established. The key technology is the combination of finite element simulation calculation and an electromigration neural network model, calculating integrated circuit interconnect reliability by continuously training the circuit interconnect reliability neural network model.

[0004] The Academy of Military Sciences of the Chinese People's Liberation Army has disclosed an invention patent (publication number CN111506962A) for a method of calculating the reliability of complex systems based on Batch Normalization (BN) and Unified Logic Graph (UGF). This method includes: analyzing the hierarchical structure of the system, establishing a multi-layered system model, numbering each level of the system from bottom to top in ascending order (level-i, where i is a natural number); using UGF to analyze level-1, using the obtained probability distribution as input to level-2, and obtaining the probability distribution of each node in level-2; using the probability distribution of each node in level-2 as the probability distribution of the root node to establish a BN-based reliability model for the complex system; and calculating the system reliability based on the BN-based reliability model. This invention's method for calculating the reliability of complex systems based on BN and UGF considers both the difficulty in describing the subsystem layer relationships (i.e., the difficulty in obtaining explicit expressions) and the large number of underlying components, thus establishing a model that can quickly obtain accurate system reliability, providing a new approach to improving the efficiency of analyzing the reliability of complex systems.

[0005] The above technical solutions all adopt the approach of finite element simulation and AI calculation of large models, which requires integrated circuit designers to complete the overall design of the design solution, and does not meet the pain point of multiple design versions and rapid iterations in the early stage of integrated circuits. Summary of the Invention

[0006] This invention provides an intelligent calculation method for integrated circuit reliability. This method has high calculation efficiency and high calculation accuracy, and can be combined with computer technology to perform reliability calculations on complex circuit systems composed of massive components.

[0007] The technical solution of the present invention is as follows:

[0008] A method for intelligent calculation of integrated circuit reliability includes the following steps:

[0009] A failure characteristic parameter table and basic failure rate of the target integrated circuit are generated and stored in the basic component library; the failure characteristic parameter table includes the serial number of the electronic component, the component name, the minimum category of the component, the list of lower-level components, and the list of upper-level components; the list of upper-level and lower-level components of the electronic component is arranged according to the current direction;

[0010] A computer search algorithm is used to identify failure loops in the target integrated circuit diagram;

[0011] According to the rules, the computer automatically determines the series and parallel failure structure of each electronic component in the target integrated circuit, draws a failure tree based on the failure loop and divides it into layers, with each layer corresponding to a branch of the failure tree.

[0012] Calculate the failure rate of each branch of the failure tree, the overall failure rate of the failure tree, and the reliability of the target integrated circuit.

[0013] The failure loop is defined as follows: after removing the capacitors from the target integrated circuit, the remaining electronic components form the main circuit of the target integrated circuit; all the branches in the main circuit and the data structure composed of the electronic components in each branch constitute the failure loop of the target integrated circuit.

[0014] The failure tree branch structure is: a path that starts from a single power source or input terminal, flows through all electronic components on a branch, and eventually returns to the single power source or output terminal.

[0015] A computer search algorithm is used to identify failure loops in the target integrated circuit diagram.

[0016] Preferably, the computer search algorithm is a depth-first search algorithm for graphs.

[0017] Preferably, identifying failure loops in the target integrated circuit includes:

[0018] (1) Read the data in the failure characteristic parameter table, starting from the power supply or input terminal, select the first component from the list of lower-level components of the power supply or input terminal as node a1, and set a1 as the target node;

[0019] (2) Continue searching for the next node a2 of a1, and then set a2 as the target node; and so on, setting a... k For the target node, the number of electronic components in the main circuit other than the power supply, input terminal, and output terminal is n, where 1≤k≤n;

[0020] (3) When a k When the next node is a power supply or output terminal, it means that a loop has been found and the loop count is 1; store the names of all electronic components corresponding to the found loop into array B1;

[0021] (4) Return to a k The parent node, and set a k The parent node is the target node; when the next node of the target node is a power supply or output terminal, it means that a loop has been found. Check if the loop is repeated; repeated loops are not counted, and the names of all electronic components corresponding to the repeated loops are not stored in the array; then search the child nodes of the target node for non-a... k Other nodes, among the child nodes of the current target node, are not 'a'. k Select the first node from the other nodes as the target node, and determine whether the next node of the target node is a power supply or an output terminal. If it is, it means that another ring has been found. Store the names of all the components corresponding to the found ring into array B2 and increment the ring count by 1. If not, no new ring has been found.

[0022] (5) Repeat steps (3) and (4) to traverse all electronic components in the graph structure and store the names of all components corresponding to the last ring into array Bm, where m is the number of failed rings in the main circuit.

[0023] The rules include:

[0024] Rule 1: Components in the same failure loop constitute a series failure;

[0025] Rule 2: If the failure of components in different failure loops has no effect on the function of other circuits, then the different failure loops constitute parallel failures; if they do have an effect, then the different failure loops constitute series failures.

[0026] Rule 3: If a component other than the power supply is in different failure loops, the failure rate of that component needs to be calculated multiple times within different branches; for the power supply in a branch, the same power supply only participates in the branch failure rate calculation once.

[0027] Based on rules 1, 2, and 3, the failure series and parallel structures of the target integrated circuit are obtained; each layer corresponds to a branch of the failure tree in the target integrated circuit, and the failure rate of each branch, the failure rate of the failure tree, and the reliability of the target integrated circuit system are calculated.

[0028] Calculate the failure rate of each branch according to Formula 1:

[0029]

[0030] In the formula, λ ！ Let J be the failure rate of the j-th component within the i-th branch. FIT j Let FIT be the fundamental failure rate of the j-th component. j Calculated according to similar standards such as GB / T 37963-2019; m is the number of internal components of the i-th branch;

[0031] The failure rate of the failure tree is calculated according to Formula 2 and used as the failure rate of the target integrated circuit system:

[0032]

[0033] In the formula, λ is the failure rate of the system, λ i Let n be the series failure rate of the i-th branch of the failure tree in the circuit, and n be the number of branches in the failure tree in the circuit.

[0034] The reliability R of the target integrated circuit system is calculated according to Formula 3:

[0035] R = e -λt Formula 3;

[0036] In the formula, λ is the failure rate of the failure tree; t is the usage duration, which is a value set by the user.

[0037] The present invention also provides an intelligent computing device for integrated circuit reliability, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the above-described intelligent computing method for integrated circuit reliability.

[0038] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0039] The method of this invention solves the problem that existing circuit diagrams can only reflect the functional combination between different components in a circuit, but cannot reflect the failure characteristics and failure chain features of circuit components. Compared with the traditional minimum cut set method, minimum path set method, and state separation method, the method of this invention has high computational efficiency, high computational accuracy, and can perform reliability calculations on circuit systems composed of massive numbers of components. Attached Figure Description

[0040] Figure 1 A flowchart illustrating the intelligent calculation method for integrated circuit reliability;

[0041] Figure 2 This is a schematic diagram of the circuit structure;

[0042] Figure 3 This is a circuit diagram of the circuit system in the embodiment. Detailed Implementation

[0043] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be noted that the embodiments described below are intended to facilitate the understanding of the present invention and do not limit it in any way.

[0044] Terminology Explanation:

[0045] The failure loop includes: the main circuit of the target integrated circuit consisting of the capacitors removed from the target integrated circuit and other electronic components; the data structure consisting of all branches in the main circuit and the electronic components in each branch constitutes the failure loop structure of the target integrated circuit.

[0046] A failure tree branch refers to the path that starts from a single power source or input terminal, flows through all electronic components on a branch, and eventually returns to the single power source or output terminal.

[0047] The intelligent calculation method for integrated circuit reliability of this invention first calculates the failure rate of a subsystem, and then calculates the reliability of the system based on the subsystem failure rate. Specifically, this involves: calculating the failure rate of each component in the integrated circuit diagram; converting the circuit diagram into a failure loop, where each node in the failure loop corresponds to a component on the circuit diagram; determining all branches of the failure tree according to rules, and calculating the branch failure rate through logical operations of the failure tree; and finally calculating the reliability of the integrated circuit. The overall process is as follows: Figure 1 As shown. The specific implementation steps are as follows:

[0048] Step 1: Data Preparation

[0049] Fill in the failure characteristic parameter table with data, as shown in Table 1. When filling in the data, follow the current direction of transistors and diodes, and for other electronic components, follow the current flow from the positive to the negative terminal of the power supply or from the input terminal to the output terminal. In Table 1, the serial number, component name, minimum component category, list of subordinate components, and list of superior components are all required fields. The remarks are optional fields. If there is more than one component in the list of superior components or subordinate components in Table 1, separate the component names with semicolons, for example, "R1; R2; R3". After filling in the data, save and rename it, and then import the failure characteristic parameter table. Save the imported failure characteristic parameter table data to the basic component library.

[0050] Table 1 Failure Characteristic Parameters

[0051]

[0052] The minimum component category is the name of the smallest category of components as defined in GB / T 37963-2019. The list of subordinate components refers to the names of components in one or more branches through which the current flowing through a certain component will flow next, in the specific format of "component xxx; component xxx; component xxx;...".

[0053] The basic failure rate of each component in the circuit system was calculated according to similar standards such as GB / T 37963-2019, as shown in Table 2.

[0054] Table 2

[0055]

[0056] The industry typically uses FIT (Failure Intake) as the failure representation method. 1 FIT refers to one unit of product within 1×10⁻⁶ hours. 9 One failure (or malfunction) occurred within an hour.

[0057] The conversion relationship between FIT and failure rate λ is:

[0058]

[0059] Step 2: Failure Loop Generation

[0060] Loop identification involves searching for loops across the entire circuit diagram structure. This is done by traversing all components in the diagram, counting the number of traversals as the total number of components in the main circuit. Computer search algorithms, such as the "depth-first search algorithm," are employed. The corresponding loop-finding logic is as follows:

[0061] 1) Starting from the single power supply or input terminal, read data from the basic component library obtained in the first step, select the first component from the power supply's lower-level component list as node a1, and then set a1 as the target node;

[0062] 2) Continue searching for the next node a2 of a1, and then set a2 as the target node; and so on, setting a... k For the target node, the number of components in the main circuit other than the power supply, input terminal, and output terminal is n, where 1≤k≤n;

[0063] 3) When a k When the next node is a power supply or output terminal, it indicates that a loop has been found, and the loop count is 1. Store the names of all components corresponding to the found loop into array B1;

[0064] 4) Return to a k The parent node, and set a k The parent node is the target node. When the next node of the target node is a power supply or output terminal, it means that a loop has been found. Check if the loop is repeated. Repeated loops are not counted, and the names of all components corresponding to the repeated loops are not stored in array Bm. Then search the child nodes of the target node for non-a k Other nodes, among the child nodes of the current target node, are not 'a'. k Select the first node from the other nodes as the target node. Determine if the next node of the target node is a power supply or output terminal. If so, it means another loop has been found. Store the names of all components corresponding to the found loop into array B2 and increment the loop count by 1. Otherwise, no new loop has been found. Repeat steps 3) and 4) to store the names of all components corresponding to the last loop into array Bm, where m is the number of loops in the main circuit.

[0065] Step 3: Rules for generating the failure tree

[0066] Rule 1: Components in the same failure loop constitute a series failure;

[0067] Rule 2: If the failure of components in different failure loops has no effect on the function of other circuits, then the different failure loops constitute parallel failures; if they do have an effect, then the different failure loops constitute series failures.

[0068] Rule 3: If a component other than the power supply is in different failure loops, the failure rate of that component needs to be calculated multiple times within different branches; for the power supply in a branch, the same power supply only participates in the branch failure rate calculation once.

[0069] Step 4: Establish the failure tree branch structure

[0070] Based on rules 1, 2, and 3 defined in step 3, the failure series-parallel structure of the entire circuit is re-obtained; each layer corresponds to a branch of the failure tree in the circuit, and the failure rate of each branch, the failure rate of the failure tree, and the reliability of the system are calculated.

[0071] The failure rate of each branch is calculated using Formula 1:

[0072]

[0073] In the formula, λ ！ Let J be the failure rate of the j-th component within the i-th branch. FIT j Let FIT be the fundamental failure rate of the j-th component. j Calculated according to similar standards such as GB / T 37963-2019; m is the number of internal components of the i-th branch.

[0074] The failure rate of the failure tree calculated according to Formula 2 is taken as the failure rate of the entire circuit system.

[0075]

[0076] In the formula, λ is the failure rate of the system, λ i Let be the series failure rate of the i-th branch of the failure tree in the circuit, and n be the number of branches in the failure tree in the circuit.

[0077] The reliability R of the target integrated circuit system is calculated according to Formula 3:

[0078] R = e -λ) Formula 3;

[0079] In the formula, λ is the failure rate of the failure tree; t is the usage duration, which is a value set by the user.

[0080] Example 1 Identification Figure 3 Circuit failure structure

[0081] 1.1 Circuit Description:

[0082] Figure 3It includes one power supply, resistors R1, R2, R3, R4, and R5, one capacitor C1, two transistors VT1 and VT2, and one diode VD. R1, R3, and R4 are all connected in series to the positive terminal of the power supply. R4 is connected in series with VD. VD is connected in series with the collector of VT2. The emitter of VT2 is connected in series with the negative terminal of the power supply. R3 is connected in series with the collector of VT1. The emitter of VT1 is connected in series with R2 and R5 respectively. R2 is connected in series with the negative terminal of the power supply. R5 is connected in series with the gate of VT2. R1 is connected in series with the gate of VT1. R1 is connected in series with C1.

[0083] 1.2. Calculating system reliability using the intelligent calculation method for integrated circuit reliability of this invention.

[0084] Step 1: Calculation Figure 3 The failure characteristic parameters are shown in Table 3.

[0085] Table 3

[0086]

[0087] The minimum component category refers to the smallest classification name of the component according to the latest national standard for electronic components. The list of subordinate components refers to the names of components in one or more branches through which the current flowing through a component will next pass, arranged in the specific format "Component xxx; Component xxx; Component xxx;...". The basic failure rate of each component in the circuit system is calculated according to similar standards such as GB / T 37963-2019, as shown in Table 4:

[0088] Table 4

[0089]

[0090]

[0091] Step 2: In Figure 3 In the main circuit diagram, based on the loop-finding logic, locate the failure loop on the complete circuit diagram:

[0092] 1) Starting with the single power source, read the data from the basic component library list obtained in the first step, select the first component R1 from the power source's lower-level component list, and set R1 as the target node;

[0093] 2) Continue searching for the next node VT1 of R1, and set VT1 as the target node; continue searching for the next node R2 of VT1, and set R2 as the target node. The next node of R2 is the power supply; at this time, the current just flows through a closed loop "power supply-R1-VT1-R2-power supply", this closed loop is the loop, and the loop count is 1; store the names of all the components R1, VT1, and R2 corresponding to the found loop into array B1;

[0094] 3) Return to the parent node VT1 of R2 and set VT1 as the target node. Search for other nodes that are not R2 among the lower-level nodes of the target node VT1. Select the first node R5 among the lower-level nodes of the current target node that is not R2 as the target node. Continue to find the next node VT2 of R5 and set VT2 as the target node. The next node of VT2 is the power supply, which means that another loop "power supply-R1-VT1-R5-VT2-power supply" has been found, and the loop count is 2. Store the names of all components R1, VT1, R5, and VT2 corresponding to the found loop into array B2.

[0095] 4) Return to the parent node R5 of VT2 and set R5 as the target node. At this point, no other nodes other than VT2 are found among the lower-level nodes of the target node R5. Continue to return to the parent node VT1 of R5. At this point, other nodes other than R5 are found among the lower-level nodes of the target node R5, such as R2. Set R2 as the target node. The next node of R2 is the power supply. At this point, a duplicate cycle "power supply-R1-VT1-R2-power supply" is found, but it is not saved.

[0096] 5) Return to the parent node R1 of VT1. At this time, no other nodes other than VT1 are found among the lower nodes of the target node R1. The parent node of R1 is the power supply. At this time, all components with R1 as the main branch have been searched.

[0097] 6) Select the second component R3 from the list of lower-level components of the power supply, and then set R3 as the target node;

[0098] 7) Continue searching for the next node VT1 of R3, and set VT1 as the target node; continue searching for the next node R2 of VT1, and set R2 as the target node. The next node of R2 is the power supply; at this time, the current flows through a closed loop "power supply-R3-VT1-R2-power supply", and the loop count is 3; store the names of all the corresponding components R3, VT1, and R2 in the found loop into array B3;

[0099] 8) Return to the parent node VT1 of R2 and set VT1 as the target node. Search for other nodes that are not R2 among the lower nodes of the target node VT1. Select the first node R5 among the lower nodes of the current target node that are not R2 as the target node. Continue to find the next node VT2 of R5 and set VT2 as the target node. The next node of VT2 is the power supply, which means that another loop "power supply-R3-VT1-R5-VT2-power supply" has been found. The loop count is 4. Store the names of all components R3, VT1, R5, and VT2 corresponding to the found loop into array B4.

[0100] 9) Return to the parent node R5 of VT2 and set R5 as the target node. At this point, no other non-VT2 nodes are found among the lower-level nodes of the target node R5. Continue to return to the parent node VT1 of R5. At this point, R2 is found among the lower-level nodes of the target node R5. Set R2 as the target node. The next node of R2 is the power supply. At this point, a duplicate cycle "power supply-R3-VT1-R2-power supply" is found, but it is not saved.

[0101] 10) Return to the parent node R3 of VT1. At this time, no other nodes other than VT1 are found among the lower nodes of the target node R3. The parent node of R3 is the power supply. At this time, all components with R3 as the main branch have been searched.

[0102] 11) Select the third component R4 from the list of lower-level components of the power supply, and then set R4 as the target node;

[0103] 12) Continue searching for the next node VD of R4. At this time, set VD as the target node; search for the next node VT2 of VD. The next node of VT2 is the power supply, which means that another loop "power supply-R4-VD-VT2-power supply" has been found. The loop count is 5; store the names of all components R4, VD and VT2 in the found loop into array B5.

[0104] 13) Return to the parent node VD of VT2 and set the parent node VD of VT2 as the target node. At this time, no other nodes other than VT2 are found among the lower nodes of the target node VD.

[0105] That's all Figure 3 After searching the three main branches, we obtained... Figure 3 There are a total of 5 failure loops:

[0106] Ring 1: Power supply - R1 - VT1 - R2 - Power supply;

[0107] Ring 2: Power supply - R1 - VT1 - R5 - VT2 - Power supply;

[0108] Ring 3: Power supply - R3 - VT1 - R2 - Power supply;

[0109] Ring 4: Power supply - R3 - VT1 - R5 - VT2 - Power supply;

[0110] Ring 5: Power supply - R4 - VD - VT2 - Power supply.

[0111] Step 3: Rules for generating the failure tree

[0112] Rule 1: Components in the same failure loop constitute a series failure;

[0113] Rule 2: If the failure of components in different failure loops has no effect on the function of other circuits, then the different failure loops constitute parallel failures; if they do have an effect, then the different failure loops constitute series failures.

[0114] Rule 3: If a component other than the power supply is in different failure loops, the failure rate of that component needs to be calculated multiple times within different branches; for the power supply in a branch, the same power supply only participates in the branch failure rate calculation once.

[0115] Step 4: Establish a hierarchical failure tree model

[0116] Based on rules 1, 2, and 3 defined in step 3, the failure series-parallel structure of the entire circuit can be obtained. The failure tree is drawn and layered, with each layer corresponding to a branch of the failure tree in the circuit. The failure rate of each branch, the failure rate of the failure tree, and the reliability of the system are calculated.

[0117] Figure 3 R1, R3, and R4 are connected in series with the power supply. R1 has a node in ring 2 ("Power Supply-R1-VT1-R5-VT2-Power Supply") that is not a downstream node of the power supply. R3 has a node in ring 4 ("Power Supply-R3-VT1-R5-VT2-Power Supply") that is not a downstream node of the power supply. R4 has a node in ring 5 ("Power Supply-R4-VD-VT2-Power Supply") that is not a downstream node of the power supply. According to rule 2, disconnecting any one of R1, R3, or R4 will affect the main circuit. Therefore, rings 2, 4, and 5 containing R1, R3, and R4 constitute a series failure. Branch 1 is formed: Power Supply-R3-R1-VT1-R5-R4-VT2-Power Supply.

[0118] According to rule 2, VT1 in ring 1 and ring 3 is in series with its parent nodes R1 and R3, and R1 and R3 are also in series. The emitter of VT1 is in series with R2 and connected to the power supply, forming a complete loop that does not affect other loops. Therefore, in the failure tree, R1, R3, and VT1 are on the same branch, forming branch 2: power supply - R3 - R1 - VT1 - R2 - power supply.

[0119] According to rule 3, the circuit continues to operate normally after C1 is disconnected. C1 is connected in parallel with other circuits, and C1 is on a separate branch, forming branch 3: power supply - R1 - C1 - power supply.

[0120] According to rule 2, the failure tree hierarchical structure is obtained: branch 1, branch 2 and branch 3 are connected in parallel.

[0121] Branch 1: Power supply - R3 - R1 - VT1 - R5 - R4 - VD - VT2 - Power supply;

[0122] Branch 2: Power supply - R3 - R1 - VT1 - R2 - Power supply;

[0123] Branch 3: Power supply - R1 - C1 - Power supply.

[0124] Calculate the failure rate of each branch according to Formula 1, and calculate the failure rate of the entire failure tree according to Formula 2.

[0125]

[0126] Where, λ ！ Let J be the failure rate of the j-th component within the i-th branch. FIT j Let FIT be the fundamental failure rate of the j-th component. j Calculated according to similar standards such as GB / T 37963-2019; m is the number of components inside the i-th branch. For the power supply in the branch, if the power supply belongs to the same power supply, it will only participate in the branch failure rate calculation once.

[0127]

[0128] Where λ is the system failure rate; n is the number of branches in the failure tree of the circuit; λ i Let be the failure rate of the i-th branch in the failure tree of the circuit.

[0129] The specific results are shown in Table 5. The failure rate λ of the integrated circuit failure tree is equal to 1.62 × 10⁻⁶. -6 .

[0130] Table 5

[0131]

[0132] According to Formula 3, the reliability R of the integrated circuit is calculated. The user inputs the usage time t, for example, 8000 hours. At this time, the reliability of the entire circuit system is calculated to be 98.71%.

[0133] R = e -λt Formula 3;

[0134] In the formula, λ is the failure rate of the failure tree, and t is the usage time.

[0135] The embodiments described above provide a detailed explanation of the technical solutions and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, additions, and equivalent substitutions made within the scope of the principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for intelligent calculation of integrated circuit reliability, characterized in that, Includes the following steps: A failure characteristic parameter table and a basic failure rate of the target integrated circuit are generated and stored in a basic component library; the failure characteristic parameter table includes the serial number of the electronic component, the component name, the minimum category of the component, the list of lower-level components, and the list of higher-level components; The list of upper and lower level components of electronic components is arranged according to the direction of current. Computer search algorithms are used to identify failure loops in target integrated circuit diagrams, including: (1) Read the data in the failure characteristic parameter table, starting from the power supply or input terminal, and select the first component from the list of subordinate components of the power supply or input terminal as the node. a 1. Settings a 1 represents the target node; (2) Continue searching a The next node of 1 a 2. At this point, set a 2 is the target node; and so on, setting... a k For the target node, the number of electronic components in the main circuit other than the power supply, input terminal, and output terminal is n, where 1≤k≤n; (3) When a k When the next node is a power supply or output terminal, it means that a loop has been found and the loop count is 1; store the names of all electronic components corresponding to the found loop into array B1; (4) Return a k The parent node, and set a k The parent node is the target node; when the next node of the target node is a power supply or output terminal, it means that a loop has been found. Check if the loop is repeated; repeated loops are not counted, and the names of all electronic components corresponding to the repeated loops are not stored in the array; then search the child nodes of the target node for non-repeating elements. a k Other nodes, in the lower-level nodes of the current target node, are not... a k Select the first node from the other nodes as the target node, and determine whether the next node of the target node is a power supply or an output terminal. If it is, it means that another ring has been found. Store the names of all the components corresponding to the found ring into array B2 and increment the ring count by 1. If not, no new ring has been found. (5) Repeat steps (3) and (4) to traverse all electronic components in the graph structure and store the names of all components corresponding to the last ring into array Bm, where m is the number of failed rings in the main circuit. The failure loop is defined as follows: after removing the capacitors from the target integrated circuit, the remaining electronic components form the main circuit of the target integrated circuit. All branches in the main circuit and the data structure composed of the electronic components in each branch constitute the failure loop of the target integrated circuit. According to the rules, the computer automatically determines the series and parallel failure structures of each electronic component in the target integrated circuit, draws a failure tree based on the failure loops, and divides it into layers, with each layer corresponding to a branch of the failure tree; the rules include: Rule 1: Components in the same failure loop constitute a series failure; Rule 2: If the failure of components in different failure loops has no effect on the function of other circuits, then the different failure loops constitute parallel failures; if they do have an effect, then the different failure loops constitute series failures. Rule 3: If a component other than the power supply is in different failure loops, the failure rate of that component needs to be calculated multiple times within different branches; for the power supply in a branch, the same power supply only participates in the branch failure rate calculation once. Calculate the failure rate of each branch of the failure tree, the overall failure rate of the failure tree, and the reliability of the target integrated circuit; Calculate the failure rate of each branch according to Formula 1: Official 1; In the formula, For the first i Internal branch road j individual component failure rate = , FIT j For the first j The basic failure rate (FIT) of individual components FIT j Calculated according to GB / T 37963-2019; m is the number of... i The number of internal components of each branch; The overall failure rate of the failure tree is calculated according to Formula 2 and used as the failure rate of the target integrated circuit system: Official 2; In the formula, λ The failure rate of the system, λ i The first fault in the circuit's failure tree i Series failure rate of branch circuits n This represents the number of branches in the failure tree of the circuit.

2. The intelligent calculation method for integrated circuit reliability according to claim 1, characterized in that, The computer search algorithm described is a depth-first search algorithm for graphs.

3. The intelligent calculation method for integrated circuit reliability according to claim 1, characterized in that, The reliability of the target integrated circuit system is calculated according to Formula 3. R : Official 3; In the formula, λ The failure rate of the failure tree; t The usage duration is a value set by the user.

4. An intelligent computing device for integrated circuit reliability, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the intelligent calculation method for integrated circuit reliability as described in any one of claims 1-3.

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