Memory device

Abstract

The present application provides a memory device, including a memory cell array, a data access circuit, a data bus inversion calculator, a multi-tasker and an output result judging circuit. The data access circuit performs a data write operation or a data read operation on the memory cell array. The data read operation is performed by the memory cell array to read out read data. The data bus inversion calculator is used to generate inversion indication data according to the read data. The multi-tasker outputs the inversion indication data or test data according to a mode signal. The output result judging circuit operates the read data with the inversion indication data or the test data to generate output information.

Description

Technical Field

[0001] This invention relates to a memory device, and more particularly to a memory device with a built-in self-test (BIST) function. Background Technology

[0002] In memory devices, a Data Bus Inversion (DBI) mechanism is often implemented to reduce the need for data to undergo state transitions on the bus, thereby reducing power consumption and noise on the bus. On the other hand, a built-in self-test function is also a necessary requirement in memory devices.

[0003] Under the aforementioned conditions, known memory devices require hardware circuitry for data reversal to accommodate data bus reversal mechanisms, as well as related circuitry for error detection in the built-in self-test function. Consequently, a certain number of circuits are needed along the data read path in known memory devices. Besides consuming circuit layout area, this also consumes excess power and generates excessive load on the data read path, reducing the data read efficiency of the memory device. Summary of the Invention

[0004] This invention relates to a memory device that simplifies the circuitry required for a built-in self-test function.

[0005] According to an embodiment of the present invention, a memory device includes a memory cell array, a data access circuit, a data bus inversion calculator, a multiplexer, and an output result determination circuit. The data access circuit is coupled to the memory cell array and performs data write or read operations on the memory cell array. The data read operation involves reading data from the memory cell array. The data bus inversion calculator is coupled to the data access circuit and receives the read data to generate inversion indication data. The multiplexer receives the inversion indication data and test data, and outputs inversion indication data or test data according to a mode signal. The output result determination circuit is coupled to the multiplexer and performs calculations on the read data and the inversion indication data or test data to generate output information.

[0006] Based on the above, the memory device of the present invention outputs inverted instruction data or test data to the output result determination circuit in different operating modes via a multiplexer. The output result determination circuit can generate the final read data or error bit information corresponding to different operating modes. In this way, the memory device of the present invention does not need to set up redundant determination circuits for test results for the built-in self-test function, effectively reducing the load on the write path in the memory device and reducing the area required for circuit layout. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of a memory device according to an embodiment of the present invention;

[0008] Figure 2 This is a block diagram of a memory device according to another embodiment of the present invention;

[0009] Figure 3 This is a schematic diagram illustrating an implementation of the output result determination circuit in a memory device according to an embodiment of the present invention.

[0010] Figure 4 This is a schematic diagram illustrating an embodiment of the data access circuit in a memory device according to an embodiment of the present invention.

[0011] Explanation of icon numbers

[0012] 100, 200: Memory devices

[0013] 110, 210: Data Convergence Reversal Calculator

[0014] 120, 220: Multitasking

[0015] 130, 230, 300: Output result judgment circuit

[0016] 140, 240, 400: Data access circuits

[0017] 150, 250: Memory cell array

[0018] 2100: Data Output Block

[0019] 280: Data Input Block

[0020] 290: Test Data Buffer

[0021] 410: Sensing Amplifier

[0022] 420: Write data buffer

[0023] DBI: Reversal Indicator Data

[0024] EBI: Error Bit Information

[0025] EBI[1]~EBI[N], ODATA[1]~ODATA[N], TDATA[1]~TDATA[N], RDATA[1]~RDATA[N]: bit

[0026] EID: External Input Data

[0027] MD: Mode signal

[0028] ODATA: Final read data

[0029] RDATA: Read data

[0030] TDATA: Test Data

[0031] WDATA: Write data

[0032] XNOR1~XNORN: XOR NOT gate Detailed Implementation

[0033] Please refer to Figure 1 The memory device 100 includes a data bus inversion calculator 110, a multiplexer 120, an output result determination circuit 130, a data access circuit 140, and a memory cell array 150. The data access circuit 140 is coupled to the memory cell array 150. The data access circuit 140 is used to perform a data write operation on the memory cell array 150 according to the write data WDATA. Alternatively, the data access circuit 140 can perform a data read operation on the memory cell array 150 to obtain read data RDATA.

[0034] In detail, when performing a data write operation, the data access circuit 140 can generate write data WDATA based on test data TDATA or external input data EID, and write the write data WDATA to one or more selected memory cells in the memory cell array 150. Specifically, in normal mode, the data access circuit 140 selects external input data EID to perform the data write operation. In test mode, the data access circuit 140 selects test data TDATA to perform the data write operation.

[0035] Furthermore, when performing a data readout operation, the data access circuit 140 can obtain the readout data RDATA by sensing the signal of the bit line of one or more selected memory cells in the memory cell array 150.

[0036] The data bus inversion calculator 110 is coupled to the data access circuit 140. In normal mode, when performing a data read operation, the data bus inversion calculator 110 receives read data RDATA and calculates the number of bits in the read data RDATA that have a first logic value. When the number of bits in the read data RDATA that have a first logic value is greater than a preset reference value, the data bus inversion calculator 110 generates an enable inversion indication data DBI. The first logic value can be either logic 0 or logic 1. The preset reference value can be half the total number of bits in the read data RDATA.

[0037] Multiplexer 120 is coupled between data bus inversion calculator 110 and output result judgment circuit 130. Multiplexer 120 can receive test data TDATA and inversion indication data DBI generated by data bus inversion calculator 110. Multiplexer 120 can output inversion indication data DBI or test data TDATA to output result judgment circuit 130 according to mode signal MD. When mode signal MD indicates that memory device 100 is operating in normal mode, multiplexer 120 can output inversion indication data DBI to output result judgment circuit 130. Conversely, when mode signal MD indicates that memory device 100 is operating in test mode, multiplexer 120 can output test data TDATA to output result judgment circuit 130.

[0038] The output result judgment circuit 130 is further coupled to the data access circuit 140. The output result judgment circuit 130 receives the inverted indicator data DBI or test data TDATA provided by the multiplexer 120, and receives the read data RDATA provided by the data access circuit 140. The output result judgment circuit 130 is used to perform an operation between the read data RDATA and the inverted indicator data DBI, or to perform an operation between the read data RDATA and the test data TDATA, and to generate output information. Specifically, in normal mode, the output result judgment circuit 130 performs an XOR operation between the read data RDATA and the inverted indicator data DBI, and generates output information as the final read data ODATA. In test mode, the output result judgment circuit 130 performs an XOR operation between the read data RDATA and the test data TDATA, and generates output information as error bit information EBI.

[0039] In terms of the overall operation details of the memory device 100, in normal mode, when performing a data write operation, the data access circuit 140 generates write data WDATA based on the received external input data EID and writes the write data WDATA into the memory cell array 150. Note that the data access circuit 140 can pre-determine multiple bits of the external input data EID and generate the write data WDATA accordingly. For example, when the external input data EID has more bits of logic 1 than bits of logic 0, the data access circuit 140 can invert the external input data EID to generate the write data WDATA. Conversely, when the external input data EID has no more bits of logic 1 than bits of logic 0, the data access circuit 140 can make the external input data EID equal to the write data WDATA. This operation is called the Data Bus Inversion (DBI) mechanism, used to improve the data write efficiency of the memory and reduce power consumption.

[0040] During normal mode data readout, data access circuit 140 reads readout data RDATA from memory cell array 150. Readout data RDATA is then transmitted to data bus inversion calculator 110. Data bus inversion calculator 110 generates inversion indication data DBI corresponding to the readout data RDATA.

[0041] Next, in normal mode, the read data RDATA and the corresponding inverted indicator data DBI can be transmitted to the output result determination circuit 130. The output result determination circuit 130 can generate the final read data ODATA based on the applied XOR NOT operation. Continuing the above example, when the inverted indicator data DBI is a logic value of 0, it indicates that there are more bits with logic values ​​of 0 in the read data RDATA, and it needs to be inverted. Therefore, the output result determination circuit 130 can perform an XOR NOT operation between the inverted indicator data DBI and the read data RDATA, and invert the read data RDATA to generate the final read data ODATA.

[0042] On the other hand, in test mode, when performing a data write operation, the data access circuit 140 generates write data WDATA based on the received test data TDATA and writes the write data WDATA into the memory cell array 150. During the data read operation, the data access circuit 140 reads the read data RDATA from the memory cell array 150. The read data RDATA is transmitted to the output result judgment circuit 130. At this time, the data bus inversion calculator 110 stops operating. The multiplexer 120 transmits the test data TDATA to the output result judgment circuit 130 according to the mode signal MD.

[0043] The output result judgment circuit 130 compares the test data TDATA and the read data RDATA to generate a test result and determine the error bit information EBI in the read data RDATA. Note that the output result judgment circuit 130 can also use XOR operations to compare the test data TDATA and the read data RDATA. The user only needs to reverse the interpretation of the error bit information EBI to determine which bits in the read data RDATA are error bits.

[0044] As explained above, the output result judgment circuit 130 uses the same XOR NOT operation to generate the final read data ODATA or error bit information EBI, regardless of whether it is in normal mode or test mode. In other words, the output result judgment circuit 130 does not require different hardware circuits for normal mode and test mode, effectively reducing the hardware requirements on the data read path in the memory device 100, thus reducing the load on the data read path and improving the data access efficiency of the memory device 100.

[0045] Please refer to Figure 2 The memory device 200 includes a data bus inversion calculator 210, a multiplexer 220, an output result judgment circuit 230, a data access circuit 240, a memory cell array 250, a data input block 280, a data output block 2100, and a test data buffer 290. The data input block 280 is coupled to the data access circuit 240 via a data write path 260 and is used to provide external input data EID. The output result judgment circuit 230 is coupled to the data output block 2100 via a data read path 270. The data output block 2100 is used to output the final read data ODATA or error bit information EBI. The test data buffer 290 is coupled to the data write path 260 and the multiplexer 220 and is used to provide test data TDATA.

[0046] In this embodiment, the test data buffer 290 is used to store the test data TDATA related to performing the Built-In Self-Test (BIST) operation. When the BIST mode is activated, the test data TDATA is provided to the memory cell array 250 to perform test operations on the memory cell array 250 and its surrounding circuitry.

[0047] The operational details of the data confluence inversion calculator 210, the multitasking unit 220, the output result judgment circuit 230, and the data access circuit 240 have been described in detail in the foregoing embodiments, and will not be repeated here.

[0048] Regarding the hardware architecture, the memory cell array 250 can be a memory cell array of dynamic random access memory. The data bus inversion calculator 210 can be implemented using digital circuitry, without a specific circuit structure. The data input block 280 and the data output block 2100 may include one or more buffers and switches, and can be implemented using input interface circuitry known to those skilled in the art. The multiplexer 220 can be implemented using multiplexer circuitry known to those skilled in the art, without specific limitations.

[0049] For the hardware architecture of the output result judgment circuit 230 and the data access circuit 240, please refer to the following. Figure 3 as well as Figure 4 An implementation example.

[0050] Please refer to Figure 3The output result judgment circuit 300 includes multiple XNOR gates XNOR1 to XNORN. The first terminals of XNOR gates XNOR1 to XNORN respectively receive multiple bits RDATA[1] to RDATA[N] of the read data, and the second terminals of XNOR gates XNOR1 to XNORN respectively receive multiple bits TDATA[1] to TDATA[N] of the test data or multiple bits DBI[1] to DBI[N] of the inverted indicator data. XNOR gates XNOR1 to XNORN respectively generate multiple bits EBI[1] to EBI[N] of the error bit information, or generate multiple bits ODATA[1] to ODATA[N] of the final read data.

[0051] Please refer to Figure 4 The data access circuit 400 includes a sense amplifier 410 and a write data buffer 420. The sense amplifier 410 can receive external input data EID and convert the external input data EID into write data WDATA. The write data WDATA can be temporarily stored in the write data buffer 420 and provided to the memory cell array by the write data buffer 420 for data writing.

[0052] The sensing amplifier 410 can also sense the bit line signal BLS on the memory cell array to obtain read data RDATA.

[0053] In this embodiment, the sensing amplifier 410 can be implemented using any form of sensing amplifier circuit known to those skilled in the art, without any fixed limitations. The data buffer 420 can be a page buffer commonly used in memory devices, similarly without specific limitations.

[0054] In summary, the output result judgment circuit in the memory device of the present invention uses the same hardware circuitry to perform data bit inversion and testing operations in different modes. In this way, the number of circuits on the data output path of the memory device of the present invention can be reduced, and the load on the data output path is also reduced accordingly, thereby improving the efficiency of data readout operations of the memory device.

[0055] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory device, characterized in that, include: Storage cell array; A data access circuit, coupled to the storage cell array, performs a data write operation or a data read operation on the storage cell array, wherein the data read operation involves reading data from the storage cell array. A data conduit inversion calculator, coupled to the data access circuit, is used to receive the readout data and generate inversion indication data based on the readout data; The multitasking unit receives the inversion indication data and test data, and outputs the inversion indication data in normal mode and the test data in test mode according to the mode signal. as well as The output result judgment circuit, coupled to the multiplexer, performs operations on the read data and the inverted indicator data in the normal mode to generate output information, and performs operations on the read data and the test data in the test mode to generate the output information.

2. The memory device according to claim 1, characterized in that, When the memory device is operating in the test mode, the multiplexer selects to output the test data to the output result judgment circuit. When the memory device is operating in the normal mode, the multiplexer selects to output the inversion indication data to the output result judgment circuit.

3. The memory device according to claim 1, characterized in that, In the normal mode, the output result judgment circuit performs an XOR NOT operation on multiple bits of the read data and multiple bits of the inverted indicator data to generate the output information as the final read data. In the test mode, the output result judgment circuit performs an XOR NOT operation on multiple bits of the read data and multiple bits of the test data to generate the output information of error bit information.

4. The memory device according to claim 1, characterized in that, In the test mode, the data confluence reversal calculator stops working.

5. The memory device according to claim 3, characterized in that, The output result judgment circuit includes multiple XOR gates. The first input terminal of each XOR gate receives each bit of the read data, the second input terminal of each XOR gate receives each bit of the test data or receives each bit of the inverted indication data, and the output terminal of each XOR gate generates each bit of the output information.

6. The memory device according to claim 1, characterized in that, Also includes: A test data buffer, coupled to the multitasking unit, is used to store the test data.

7. The memory device according to claim 1, characterized in that, Also includes: A data input block is coupled to the data access circuit to provide external input data to the data access circuit. as well as The data output block is coupled to the output result judgment circuit to output the output information.

8. The memory device according to claim 7, characterized in that, The data input block and the data access circuit have a data write path, and the data output block and the output result judgment circuit have a data read path.

9. The memory device according to claim 7, characterized in that, The data access circuit includes: A sensing amplifier for providing write data to the memory cell array, or for sensing read data by the memory cell array; and A write data buffer, coupled to the sensing amplifier, is used to temporarily store the write data.

10. The memory device according to claim 1, characterized in that, The data bus reversal calculator calculates the number of first logic values ​​among the multiple bits of the read data, and generates the reversal indication data to enable the data when the number is greater than a preset reference value.

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