Non-op-amp clamping multi-value storage-in-computation circuit and memory

Abstract

The application provides a non-operational clamping multi-value in-memory computing circuit and memory, wherein the circuit comprises an oxide semiconductor array, a driving circuit connected with the oxide semiconductor array, a read-write and computing circuit, a multiplexer and a lookup table; the driving circuit is used for driving read word lines and write word lines of the oxide semiconductor array; the read-write and computing circuit is used for sampling and holding a voltage on a global read bit line, converting the voltage into a digital value representing a computing or reading result, and converting a multi-value digital input into a to-be-stored voltage to drive a global write bit line; the multiplexer is used for realizing that multiple storage columns share one successive approximation analog-to-digital converter; and the lookup table is used for calculating back a gate voltage of a storage unit through an analog-to-digital converter output in a refresh mode to determine a multi-value digital input to be applied. The above application can improve the computing energy efficiency and parallelism of the in-memory computing circuit.

Description

Technical Field

[0001] This invention relates to the fields of non-volatile memory and compute-in-memory (CIM) in semiconductor and CMOS ultra-large-scale integrated circuits (ULSI), and specifically to a non-op-amp clamped multi-value CIM circuit and memory that uses oxide semiconductor 2T0C memory cells to perform vector matrix multiplication. Background Technology

[0002] With the continuous development of artificial intelligence and deep learning technologies, artificial neural networks have been widely applied in fields such as natural language processing, image recognition, autonomous driving, and graph neural networks. However, the ever-increasing network size leads to a significant energy consumption in data transfer between memory and traditional computing devices such as CPUs and GPUs, a phenomenon known as the von Neumann bottleneck. Vector matrix multiplication is the most crucial computational component in artificial neural network algorithms. Compute-in-Memory (CIM), based on non-volatile memory, stores weights in non-volatile memory cells and performs simulated vector matrix multiplication within an array. This avoids frequent data transfer between memory and computing units and is considered a promising approach to addressing the von Neumann bottleneck.

[0003] Figure 1 This diagram illustrates a current method for vector matrix multiplication based on a memory array. After the weights are written, they are stored in the memory cells. Several devices are organized into an array. A voltage is input from one end as the input to the vector matrix multiplication. The array performs calculations using Ohm's law and Kirchhoff's laws. The current obtained at the other end of the array is the sum of the vector matrix multiplication results. Typically, the input can be a multi-valued voltage input via a digital-to-analog converter (DAC) or a binary voltage input via a buffer. The summation result is usually read out using an analog-to-digital converter (ADC).

[0004] However, current memory devices, such as traditional CMOS transistor-based DRAM, typically have large leakage currents, short retention times, and cannot achieve low-frequency refresh operations. They also cannot reduce the impact of voltage drop across the array's wires when enabling more rows of parallel computing, resulting in poor computational efficiency and parallelism. Summary of the Invention

[0005] In view of the above problems, the purpose of this invention is to provide a non-op-amp clamped multi-value in-memory computing circuit and memory to solve the problems of existing in-memory computing circuits, such as the inability to achieve low-frequency refresh operations and poor computing energy efficiency and computing parallelism.

[0006] The non-op-amp clamped multi-value in-memory computing circuit provided by this invention includes an oxide semiconductor array, a driving circuit connected to the oxide semiconductor array, a read / write and computing circuit, a multiplexer, and a lookup table. The driving circuit drives the read word lines and write word lines of the oxide semiconductor array. The read / write and computing circuit samples and holds the voltage on the global read bit lines, converts the voltage into a digital value representing the calculation or reading result, and converts the multi-value digital input into a voltage to be stored to drive the global write bit lines. The multiplexer enables multiple memory columns to share a successive approximation analog-to-digital converter (ADC). The lookup table, in refresh mode, outputs the gate voltage of the back-calculation memory cell through the ADC to determine the multi-value digital input to be applied.

[0007] In addition, an optional technical solution is that the read / write and calculation circuit includes a sample-and-hold circuit and an analog-to-digital converter; wherein, the sample-and-hold circuit is used to sample and hold the voltage on the read bit line of the oxide semiconductor array according to a preset frequency; the analog-to-digital converter is used to convert the voltage into a digital value representing the calculation or reading result, and to convert the multi-value digital input into a voltage to be stored to drive the global write bit line.

[0008] In addition, the optional technical solution includes a write mode, a read mode, a refresh mode, and a calculation mode; wherein the write mode, read mode, and refresh mode are used to write, read, and refresh the multi-value storage value, respectively; and the calculation mode is used to perform multiplication operations between the input vector and the weight matrix.

[0009] Alternatively, an optional technical solution is that the semiconductor array includes memory cells arranged in an array, each memory cell including a write transistor and a read transistor; wherein the write transistor is connected to the corresponding write word line and write bit line, and the read transistor is connected to the corresponding read word line and read bit line.

[0010] In addition, an optional technical solution is that the driving circuit includes a write word line driving circuit and an input driving circuit; wherein, the write mode includes: turning off all write word lines; sequentially converting multi-value digital inputs into voltages to be stored through an analog-to-digital converter, so as to input to each write bit line through a multiplexer; starting a row of write word lines through the write word line driving circuit, and storing the voltages to be stored in the gate capacitor of the corresponding read transistor through the opened write transistor.

[0011] In addition, an optional technical solution is that the read mode includes: pre-charging the read bit line to voltage V. RBLConnect the global read bit lines to the read bit lines of the column containing the selected memory cell; apply a voltage V to the read word lines of the unselected rows through the input drive circuit. Gmax And apply voltage GND to the read word line of the selected row; the current of the selected memory cell is expressed as:

[0012] I cell =K*(V G -V TH ) 2

[0013] Where K represents a constant, V G V represents the gate voltage of the read transistor of the memory cell. TH This indicates the threshold voltage of the read transistor; after a preset time, the voltage on the read bit line is sampled by a sample-and-hold circuit and read out by an analog-to-digital converter.

[0014] In addition, an optional technical solution is that the refresh mode includes: based on the read mode, in the read / write and calculation circuit, by using a lookup table, the gate voltage of the read transistor in the memory cell is calculated back based on the output of the analog-to-digital converter; based on the write mode, the calculated voltage is stored in the gate capacitor of the read transistor to refresh the stored value.

[0015] In addition, an optional technical solution is that the calculation mode includes: first pre-charging the current read bit line to voltage V. RBL The global read lines are connected to the read lines of the corresponding memory columns via a multiplexer; a voltage V is applied to the read word lines of all rows via an input drive circuit. Gmax At this time, all storage units have V. GS =V G -V Gmax ≤0, no current flows through the storage cell; pulses with amplitude of GND and width proportional to the multi-value digital input are applied to each read word line; the current of the read bit line is the total current of each row of read word lines, and the capacitors on the read bit lines are discharged through the total current to make the voltage on the read bit lines drop; after a preset time, the voltage on the read bit lines is sampled and read out through an analog-to-digital converter, and the voltage drop of the read bit lines represents the result of multiplying the input vector and the weight matrix.

[0016] Alternatively, an alternative technical solution is to express the voltage drop on the read line as follows:

[0017]

[0018] Among them, I ds t represents the saturation current of the transistor. j This represents the width of the pulse applied to the read line of the j-th line, where n represents the total number of lines, and C... RBL This indicates the capacitance value on the read bit line; the voltage drop on the read bit line is proportional to... This represents the input values ​​(V1, V2, ..., V). n ) and stored values ​​(W1, W2, ..., W n The result of the vector dot product.

[0019] On the other hand, the present invention also provides a memory including the above-described non-op-amp clamped multi-value memory computing circuit.

[0020] By utilizing the aforementioned non-op-amp clamped multi-value in-memory computing circuit and memory, the read and write word lines of the oxide semiconductor array are driven by a driver circuit. The voltage on the global read bit lines is sampled and held by the read / write and computing circuits, and the voltage is converted into a digital value representing the calculation or read result. A multiplexer is used to allow multiple memory columns to share a single successive approximation analog-to-digital converter (ADC), solving the problem of large ADC area and width mismatch with individual memory cells. The oxide semiconductor memory cell has a low on-current. In refresh mode, a lookup table is used to calculate the gate voltage of the memory cell through the ADC output, determining the multi-value digital input to be applied, enabling lower-frequency refresh operations. Furthermore, the low on-current characteristic effectively improves the computational efficiency of the in-memory computing circuit, helping to reduce the impact of wire voltage drop in the array when enabling more rows of parallel computing, thus achieving higher computational parallelism.

[0021] To achieve the foregoing and related objectives, one or more aspects of the invention include the features that will be described in detail below. The following description and accompanying drawings illustrate certain exemplary aspects of the invention. However, these aspects indicate only a few of the various ways in which the principles of the invention can be used. Furthermore, the invention is intended to encompass all such aspects and their equivalents. Attached Figure Description

[0022] Other objects and results of the invention will become more apparent and readily understood with reference to the following description taken in conjunction with the accompanying drawings. In the drawings:

[0023] Figure 1 This is a schematic diagram of vector-matrix multiplication based on a memory array;

[0024] Figure 2 A schematic diagram of an array structure for an oxide semiconductor 2T0C used for in-memory computing;

[0025] Figure 3 This is a schematic diagram of the non-op-amp clamped multi-value in-memory computing circuit according to an embodiment of the present invention;

[0026] Figure 4 This is a schematic diagram of the circuit structure for the write mode in an embodiment of the present invention;

[0027] Figure 5This is a schematic diagram of the circuit structure of the reading mode according to an embodiment of the present invention;

[0028] Figure 6 This is a schematic diagram of the circuit structure of the refresh mode according to an embodiment of the present invention;

[0029] Figure 7 This is a schematic diagram of the circuit structure of the computing mode according to an embodiment of the present invention. Detailed Implementation

[0030] In the following description, numerous specific details are set forth for illustrative purposes and to provide a thorough understanding of one or more embodiments. However, it will be apparent that these embodiments may also be implemented without these specific details. In other instances, well-known structures and devices are shown in block diagram form for ease of description of one or more embodiments.

[0031] Current in-memory computing solutions, due to the use of traditional CMOS transistor-based DRAMs, suffer from high leakage current, short retention time, inability to achieve low-frequency refresh operations, and inability to reduce the impact of voltage drop across the array's wires when enabling more rows of parallel computing. This results in poor computational efficiency and parallelism. To address these issues, this invention provides a non-op-amp clamped multi-value in-memory computing circuit based on 2TOC (Oxide-Semiconductor 2-channel CMOS), utilizing the low on-current characteristics of 2TOC to improve computational efficiency and parallelism.

[0032] Specifically, Figure 2 An array structure of an oxide semiconductor 2TOC for in-memory computing is shown.

[0033] like Figure 2 As shown, each memory cell consists of two transistors, M1 and M2. M1 is the write transistor. During the write process, M1 is turned on through the write word line (WWL), and the voltage value to be stored is written through the write bit line (WBL) and stored in the gate capacitance of M2. M2 is the read transistor. During the read process, a voltage is applied to the read word line (RWL). Depending on whether the voltage stored on the gate capacitance of M2 is in an on-state ("1") or off-state ("0"), an on-state or off-state read current is generated on the read bit line (RBL). Compared with traditional CMOS transistor-based DRAM, the oxide semiconductor 2TOC cell has lower leakage current and longer hold time, thus allowing for refresh operations at lower frequencies. Simultaneously, the on-current of the oxide semiconductor 2TOC cell can be reduced through process technology, resulting in higher computational energy efficiency and helping to reduce the impact of wire voltage drop in the array when enabling more rows of parallel computing, thereby achieving higher computational parallelism.

[0034] To provide a detailed description of the non-op-amp clamped multi-value in-memory computing circuit and memory of the present invention, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0035] Specifically, Figure 3 The schematic structure of the non-op-amp clamped multi-value in-memory computing circuit of an embodiment of the present invention is shown.

[0036] like Figure 3 As shown, the non-op-amp clamped multi-value in-memory computing circuit of the present invention includes an oxide semiconductor array, a driving circuit connected to the oxide semiconductor array, a read / write and computing circuit, a multiplexer, and a lookup table. The driving circuit drives the read word lines and write word lines of the oxide semiconductor array. The read / write and computing circuit samples and holds the voltage on the global read bit lines, converts the voltage into a digital value representing the calculation or reading result, and converts the multi-value digital input into a voltage to be stored to drive the global write bit lines. The multiplexer enables multiple memory columns to share a successive approximation analog-to-digital converter (ADC). The lookup table, in refresh mode, outputs the gate voltage of the back-calculation memory cell through the ADC to determine the multi-value digital input to be applied.

[0037] Specifically, the non-op-amp clamped multi-value in-memory computing circuit includes a 2T0C array, an external input driver circuit, a write word line driver circuit, a multiplexer (MUX), a read / write and computing circuit based on a successive approximation analog-to-digital converter (SAR-ADC-based), and a look-up table (LUT).

[0038] The read / write and calculation circuit includes a sample-and-hold circuit and an analog-to-digital converter. The sample-and-hold circuit is used to sample and hold the voltage on the read bit line of the oxide semiconductor array according to a preset frequency. The analog-to-digital converter is used to convert the voltage into a digital value representing the calculation or reading result, and to convert multi-value digital input into a voltage to be stored to drive the global write bit line.

[0039] Furthermore, the non-op-amp clamped multi-value in-memory computation circuit of this invention has four operating modes: write mode, read mode, refresh mode, and computation mode. The write mode, read mode, and refresh mode are used for writing, reading, and refreshing the multi-value stored values ​​(weights), respectively, while the computation mode performs multiplication operations between the input vector and the weight matrix.

[0040] In the in-memory computing circuit of the present invention, the semiconductor array includes a plurality of memory cells arranged in an array, each memory cell including a write transistor (M1, the same below) and a read transistor (M2, the same below); wherein, the write transistor is connected to the corresponding write word line and write bit line, and the read transistor is connected to the corresponding read word line and read bit line.

[0041] Furthermore, the aforementioned driving circuit further includes a write word line driving circuit and an input driving circuit, whose operating states differ under different operating modes. Specifically, the read / write and calculation circuits include a sample-and-hold circuit (S / H) and a successive approximation analog-to-digital converter (SAR-ADC). The S / H circuit samples and holds the voltage on the global read bit lines at fixed intervals; the successive approximation ADC converts this voltage into a digital value representing the calculation / read result. A multiplexer is used to enable multiple memory columns to share the same SAR-ADC, solving the problem of the large area and width of the SAR-ADC not matching that of a single memory cell. A lookup table is used to calculate the gate voltage of the memory cell from the ADC output during refresh and to determine the multi-value digital input to be applied. The input driving circuit drives each read word line, and the write word line driving circuit drives each write word line. In this architecture, reading, writing, and calculation are all performed using capacitors on the write or read bit lines.

[0042] The working principle of the non-op-amp clamped multi-value in-memory computing circuit of this invention will be described below, based on the characteristics of each working mode.

[0043] Specifically, Figure 4 A schematic circuit structure for a write mode according to an embodiment of the present invention is shown.

[0044] like Figure 4 As shown, the black lines are the working lines and the gray lines are the non-working lines. The working principle of this write mode includes: turning off all write word lines; converting the multi-value digital input into the voltage to be stored through the analog-to-digital converter in sequence, so as to input to each write word line through the multiplexer; starting a write word line through the write word line drive circuit, and the voltage to be stored is stored in the gate capacitor of the corresponding read transistor through the opened write transistor.

[0045] In write mode, the input drive circuit is inactive. Furthermore, all write word lines are first turned off to prevent charge leakage from unselected memory cells located in the same row and multiplexing the same SAR-ADC. Then, the multi-valued digital input is sequentially converted to the voltage to be stored via the DAC in the read / write and calculation circuit, and then input to each write bit line via a multiplexer. Next, a row is turned on via the write word line drive circuit, and the voltage to be stored is stored in the gate capacitor M2 through the opened M1. It can be seen that due to the write bit line capacitor (C... WBL ) is much larger than the gate capacitance of M2 (CG This makes the voltage on the write line almost unchanged.

[0046] Figure 5 A schematic structure of the circuit for the read mode according to an embodiment of the present invention is shown.

[0047] like Figure 5 As shown, the black lines represent the working lines, and the gray lines represent the non-working lines. In read mode, the write line drive circuit is not working. Specific read modes include: pre-charging the read lines to voltage V. RBL Connect the global read line (GRBL) to the read line of the column containing the selected memory cell; apply a voltage V to the read word lines of the unselected rows through the input drive circuit. Gmax And apply voltage GND to the read word line of the selected row; the current of the selected memory cell is expressed as:

[0048] I cell =K*(V G -V TH ) 2

[0049] Where K represents a constant, V G V represents the gate voltage of the read transistor of the memory cell. TH This indicates the threshold voltage of the read transistor; after a preset time, the voltage on the read bit line is sampled by a sample-and-hold circuit and read out by an analog-to-digital converter.

[0050] Specifically, a voltage V is applied to the word lines of the unselected rows through the input drive circuit. Gmax That is, the maximum gate voltage for multi-value storage, so all cells in the unselected row have V. GS =V G -V Gmax ≤0, at this time no current flows through the memory cell; but when a voltage GND is applied to the read word line of the selected row, the current flowing through the selected cell is expressed as: I ds =K*(V G -V TH ) 2 The voltage on the read line drops; where K represents a constant, V G V represents the gate voltage of the read transistor of the memory cell. TH This represents the threshold voltage for reading the transistor. After a preset fixed time, the voltage on the read bit line is sampled and then read out via an ADC.

[0051] To ensure that M2 remains in the saturation region during the reading process, it is necessary to ensure that the voltage on the read bit line is always higher than V during the reading process. Gmax -V TH .

[0052] Figure 6A schematic diagram of the circuit structure of the refresh mode according to an embodiment of the present invention is shown.

[0053] like Figure 6 As shown, black lines represent active circuits, and gray lines represent inactive circuits. In refresh mode, all peripheral circuits participate in the operation. The reading process is similar to... Figure 5 The circuitry for the read / write mode is consistent. In the read / write and calculation circuitry, a lookup table is needed to calculate the gate voltage of M2 in the memory cell from the ADC output. Then, through... Figure 4 The write process shown stores the calculated voltage into the gate capacitor M2 to refresh the stored value and complete the refresh process.

[0054] It should be noted that, in order to effectively refresh the stored value, it is necessary to refresh periodically before misreading occurs due to leakage current in the gate capacitor. Therefore, the maximum refresh period is proportional to the gate capacitance of M2 and inversely proportional to the leakage current of M1. The specific period parameters can be set through experimental measurement.

[0055] Figure 7 A schematic diagram of the circuit structure of the computing mode according to an embodiment of the present invention is shown.

[0056] like Figure 7 As shown, the black lines represent the working lines, and the gray lines represent the non-working lines. In calculation mode, the write line drive circuit is not working. The calculation mode includes: first pre-charging the current read bit line to voltage V. RBL The global read lines are connected to the read lines of the corresponding memory columns via a multiplexer; a voltage V is applied to the read word lines of all rows via an input drive circuit. Gmax At this time, all storage units have V. GS =V G -V Gmax ≤0, no current flows through the storage cell; then, pulses with an amplitude of GND and a width proportional to the multi-value digital input are applied to each read word line; the current of the read bit line is the total current of each row of read word lines, and the capacitors on the read bit lines are discharged through this total current to make the voltage on the read bit lines drop; after a preset time, the voltage on the read bit lines is sampled and read out through an analog-to-digital converter, and the voltage drop of the read bit lines represents the result of multiplying the input vector and the weight matrix.

[0057] Specifically, in the computation mode, it is necessary to ensure that V remains constant throughout the entire computation process. RBL >V Gmax -V TH This ensures that M2 is always in the saturation region when it is turned on. Furthermore, according to Kirchhoff's laws, the current flowing through the read line is the total current obtained by summing the currents of each row. This current affects the read line capacitance (C). RBLDischarge causes the voltage on the read line to drop. After a preset fixed time, the voltage on the read line is sampled and then read out through an analog-to-digital converter.

[0058] It should be noted that the multi-valued weight W stored in the storage unit needs to be proportional to (V G -V TH ) 2 V G This is the gate voltage of M2. The transistor saturation current I... ds =K*(V G -V TH ) 2 Then at this point, the weight W is... j Proportional to I dsj (j is the row number, 1≤j≤n). Simultaneously, there is also a pulse width t. j Proportional to multi-valued input V j (t j V represents the width of the pulse applied in the j-th row. j If the j-th row represents a multi-valued input, then the voltage drop on the read line is expressed as:

[0059]

[0060] Among them, I ds t represents the saturation current of the transistor. j This represents the width of the pulse applied to the read line of the j-th line, where n represents the total number of lines, and C... RBL This represents the capacitance value on the read bit line; it can be seen that the voltage drop on this read bit line is proportional to... It can be used to represent input values ​​(V1, V2, ..., V n ) and stored values ​​(W1, W2, ..., W n The vector dot product of the input vector and the weight matrix is ​​the result of the input vector multiplied by the weight matrix for the entire oxide semiconductor array.

[0061] Corresponding to the above-mentioned non-op-amp clamped multi-value in-memory calculation circuit, the present invention also provides a memory including the above-mentioned non-op-amp clamped multi-value in-memory calculation circuit.

[0062] It should be noted that the specific embodiments of the memory described above can be found in the description of the non-op-amp clamped multi-value in-memory computing circuit embodiment, and will not be repeated here.

[0063] According to the above-described non-op-amp clamped multi-value in-memory computing circuit and memory of the present invention, there is a smaller leakage current and a longer hold time, enabling refresh operations at a lower frequency. At the same time, the on-state current of the oxide semiconductor 2T0C cell can be reduced through the process, thus achieving higher computing power efficiency. It also helps to reduce the impact of wire voltage drop in the array when enabling more rows of parallel computing, thereby achieving higher computing parallelism. In addition, the capacitor on the write bit line is used to realize the multiplexing of the ADC, and the capacitor on the read bit line is used to perform current summation calculation on each column, enabling multi-value storage and multi-value calculation. Compared with the design of using an operational amplifier to clamp the read bit line voltage, the present invention has no DC path throughout and no op-amp power consumption, thus achieving higher computing power efficiency.

[0064] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0065] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A non-op-amp clamped multi-value in-memory computing circuit, characterized in that, The system includes an oxide semiconductor array, a driving circuit connected to the oxide semiconductor array, read / write and calculation circuits, a multiplexer, and a lookup table. The driving circuit includes a write line driving circuit and an input driving circuit. The oxide semiconductor array includes memory cells arranged in an array, each memory cell including a write transistor and a read transistor; wherein, The write transistor is connected to the corresponding write word line and write bit line, and the read transistor is connected to the corresponding read word line and read bit line; The driving circuit is used to drive the read lines and write lines of the oxide semiconductor array; The read / write and calculation circuit is used to sample and hold the voltage on the global read bit line, convert the voltage into a digital value representing the calculation or reading result, and convert multi-value digital input into a voltage to be stored to drive the global write bit line; The multiplexer is used to enable multiple storage columns to share a successive approximation analog-to-digital converter; The lookup table is used in refresh mode to calculate the gate voltage of the memory cell by back-calculating the output of the analog-to-digital converter to determine the multi-valued digital input to be applied. It also includes a computation mode for performing multiplication operations between the input vector and the weight matrix, the computation mode including: First, precharge the current read bit line to voltage V. RBL ; The global read lines are connected to the read lines of the corresponding storage columns through the multiplexer; The input drive circuit applies a voltage V to the read lines of all rows. Gmax At this time, all storage units have V. GS =V G -V Gmax ≤0, no current flows through the storage unit; Apply pulses with an amplitude of GND and a width proportional to the multi-value digital input to each reading line; The current of the read bit line is the total current of each row of read word lines. The total current discharges the capacitor on the read bit line, thereby reducing the voltage on the read bit line. After a preset time, the voltage on the read line is sampled and read out by the analog-to-digital converter. The voltage drop on the read line represents the result of multiplying the input vector with the weight matrix.

2. The non-op-amp clamped multi-value in-memory calculation circuit as described in claim 1, characterized in that, The read / write and calculation circuit includes a sample-and-hold circuit and the analog-to-digital converter; wherein... The sample-and-hold circuit is used to sample and hold the voltage on the read lines of the oxide semiconductor array according to a preset frequency. The analog-to-digital converter is used to convert the voltage into a digital value representing the result of a calculation or reading, and to convert multi-value digital inputs into a voltage to be stored to drive the global write bit line.

3. The non-op-amp clamped multi-value in-memory calculation circuit as described in claim 2, characterized in that, It also includes write mode, read mode, and refresh mode; among which, The write mode, the read mode, and the refresh mode are used to write, read, and refresh the multi-value storage value, respectively.

4. The non-op-amp clamped multi-value in-memory calculation circuit as described in claim 3, characterized in that, The write modes include: Turn off all text lines; The multi-value digital input is sequentially converted into a voltage to be stored by the analog-to-digital converter, and then input to each write bit line through the multiplexer; The write line driving circuit activates a write line, and the voltage to be stored is stored in the gate capacitor of the corresponding read transistor through the open write transistor.

5. The non-op-amp clamped multi-value in-memory calculation circuit as described in claim 3, characterized in that, The reading modes include: Precharge the read line to voltage V RBL Connect the global read lines to the read lines of the column containing the selected memory cell; The input drive circuit applies a voltage V to the word lines of the unselected rows. Gmax And apply voltage GND to the read line of the selected row; The current of the selected memory cell is expressed as follows: I cell =K (V G -V TH ) 2 Where K represents a constant, V G V represents the gate voltage of the read transistor of the memory cell. TH This indicates the threshold voltage of the read transistor; After a preset time, the voltage on the read line is sampled by the sample-and-hold circuit and read out by the analog-to-digital converter.

6. The non-op-amp clamped multi-value in-memory calculation circuit as described in claim 5, characterized in that, The refresh modes include: Based on the read mode, in the read-write and calculation circuit, the gate voltage of the read transistor in the memory cell is calculated back based on the output of the analog-to-digital converter using the lookup table. Based on the write mode, the calculated voltage is stored in the gate capacitor of the read transistor to refresh the stored value.

7. The non-op-amp clamped multi-value in-memory calculation circuit as described in claim 6, characterized in that, The voltage drop on the read line is expressed as: Among them, I dsj t represents the saturation current of the read transistor described in row j. j This represents the width of the pulse applied to the read line of the j-th line, where n represents the total number of lines, and C... RBL This indicates the capacitance value on the read bit line; The voltage drop on the read line is proportional to The voltage drop on the read line represents the input value (V1, V2, ..., V). n ) and stored values ​​(W1, W2, ..., W n The result of the vector dot product.

8. A memory, characterized in that, Includes the non-op-amp clamped multi-value in-memory computing circuit as described in any one of claims 1 to 7.

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