Memory cell and array structure for non-volatile memory and associated control method

Abstract

The present application is a memory cell and array structure of a non-volatile memory and a related control method. The memory cell of the non-volatile memory includes a select transistor, a floating gate transistor, a first capacitor, a switch transistor and a second capacitor. A first drain / source of the select transistor is connected to a source line. A gate of the select transistor is connected to a word line. Two drains / sources of the floating gate transistor are connected to a second drain / source of the select transistor and a bit line, respectively. The first capacitor is connected between a floating gate of the floating gate transistor and an erase node. Two drains / sources of the switch transistor are connected to the erase node and an erase line, respectively. A gate of the switch transistor is connected to a control line. The second capacitor is connected between the erase node and a boost line.

Description

Technical Field

[0001] This invention relates to a non-volatile memory, and more particularly to a memory cell and array structure of a non-volatile memory and a related control method. Background Technology

[0002] As is well known, non-volatile memory can retain data even after the power is lost, and therefore it is widely used in electronic products. Furthermore, non-volatile memory consists of multiple non-volatile cells arranged in an array structure, and each non-volatile cell contains a floating gate transistor.

[0003] US Patent 8,941,167 discloses an erasable programmable single-polysilicon nonvolatile memory. Please refer to... Figure 1A The diagram depicts a known nonvolatile memory cell. In the following description, the nonvolatile memory cell will be simply referred to as a memory cell.

[0004] Known memory cells include: selection transistor M S Floating gate transistor M F Metal-oxide-semiconductor capacitors (MOS capacitors) MOS In other words, this memory cell is a 2T1C memory cell consisting of two transistors and one capacitor.

[0005] Select transistor M S With floating gate transistor M F Formed in an N-well region, selective transistor M S With floating gate transistor M F It is a p-type transistor. Additionally, the MOS capacitor C... MOS It is composed of n-type transistors. The n-type transistor is formed in a P-well region, and the two drain / source terminals of the n-type transistor are interconnected to form a MOS capacitor C. MOS Among them, the N-type well area receives the N-type well area voltage V. NW The P-type well area receives the P-type well area voltage V. PWThat is, select transistor M. S With floating gate transistor M F The body receives the N-type well voltage V. NW The body of an n-type transistor receives the P-type well voltage V. PW .

[0006] like Figure 1A As shown, select transistor M S The first drain / source is connected to the source line and receives the source line voltage V. SL Select transistor M S The gate is connected to the select gate line and receives the select gate line voltage V. SG Floating gate transistor M F The first drain / source is connected to the selection transistor M. S Second drain / source, floating gate transistor M F The second drain / source is connected to the bit line and receives the bit line voltage V. BL MOS capacitor C MOS The first terminal is connected to the floating gate transistor M F Floating gate 36, MOS capacitor C MOS The second terminal is connected to the erase line and receives the erase line voltage V. EL .

[0007] Provide an appropriate bias voltage as the gate voltage selection voltage V SG Source line voltage V SL Line voltage V BL Erasure line voltage V EL N-type well area voltage V NW P-type well area voltage V PW It can perform programming, erasing, or reading operations on non-volatile memory cells.

[0008] During programming, the hot carrier (e.g., electron) injection or non-injection can be controlled in the floating gate transistor M. F A floating gate. For example, controlling hot carriers (e.g., electrons) not to be injected into a floating gate transistor M. F With a floating gate, the memory cell is programmed into the first storage state. Alternatively, hot carrier injection is controlled by the floating gate transistor M. F If the floating gate is used, the memory cell is programmed into the second storage state.

[0009] Furthermore, during the erase operation, the data stored in the floating gate transistor M can be... FHot carriers via MOS capacitor C MOS Eject to erase line EL, causing the memory cell to be in its first storage state.

[0010] In addition, when performing a read operation, the storage state of the memory cell can be determined as either the first storage state or the second storage state based on the magnitude of the read current generated by the memory cell.

[0011] During programming, the source line voltage V SL Program voltage (V) PP The voltage is approximately 7.5V. During the erase operation, the erase line voltage V... EL Erase voltage (V) EE The voltage is approximately 15V. During a read operation, the source line voltage V... SL The read voltage is approximately 2.0V. That is, among the bias voltages for the various operations described above, the erase voltage V... EE maximum.

[0012] Please refer to Figure 1B The diagram shown is a schematic of a known non-volatile memory. The non-volatile memory includes an array structure, a word line driver 110, a bit line driver 120, and an erase line driver 130.

[0013] The array structure includes M×N memory cells. 11 ~c MN Source line SL, word lines WL1~WL M Erasure lines EL1 to EL M Bit lines BL1~BL N Where M and N are positive integers. Furthermore, each memory cell c 11 ~c MN The structure and internal connection relationship are the same as Figure 1A This will not be elaborated upon here. Taking memory cell c as an example... 11 Taking transistor M as an example, S The first drain / source is connected to the source line SL, selecting transistor M. S The gate of the floating gate transistor M is connected to word line WL1. F The second drain / source is connected to bit line BL1, capacitor C MOS The second end is connected to the erase line EL1.

[0014] In the array structure, the first row has N memory cells c11 ~c 1N Connected to source line SL, word line WL1 and erase line EL1, N memory cells in the first row c 11 ~c 1N Connect to the corresponding N bit lines BL1~BL N Similarly, the N memory cells c in the second row 21 ~c 2N Connected to source line SL, word line WL2 and erase line EL2, N memory cells in the second row c 21 ~c 2N Connect to the corresponding N bit lines BL1~BL N And so on, the N memory cells in the Mth row... M1 ~c MN Connect to source line SL, word line WL M With the erase line EL M The N memory cells in the Mth row c M1 ~c MN Connect to the corresponding N bit lines BL1~BL N .

[0015] Word line driver 110 is connected to the M word lines WL1 to WL of the array structure. M According to the selection signal S1, the word line driver 110 can activate M word lines WL1 to WL2. M One of them. For example, word line driver 110 activates word line WL1 according to selection signal S1.

[0016] At this time, the word line driver 110 provides an enable voltage V. ON To word line WL1, provide the shutdown voltage V OFF To other character lines WL2~WL M For example, the turn-on voltage V ON It can be 0V, the shut-off voltage V OFF It can be 7.5V. That is, according to the selection signal S1, the word line driver 110 determines a row in the array structure as the selected row.

[0017] Bit line driver 120 is connected to N bit lines BL1 to BL2 of the array structure. N Based on the selection signal S2, the bit line driver 120 can drive N word lines BL1 to BL2. N One of them is used to determine the selected cell on the selected row.

[0018] Furthermore, the erase line driver 130 is connected to the M erase lines EL1 to EL1 of the array structure. MAccording to the selection signal S3, the erase line driver 130 can provide various voltages to the M erase lines EL1 to EL2 during programming, erasing, and reading operations. M For example, during the erase operation, the erase line driver 130 activates the erase line EL1 according to the selection signal S3. At this time, the erase line driver 130 provides an erase voltage V. EE To erase line EL1, and provide ground voltage (0V) to other erase lines EL2~EL1. M .

[0019] Please refer to Figure 1C The diagram illustrates the bias voltage for erasing a known non-volatile memory. For example, it shows the bias voltage for memory cells c in the first row of the array structure. 11 ~c 1N During the erase operation, word line driver 110 activates word line WL1 according to selection signal S1, and erase line driver 130 activates erase line EL1 according to selection signal S3. Therefore, the first row in the array structure is the selected row.

[0020] At this time, the source line SL receives the ground voltage (0V), and the word line driver 110 provides the turn-on voltage V. ON To word line WL1, word line driver 110 provides a shutdown voltage V. OFF To other character lines WL2~WL M The erase line driver 130 provides the erase voltage V. EE To erase line EL1, erase line driver 130 provides ground voltage (0V) to other erase lines EL2~EL1. M The bit line driver 120 provides a ground voltage (0V) to the N bit lines BL1 to BL2. N .

[0021] like Figure 1C As shown, due to the array structure, the erase lines EL2 to EL3 of the non-selected rows... M Receive ground voltage (0V), word lines WL2~WL M Receive shutdown voltage V OFF Therefore, all memory cells c in the non-selected rows 21 ~C MN The storage state will not be changed.

[0022] Additionally, the first row of the array structure is the selected row. In memory cell c 11 In the middle, the floating gate transistor M F The stored hot carriers (e.g., electrons) are transported by a floating gate through a capacitor C. MOS Eject to erase line EL1, causing memory cell c 11The memory cell c changes from the second storage state to the first storage state. 1N The memory state changes from the second storage state to the first storage state. Additionally, due to memory cell c... 12 In the first storage state, the floating gate transistor does not store hot carriers, so the memory cell c 12 Maintain in the first storage state.

[0023] As explained above, after the erase operation, all memory cells in the selected row (first row) are erased. 11 ~c 1N It will become the first storage state without stored hot carriers.

[0024] When the non-volatile memory performs an erase operation, the erase line driver 130 will adjust the erase voltage V according to the selection signal S3. EE The erase line is transmitted to the selected row. As is well known, the erase line driver 130 contains many electronic components forming multiple switching paths. By using the selection signal S3 to control the switching paths in the erase line driver 130, the erase voltage V can be adjusted. EE The erase line passed to the selected row. Figure 1C For example, during the erase operation, the selection signal S3 turns on to switch path 131, causing the erase voltage V to... EE The erase line EL1 is passed to the selected row via switching path 131.

[0025] During the erase operation, the erase voltage V is transmitted through the switching path 131 in the erase line driver 130. EE Therefore, the electronic components on switching path 131 and erase line EL1 may experience the greatest voltage stress. For example, when the erase voltage V... EE At 15V, the electronic components on switching path 131 and erase line EL1 may be subjected to a voltage stress of 15V. If any electronic component on switching path 131 or erase line EL1 is damaged due to the voltage stress of 15V, the non-volatile memory will not function properly. Summary of the Invention

[0026] This invention relates to an array structure for a non-volatile memory, the array structure having a first memory cell, the first memory cell comprising: a first select transistor, a first drain / source of the first select transistor connected to a source line, and a gate of the first select transistor connected to a first word line; a first floating gate transistor, a first drain / source of the first floating gate transistor connected to a second drain / source of the first select transistor, and a second drain / source of the first floating gate transistor connected to a first bit line; a first capacitor, a first terminal of the first capacitor connected to a floating gate of the first floating gate transistor, and a second terminal of the first capacitor connected to a first erase node; a first switching transistor, a first drain / source of the first switching transistor connected to the first erase node, a second drain / source of the first switching transistor connected to a first erase line, and a gate of the first switching transistor connected to a control line; and a second capacitor, a first terminal of the second capacitor connected to the first erase node, and a second terminal of the second capacitor connected to a first boost line.

[0027] This invention relates to a control method applied to a memory cell in a non-volatile memory. The memory cell includes: a select transistor having a first drain / source connected to a source line and a gate connected to a word line; a floating gate transistor having a first drain / source connected to a second drain / source of the first select transistor and a second drain / source connected to a bit line; and a first capacitor having a first terminal connected to a floating gate of the floating gate transistor and a second terminal connected to an erase node. The control method includes the following steps: during a programming operation, An enable voltage is provided to the word line, a programming voltage is provided between the source line and the bit line, and the programming voltage is transmitted to the erase node; during a precharge phase of an erase operation, the enable voltage is provided to the word line, a ground voltage is provided to the source line and the bit line, and a precharge voltage is transmitted to the erase node; and during an erase operation, in an erase phase following the precharge phase, the enable voltage is provided to the word line, the ground voltage is provided to the source line and the bit line, and a voltage of the erase node is boosted from the precharge voltage to an erase voltage.

[0028] To provide a better understanding of the above and other aspects of the present invention, preferred embodiments are described below in detail with reference to the accompanying drawings: Attached Figure Description

[0029] Figure 1A For memory cells of known nonvolatile memory;

[0030] Figure 1B A schematic diagram of a known non-volatile memory;

[0031] Figure 1CA schematic diagram of the bias voltage for an erase operation of a known non-volatile memory;

[0032] Figure 2 The memory cell of the non-volatile memory of this invention;

[0033] Figure 3A A schematic diagram of the bias voltage used to control the memory cell to present a second storage state;

[0034] Figure 3B A schematic diagram of the bias voltage used to control the memory cell to present its first storage state;

[0035] Figure 3C This is a schematic diagram of the bias voltage during the reading operation of the memory cell;

[0036] Figures 4A to 4C This is a schematic diagram of the bias voltage and related signals during the erasure operation of the memory cell in this invention.

[0037] Figure 5 This is a schematic diagram of the non-volatile memory of the present invention;

[0038] Figure 6 A schematic diagram of the bias voltage used to program selected memory cells in an array structure;

[0039] Figure 7 This is a schematic diagram of the bias voltage used to read a selected row in the array structure.

[0040] Figure 8A and Figure 8B A schematic diagram of the bias voltage used to erase selected memory cells in the array structure; and

[0041] Figure 9A and Figure 9B This is a schematic diagram of the bias voltage applied to a selected row of the array structure for erasing.

[0042] [Symbol Explanation]

[0043] 36, 200: Floating gate

[0044] 110, 510: Word line drivers

[0045] 120, 520: Bit line drivers

[0046] 130, 540: Erase Line Driver

[0047] 131: Switch Path

[0048] 530: Boost Line Driver Detailed Implementation

[0049] This invention proposes a memory cell and array structure for non-volatile memory and a related control method. The invention designs a novel memory cell architecture, enabling the erase line driver to eliminate the need to provide an erase voltage V during the erase operation of the non-volatile memory. EE This allows hot carriers (such as electrons) in the memory cell to exit the floating gate.

[0050] Please refer to Figure 2 The illustration depicts a nonvolatile memory cell of the present invention. In the following description, the nonvolatile memory cell will be simply referred to as a memory cell. The memory cell includes: a selection transistor M... S Floating gate transistor M F Switching transistor M SW Capacitor C1 and capacitor C2. In other words, this memory cell is a 3T2C memory cell with three transistors and two capacitors.

[0051] Select transistor M S The first drain / source is connected to the source line SL, selecting transistor M. S The gate of the floating gate transistor M is connected to the word line WL. F The first drain / source is connected to the selection transistor M. S Second drain / source, floating gate transistor M F The second drain / source is connected to the bit line BL. The first terminal of capacitor C1 is connected to the floating gate transistor M. F The floating gate 200, the second terminal of capacitor C1 is connected to the erase node (E). N The first terminal of capacitor C2 is connected to the erase node E. N The second terminal of capacitor C2 is connected to the boost line (BSTL). Switching transistor M SW The first drain / source is connected to the erase node E. N Switching transistor M SW The second drain / source is connected to the erase line (EL), and the switching transistor M... SW The gate is connected to the control line (CL).

[0052] According to an embodiment of the present invention, transistor M is selected. S With floating gate transistor M F It is a p-type transistor, and the switching transistor M is... SWThis is an n-type transistor, and capacitors C1 and C2 are MOS capacitors. Of course, this invention is not limited to this, and those skilled in the art can design and select transistors of various types. S With floating gate transistor M F It is an n-type transistor, and the switching transistor is M. SW It is a p-type transistor. Alternatively, the design selects transistor M. S Floating gate transistor M F With switching transistor M SW Both can be p-type transistors or both can be n-type transistors. Alternatively, capacitors C1 and C2 can also be other types of capacitors, such as plate capacitors.

[0053] Furthermore, by providing appropriate bias voltages to the source line SL, word line WL, bit line BL, boost line BSTL, erase line EL, and control line CL, the memory cell can be programmed, inhibited, erased, or read. The operating principle of the memory cell of this invention is explained in detail below.

[0054] During programming, the hot carrier injection floating gate transistor M can be controlled. F The floating gate 200. During programming suppression, hot carriers can be prevented from being injected into the floating gate transistor M. F The floating gate 200. For example, the floating gate transistor M controls the hot carriers not injected. F If the floating gate 200 is used, the memory cell remains in the first storage state. Alternatively, the hot carrier injection floating gate transistor M can be controlled. F If the floating gate 200 is used, the memory cell is programmed into the second storage state.

[0055] Please refer to Figure 3A The diagram illustrates the bias voltage controlling the memory cell to present its second storage state. During programming, the source line SL receives the programming voltage V. PP Bit line BL receives ground voltage (0V), boost line BSTL receives ground voltage (0V), and erase line EL receives programming voltage V. PP The word line WL receives the turn-on voltage V. ON The control line CL receives the control voltage V. CTRL1 For example, the programming voltage V PP It is 7.5V, and the turn-on voltage is V. ON The ground voltage is 0V, and the control voltage is V. CTRL1 It equals 7.5V.

[0056] like Figure 3A As shown, the control line CL receives the control voltage V. CTRL1This makes the switching transistor M SW Start, programming voltage V PP Passed to erase node E N Furthermore, the word line WL receives the turn-on voltage V. ON This makes the selection transistor M S When activated, the memory cell generates a programming current I. P The current flows from the source line SL to the bit line BL. When the programming current I... P Flow through floating gate transistor M F In the channel region, hot carriers (e.g., electrons) are controlled by the floating gate transistor M. F A floating gate is injected into the channel region, causing the memory cell to change from the first storage state to the second storage state.

[0057] Please refer to Figure 3B The diagram illustrates the bias voltage controlling the memory cell to present its first storage state. During the programming suppression operation, the source line SL receives the programming voltage V. PP Bit line BL receives ground voltage (0V), boost line BSTL receives ground voltage (0V), and erase line EL receives programming voltage V. PP The word line WL receives the off voltage V. OFF The control line CL receives the control voltage V. CTRL1 For example, the off voltage V OFF It equals 7.5V.

[0058] Due to the word line WL receiving shutdown voltage V OFF This makes the selection transistor M S Shut down. Therefore, the memory cell does not generate the programming current I. P Therefore, there is no hot carrier injection into the floating gate transistor M. F The floating gate allows the memory cell to remain in the first storage state.

[0059] Of course, the present invention can also utilize other bias methods to control the memory cell from generating the programming current I. P This allows the memory cell to remain in its first storage state. For example, during a programming suppression operation, the source line SL receives the programming voltage V. PP Bit line BL receives programming voltage V PP The BSTL boost line receives the ground voltage (0V), and the EL erase line receives the programming voltage (V). PP The word line WL receives the turn-on voltage V. ON The control line CL receives the control voltage V. CTRL1 Since both the source line SL and the bit line BL receive the programming voltage V. PP Regardless of the word line WL receiving turn-on voltage V ON Or turn off voltage VOFF The memory cells are all unable to generate the programming current I. P .

[0060] Please refer to Figure 3C The diagram illustrates the bias voltage during a read operation of the memory cell. During the read operation, the bias voltage can be adjusted based on the floating gate transistor M. F Whether or not hot carriers are stored determines the storage state of the memory cell. During a read operation, a voltage difference is provided between the source line SL and the bit line BL; this voltage difference is the read voltage (V). R ).

[0061] exist Figure 3C In the middle, the source line SL receives the read voltage V. R The bit line BL receives the ground voltage (0V) or the voltage V that is read. R At lower voltages (e.g., 0.4V), the boost line BSTL receives the ground voltage (0V), the erase line EL receives the ground voltage (0V), and the word line WL receives the turn-on voltage V. ON The control line CL receives the control voltage V. CTRL2 At this time, the switching transistor M SW When activated, the ground voltage (0V) is transmitted to the erase node E. N This makes the erase node E N It will not be in a floating state, allowing for smooth reading operations. For example, the control voltage V... CTRL2 It is 3.3V, read voltage V R It is 2.0V.

[0062] Of course, in other embodiments, during the read operation, the source line SL can receive the first read voltage V. R1 The bit line BL receives a voltage higher than the first read voltage V. R1 The second reading voltage V is still low R2 The control line CL receives the third read voltage V. R3 For example, a first read voltage V of 2.4V is provided. R1 The source line SL provides a second read voltage V of 0.4V. R2 To the bit line BL, a third read voltage V of 0V is provided. R3 To the erase line EL. Therefore, the voltage difference between the source line SL and the bit line BL is equal to the read voltage V of 2.0V. R .

[0063] like Figure 3C As shown, due to the word line WL receiving the turn-on voltage V ON Select transistor M S When activated, the memory cell generates a read current I. RThe current flows from the source line SL to the bit line BL. Furthermore, based on the read current I... R The size of the gate transistor M determines the storage state of the memory cell. For example, when the floating gate transistor M... F When storing hot carriers, the read current I of the memory cell R Larger. When the floating gate transistor M F When no hot carriers are stored, the read current I of the memory cell R It is very small, almost zero. Therefore, a sensing circuit (not shown) and a reference current I can be provided. REF To determine the storage status of memory cells.

[0064] For example, a sensing circuit (not shown) receives a reference current I. REF With reading current I R When reading current I R Less than the reference current I REF The sensing circuit (not shown) determines that the memory cell is in the first storage state. When the read current I... R Greater than the reference current I REF The sensing circuit (not shown) determines that the memory cell is in the second storage state.

[0065] According to an embodiment of the present invention, in order to allow the erase line EL to withstand lower voltage stress during the erase operation, the memory cell of the present invention also includes a switching transistor M. SW With a capacitor C2, a switching transistor M SW Connected to erase node E N Between the erase line EL and the erase node E, capacitor C2 is connected to erase node E. N Between the boost line BSTL and the memory cell of this invention. The following details the operation of the memory cell during the erase operation.

[0066] Please refer to Figures 4A to 4C The diagram illustrates the bias voltage and related signals during the erase operation of the memory cell according to the present invention. According to an embodiment of the present invention, the erase operation includes a pre-charge phase (PH). PRE ) and the erase phase (pH ERS Assuming that the memory cell is in a second storage state before the erase operation, i.e., hot carriers (e.g., electrons) are stored in the floating gate transistor M. F Floating gate.

[0067] like Figure 4A and Figure 4C As shown, time point t A up to time point t B Pre-charge phase PH for the erase action PREAt this time, the source line SL receives the ground voltage (0V), the bit line BL receives the ground voltage (0V), and the word line WL receives the turn-on voltage V. ON The boost line BSTL receives the ground voltage (0V), and the erase line EL receives the precharge voltage (V). PRE The control line CL receives the control voltage V. CTRL1 Among them, the control voltage V CTRL1 Equal to pre-charge voltage V PRE And the pre-charge voltage V PRE Less than the erase voltage V EE For example, the control voltage V CTRL1 With pre-charge voltage V PRE The erase voltage is 7.5V. EE It is 15V.

[0068] Due to the word line WL receiving turn-on voltage V ON Select transistor M S Turn on, enabling the floating gate transistor M F The first drain / source and the second drain / source are grounded at ground voltage (0V). Furthermore, since the control line CL receives the control voltage V... CTRL1 Switching transistor M SW Start-up, pre-charge voltage V PRE Passed to erase node E N Clearly, in the pre-charge phase PH PRE At that time, due to the erasure of node E N The voltage is the pre-charge voltage V. PRE And the pre-charge voltage V PRE Less than the erase voltage V EE Therefore, the hot carriers are still stored in the floating gate and cannot exit the floating gate.

[0069] like Figure 4B and Figure 4C As shown, time point t B up to time point t C The erase electrical phase PH for the erase action ERS At this time, the source line SL receives the ground voltage (0V), the bit line BL receives the ground voltage (0V), and the word line WL receives the turn-on voltage V. ON The BSTL boost line receives the boost voltage (V). BST The erase line EL receives the pre-charge voltage V. PRE The control line CL receives the control voltage V. CTRL1 Among them, the boost voltage V BST Less than the erase voltage V EE And the precharge voltage V PRE Apply boost voltage VBST Greater than or equal to the erase voltage V EE For example, the boost voltage V BST It is 7.5V.

[0070] At time t B The boost line BSTL rises from ground voltage (0V) to boost voltage V. BST Furthermore, the boost voltage V BST Erasing node E via capacitor C2 N This makes the erase node E N The voltage is determined by the pre-charge voltage V. PRE Increase the voltage by another increment, which is approximately equal to the boost voltage V. BST Therefore, erase node E. N The voltage is approximately the pre-charge voltage V. PRE Apply boost voltage V BST Equal to the erase voltage V EE , (V EE =V PRE +V BST In other words, during the erasure of phase pH... ERS At that time, erase node E N The voltage is boosted to the erase voltage V. EE .

[0071] When erase node E N Boosted to the erase voltage V EE At that time, the switching transistor M SW The first drain / source is the erase voltage V. EE (e.g., 15V), switching transistor M SW The gate voltage is the control voltage V CTRL1 (e.g., 7.5V), switching transistor M SW The second drain / source is the precharge voltage V. PRE (e.g., 7.5V), therefore the switching transistor M SW Turn off, thus erasing node E N It becomes floating and erases node E. N The voltage is maintained at the erase voltage V. EE .

[0072] Furthermore, due to the erasure of node E N The voltage is the erase voltage V. EE Therefore, the floating gate transistor M F The stored hot carriers are ejected from the floating gate to the erase node E. N This causes the memory cell to change from the second storage state to the first storage state.

[0073] As can be seen from the above explanation, during the erasure process, only when erasing the phase pH... ERS At that time, erase node E N Only then will the highest erase voltage VEE be reached, while other connections (such as erase line EL and boost line BSTL) will not receive the highest erase voltage V. EE In other words, all electronic components connected to the erase line EL and the boost line BSTL will not be subjected to the highest voltage stress, ensuring that these electronic components are not easily damaged.

[0074] Please refer to Figure 5 The diagram shown is a schematic representation of the non-volatile memory of the present invention. The non-volatile memory includes an array structure, a word line driver 510, a bit line driver 520, a boost line driver 530, and an erase line driver 540.

[0075] The array structure includes M×N memory cells. 11 ~c MN Source line SL, control line CL, word lines WL1~WL M Boost converter BSTL1~BSTL M Bit lines BL1~BL N Erasure lines EL1 to EL N Where M and N are positive integers. Furthermore, each memory cell c 11 ~c MN The structure and internal connection relationship are the same as Figure 2 This will not be elaborated upon here. Taking memory cell c as an example... 11 Taking transistor M as an example, S The first drain / source is connected to the source line SL, selecting transistor M. S The gate of the floating gate transistor M is connected to word line WL1. F The second drain / source is connected to bit line BL1, switching transistor M SW The second drain / source is connected to the erase line EL1, and the switching transistor M... SW The gate of capacitor C2 is connected to the control line CL, and the second end of capacitor C2 is connected to the boost line BSTL1.

[0076] In the array structure, the first row has N memory cells c 11 ~c 1N Connect to the source line SL, control line CL, word line WL1, and boost line BSTL1. The first row contains N memory cells c. 11 ~c1N Connect to the corresponding N bit lines BL1~BL N With N erase lines EL1~EL N Similarly, the N memory cells c in the second row 21 ~c 2N Connect to the source line SL, control line CL, word line WL2, and boost line BSTL2. The second row contains N memory cells c. 21 ~c 2N Connect to the corresponding N bit lines BL1~BL N With N erase lines EL1~EL N And so on, the N memory cells in the Mth row... M1 ~c MN Connect to source line SL, control line CL, and word line WL M With boost line BSTL M The N memory cells c in the Mth row M1 ~c MN Connect to the corresponding N bit lines BL1~BL N With N erase lines EL1~EL N .

[0077] The word line driver 510 is connected to the M word lines WL1 to WL of the array structure. M According to the selection signal S1, the word line driver 510 can activate M word lines WL1 to WL2. M One of them. For example, word line driver 510 activates word line WL1 according to selection signal S1. At this time, word line driver 510 provides an enable voltage V. ON To word line WL1, provide the shutdown voltage V OFF To other character lines WL2~WL M For example, the turn-on voltage V ON It can be 0V, the shut-off voltage V OFF It can be 7.5V. That is, according to the selection signal S1, the word line driver 510 determines a row in the array structure as the selected row.

[0078] Bit line driver 520 is connected to N bit lines BL1 to BL2 of the array structure. N Based on the selection signal S2, the bit line driver 520 can drive N word lines BL1 to BL2. N One of them is used to determine the selected cell on the selected row.

[0079] The boost line driver 530 is connected to the M boost lines BSTL1 to BSTL in the array structure. MBased on the selection signal S3, the boost line driver 530 can provide various voltages to the M boost lines BSTL1 to BSTL1 during programming, erasing, and reading operations. M For example, during the erase operation, the boost line driver 530 activates the boost line BSTL1 according to the selection signal S3. At this time, the boost line driver 530 provides a boost voltage V. BST To boost line BSTL1, provide ground voltage (0V) to other boost lines BSTL2~BSTL1. M .

[0080] The erase line driver 540 is connected to N erase lines EL1 to EL1 of the array structure. N Based on the selection signal S4, the erase line driver 540 can provide various voltages to the N erase lines EL1 to EL2 during programming, erasing, and reading operations. N For example, during the erase operation, the erase line driver 540 activates erase line EL1 according to the selection signal S4. At this time, the erase line driver 540 provides a pre-charge voltage V. PRE Provide ground voltage (0V) to erase line EL1 and to other erase lines EL2~EL1. N .

[0081] Furthermore, provide appropriate bias voltage to the source line SL, control line CL, and word lines WL1 to WL. M Bit lines BL1~BL N Boost converter BSTL1~BSTL M With erasure lines EL1~EL N It can perform programming, programming suppression, erasure, or reading operations on any memory cell in non-volatile memory. The following discussion uses memory cell c as an example. 11 The operating principle of the non-volatile memory of the present invention will be explained in detail using an example.

[0082] Please refer to Figure 6 The diagram illustrates the bias voltage used to program selected memory cells in the array structure. During programming, the source line SL receives the programming voltage V. PP The control line CL receives the control voltage V. CTRL1 The word line WL1 receives the turn-on voltage V. ON , character lines WL2~WL M Receive shutdown voltage V OFF Bit line BL1 receives the ground voltage (0V), bit lines BL2~BL N Receive programming voltage V PP Boost converter BSTL1~BSTL M Receives ground voltage (0V), erase line EL1 receives programming voltage V PPErasure lines EL2~EL N Receives ground voltage (0V). For example, programming voltage V. PP It is 7.5V, and the turn-on voltage is V. ON Ground voltage (0V), shut-off voltage V OFF It is 7.5V, and the control voltage V CTRL1 It equals 7.5V.

[0083] Furthermore, since word line WL1 and bit line BL1 are activated, the first row is the selected row, and the other rows are non-selected rows. In the array structure, the memory cells of the non-selected rows are... 21 ~c MN This is a non-selected memory cell. Additionally, the memory cell c for the selected row... 11 To select a memory cell, select the other memory cells in the row c. 12 ~c 1N These are non-selected memory cells.

[0084] The non-selected memory cell c in the first row 12 ~c 1N In the middle, due to the source line SL and the bit lines BL2~BL N Receive programming voltage V PP Therefore, the non-selected memory cell c in the first row 12 ~c 1N Unable to generate programming current. That is, the non-selected memory cell c in the first row. 12 ~c 1N This involves performing a programmed suppression action without changing the stored state. For example, maintaining the first stored state.

[0085] Non-selected memory cells in other rows c 21 ~c MN In the middle, due to the character lines WL2~WL M Receive shutdown voltage V OFF Therefore, the non-selected memory cells c in other rows 21 ~c MN Unable to generate programming current. That is, the non-selected memory cells c in other rows... 21 ~c MN It also involves performing a programmed suppression action without changing the stored state. For example, maintaining the first stored state.

[0086] like Figure 6 As shown, in the selected memory cell c in the first row 11 In the middle, the word line WL1 receives the turn-on voltage V. ON The source line SL receives the programming voltage V. PP Bit line BL1 receives the ground voltage (0V), and control line CL receives the control voltage V. CTRL1The boost line BSTL1 receives the ground voltage (0V), and the erase line EL1 receives the programming voltage V. PP Therefore, the switching transistor M SW Start, programming voltage V PP Passed to erase node E N Furthermore, the transistor M is selected. S When activated, the memory cell generates a programming current I. P The current flows from the source line SL to the bit line BL1. When the programming current I... P Flow through floating gate transistor M F In the channel region, hot carriers (e.g., electrons) are controlled by the floating gate transistor M. F A floating gate is injected into the channel region, causing the memory cell to change from the first storage state to the second storage state.

[0087] Please refer to Figure 7 The diagram illustrates the bias voltage during a read operation on a selected row of the array structure. During the read operation, the source line SL receives the read voltage V. R The control line CL receives the control voltage V. CTRL2 The word line WL1 receives the turn-on voltage V. ON , character lines WL2~WL M Receive shutdown voltage V OFF Bit lines BL1~BL N Receive ground voltage (0V), boost line BSTL1~BSTL M Receive ground voltage (0V), erase lines EL1 to EL1 N Receives ground voltage (0V). For example, reads voltage V. R The voltage is 2.0V, and the control voltage is V. CTRL2 It equals 3.3V.

[0088] Furthermore, due to the activation of word line WL1, the first row of the array structure is the selected row, and the other rows are non-selected rows, and the memory cells in the non-selected rows are... 21 ~c MN Unable to generate read current.

[0089] like Figure 7 As shown, in the selected row of the first line, word line WL1 receives the turn-on voltage V. ON Bit lines BL1~BL N Receives ground voltage (0V), source line SL receives read voltage V R The control line CL receives the control voltage V. CTRL2 The boost line BSTL1 receives the ground voltage (0V), and the erase lines EL1 to EL2... NReceives ground voltage (0V). Therefore, the memory cell c of the selected row... 11 ~c 1N Generate read current I R1 ~I RN They flow to the corresponding bit lines BL1 to BL2 respectively. N .

[0090] Furthermore, based on the reading current I R1 ~I RN The size of the memory cell c 11 ~c 1N The storage state. For example, memory cell c 11 Stores hot carriers, so memory cell c 11 The generated reading current I R1 The value is relatively large, and can be determined as a second storage state by a sensing circuit (not shown). Furthermore, memory cell c 12 No hot carriers are stored, so the memory cell c 12 The generated reading current I R1 It is small, almost zero, and can be determined as the first storage state by a sensing circuit (not shown).

[0091] Please refer to Figure 8A and Figure 8B The diagram illustrates the bias voltage applied during the erasure of selected memory cells in the array structure. Figure 8A A schematic diagram of the bias voltage during the pre-charge phase. Figure 8B This is a schematic diagram of the bias voltage when erasing the electrical phase.

[0092] like Figure 8A As shown, during the pre-charge phase of the erase operation, the source line SL receives a ground voltage (0V), and the bit lines BL1 to BL2... N Receives ground voltage (0V), word line WL1 receives turn-on voltage V ON , character lines WL2~WL M Receive shutdown voltage V OFF The control line CL receives the control voltage V. CTRL1 Boost converter BSTL1~BSTL M Receives ground voltage (0V), erase line EL1 receives pre-charge voltage V PRE Erasure lines EL2~EL N Receives ground voltage (0V). For example, pre-charge voltage V. PRE It is 7.5V.

[0093] Furthermore, since word line WL1 and erase line EL1 are activated, the first row is the selected row, and the other rows are non-selected rows. In the array structure, the memory cells of the non-selected rows are... 21 ~c MNThis is a non-selected memory cell. Additionally, the memory cell c for the selected row... 11 To select a memory cell, select the other memory cells in the row c. 12 ~c 1N These are non-selected memory cells.

[0094] like Figure 8A As shown, in the memory cell c in the first row 11 In the middle, because the erase line EL1 receives the pre-charge voltage V PRE Therefore, erase node E N The voltage is the pre-charge voltage V. PRE Additionally, in the memory cell c in the first row... 12 ~c 1N In the middle, due to the erasure lines EL2~EL N Since the received ground voltage is 0V, the corresponding erase node voltage is the ground voltage (0V). Similarly, in the memory cell c in the second row... 21 In the process, the voltage of the erase node is the pre-charge voltage V. PRE In the memory cell c in the second row 22 ~c 2N In this context, the corresponding erase node voltage is the ground voltage (0V). And so on. In the memory cell c of the Mth row... M1 In the process, the voltage of the erase node is the pre-charge voltage V. PRE In the memory cell c in the Mth row M2 ~c MN In this case, the voltage of the corresponding erase node is the ground voltage (0V).

[0095] Taking the bit erase operation as an example, such as Figure 8B As shown, during the erase phase of the erase operation, the source line SL receives the ground voltage (0V), and the bit lines BL1 to BL2... N Receives ground voltage (0V), word line WL1 receives turn-on voltage V ON , character lines WL2~WL M Receive shutdown voltage V OFF The control line CL receives the control voltage V. CTRL1 The boost line BSTL1 receives the boosted voltage V. BST Boost converter BSTL2~BSTL M Receives ground voltage (0V), erase line EL1 receives pre-charge voltage V PRE Erasure lines EL2~EL N Receives ground voltage (0V). For example, boost voltage V BST It is 7.5V.

[0096] like Figure 8B As shown, in the selected memory cell c in the first row11 In the middle, because the boost line BSTL1 receives the boost voltage V BST Therefore, memory cell c is selected. 11 Internal erase node E N The voltage is pushed up to the erase voltage V. EE That is, V EE =V PRE +V BST Furthermore, due to the switching transistor M SW Close and erase node E N The voltage is maintained at the erase voltage V. EE This causes hot carriers to exit from the floating gate via capacitor C1 to the erase node E. N Select memory cell c 11 It becomes the first storage state.

[0097] The non-selected memory cell c in the first row 12 ~c 1N In the process of erasing, the node voltage is boosted from the ground voltage (0V) to the boost voltage V. BST Furthermore, the switching transistor M SW The gate receives the control voltage V CTRL1 Switching transistor M SW To enable the erase node voltage, the voltage is further boosted by the voltage V. BST Discharge to ground voltage (0V). Because the voltage at the erase node is less than the erase voltage V. EE Therefore, non-selected memory cell c 12 ~c 1N The hot carriers in the cell will not exit the floating gate. That is, the non-selected memory cell c... 12 ~c 1N Erase inhibition did not change the storage state.

[0098] Additionally, during in-situ erase operation, due to the boost lines BSTL2~BSTL M It still receives the ground voltage (0V), therefore all non-selected memory cells c in the non-selected rows (i.e., rows 2 to M) 21 ~c MN Internal erase node E N The voltage will not change, and Figure 8A Exactly the same. That is, the memory cell c of the non-selected row. 21 ~c MN Erase inhibition did not change the storage state.

[0099] As explained above, providing appropriate bias voltage to the source line SL, control line CL, and word lines WL1 to WL MBit lines BL1~BL N Boost converter BSTL1~BSTL M With erasure lines EL1~EL N It can perform programming, programming suppression, erasure, or reading operations on any memory cell in non-volatile memory.

[0100] Furthermore, in addition to the bit erase operation performing the erase action only on a single memory cell, the present invention can also perform the erase action on an entire row of memory cells. This will be described below.

[0101] Please refer to Figure 9A and Figure 9B The diagram illustrates the bias voltage used for erasing selected rows of the array structure. Figure 9A A schematic diagram of the bias voltage during the pre-charge phase. Figure 9B This is a schematic diagram of the bias voltage when erasing the electrical phase.

[0102] As shown in Figure 9A, during the pre-charge phase of the erase operation, the source line SL receives the ground voltage (0V), and the bit lines BL1 to BL2... N Receives ground voltage (0V), word line WL1 receives turn-on voltage V ON , character lines WL2~WL M Receive shutdown voltage V OFF The control line CL receives the control voltage V. CTRL1 Boost converter BSTL1~BSTL M Receive ground voltage (0V), erase lines EL1 to EL1 N Receive pre-charge voltage V PRE .

[0103] like Figure 9A As shown, during the pre-charge phase, all memory cells c of the array structure 11 ~c MN All the switching transistors in the memory cell are turned on, so all memory cells c 11 ~c MN The voltage of the erase node is the pre-charge voltage V. PRE .

[0104] Furthermore, compared to Figure 9B and Figure 8B The difference is that the erasure action of this invention can target N memory cells in a selected row. 11 ~c 1N To be carried out simultaneously. For example... Figure 9B As shown, during the erase phase of the erase operation, the source line SL receives the ground voltage (0V), and the bit lines BL1 to BL2... N Receives ground voltage (0V), word line WL1 receives turn-on voltage V ON, character lines WL2~WL M Receive shutdown voltage V OFF The control line CL receives the control voltage V. CTRL1 The boost line BSTL1 receives the boosted voltage V. BST Boost converter BSTL2~BSTL M Receives ground voltage (0V), N erase lines EL1~EL N Receive pre-charge voltage V PRE To select N memory cells c for the chosen row 11 ~c 1N To perform the erasure operation.

[0105] like Figure 9B As shown, the first row is the selected row because the boost line BSTL1 receives the boost voltage V. BST Therefore, memory cell c 11 ~c 1N The voltage at the internal erase node is boosted to the erase voltage V. EE That is, V EE =V PRE +V BST Therefore, the memory cell c of the selected row. 11 ~c 1N In the process, hot carriers exit from the floating gate via capacitor C1 to the erase node E. N This makes the memory cell c of the selected row... 11 ~c 1N It becomes the first storage state.

[0106] In non-selected rows, the erase node voltage is maintained at the precharge voltage V. PRE Therefore, the memory cell c of the non-selected rows 21 ~c MN Hot carriers in the memory cell will not exit the floating gate. That is, memory cells in non-selected rows... 21 ~c 1N Erase inhibition did not change the storage state.

[0107] Of course, when erasing the phase, Figure 9B The boost line driver 530 in the middle can also boost the voltage V BST Simultaneously, the signal is transmitted to the M boost lines BSTL. At this time, all memory cells in the array structure... 11 ~c MN All of them will undergo an erase operation and become the first storage state.

[0108] As described above, this invention proposes a memory cell and associated array structure for a non-volatile memory. This invention designs a novel memory cell such that, during the erase operation of the non-volatile memory, the erase line driver 540 provides a pre-charge voltage V. PRE The boost line controller 530 provides the boost voltage V. BST And the pre-charge voltage V PRE With boost voltage V BST All are less than the erase voltage V EE Pre-charge voltage V PRE Apply boost voltage V BST Greater than or equal to the erase voltage V EE In other words, due to the design of the memory cells, during the erase operation of the non-volatile memory, the switching paths in both the erase line driver 540 and the boost line driver 530 will not transmit the highest erase voltage V. EE Therefore, it can be ensured that the electronic components in the cut-off line driver 540 and the boost line driver 530 are not subjected to the highest voltage stress, making these electronic components less susceptible to damage.

[0109] Furthermore, the present invention is not limited to the programming voltage V. PP Erasure voltage V EE Read voltage V R Pre-charge voltage V PRE Boost voltage V BST Turn-on voltage V ON , Turn off voltage V OFF Control voltage V CTRL1 With control voltage V CTRL2 The actual voltage value. Those skilled in the art can appropriately modify the various voltages described above to achieve the objectives of this invention.

[0110] In summary, although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. An array structure of a non-volatile memory, the array structure having a first memory cell, the first memory cell comprising: A first selection transistor, wherein the first drain / source of the first selection transistor is connected to the source line, and the gate of the first selection transistor is connected to the first word line; A first floating gate transistor, wherein the first drain / source of the first floating gate transistor is connected to the second drain / source of the first select transistor, and the second drain / source of the first floating gate transistor is connected to the first bit line; A first capacitor, the first end of which is connected to the floating gate of the first floating gate transistor, and the second end of which is connected to the first erase node; A first switching transistor, wherein the first drain / source of the first switching transistor is connected to the first erase node, the second drain / source of the first switching transistor is connected to the first erase line, and the gate of the first switching transistor is connected to the control line; as well as A second capacitor, the first end of which is connected to the first erase node, and the second end of which is connected to the first boost line.

2. The array structure of claim 1, further comprising a second memory cell, the second memory cell comprising: A second selection transistor, wherein the first drain / source of the second selection transistor is connected to the source line, and the gate of the second selection transistor is connected to the second word line; The second floating gate transistor has its first drain / source connected to the second drain / source of the second select transistor, and its second drain / source connected to the first bit line. A third capacitor, the first end of which is connected to the floating gate of the second floating gate transistor, and the second end of which is connected to the second erase node; A second switching transistor, wherein the first drain / source of the second switching transistor is connected to the second erase node, the second drain / source of the second switching transistor is connected to the first erase line, and the gate of the second switching transistor is connected to the control line; as well as A fourth capacitor, the first end of which is connected to the second erase node, and the second end of which is connected to the second boost line.

3. The array structure as described in claim 1, further comprising a second memory cell, the second memory cell comprising: A second selection transistor, wherein the first drain / source of the second selection transistor is connected to the source line, and the gate of the second selection transistor is connected to the first word line; The second floating gate transistor has its first drain / source connected to the second drain / source of the second select transistor, and its second drain / source connected to the second bit line. A third capacitor, the first end of which is connected to the floating gate of the second floating gate transistor, and the second end of which is connected to the second erase node; A second switching transistor, wherein the first drain / source of the second switching transistor is connected to the second erase node, the second drain / source of the second switching transistor is connected to the second erase line, and the gate of the second switching transistor is connected to the control line; as well as A fourth capacitor, the first end of which is connected to the second erase node, and the second end of which is connected to the first boost line.

4. The array structure as claimed in claim 1, wherein the first selection transistor and the first floating gate transistor are p-type transistors, and the first switching transistor is an n-type transistor.

5. The array structure as claimed in claim 1, wherein the first capacitor and the second capacitor are metal-oxide-semiconductor capacitors.

6. The array structure as claimed in claim 1, wherein during programming, the first word line receives an enable voltage, the first erase line receives a programming voltage, the first boost line receives a ground voltage, the control line receives a first control voltage, the first switching transistor is enabled, the programming voltage is transmitted to the first erase node, the first select transistor is enabled and generates a programming current; and when the programming current flows through the channel region of the first floating gate transistor, a plurality of hot carriers are injected from the channel region of the floating gate transistor into the floating gate, causing the first memory cell to change from a first storage state to a second storage state.

7. The array structure as claimed in claim 6, wherein during the programming operation, the source line receives the programming voltage, the first bit line receives the ground voltage, and the programming current flows from the source line to the first bit line.

8. The array structure as claimed in claim 1, wherein during a read operation, the first word line receives an enable voltage, the source line receives a first read voltage, the first bit line receives a second read voltage less than the first read voltage, the first erase line receives a third read voltage, the first boost line receives a ground voltage, and the control line receives a first control voltage.

9. The array structure as claimed in claim 8, wherein during the read operation, the first selection transistor is turned on, and the read current flows from the source line to the first bit line; when the read current is less than the reference current, the first memory cell is determined to be in a first storage state; when the read current is greater than the reference current, the first memory cell is determined to be in a second storage state.

10. The array structure as claimed in claim 1, wherein during the pre-charge phase of the erase operation, the first word line receives an enable voltage, the source line receives a ground voltage, the first bit line receives the ground voltage, the first erase line receives a pre-charge voltage, the first boost line receives the ground voltage, and the control line receives a first control voltage.

11. The array structure of claim 10, wherein during the precharge phase, the first switching transistor is turned on, and the precharge voltage is delivered to the first erase node.

12. The array structure of claim 11, wherein during the erase phase following the precharge phase, the first word line receives the turn-on voltage, the source line receives the ground voltage, the first bit line receives the ground voltage, the first erase line receives the precharge voltage, the first boost line receives the boost voltage, and the control line receives the first control voltage.

13. The array structure of claim 12, wherein during the erase phase, the first erase node is increased by a voltage increment from the precharge voltage, and the voltage increment is the boost voltage, such that the voltage of the first erase node is pushed up to the erase voltage; and a plurality of hot carriers exit from the floating gate of the first floating gate transistor, such that the first memory cell changes from the second storage state to the first storage state.

14. The array structure of claim 13, wherein the precharge voltage is less than the erase voltage, the boost voltage is less than the erase voltage, and the precharge voltage plus the boost voltage is greater than or equal to the erase voltage.

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