Fuse device and method of operating the same

Abstract

A fuse device and a method of operating the same are provided. The fuse device includes a plurality of fuse circuits, a global latch circuit, and a plurality of local latch circuits. The global latch circuit is coupled to the fuse circuits. The global latch circuit is configured to sense a fuse state of the fuse circuits at different times to output fuse information of the fuse circuits at the different times. The local latch circuits are coupled to the global latch circuit. Each of the local latch circuits latches the fuse information output by the global latch circuit at the different times.

Description

Technical Field

[0001] This invention relates to an information latching circuit, and more particularly to a fuse device and its operating method. Background Technology

[0002] Fuse, or anti-fuse, can be used in various electronic circuits to latch different information (fuse information). For example, dynamic random-access memory (DRAM) chips can use antifuses to determine which redundant row and / or redundant column to turn on. For antifuses, blown antifuses have low resistance, while unblown antifuses have high resistance. Depending on the antifuse material, in some embodiments, the resistance of blown antifuses can range from 2 to 100 kΩ, while the resistance of unblown antifuses can range from 5000 to 20000 kΩ. A fuse latching circuit can sense the antifuse's resistance state (blown state) and thus latch the antifuse information. Furthermore, the fuse latching circuit can coordinate the blown antifuse operation. Generally, an antifuse (fuse circuit) requires a dedicated fuse latching circuit. The more fuse circuits there are, the more dedicated fuse latching circuits are needed. Reducing circuit area is one of the many important issues in this technical field. Summary of the Invention

[0003] The present invention provides a fuse device and its operating method, so that multiple fuse circuits can share a wide-area latching circuit.

[0004] In an embodiment of the invention, the fuse device described above includes a plurality of fuse circuits, a wide-area latching circuit, and a plurality of local latching circuits. The wide-area latching circuit is coupled to the fuse circuits. The wide-area latching circuit is used to sense the recorded states of the fuse circuits at different times to output fuse information of the fuse circuits at said different times. The local latching circuits are coupled to the wide-area latching circuit. Each of the local latching circuits latches the fuse information output by the wide-area latching circuit at said different times.

[0005] In an embodiment of the present invention, the above-described operation method includes: sensing the recording states of a plurality of fuse circuits of the fuse device at different times by a wide-area latching circuit of the fuse device; outputting fuse information of these fuse circuits by the wide-area latching circuit at the different times; and latching the fuse information output by the wide-area latching circuit by a plurality of local latching circuits of the fuse device at the different times.

[0006] Based on the above, the wide-area latching circuit of the fuse device described in the embodiments of the present invention can sense the resistance state (recording state) of any fuse circuit at different times, and then output fuse information to the corresponding local latching circuit. Furthermore, the wide-area latching circuit can collaboratively perform the recording operation on any fuse circuit. That is, multiple fuse circuits can share the same wide-area latching circuit in a time-sharing manner. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of a circuit block of a fuse device according to an embodiment of the present invention;

[0008] Figure 2 This is a schematic flowchart illustrating the operation method of a fuse device according to an embodiment of the present invention;

[0009] Figure 3 The circuit block diagram of the fuse circuit, the wide-area latching circuit and the local latching circuit is shown according to an embodiment of the present invention.

[0010] Figure 4 The circuit block diagram of the controller is shown according to an embodiment of the present invention;

[0011] Figure 5 The circuit block diagram of a fuse latch circuit is shown according to an embodiment of the present invention.

[0012] Figure 6 This is a timing diagram of word line signals and enable pulses according to an embodiment of the present invention.

[0013] Explanation of reference numerals in the attached figures

[0014] 100: Fuse Device

[0015] 110_1, 110_2, 110_n: Fuse circuits

[0016] 111: Recording Pad

[0017] 113: Anti-fuse

[0018] 120: Wide-area latching circuit

[0019] 121: Selection Circuit

[0020] 122: Fuse latch circuit

[0021] 130_1, 130_2, 130_n: Local latch-up circuits

[0022] 131: Switch

[0023] 132: Latch

[0024] 140: Control Circuit

[0025] 141: Controller

[0026] 141a: Enable signal generation circuit

[0027] 141b: Oscillator

[0028] 141c: Address Counter

[0029] 142: Decoder

[0030] 143: Shift Register

[0031] 510: Recording switch

[0032] 520: Enable Switch

[0033] 530: Read switch

[0034] 540: NOT gate

[0035] 550, 560, 570: Transistors

[0036] ADDR: Fuse Address

[0037] CLK: Clock

[0038] EN: Enable signal

[0039] EN0: Source-driven pulse

[0040] EN1, EN2, ENn: Enabling pulses

[0041] S210, S220, S230: Steps

[0042] Vdd: Read voltage source

[0043] Vss: Reference voltage source

[0044] WL1, WL2, WLn: Word line signals Detailed Implementation

[0045] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0046] The term "coupled (or connected)" as used throughout this specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection. The terms "first," "second," etc., used throughout this specification (including the claims) are used to name components or distinguish different embodiments or scopes, and are not intended to limit the upper or lower limit of the number of components, nor to limit the order of components. Furthermore, wherever possible, components / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Components / components / steps using the same reference numerals or the same terms in different embodiments may be referred to mutually in the relevant descriptions.

[0047] Figure 1 This is a schematic circuit block diagram of a fuse device 100 according to an embodiment of the present invention. The fuse device 100 includes multiple fuse circuits, for example... Figure 1 The fuse circuits shown are 110_1, 110_2, ..., 110_n. The number n of fuse circuits 110_1 to 110_n can be determined according to the actual design. The fuse device 100 also includes multiple local latching circuits, for example... Figure 1 The local latching circuits 130_1, 130_2, ..., 130_n are shown. The wide-area latching circuit 120 of the fuse device 100 is coupled between the fuse circuits 110_1 to 110_n and the local latching circuits 130_1 to 130_n.

[0048] Figure 2 This is a schematic flowchart illustrating the operation method of a fuse device according to an embodiment of the present invention. Please refer to... Figure 1 and Figure 2 Based on the control of the control circuit 140, the wide-area latching circuit 120 can sense the recording states of fuse circuits 110_1 to 110_n at different times (step S210), and output the fuse information (recording state) of fuse circuits 110_1 to 110_n to the local latching circuits 130_1 to 130_n at the different times (step S220). Each of the local latching circuits 130_1 to 130_n can latch the fuse information output by the wide-area latching circuit 120 at the different times (step S230).

[0049] For example, the wide-area latching circuit 120 can sense the recording state of fuse circuit 110_1 and output the fuse information of fuse circuit 110_1 to the local latching circuit 130_1 during the first read time, so that the local latching circuit 130_1 can latch the fuse information of fuse circuit 110_1 during the first read time. During the second read time, the wide-area latching circuit 120 can sense the recording state of fuse circuit 110_2 and output the fuse information of fuse circuit 110_2 to the local latching circuit 130_2, so that the local latching circuit 130_2 can latch the fuse information of fuse circuit 110_2. Similarly, during the nth read time, the wide-area latching circuit 120 can sense the recording state of the fuse circuit 110_n and output the fuse information of the fuse circuit 110_n to the local latching circuit 130_n, so that the local latching circuit 130_n can latch the fuse information of the fuse circuit 110_n.

[0050] In summary, the wide-area latching circuit 120 of the fuse device 100 described in this embodiment can sense the resistance state (writing state) of any fuse circuit at different times, and then output its fuse information to the corresponding local latching circuit. Furthermore, the wide-area latching circuit 120 can collaboratively perform writing operations on any fuse circuit. Therefore, multiple fuse circuits 110_1 to 110_n can share the same wide-area latching circuit 120 in a time-sharing manner, thereby saving circuit area.

[0051] Figure 3 This is a circuit block diagram of fuse circuit 110_1, wide-area latch circuit 120 and local latch circuit 130_1, according to an embodiment of the present invention. Figure 3 The circuit shown can be used as Figure 1 This is one of many embodiments of the fuse device 100 shown. Details of the implementation of other fuse circuits 110_2 to 110_n in the fuse device 100 can be found in [reference needed]. Figure 3 The description of fuse circuit 110_1 shown can be extrapolated from this example, and the implementation details of other local latching circuits 130_2 to 130_n in fuse device 100 can be found in [reference needed]. Figure 3 The relevant descriptions of the local latch circuit 130_1 shown can be deduced by analogy, so they will not be repeated here.

[0052] exist Figure 3In the illustrated embodiment, fuse circuit 110_1 includes a recording pad 111 and an antifuse 113. A first end of the antifuse 113 is coupled to a wide-area latching circuit 120. The recording pad 111 is coupled to a second end of the antifuse 113. When the antifuse 113 is being recorded, the recording pad 111 can be coupled to an external recording voltage source (not shown). When the antifuse 113 is not being recorded, the recording pad 111 can be electrically floating, meaning the recording pad 111 is not coupled to an external recording voltage source.

[0053] exist Figure 3 In the illustrated embodiment, the wide-area latch circuit 120 includes a selection circuit 121 and a fuse latch circuit 122. The fuse latch circuit 122 is coupled to the common terminal of the selection circuit 121. The output terminal of the fuse latch circuit 122 is coupled to the input terminal of each of the local latch circuits 110_1 to 110_n. The fuse latch circuit 122 can sense the resistance state (writing state) of the fuse circuits 110_1 to 110_n at different times, and then output its fuse information to the corresponding local latch circuit. Furthermore, the fuse latch circuit 122 can collaboratively perform writing operations on any one of the fuse circuits. This embodiment does not limit the specific implementation of the fuse latch circuit 122. For example, according to actual design, the fuse latch circuit 122 can be... Figure 5 The fuse latch circuit 122 shown (described in detail later) is either a known fuse latch circuit or another fuse latch circuit.

[0054] Multiple selection terminals of selection circuit 121 are coupled one-to-one to the first terminals of the antifuses of fuse circuits 110_1 to 110_n. Selection circuit 121 can selectively couple one of fuse circuits 110_1 to 110_n to fuse latch circuit 122. Selection circuit 121 is controlled by word line signals WL1, WL2, ..., WLn of control circuit 140. When word line signal WL1 is at a high logic level, selection circuit 121 can selectively couple the first terminal of antifuse 113 of fuse circuit 110_1 to fuse latch circuit 122. When word line signal WL2 is at a high logic level, selection circuit 121 can selectively couple the first terminal of antifuse (not shown) of fuse circuit 110_2 to fuse latch circuit 122. Similarly, when the word line signal WLn is at a high logic level, the selection circuit 121 can selectively couple the first terminal of the antifuse (not shown) of the fuse circuit 110_n to the fuse latch circuit 122.

[0055] For example, selection circuit 121 can selectively couple the first terminal of antifuse 113 of fuse circuit 110_1 to fuse latch circuit 122 during the first read time, so that fuse latch circuit 122 can sense and latch fuse information (recorded state) of fuse circuit 110_1 during the first read time, and output the fuse information of fuse circuit 110_1 to local latch circuit 130_1. During the second read time, selection circuit 121 can selectively couple the first terminal of antifuse of fuse circuit 110_2 to fuse latch circuit 122, so that fuse latch circuit 122 can sense and latch fuse information of fuse circuit 110_2, and output the fuse information of fuse circuit 110_2 to local latch circuit 130_2. Similarly, during the nth read time, the selection circuit 121 can selectively couple the first end of the anti-fuse of the fuse circuit 110_n to the fuse latch circuit 122, so that the fuse latch circuit 122 can sense the fuse information of the latching fuse circuit 110_n and output the fuse information of the output fuse circuit 110_n to the local latch circuit 130_n.

[0056] exist Figure 3 In the illustrated embodiment, the control circuit 140 includes a controller 141 and a decoder 142. The controller 141 can generate a fuse address ADDR. The decoder 142 is coupled to the controller 141 to receive the fuse address ADDR. The decoder 142 can decode the fuse address ADDR to generate multiple word line signals WL1 to WLn for the selection circuit 121. For example (but not limited to), when the fuse address ADDR represents the value "0", word line signal WL1 is logic "1" and the remaining word line signals WL2 to WLn are logic "0". When the fuse address ADDR represents the value "1", word line signal WL2 is logic "1" and the remaining word line signals are logic "0". And so on, when the fuse address ADDR represents the value "n-1", word line signal WLn is logic "1" and the remaining word line signals are logic "0". Selection circuit 121 can select one of fuse circuits 110_1 to 110_n according to word line signals WL1 to WLn.

[0057] Figure 4 The circuit block diagram of controller 141 is shown according to an embodiment of the present invention. Figure 4 The controller 141 shown can be used as Figure 3 This is one of many implementation examples of the controller 141 shown. Figure 4In the illustrated embodiment, the controller 141 includes an enable signal generation circuit 141a, an oscillator 141b, and an address counter 141c. When the fuse device 100 enters the fuse information reading period, the enable signal generation circuit 141a can generate an enable signal EN for the oscillator 141b. The oscillator 141b is controlled by the enable signal EN to selectively generate a clock CLK. For example, when the enable signal EN is at a high logic level, the oscillator 141b can generate the clock CLK. When the enable signal EN is at a low logic level, the oscillator 141b can stop generating the clock CLK. The address counter 141c is coupled to the oscillator 141b to receive the clock CLK. The address counter 141c can count the clock CLK to generate a fuse address ADDR for the decoder 142.

[0058] Figure 5 This is a circuit block diagram of the fuse latch circuit 122 according to an embodiment of the present invention. Figure 5 The fuse latch circuit 122 shown can be used as Figure 3 This is one of many implementation examples of the fuse latch circuit 122 shown. Figure 5 In the illustrated embodiment, the fuse latch circuit 122 includes a record switch 510, an enable switch 520, a read switch 530, a NOT gate 540, a transistor 550, a transistor 560, and a transistor 570. A first terminal of the record switch 510 is coupled to a common terminal of the selection circuit 121. A second terminal of the record switch 510 is coupled to a reference voltage source Vss. The level of the reference voltage source Vss can be determined according to the actual design. For example, the reference voltage source Vss can provide ground voltage or other fixed voltage. The record switch 510 is turned on when any of the fuse circuits 110_1 to 110_n is being recorded. For example, when writing to fuse circuit 110_1, an external writing voltage source (not shown) is coupled to writing pad 111, selection circuit 121 selectively couples the first terminal of antifuse 113 of fuse circuit 110_1 to fuse latch circuit 122, and writing switch 510 is turned on. Therefore, the external writing voltage source can write to antifuse 113 of fuse circuit 110_1. When fuse circuits 110_1 to 110_n are not being written, writing switch 510 is turned off.

[0059] The first terminal of enable switch 520 is coupled to the common terminal of select circuit 121. The first terminal of read switch 530 is coupled to read voltage source Vdd. The level of read voltage source Vdd can be determined according to the actual design. The second terminal of read switch 530 is coupled to the second terminal of enable switch 520. The control terminal of transistor 570 is coupled to the control terminal of read switch 530 and is controlled by the same read signal. When reading / sensing any of fuse circuits 110_1 to 110_n, enable switch 520 and read switch 530 are turned on, and transistor 570 is turned off. When not reading fuse circuits 110_1 to 110_n, enable switch 520 and read switch 530 are turned off, and transistor 570 is turned on. Enable switch 520 is turned on at all times except when recording any of fuse circuits 110_1 to 110_n. The input of NOT gate 540 is coupled to the second terminal of enable switch 520. The output of NOT gate 540 is coupled to the output of fuse latch circuit 122.

[0060] The first terminal (e.g., source) of transistor 550 is coupled to the read voltage source Vdd. The second terminal (e.g., drain) of transistor 550 is coupled to the input of NOT gate 540. The control terminal (e.g., gate) of transistor 550 is coupled to the output of NOT gate 540. The first terminal (e.g., drain) of transistor 560 is coupled to the input of NOT gate 540. The control terminal (e.g., gate) of transistor 560 is coupled to the output of NOT gate 540. The first terminal (e.g., source) of transistor 570 is coupled to the reference voltage source Vss. The second terminal (e.g., drain) of transistor 570 is coupled to the second terminal (e.g., source) of transistor 560. When reading any of fuse circuits 110_1 to 110_n, transistor 570 is off. When not reading fuse circuits 110_1 to 110_n, transistor 570 is on.

[0061] exist Figure 3 In the illustrated embodiment, the local latching circuit 130_1 includes a switch 131 and a latch 132. Implementation details of the other local latching circuits 130_2 to 130_n in the fuse device 100 can be found in [reference needed]. Figure 3 The description of the local latch circuit 130_1 shown is analogous and will not be repeated here. The first terminal of switch 131 is coupled to the output terminal of fuse latch circuit 122 of wide-area latch circuit 120. The second terminal of switch 131 is coupled to the input terminal of latch 132. When wide-area latch circuit 120 reads a corresponding fuse circuit from fuse circuits 110_1 to 110_n, switch 131 is turned on to transmit the fuse information of the corresponding fuse circuit to the input terminal of latch 132. When wide-area latch circuit 120 does not read the corresponding fuse circuit, switch 131 is turned off.

[0062] For example, when the wide-area latching circuit 120 reads fuse circuit 110_1 (the corresponding fuse circuit of the local latching circuit 130_1), switch 131 is turned on to transmit the fuse information of fuse circuit 110_1 to latch 132. When the wide-area latching circuit 120 does not read fuse circuit 110_1, switch 131 is turned off. Similarly, when the wide-area latching circuit 120 reads fuse circuit 110_2 (the corresponding fuse circuit of local latching circuit 130_2), the switch (not shown) of local latching circuit 130_2 is turned on to transmit the fuse information of fuse circuit 110_2 to latch (not shown) of local latching circuit 130_2. When the wide-area latch circuit 120 reads the fuse circuit 110_n (the corresponding fuse circuit of the local latch circuit 130_n), the switch (not shown) of the local latch circuit 130_n is turned on to transmit the fuse information of the fuse circuit 110_n to the latch (not shown) of the local latch circuit 130_n.

[0063] exist Figure 3 In the illustrated embodiment, the control circuit 140 further includes a shift register 143. The shift register 143 is coupled to the controller 141 to receive the source enable pulse EN0 generated by the controller 141. The shift register 143 can shift the source enable pulse EN0 based on the clock CLK to generate multiple enable pulses EN1, EN2, ..., ENn of different phases for the local latch circuits 130_1 to 130_n. A switch (e.g., switch 131) in each of the local latch circuits 130_1 to 130_n can latch the fuse information output by the fuse latch circuit 122 of the wide-area latch circuit 120 according to a corresponding enable pulse from EN1 to ENn.

[0064] Figure 6 This is a timing diagram of word line signals WL1~WLn and enable pulses EN1~ENn, as shown in an embodiment of the present invention. Figure 6 The horizontal axis shown represents time. Figure 6 The enable signal EN and clock CLK shown can be used as Figure 4 The example shown is an example of the enable signal EN and the clock CLK. Figure 6 The word line signals WL1~WLn shown can be used as Figure 3 The example shown is a word line signal WL1 to WLn. Figure 6 The source enable pulses EN0 and EN1 to ENn shown can be used as... Figure 3 The example shown is of the source enable pulse EN0 and enable pulses EN1 to ENn.

[0065] In summary, the wide-area latching circuit 120 of the fuse device 100 described in the above embodiments can sense the resistance state (writing state) of any fuse circuit 110_1 to 110_n at different times, and then output the fuse information of fuse circuits 110_1 to 110_n to the corresponding local latching circuits 130_1 to 130_n at different times. Furthermore, the wide-area latching circuit 120 can collaboratively perform writing operations on any fuse circuit 110_1 to 110_n. That is, multiple fuse circuits 110_1 to 110_n can share the same wide-area latching circuit 120 in a time-sharing manner to save circuit area.

[0066] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A fuse device, characterized in that, The fuse device includes: Multiple fuse circuits; A wide-area latching circuit, coupled to the plurality of fuse circuits, is used to sense the recording state of the plurality of fuse circuits at different times, so as to output fuse information of the plurality of fuse circuits at the different times; and Multiple local latching circuits are coupled to the wide-area latching circuit, wherein each of the multiple local latching circuits latches the fuse information output by the wide-area latching circuit at different times.

2. The fuse device according to claim 1, characterized in that, Each of the plurality of fuse circuits includes: An antifuse having a first end coupled to the wide-area latching circuit; and A recording pad is coupled to the second end of the antifuse to be coupled to an external recording voltage source when the antifuse is being recorded.

3. The fuse device according to claim 1, characterized in that, The wide-area latching circuit includes: A fuse latching circuit having an output terminal coupled to the input terminal of each of the plurality of local latching circuits; and A selection circuit having a common terminal coupled to the fuse latching circuit, wherein a plurality of selection terminals of the selection circuit are coupled to the plurality of fuse circuits in a one-to-one manner, and the selection circuit is configured to selectively couple one of the plurality of fuse circuits to the fuse latching circuit.

4. The fuse device according to claim 3, characterized in that, The fuse latch circuit includes: A recording switch has a first terminal and a second terminal respectively coupled to the common terminal of the selection circuit and a reference voltage source, wherein the recording switch is turned on when any of the plurality of fuse circuits is being recorded, and the recording switch is turned off when the plurality of fuse circuits are not being recorded; An enable switch having a first terminal coupled to the common terminal of the selection circuit; A read switch has a first terminal and a second terminal respectively coupled to a read voltage source and the second terminal of the enable switch; and A NOT gate having an input coupled to the second terminal of the enable switch, wherein the output of the NOT gate is coupled to the output of the fuse latch circuit.

5. The fuse device according to claim 4, characterized in that, The fuse latch circuit also includes: A first transistor has a first terminal and a second terminal respectively coupled to the read voltage source and the input terminal of the NOT gate, wherein the control terminal of the first transistor is coupled to the output terminal of the NOT gate; A second transistor having a first terminal coupled to the input terminal of the NOT gate, wherein the control terminal of the second transistor is coupled to the output terminal of the NOT gate; and The third transistor has a first terminal and a second terminal respectively coupled to the reference voltage source and the second terminal of the second transistor, wherein the control terminal of the third transistor is coupled to the control terminal of the read switch.

6. The fuse device according to claim 3, characterized in that, The fuse device further includes: The controller is used to generate fuse addresses; and A decoder, coupled to the controller, receives the fuse address and decodes the fuse address to generate multiple word line signals for the selection circuit, wherein the selection circuit selects one of the multiple fuse circuits based on the multiple word line signals.

7. The fuse device according to claim 6, characterized in that, The controller includes: Enable signal generation circuit, used to generate enable signal; An oscillator, controlled by the enable signal, selectively generates a clock signal; and An address counter is coupled to the oscillator to receive the clock signal and counts the clock signal to generate the fuse address for the decoder.

8. The fuse device according to claim 1, characterized in that, Each of the plurality of local latching circuits includes: latches; and A switch has a first terminal and a second terminal respectively coupled to the output terminal of the wide-area latching circuit and the input terminal of the latch, wherein the switch is turned on when the wide-area latching circuit reads a corresponding fuse circuit from the plurality of fuse circuits to transmit the fuse information of the corresponding fuse circuit to the input terminal of the latch, and the switch is turned off when the wide-area latching circuit does not read the corresponding fuse circuit.

9. The fuse device according to claim 8, characterized in that, The fuse device further includes: Controller, used to generate source-enabled pulses; and A shift register, coupled to the controller, receives the source enable pulse and shifts the source enable pulse based on a clock to generate multiple enable pulses of different phases for the multiple local latching circuits, wherein each of the multiple local latching circuits latches the fuse information output by the wide-area latching circuit according to a corresponding enable pulse in one of the multiple enable pulses.

10. A method of operating the fuse device as described in claim 1, characterized in that, The operation method includes: The wide-area latching circuit of the fuse device senses the recorded states of multiple fuse circuits of the fuse device at different times; The wide-area latching circuit outputs fuse information from the plurality of fuse circuits at different times; and The fuse information output by the wide-area latching circuit is latched by multiple local latching circuits of the fuse device at different times.

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