Method of manufacturing semiconductor device and semiconductor wafer

Abstract

A method of manufacturing a semiconductor device includes preparing a silicon carbide substrate (12), growing an epitaxial layer (50), and forming a structure (20b, 80). The silicon carbide substrate has an upper surface (12a) on which an alignment mark (20, 20a) of a recessed shape is disposed, and a perpendicular line (12s) perpendicular to the upper surface is inclined toward a [11-20] direction relative to a [0001] direction. The epitaxial layer is grown on the upper surface and covers the alignment mark. The structure is formed on or above the upper surface at a position at a distance P from the alignment mark in the [11-20] direction along the upper surface. The distance P satisfies a relationship D / tanθ < P < 10D / tanθ, where D is a depth of the alignment mark and θ is an inclination angle of the perpendicular line relative to the [0001] direction.

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing a semiconductor device, and also to a semiconductor wafer. Background Technology

[0002] JP2019-056726 A discloses a silicon carbide (SiC) substrate having an upper surface on which alignment marks with recessed shapes are arranged. In this silicon carbide substrate, the upper surface is inclined relative to the (0001) plane such that the off-direction is the [11-20] direction. In other words, in the silicon carbide substrate, a vertical line perpendicular to the upper surface of the silicon carbide substrate is inclined relative to the

[0001] direction towards the [11-20] direction. When an epitaxial layer is grown on the upper surface of the silicon carbide substrate to cover the alignment marks, a facet surface inclined relative to the upper surface of the silicon carbide substrate is formed at a position adjacent to the alignment marks in the [11-20] direction. According to the technology disclosed in JP2019-056726 A, the formation of the facet surface is limited by forming the alignment marks into a predetermined shape. Summary of the Invention

[0003] Even when using the technique disclosed in JP2019-056726 A, there may be instances where the formation of facets is not prevented. Furthermore, due to various limitations, it may be impossible to form the alignment marks disclosed in JP2019-056726 A and prevent the formation of facets. After forming an epitaxial layer to cover the alignment marks, alignment is performed using a recess on the upper surface of the epitaxial layer (i.e., a recess formed following the alignment marks). At this time, if the facets formed on the epitaxial layer interfere with other structures, the alignment device cannot correctly identify the recesses on the upper surface of the epitaxial layer and cannot perform correct alignment. This disclosure proposes a technique that enables correct alignment even when facets are formed in the epitaxial layer.

[0004] According to one aspect of the present disclosure, a method for manufacturing a semiconductor device includes preparing a silicon carbide substrate, growing an epitaxial layer, and forming a structure. The silicon carbide substrate has an upper surface, on which an alignment mark having a recessed shape is disposed, and a vertical line perpendicular to the upper surface of the silicon carbide substrate is inclined toward the [11-20] direction relative to the

[0001] direction. The epitaxial layer is grown on the upper surface of the silicon carbide substrate to cover the alignment mark. The structure is formed on or above the upper surface of the silicon carbide substrate at a position spaced apart from the alignment mark by an interval P in the [11-20] direction along the upper surface of the silicon carbide substrate. The interval P satisfies a relationship of D / tanθ < P < 10D / tanθ, where D is the depth of the alignment mark, and θ is the inclination angle of the vertical line relative to the

[0001] direction.

[0005] Note that preparing the silicon carbide substrate may include bringing the silicon carbide substrate having the alignment mark into a manufacturing facility, or forming the alignment mark on the upper surface of the silicon carbide substrate.

[0006] Forming the structure on or above the upper surface of the silicon carbide substrate may be performed after or before growing the epitaxial layer. In other words, the structure may be formed on the upper surface of the silicon carbide substrate before forming the epitaxial layer, or may be formed above the upper surface of the silicon carbide substrate (i.e., on the upper surface of the epitaxial layer) after forming the epitaxial layer.

[0007] According to experiments by the inventors, it has been found that the width of a facet formed adjacent to the alignment mark when growing the epitaxial layer to cover the alignment mark can be estimated by the inclination angle θ (so-called off-angle) of the upper surface of the silicon carbide substrate relative to the

[0001] direction and the depth D of the alignment mark. In general, the width of the facet is narrower than the width W calculated by the equation W=D / tanθ. Therefore, by setting the interval P to satisfy the relationship D / tanθ < P, it is possible to restrict the facet from interfering with the structure. If the interval P is unnecessarily widened, the region occupied by the interval P becomes wider, which leads to a reduction in the number of semiconductor devices manufactured from the silicon carbide substrate. As described above, by setting the interval P to satisfy the relationship D / tanθ < P < 10D / tanθ (i.e., W < P < 10W), interference between the facet and the structure can be restricted without unnecessarily widening the interval P. Since the interference between the facet and the structure can be restricted, correct alignment can be performed using a recessed portion on the upper surface of the epitaxial layer (i.e., a recessed portion formed following the alignment mark).

[0008] According to another aspect of the present disclosure, a semiconductor wafer includes a base substrate, an epitaxial layer, and a structure. The base substrate is made of silicon carbide and has an upper surface, on which an alignment mark having a recessed shape is arranged. A vertical line perpendicular to the upper surface of the base substrate is inclined toward the [11-20] direction relative to the

[0001] direction. The epitaxial layer is disposed on the upper surface of the base substrate and covers the alignment mark. The structure is disposed on the upper surface of the base substrate or the upper surface of the epitaxial layer. The structure is arranged on the upper surface of the base substrate at a position spaced apart from the alignment mark by an interval P along the [11-20] direction. The interval P satisfies the relationship D / tanθ < P < 10D / tanθ, where D is the depth of the alignment mark, and θ is the inclination angle of the vertical line relative to the

[0001] direction.

[0009] According to the semiconductor wafer described above, correct alignment can be performed using the recessed portion on the upper surface of the epitaxial layer. Brief Description of the Drawings

[0010] The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description with reference to the accompanying drawings. In the accompanying drawings: Figure 1 is a plan view of a silicon carbide substrate; Figure 2 is a cross-sectional view of the silicon carbide substrate; Figure 3 is a plan view of an alignment mark on the upper surface of the silicon carbide substrate; Figure 4 is a cross-sectional view illustrating a first manufacturing method of the alignment mark; Figure 5 is a cross-sectional view illustrating a process in a second formation method of the alignment mark; Figure 6 is a cross-sectional view illustrating a process subsequent to the process shown in the second formation method of the alignment mark in Figure 5 ; Figure 7 is a cross-sectional view illustrating a process subsequent to the process shown in the second formation method of the alignment mark in Figure 6 ; Figure 8 is a cross-sectional view illustrating a process in a third formation method of the alignment mark; Figure 9 is a cross-sectional view illustrating a process subsequent to the process shown in the third formation method of the alignment mark in Figure 8 ; Figure 10 is a cross-sectional view illustrating a process subsequent to the process shown in the third formation method of the alignment mark in Figure 9A cross-sectional view of the process following the one shown; Figure 11 It is an enlarged cross-sectional view of the alignment marks; Figure 12 It is a plan view of the alignment marks on the upper surface of the silicon carbide layer; Figure 13 It is a cross-sectional view showing the process of epitaxial growth; Figure 14 This shows that during the epitaxial growth process... Figure 13 A cross-sectional view of the process following the one shown; Figure 15 This shows that during the epitaxial growth process... Figure 14 A cross-sectional view of the process following the one shown; Figure 16 This shows that during the epitaxial growth process... Figure 15 A cross-sectional view of the process following the one shown; Figure 17 This is an enlarged cross-sectional view showing the alignment marks according to the second embodiment; Figure 18 This is a cross-sectional view showing the epitaxial growth process according to the second embodiment; Figure 19 This is a cross-sectional view showing the structure formation process according to the second embodiment; Figure 20 This is a cross-sectional view showing the structural formation process of a variant according to the second embodiment; Figure 21 This is a plan view showing alignment marks formed on the upper surface of a silicon carbide substrate according to a variant. Detailed Implementation

[0011] (First embodiment) In the manufacturing method of the first embodiment, the semiconductor device is made of Figure 1 and Figure 2 The silicon carbide substrate 12 shown is manufactured as follows. The silicon carbide substrate 12 is made of 4H-SiC. In the following text, the thickness direction of the silicon carbide substrate 12 is referred to as the z-direction, a direction perpendicular to the z-direction is referred to as the x-direction, and a direction perpendicular to both the z and x directions is referred to as the y-direction. The x and y directions are parallel to the upper surface 12a of the silicon carbide substrate 12. Figure 2 As shown, the [1-100] direction of the silicon carbide substrate 12 is aligned with the y-direction. The (0001) surface of the silicon carbide substrate 12 is tilted relative to the upper surface 12a of the silicon carbide substrate 12 about an angle θ in the [1-100] direction. In other words, the (0001) surface is tilted relative to the upper surface 12a in a cross-section including both the [11-20] and

[0001] directions. Figure 2The vertical line 12s in the diagram represents a line perpendicular to the upper surface 12a. Since the (0001) surface is inclined at an angle θ relative to the upper surface 12a, the vertical line 12s is inclined at an angle θ relative to the

[0001] direction towards the [11-20] direction. Note that the angle θ can be 10 degrees or less, or it can be 5 degrees or less. For example, the angle θ can be approximately 4 degrees. Figure 1 As shown, when the upper surface 12a of the silicon carbide substrate 12 is viewed from above, the x-direction extends along the [11-20] direction.

[0012] In the manufacturing method of the first embodiment, an alignment mark formation process is first performed. During the alignment mark formation process, alignment marks are formed on the upper surface of the silicon carbide substrate 12. Figure 3 The alignment marks 20 are shown. Each of the alignment marks 20 has a recessed shape provided on the upper surface 12a of the silicon carbide substrate 12. Each alignment mark 20 has a long side extending in the y-direction and a short side extending in the x-direction. Therefore, when the upper surface 12a of the silicon carbide substrate 12 is viewed from above, the side surface 24 (i.e., the edge portion) of each alignment mark 20 located in the [11-20] direction is perpendicular to the [11-20] direction. The alignment marks 20 are arranged such that they have a spacing P between them in the x-direction. Although in Figure 1 Not shown, but the upper surface 12a of the silicon carbide substrate 12 has a component region for forming a semiconductor device structure and an external region outside the component region. The external region is the region removed when the silicon carbide substrate 12 is divided into multiple semiconductor devices by dicing or the like. Each alignment mark 20 is formed in the external region of the upper surface 12a of the silicon carbide substrate 12.

[0013] During the alignment mark formation process, alignment marks 20 can be formed using various methods. The following will refer to... Figure 4 A first method for forming the alignment mark 20 is described. In the first method, firstly, as... Figure 4 As shown, a resist mask 30 with openings 30a is formed on the upper surface 12a of the silicon carbide substrate 12. Next, the upper surface 12a of the silicon carbide substrate 12 is etched through the openings 30a by anisotropic etching. Therefore, each alignment mark 20 with a recessed shape is formed in each opening 30a. After forming the alignment marks 20, the resist mask 30 is removed.

[0014] Reference Figures 5 to 7 The second method for forming alignment mark 20 is described. Figures 5 to 7 Cross-sections of element region 13 and outer region 14 are shown. In the second forming method, firstly, as... Figure 5As shown, a hard mask 32 (e.g., a mask made of silicon dioxide) is formed on the upper surface 12a of the silicon carbide substrate 12. The hard mask 32 is a mask used to control the range of ion implantation into the silicon carbide substrate 12. Next, a resist mask 34 having an opening 34a is formed on the hard mask 32. Then, as... Figure 6 As shown, the hard mask 32 is etched through the opening 34a using anisotropic etching. Therefore, the opening 32a is formed in the hard mask 32. Since the opening 32a is formed to reach the silicon carbide substrate 12, the upper surface 12a of the silicon carbide substrate 12 is over-etched when forming the opening 32a. Therefore, a recessed shape is formed on the upper surface 12a of the silicon carbide substrate 12. The recessed shape formed in the outer region 14 becomes the alignment mark 20. After forming the opening 32a in the hard mask 32, the resist mask 34 is removed. Next, n-type or p-type impurity ions are implanted into the upper surface 12a of the silicon carbide substrate 12 through the hard mask 32. Therefore, as... Figure 7 As shown, a diffusion layer 40 is formed in the silicon carbide substrate 12 below the opening 32a. In the element region 13, the diffusion layer 40 is formed at the desired location. In the outer region 14, the diffusion layer 40 is formed below the alignment mark 20. Even though the diffusion layer 40 is formed below the alignment mark 20, there is no particular problem. As described above, in the second formation method, the alignment mark 20 is formed by utilizing the phenomenon that the upper surface 12a of the silicon carbide substrate 12 is over-etched when the opening 32a is formed in the hard mask 32 for ion implantation.

[0015] Reference Figures 8 to 10 This describes the third method for forming alignment mark 20. Figures 8 to 10 Cross-sections of element region 13 and outer region 14 are shown. In the third forming method, firstly, as... Figure 8 As shown, a resist mask 36 with an opening 36a is formed on the upper surface 12a of the silicon carbide substrate 12. Next, n-type or p-type impurity ions are implanted into the upper surface 12a of the silicon carbide substrate 12 through the resist mask 36. Therefore, as... Figure 9 As shown, a diffusion layer 40 is formed in the silicon carbide substrate 12 below the opening 36a. In the element region 13, the diffusion layer 40 is formed at the desired location. Furthermore, in the outer region 14, the diffusion layer 40 is formed at the location where alignment marks 20 are to be formed. Next, the silicon carbide substrate 12 is etched through the opening 36a using anisotropic etching. Therefore, as... Figure 10 As shown, a recessed shape is formed on the upper surface 12a of the silicon carbide substrate 12. The recessed shape formed in the outer region 14 is called an alignment mark 20. After the alignment mark 20 is formed, the resist mask 36 is removed.

[0016] Figure 11 It shows along Figure 3 A cross-sectional view of the XI-XI line. In other words, Figure 11 A cross-sectional view of alignment marks 20a and 20b along the x-direction is shown. Although Figure 11 Alignment marks 20a and 20b are shown, but they can also be aligned with... Figure 11 The same shape shown forms other alignment marks 20. For example... Figure 11 As shown, the depth D of each of the alignment marks 20 is less than the width Wa of each of the alignment marks 20 in the x-direction. A spacing P is set between each alignment mark 20 in the x-direction.

[0017] In the manufacturing method of the first embodiment, an epitaxial growth process is performed after the alignment mark formation process. During the epitaxial growth process, epitaxial growth is performed on the upper surface 12a of the silicon carbide substrate 12. Figure 13 The silicon carbide layer 50 is shown. The silicon carbide layer 50 is formed to cover each alignment mark 20. When each alignment mark 20 is covered by the silicon carbide layer 50, a recessed shape following the recessed shape of the alignment mark 20 is formed on the upper surface of the silicon carbide layer 50. The recessed shape following the shape of the alignment mark 20 and formed on the upper surface of the silicon carbide layer 50 is referred to below as alignment mark 60. Figure 12 As shown, a facet 60F is formed at a portion of each alignment mark 60. The formation of the facet 60F will be described below.

[0018] Figures 13 to 16 This illustrates how a silicon carbide layer 50 is epitaxially grown on the upper surface 12a of a silicon carbide substrate 12 during the epitaxial growth process. In the following description, the silicon carbide substrate 12 before the epitaxial growth process is referred to as the base substrate 12b, and the base substrate 12b and the silicon carbide layer 50 collectively are referred to as the silicon carbide substrate 12. Figure 13 As shown, when a silicon carbide layer 50 is grown on the base substrate 12b, alignment marks 60 are formed on the upper surface of the silicon carbide layer 50. Alignment marks 60 have a recessed shape that follows the recessed shape of alignment marks 20. In the following description, alignment marks 60 following the recessed shape of alignment marks 20a may be referred to as alignment mark 60a, and alignment marks 60 following the recessed shape of alignment marks 20b may be referred to as alignment mark 60b. Figure 13As shown, a silicon carbide layer 50 is grown to have a substantially uniform film thickness within a range extending above the upper surface 12a of the substrate 12b, the side surface 22 of the alignment mark 20 in the [-1-120] direction, and the bottom surface 23 of the alignment mark 20. Hereinafter, the film thickness of the silicon carbide layer 50 on the upper surface 12a of the substrate 12b (more specifically, the film thickness of the portion with uniform film thickness) is referred to as film thickness T. Almost no silicon carbide layer 50 is grown on the side surface 24 of the alignment mark 20 in the [11-20] direction. Therefore, the silicon carbide layer 50 grows unevenly on the upper surface 12a within a range adjacent to the alignment mark 20 in the [11-20] direction. Within this range, the silicon carbide layer 50 is grown such that the film thickness of the silicon carbide layer 50 increases with increasing distance from the alignment mark 20, and the surface of the silicon carbide layer 50 becomes parallel to the (0001) plane. The surface of the silicon carbide layer 50 parallel to the (0001) plane is a small plane 60F.

[0019] When the film thickness T of silicon carbide layer 50 is from Figure 13 When the shown state is further increased, we get Figure 14 The state shown. In Figure 14 In the middle, the dashed line 50x indicates that in Figure 13 The surface of the silicon carbide layer 50 in the state of [condition], and the increase in film thickness ΔT1 represents [the change in thickness from [previous state]]. Figure 13 The increased film thickness is due to the state of the membrane. For example... Figure 14 As shown, even with an increase in film thickness T, the silicon carbide layer 50 does not grow on the original facet 60F. Furthermore, as film thickness T increases, the silicon carbide layer 50 grows such that the surface of the silicon carbide layer 50 adjacent to the original facet 60F in the [11-20] direction is parallel to the (0001) plane. That is, the facet 60F extends in the [11-20] direction. Figure 13 and Figure 14 The width Wf in the figure represents the width of the small plane 60F in the x-direction. For example... Figure 13 and Figure 14 As shown, the width Wf of the facet 60F increases with increasing film thickness T. Therefore, when the film thickness T is less than the depth D of the alignment mark 20, the width Wf of the facet 60F increases with increasing film thickness T. In this case, the width Wf of the facet 60F relatively accurately satisfies the relationship Wf = T / tanθ.

[0020] When the film thickness T is from Figure 14 When the state is further increased, the film thickness T reaches as shown Figure 15 The depth D of the alignment mark 20 is shown. Thus, the alignment mark 20 is filled with the silicon carbide layer 50. In this state (i.e., T=D), the width Wf of the facet 60F relatively accurately satisfies the relationship Wf=D / tanθ.

[0021] When the film thickness T from Figure 15 the state shown further increases, the silicon carbide layer 50 grows as shown in Figure 16 . Figure 16 , the dashed line 50y represents the surface of the silicon carbide layer 50 in the state of Figure 15 , and the film thickness increase amount ΔT2 represents the film thickness increased from the state of Figure 15 . Figure 16 As shown in the film thickness increase amount ΔT2 in, after filling the alignment mark 20, the silicon carbide layer 50 grows substantially uniformly over the entire surface. In other words, the silicon carbide layer 50 grows on the facet 60F with a uniform film thickness similar to that of other surfaces. When the silicon carbide layer 50 is grown in this manner, the width Wf of the facet 60F hardly changes even if the film thickness T of the silicon carbide layer 50 increases. Therefore, when the film thickness T is greater than the depth D, the width Wf of the facet 60F hardly changes even if the film thickness T increases. Therefore, when the film thickness T is greater than the depth D, the width Wf of the facet 60F relatively accurately satisfies the relationship Wf=D / tanθ.

[0022] As described above, when the film thickness T is less than the depth D (i.e., in the states of Figure 13 and Figure 14 ), the width Wf of the facet 60F can relatively accurately satisfy the relationship Wf=T / tanθ. In this case, since T<D, the width Wf relatively accurately satisfies the relationship Wf<D / tanθ. Further, when the film thickness T is greater than or equal to the depth D (i.e., in the states of Figure 15 and 16 ), the width Wf relatively accurately satisfies the relationship Wf=D / tanθ. Therefore, in general, regardless of the film thickness T, the width Wf is not larger than the width W calculated by the equation W=D / tanθ. Therefore, by making the interval P between the alignment marks 20a and 20b in the x direction larger than the width W calculated by the above equation, it is possible to restrict the facet 60F of the alignment mark 60a from interfering with the alignment mark 60b.

[0023] Note that the actual width Wf of the facet 60F may be greater than the calculated width W due to the influence of manufacturing conditions and the like. Therefore, it is preferable to set the interval P to have a margin relative to the calculated width W. However, if the interval P is increased more than necessary relative to the calculated width W, the area occupied by the plurality of alignment marks 20 becomes large, which leads to a reduction in the number of semiconductor devices manufactured from the silicon carbide substrate 12. In addition, when the area occupied by the plurality of alignment marks 20 becomes large, the imaging magnification when the plurality of alignment marks are imaged by the alignment camera becomes small, and the alignment accuracy deteriorates. According to various experiments conducted by the inventors, it has been found that the actual width Wf of the facet 60F does not reach ten times the calculated width W. Therefore, if the interval P is set to satisfy the relationship W<P<10W (that is, the relationship D / tanθ<P<10D / tanθ), it is possible to limit the interference between the facet 60F of the alignment mark 60 and the adjacent alignment mark 60 and the expansion of the area occupied by the alignment mark 20. In the manufacturing method of the first embodiment, since the interval P satisfies the relationship W<P<10W, it is possible to limit the interference between the facet 60F of the alignment mark 60 and the adjacent alignment mark 60 and the expansion of the area occupied by the alignment mark 20.

[0024] In the manufacturing method of the first embodiment, the alignment process is performed using the alignment mark 60 after the epitaxial growth process. For example, alignment is performed using the alignment mark 60, and etching, ion implantation, and the like can be performed on the silicon carbide layer 50, a semiconductor layer other than the silicon carbide layer 50, or other layers such as an electrode layer, an insulating layer, and the like. For example, when ions are implanted into the grown silicon carbide layer 50, the alignment mark 60 can be used to perform alignment to accurately form an opening in the ion implantation mask, and ions can be implanted into the silicon carbide layer 50 through the ion implantation mask. Since the facet 60F of the alignment mark 60 does not interfere with other alignment marks 60, the alignment using the alignment mark 60 can be performed correctly. In addition, since the interval P between the alignment marks 60 is relatively narrow, the magnification can be increased when the alignment marks 60 are imaged using the alignment camera. Therefore, alignment can be performed with high accuracy.

[0025] After that, the silicon carbide substrate 12 is cut and divided into a plurality of pieces, thereby manufacturing a plurality of semiconductor devices.

[0026] Figure 16 The illustrated semiconductor wafer (that is, the silicon carbide substrate 12) has the following configuration. The semiconductor wafer (that is, the silicon carbide substrate 12) has a base substrate 12b and an epitaxial layer (that is, the silicon carbide layer 50). The base substrate 12b has an upper surface 12a, and alignment marks 20a having a recessed shape are provided on the upper surface 12a. As shown in Figure 2 as shown in, a vertical line 12s perpendicular to the upper surface 12a is inclined toward the [11-20] direction relative to the

[0001] direction. As shown in Figure 16As shown, the epitaxial layer (i.e., the silicon carbide layer 50) is disposed on the upper surface 12a of the base substrate 12b, and covers the alignment mark 20a. On the upper surface 12a of the base substrate 12b, the alignment mark 20b having a recessed shape is provided as a structure. This structure (i.e., the alignment mark 20b) is arranged on the upper surface 12a of the substrate 12b at a position spaced apart from the alignment mark 20a by an interval P along the [11-20] direction. The interval P satisfies the relationship D / tanθ < P < 10D / tanθ, where D is the depth of the alignment mark 20a, and θ is the inclination angle (i.e., off-angle) of the vertical line 12s perpendicular to the upper surface 12a relative to the

[0001] direction. Therefore, in this semiconductor wafer, the facet 60F of the alignment mark 60a does not interfere with the alignment mark 60b, and accurate alignment can be performed using the alignment mark 60a. That is, by using this semiconductor wafer, a semiconductor device can be appropriately manufactured.

[0027] (Second Embodiment) In the manufacturing method of the second embodiment, as in the first embodiment, from Figure 1 and Figure 2 The semiconductor device is manufactured from the silicon carbide substrate 12 shown. In this manufacturing method, the alignment mark 20 having a recessed shape is formed on the upper surface 12a of the silicon carbide substrate 12 in a manner similar to that in the first embodiment. For example, as shown in Figure 17 As shown, the alignment mark 20 having a depth D smaller than the width Wa is formed. Next, as shown in Figure 18 As shown, the silicon carbide layer 50 is epitaxially grown on the silicon carbide substrate 12 (i.e., the base substrate 12b) to cover the alignment mark 20. Therefore, the alignment mark 60 following the shape of the alignment mark 20 is formed on the upper surface of the silicon carbide layer 50. Further, a facet 60F is formed at a position adjacent to the alignment mark 60 in the [11-20] direction.

[0028] Next, as shown in Figure 19 As shown, the structure 80 having a protruding shape is formed on the upper surface of the silicon carbide substrate 12 (i.e., the upper surface of the silicon carbide layer 50). Note that the structure 80 may be a conductor, an insulator, or a semiconductor. The structure 80 may be a part of a semiconductor device or a part of a mask. In the present embodiment, the structure 80 having a protruding shape is formed at a position away from the alignment mark 20 along the [11-20] direction. An interval P is provided between the alignment mark 20 and the structure 80. The interval P is set to satisfy the relationship W < P < 10W, that is, the relationship D / tanθ < P < 10D / tanθ. Therefore, interference between the structure 80 and the facet 60F can be restricted without increasing the interval between the structure 80 and the alignment mark 20 more than necessary.

[0029] Thereafter, an alignment process is performed using the alignment mark 60. Since the facet 60F of the alignment mark 60 does not interfere with the structure 80, alignment can be performed correctly using the alignment mark 60.

[0030] Thereafter, the silicon carbide substrate 12 is cut and divided into a plurality of pieces, so that a plurality of semiconductor devices are manufactured.

[0031] Figure 19 The semiconductor wafer (that is, the silicon carbide substrate 12) shown in has the following configuration. The semiconductor wafer (that is, the silicon carbide substrate 12) has a base substrate 12b and an epitaxial layer (that is, the silicon carbide layer 50). The base substrate 12b has an upper surface 12a, and the alignment mark 20 having a recessed shape is provided on the upper surface 12a. As Figure 2 shown, a vertical line 12s perpendicular to the upper surface 12a is inclined toward the [11-20] direction relative to the

[0001] direction. As Figure 19 shown, the epitaxial layer (that is, the silicon carbide layer 50) is provided on the upper surface 12a of the base substrate 12b, and covers the alignment mark 20. The structure 80 is provided on the upper surface of the epitaxial layer (that is, the silicon carbide layer 50). The structure 80 is arranged on the upper surface 12a of the base substrate 12b at a position spaced apart from the alignment mark 20a by an interval P in the [11-20] direction. The interval P satisfies the relationship D / tanθ<P<10D / tanθ, where D is the depth of the alignment mark 20a, and θ is the inclination angle (that is, the off-angle) of the vertical line 12s perpendicular to the upper surface 12a relative to the

[0001] direction. Therefore, in this semiconductor wafer, the facet 60F does not interfere with the structure 80, and correct alignment can be performed using the alignment mark 60.

[0032] In the above-described second embodiment, the structure 80 is a protruding portion provided on the upper surface of the silicon carbide layer 50. However, as Figure 20 shown, the structure 80 may also be a recessed portion provided on the upper surface of the silicon carbide layer 50. This configuration can also restrict interference between the structure 80 and the facet 60F.

[0033] In the above-described first embodiment and second embodiment, each alignment mark 20 has a rectangular shape on the upper surface 12a of the silicon carbide substrate 12. Each alignment mark 20 may also have other shapes. In these cases, the side surface of each alignment mark 20 located in the [11-20] direction does not necessarily have to be perpendicular to the [11-20] direction. For example, as Figure 21 shown, the side surface 24 (that is, the edge portion) of each alignment mark located in the [11-20] direction may extend along a direction that obliquely intersects the [11-20] direction.

[0034] In the above first embodiment and second embodiment, the silicon carbide layer 50 is grown such that the thickness T of the silicon carbide layer 50 is greater than the depth D of the alignment mark 20. Alternatively, the silicon carbide layer 50 may be grown such that the thickness T of the silicon carbide layer 50 is less than the depth D of the alignment mark 20. Even in this case, by setting the interval P to satisfy the relationship D / tan θ < P < 10D / tan θ, interference between the facet 60F and other structures can be restricted without increasing the interval P beyond a necessary extent.

[0035] In the above first embodiment and second embodiment, the alignment mark 20 is formed. Alternatively, a silicon carbide substrate 12 on which the alignment mark 20 satisfying the relationship D / tan θ < P < 10D / tan θ has been pre-formed may be purchased and brought into a manufacturing facility. Even if the same epitaxial growth process and alignment process as those in the first and second embodiments are performed on the silicon carbide substrate 12 on which the alignment mark 20 is pre-formed, the same effects as those in the first and second embodiments can be obtained.

[0036] The silicon carbide layer 50 in the first embodiment and the second embodiment is an example of an epitaxial layer. The alignment marks 20a, 20 in the first embodiment and the second embodiment are examples of a first alignment mark. The alignment mark 20b in the first embodiment is an example of a recess-shaped structure formed on the upper surface of the silicon carbide substrate before the epitaxial layer is formed. The structure 80 of the second embodiment is an example of a protruding-shaped or recess-shaped structure formed on the upper surface of the epitaxial layer. The alignment marks 60a and 60 of the first embodiment and the second embodiment are examples of a second alignment mark.

[0037] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing the application. Furthermore, the technology shown in this specification or the drawings achieves a plurality of objectives at the same time, and achieving one of the objectives itself has technical practicability.

Claims

1. A method of manufacturing a semiconductor device, comprising: preparing a silicon carbide substrate, the silicon carbide substrate having an upper surface, an alignment mark having a recessed shape being disposed on the upper surface, a vertical line perpendicular to the upper surface of the silicon carbide substrate being inclined toward the [11-20] direction relative to the [0001] direction; growing an epitaxial layer on the upper surface of the silicon carbide substrate to cover the alignment mark; and forming a structure on or above the upper surface of the silicon carbide substrate, wherein the structure is formed on the upper surface of the silicon carbide substrate at a position spaced apart from the alignment mark by a pitch P along the [11-20] direction, and the pitch P satisfies a relationship of D / tanθ<P<10D / tanθ, where D is the depth of the alignment mark, and θ is the inclination angle of the vertical line relative to the [0001] direction.

2. The manufacturing method according to claim 1, wherein forming the structure includes forming the structure having a recessed shape on the upper surface of the silicon carbide substrate before growing the epitaxial layer.

3. The manufacturing method according to claim 1, wherein forming the structure includes forming the structure having a protruding shape or a recessed shape on the upper surface of the epitaxial layer.

4. The manufacturing method according to claim 1, wherein when the upper surface of the silicon carbide substrate is viewed from above, an edge portion of the alignment mark located in the [11-20] direction is perpendicular to the [11-20] direction.

5. The manufacturing method according to any one of claims 1 to 4, wherein the alignment mark is a first alignment mark, growing the epitaxial layer includes forming a second alignment mark on the upper surface of the epitaxial layer, the second alignment mark having a recessed shape that follows the recessed shape of the first alignment mark, and the manufacturing method further comprises performing alignment using the second alignment mark.

6. A semiconductor wafer, comprising: a base substrate, which is made of silicon carbide and has an upper surface, an alignment mark having a recessed shape being disposed on the upper surface, a vertical line perpendicular to the upper surface of the base substrate being inclined toward the [11-20] direction relative to the [0001] direction; an epitaxial layer, which is disposed on the upper surface of the base substrate and covers the alignment mark; and a structure disposed on the upper surface of the base substrate or the upper surface of the epitaxial layer, wherein the structure is disposed on the upper surface of the base substrate at a position spaced apart from the alignment mark by a pitch P along the [11-20] direction, and the pitch P satisfies a relationship of D / tanθ<P<10D / tanθ, where D is the depth of the alignment mark, and θ is the inclination angle of the vertical line relative to the [0001] direction.

7. The semiconductor wafer according to claim 6, wherein the structure is a recess portion disposed on the upper surface of the base substrate.

8. The semiconductor wafer according to claim 6, wherein the structure is a protruding portion or a recess portion disposed on the upper surface of the epitaxial layer.

9. The semiconductor wafer of claim 6, wherein when the upper surface of the base substrate is viewed from above, the edge of the alignment mark located in the [11-20] direction is perpendicular to the [11-20] direction.

10. The semiconductor wafer according to any one of claims 6 to 9, wherein The alignment mark is the first alignment mark, and The upper surface of the epitaxial layer has a second alignment mark, the second alignment mark having a recessed shape that follows the recessed shape of the first alignment mark.

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