T-shaped source region negative capacitance heterojunction tunneling field effect transistor based on double-gate tfet and preparation method thereof

Abstract

The application relates to a T-shaped source region negative capacitance heterojunction tunneling field effect transistor based on a double-gate TFET and a preparation method thereof; the technical problems of a steep subthreshold swing characteristic and a low on-state current of an existing double-gate T-shaped source region heterojunction TFET (T-source-HJTFET) are solved; the transistor comprises a T-shaped source region, a channel region, a drain region, a silicon-based epitaxial layer and a substrate which are sequentially connected; a buried groove is horizontally arranged at the middle of the upper end of the channel region; a small-diameter section of the source region is arranged in the buried groove; high-k gate oxide layers are arranged on the left and right sides of the source region and the channel region, and ferroelectric layers are arranged on the high-k gate oxide layers; a source electrode is arranged at the upper end of the source region, a drain electrode is arranged below the drain region, and a gate electrode is arranged at the left end of the left ferroelectric layer and the right end of the right ferroelectric layer; the source region is P-type doped or N-type doped, the doping type of the channel region is the same as that of the source region, and the doping type of the drain region is opposite to that of the source region; the source region is prepared by using Si 1‑x Ge x , the channel region and the drain region are prepared by using silicon; and the application further provides a preparation method of the transistor.

Description

Technical Field

[0001] This invention belongs to the field of microelectronic device technology and relates to a dual-gate tunneling field-effect transistor and its fabrication method. Specifically, it relates to a T-type source region negative capacitance heterojunction tunneling field-effect transistor based on a dual-gate TFET and its fabrication method, which can be used in the fabrication of semiconductor devices in the field of high-performance, low-power integrated circuits. Background Technology

[0002] For over half a century, as the feature size of metal-oxide-semiconductor field-effect transistors (MOSFETs) has continued to shrink, their total power consumption and off-state leakage current have inevitably increased. Simultaneously, due to the carrier transport mechanism of MOSFETs, their subthreshold swing (SS) is limited to above 60 mV / dec at room temperature. Clearly, these limitations render MOSFETs unsuitable for future demands for ultra-low-power integrated circuits.

[0003] In 1934, Zener et al. first proposed the tunneling theory. In 1958, Esaki et al. discovered that PN junction diodes exhibit negative resistance characteristics under forward bias conditions (see ZENER CA theory of the electrical breakdown of solid dielectrics. Series A, Containing Papers of a Mathematical and Physical Character[J]. 1934, 145(855): 523-529.). This is due to band-to-band tunneling, marking the first experimental discovery of the band-to-band tunneling phenomenon. Based on this concept, the tunneling field-effect transistor (TFET) breaks the subthreshold swing limitation of MOSFETs with its inter-band tunneling conduction mechanism, greatly reducing device power consumption. Research on the "spontaneous polarization" behavior of ferroelectric thin films can be traced back to the 1950s. According to the ferroelectric model, ferroelectric thin film materials exhibit typical negative capacitance effects in their energy-charge and charge-voltage relationship curves due to their unique "spontaneous polarization" phenomenon. However, it was not until 2008 that researchers proposed the concept of negative capacitance effect and NCFET. Inventors S. Salahuddin and S. Dutta believe that the main reason is that the negative capacitance effect in ferroelectric thin films is not stable (see Salahuddin S, Datta S. Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices[J].Nano Lettes,2008,8(2):405-410.).To address the aforementioned issue of "the existence of negative capacitance," the Swiss Federal Institute of Technology in Lausanne (EPFL) indirectly demonstrated the existence of negative capacitance in 2008 and 2010 through enhanced total gate capacitance and gate voltage amplification effects (see Hoffmann M, Fengler F, Herzig M, et al. Unveiling the double-well energy landscape in a ferroelectric layer[J]. Nature, 2019, 565: 464-467. & Rusu A, Salvatore G, Jiménez D, et al. Metal-Ferroelectric-Meta-Oxide-semiconductor field effect transistor with sub-60mV / decade subthreshold swing and internal voltage amplification[C]. IEEE Electron Devices Meeting (IEDM), 2010: 395-398.). In 2019, NaMLabg GmbH in Germany and Xi'an University of Electronic Science and Technology confirmed the existence of the negative capacitance effect again through experimentally measured negative slope "S"-shaped curves (see Hoffmann M, Max B, Mittmann T, et al. Demonstration of High-speed Hysteresis-free Negative Capacitance in Ferroelectric Hf0.5Zr0.5O2[C].IEEE Electron Devices Meeting (IEDM), 2018: 727-730. & Zhou J, Han G, Xu N, et al. Incomplete Dipoles Flipping Produced Near Hysteresis-free Negative Capacitance Transistors[J].IEEE Electron Device Letters, 2018, 40(2): 329-332.). Currently, by adjusting the ratio of ferroelectric negative capacitance to transistor capacitance, the hysteresis window can be reduced to almost zero.The mathematical model of negative capacitance that closely matches the experimental figures did not appear until 2017. However, there is still no scientific method to measure the data in the model (see Tan Xin, Zhai Yahong. Research progress of ferroelectric negative capacitance transistors [J]. Materials Reports, 2019, 33(03): 433-437). It is still in the development and improvement stage and requires a lot of research and exploration.

[0004] Traditional TFETs suffer from low on-state current, typically two to three orders of magnitude lower than MOSFETs, which is a significant drawback. Ferroelectric negative capacitance transistors, as a newly emerging type of low-power transistor, hold great potential. Introducing ferroelectric negative capacitance material onto the gate of a MOSFET can reduce the subthreshold swing to below 60mV / dec, and maintain a constant drive current even with a significant reduction in VDD. This significantly reduces the power consumption of integrated circuits, allowing for further reduction in device size. Recently, ferroelectric materials have been introduced into tunneling field-effect transistors (TFETs), providing new insights into achieving steeper subthreshold swings, higher on-state currents, and lower off-state leakage currents. Figure 2 The device shown is an existing dual-gate TFET (DGTFET), whose dual-gate structure exhibits twice the gate control capability in the channel region, improving the on-state current. However, the subthreshold swing characteristics and on-state current of this structure are not particularly outstanding. Therefore, there is a need to develop a tunneling field-effect transistor that improves the subthreshold swing while maintaining high on-state current and low off-state leakage current. Summary of the Invention

[0005] To address the technical problems of steep subthreshold swing characteristics and low on-state current in existing dual-gate T-source heterojunction TFETs (T-source-HJTFETs), this invention provides a T-source negative capacitance heterojunction tunneling field-effect transistor based on a dual-gate TFET and its fabrication method.

[0006] This invention utilizes dual-gate T-type source region engineering, heterojunction engineering, and ferroelectric negative capacitance engineering. It leverages the gate control capability of dual-gate tunneling field-effect transistors and uses the MFIS (metal-ferroelectric-insulator-semiconductor) structure to more easily achieve stable capacitance matching.

[0007] The aforementioned engineering and structural methods are used to optimize the TFET as a whole, aiming to improve device performance in all aspects. Significant improvements are made to the on-state current, off-state leakage current, and subthreshold swing of traditional TFETs. Through research on structural optimization and performance prediction of tunneling field-effect transistors, the TFET can meet the requirements of ultra-low power integrated circuits.

[0008] The technical solution adopted in this invention is:

[0009] A T-type source region negative capacitance heterojunction tunneling field-effect transistor based on a dual-gate TFET, characterized by:

[0010] It includes a T-shaped source region and a channel region, a drain region, a silicon-based epitaxial layer, and a substrate connected from top to bottom;

[0011] A burial groove is provided laterally in the middle of the upper end of the channel area, thereby dividing the channel area into a thick end and two thin ends. The thickness of the leaking area is equal to the thickness of the thick end of the channel area.

[0012] The small-diameter section structure of the source region is adapted to the structure of the burial trench, and the thickness of the large-diameter section of the source region is equal to the thickness of the thick end of the trench region; the small-diameter section of the source region is set in the burial trench.

[0013] Both sides of the source region and the channel region are covered with high-k gate oxide layers, and ferroelectric layers are provided at the left end of the left high-k gate oxide layer and the right end of the right high-k gate oxide layer.

[0014] A source electrode is provided at the upper end of the source region, a drain electrode is provided below the drain region, and gate electrodes are provided at the left end of the left ferroelectric layer and the right end of the right ferroelectric layer.

[0015] The source region is P-type doped or N-type doped, the channel region has the same doping type as the source region, and the drain region has the opposite doping type to the source region.

[0016] The source region uses Si 1-x Ge x In the fabrication process, the channel and drain regions are fabricated using silicon, thereby forming Si between the source and channel regions. 1-x Ge x / Si tunneling heterojunction, where x represents the germanium content in SiGe, 0 < x < 1.

[0017] Furthermore, the high-k gate oxide layer is prepared using a high-k dielectric material, namely HfO2.

[0018] Furthermore, the ferroelectric layer is prepared using a ferroelectric material, namely HfSiO.

[0019] Furthermore, the parameter α of the ferroelectric material is -9.32 × 10⁻⁶. 10 cm / F; β is 3.86 × 10 18 cm 5 / FC 2 γ is 6.48 × 10 28 cm 9 / FC 4 .

[0020] Furthermore, the source region has a large-diameter segment with a length of 10 nm, a small-diameter segment with a length of 40 nm, and a thickness of 10 nm.

[0021] The thin end of a single channel region has a length of 40 nm and a thickness of 10 nm, while the thick end of the channel region has a length of 30 nm and a thickness of 30 nm.

[0022] The length of the drain region is 10 nm;

[0023] The thickness of the high-k gate oxide layer is 2 nm;

[0024] The thickness of the ferroelectric layer is 4 nm.

[0025] Furthermore, the doping concentration of the source region is 1×10⁻⁶. 19 cm -3 ~1×10 20 cm -3 ;

[0026] The doping concentration of the channel region is 1×10⁻⁶. 15 cm -3 ~1×10 16 cm -3 ;

[0027] The doping concentration of the drain region is 1×10⁻⁶. 17 cm -3 ~1×10 18 cm -3 .

[0028] Furthermore, the metal work function of the gate is 4.45 eV.

[0029] Furthermore, the N-type dopant is arsenic or phosphorus, and the P-type dopant is boron.

[0030] This invention also proposes a method for fabricating the above-mentioned T-type source region negative capacitance heterojunction tunneling field-effect transistor based on a dual-gate TFET, characterized by the following steps:

[0031] Step 1: Grow a silicon-based epitaxial layer on top of the substrate;

[0032] Step 2: Grow a silicon-based channel layer above the silicon-based epitaxial layer, wherein the silicon-based epitaxial layer and the silicon-based channel layer have opposite doping types;

[0033] Step 3: Vertically etch the middle part of the upper end of the silicon-based trench layer to form a buried trench;

[0034] Step 4: Grow T-type Si sequentially from the bottom to the top inside the embedding trench. 1-x Ge x Small diameter segment of the layer and Si 1-x Gex Large diameter end of the layer, Si 1-x Ge x The doping type of the layer is the same as that of the silicon-based channel layer;

[0035] Step 5: Arrange the T-type Si from top to bottom 1-x Ge x The left and right sides of the silicon-based epitaxial layer, silicon-based channel layer, and silicon-based epitaxial layer are etched to form a T-type source region, channel region, and drain region.

[0036] Step 6: Then deposit a high-k gate dielectric layer and a ferroelectric layer on the left and right sides of the source region and the channel region respectively;

[0037] Step 7: Deposit the source, gate, and drain electrodes in the source region, ferroelectric layer, and drain region respectively to complete the transistor fabrication.

[0038] Furthermore, in step 1, a silicon-based epitaxial layer is grown on the substrate using chemical vapor phase epitaxy.

[0039] In step 2, a silicon-based channel layer is grown on top of the silicon-based epitaxial layer using chemical vapor deposition (CVD).

[0040] In steps 3 and 5, etching is performed using reactive ion etching.

[0041] In step 4, T-type Si is grown using ultra-high vacuum chemical vapor deposition. 1-x Ge x Small diameter segment of the layer and Si 1- x Ge x The large diameter end of the layer;

[0042] In step 6, a high-k gate dielectric layer and a ferroelectric layer are deposited sequentially using atomic layer deposition.

[0043] The beneficial effects of this invention are:

[0044] In this invention, a high-k gate oxide layer is set to enhance the tunneling current. The source region is set as a T-shaped structure, and the small-diameter section of the T-shaped structure is laterally buried in the channel region, which increases the tunneling area and effectively increases the tunneling current. Ferroelectric layers are set at the left end of the left high-k gate oxide layer and the right end of the right high-k gate oxide layer, so that the entire device has a negative capacitance effect, which effectively improves the on-state current, reduces the off-state leakage current, effectively improves the subthreshold characteristics, and greatly reduces the subthreshold swing. Through the above structural settings, this invention forms an MFIS (metal-ferroelectric-insulator-semiconductor) structure.

[0045] By setting Si 1-x Ge xThe / Si tunneling heterojunction structure reduces the bandgap of the source material, which can significantly improve the carrier band tunneling rate from the source region to the channel region, increase the on-state current of the device, and reduce the device turn-on voltage.

[0046] In summary, this invention utilizes T-type source region engineering, heterojunction engineering, and ferroelectric negative capacitance engineering, leverages the gate control capability of dual-gate tunneling field-effect transistors, and employs an MFIS structure to more easily achieve stable capacitance matching. Attached Figure Description

[0047] Figure 1 This is a schematic diagram of the structure of a T-type source region negative capacitance heterojunction tunneling field-effect transistor based on a dual-gate TFET according to the present invention (the substrate and silicon-based epitaxial layer are not shown, and the drain is located at the bottom of the drain region);

[0048] Figure 1 The attached figures are labeled as follows:

[0049] 1. Source region; 2. Channel region; 3. Drain region; 4. High-k gate oxide layer; 5. Ferroelectric layer; 6. Gate; 7. Source; 8. Drain; 9. Substrate; 10. Silicon epitaxial layer; 11. Silicon channel layer; 12. Si 1-x Ge x layer;

[0050] Figure 2 This is a schematic diagram of the structure of a dual-gate tunneling field-effect transistor (DGTFET) in the prior art (the substrate and silicon-based epitaxial layer are not shown, and the drain is located at the bottom of the drain region);

[0051] Figure 2 The attached figures are labeled as follows:

[0052] 01. Source region; 02. Channel region; 03. Drain region; 04. High-k gate oxide layer; 05. Gate; 06. Source; 07. Drain;

[0053] Figure 3 This is a comparison chart of the transfer characteristic curves of the embodiment of the present invention and the dual-gate tunneling field-effect transistor in the prior art within the gate voltage range of 0V to 1V;

[0054] Figure 4(a) is a comparison of the energy bands of the dual-gate tunneling field-effect transistor in the embodiment of the present invention and the prior art under the on-state condition, along the longitudinal center of the high-k gate oxide layer, from the source region to the channel region to the drain region.

[0055] Figure 4(b) is a comparison diagram of the energy bands of the dual-gate tunneling field-effect transistor in the embodiment of the present invention and the prior art under the on-state condition, along the contact surface between the channel region and the source region, viewed longitudinally from the source region to the channel region to the source region.

[0056] Figure 5This is a comparison diagram of the lateral electric field of a dual-gate tunneling field-effect transistor in the present invention and the prior art under the on-state condition, along the longitudinal center of the high-k gate oxide layer.

[0057] Figure 6 This is the ferroelectric negative capacitance hysteresis curve test circuit in this embodiment of the invention;

[0058] Figure 7 This is the charge-voltage relationship curve output by the test circuit after the ferroelectric negative capacitor in this embodiment of the invention;

[0059] Figure 8 This is a schematic diagram of the process structure of step 1 in the fabrication method of the T-type source region negative capacitance heterojunction tunneling field-effect transistor based on dual-gate TFET of the present invention.

[0060] Figure 9 This is a schematic diagram of the process structure of step 2 in the fabrication method of the T-type source region negative capacitance heterojunction tunneling field-effect transistor based on dual-gate TFET of the present invention.

[0061] Figure 10 This is a schematic diagram of the process structure of step 3 in the fabrication method of the T-type source region negative capacitance heterojunction tunneling field-effect transistor based on dual-gate TFET of the present invention.

[0062] Figure 11 This is a schematic diagram of the process structure of step 4 in the fabrication method of the T-type source region negative capacitance heterojunction tunneling field-effect transistor based on dual-gate TFET of the present invention.

[0063] Figure 12 This is a schematic diagram of the process structure of step 5 in the fabrication method of the T-type source region negative capacitance heterojunction tunneling field-effect transistor based on dual-gate TFET of the present invention.

[0064] Figure 13 This is a schematic diagram of the process structure of step 6 in the fabrication method of the T-type source region negative capacitance heterojunction tunneling field-effect transistor based on dual-gate TFET of the present invention.

[0065] Figure 14 This is a schematic diagram of the process structure of step 7 in the fabrication method of the T-type source region negative capacitance heterojunction tunneling field-effect transistor based on dual-gate TFET of the present invention. Detailed Implementation

[0066] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0067] The terms "up," "down," "left," "right," "horizontal," and "vertical" in the text refer to... Figure 1 or Figure 2 The description is based on the perspective of the vertical direction, which represents the length direction, and the horizontal direction, which represents the thickness direction.

[0068] like Figure 2The diagram shows a schematic of a conventional dual-gate tunneling field-effect transistor (DGTFET), which includes a source region 01, a channel region 02, a drain region 03, a silicon-based epitaxial layer, and a substrate connected sequentially from top to bottom. High-k gate oxide layers 04 are provided at both ends of the channel region 02. Gates 05 are provided at the left end of the left high-k gate oxide layer 04 and the right end of the right high-k gate oxide layer 04. The source 06 is located at the upper end of the source region 01, and the drain 07 is located at the lower end of the drain region 03.

[0069] The subthreshold swing characteristics and on-state current of the aforementioned dual-gate T-source heterojunction TFET (T-source-HJTFET) are not particularly outstanding.

[0070] To solve the above problems, such as Figure 1 As shown, the present invention proposes a T-type source region negative capacitance heterojunction tunneling field-effect transistor based on a dual-gate TFET, including a source region 1, a channel region 2, a drain region 3, a high-k gate oxide layer 4, a ferroelectric layer 5, and a silicon-based epitaxial layer 10 and a substrate 9 sequentially disposed at the lower end of the drain region 3.

[0071] like Figure 1 As shown, source region 1 has a T-shaped structure. The length of the large diameter section of the T-shaped structure along the axial direction is 10 nm and the thickness is 30 nm. The length of the small diameter section of the T-shaped structure along the axial direction is 40 nm and the thickness is 10 nm.

[0072] The upper end of the channel region 2 is longitudinally provided with a buried groove that matches the small-diameter section structure and size of the T-shaped source region 1. The buried groove divides the channel region 2 from top to bottom into two thin ends and one thick end. The length of a single thin end of the channel region is 40nm and the thickness is 10nm, and the length of the thick end of the channel region is 30nm and the thickness is 30nm, that is, the total length of the channel region 2 is 70nm; the length of the drain region 3 is 10nm and the thickness is 30nm.

[0073] The small-diameter section of the T-shaped source region 1 is embedded in the embedding groove of the channel region 2, and the stepped surface of the T-shaped source region 1 is in contact with the upper end face of the channel region 2. The drain region 3 is connected to the lower end face of the channel region 2. Both the left and right sides of the T-shaped source region 1 and the channel region 2 are covered by a high-k gate oxide layer 4. The high-k gate oxide layer 4 is prepared using HfO2, a high-k dielectric material, and has a length of 80 nm and a thickness of 2 nm. On the opposite sides of the left and right high-k gate oxide layers 4, there is a ferroelectric layer 5 with a thickness of 4 nm and a length of 80 nm. The ferroelectric layer 5 is prepared using HfSiO, a ferroelectric material, and the ferroelectric material parameter α is -9.32 × 10⁻⁶. 10 cm / F; β is 3.86 × 10 18 cm 5 / FC 2 γ is 6.48 × 10 28 cm9 / FC 4 (α, β, γ are intrinsic parameters of ferroelectric materials, determined by the material itself); gates 6 are provided on the left and right sides of the ferroelectric layer 5, which are far apart from each other; source 7 is provided on the upper end face of source region 1; and drain 8 is provided below drain region 3 (drain 8 is distributed on the left and right sides of drain region 3). Through gate 6, ferroelectric layer 5, high-k gate oxide layer 4, source region 1 and channel region 2, a metal-ferroelectric-insulator-semiconductor (MFIS) structure is formed.

[0074] The entire device is symmetrical about the direction of the source region 1 and the drain region 3.

[0075] Source region 1 is either P-type or N-type doped. Channel region 2 has the same doping type as source region 1, while drain region 3 has the opposite doping type. For an N-type dual-gate tunneling field-effect transistor, source region 1 is heavily P-type doped, and drain region 3 is lightly N-type doped. For a P-type dual-gate tunneling field-effect transistor, source region 1 is heavily N-type doped, and drain region 3 is lightly P-type doped. The N-type dopant is arsenic or phosphorus, and the P-type dopant is boron. Therefore, the doping concentration of source region 1 is 1 × 10⁻⁶. 19 cm -3 -1×10 20 cm -3 The doping concentration of channel region 2 is 1×10⁻⁶. 15 cm -3 -1×10 16 cm -3 The doping concentration of drain region 3 is 1×10⁻⁶. 17 cm -3 -1×10 18 cm -3 .

[0076] Source region 1 uses Si 1-x Ge x The material used is silicon, while channel region 2 and drain region 3 still use silicon to form Si between source region 1 and channel region 2. 1-x Ge x / Si tunneling heterojunction, where x represents the germanium content in SiGe, 0 < x < 1.

[0077] The metal work function of gate 6 is set to 4.45 eV.

[0078] Based on the above structure, the present invention also proposes a method for fabricating the above transistor, taking N-type doping of drain region 3 as an example, including the following steps:

[0079] 1. For example Figure 8 As shown, an N-type atom was grown on substrate 9 using chemical vapor phase epitaxy (CVE). + Silicon-based epitaxial layer 10, where + indicates heavy doping;

[0080] 2. For example Figure 9 As shown, in N + P is grown on top of silicon-based epitaxial layer 10 using a CVE growth device. - Silicon-based channel layer 11, where - indicates light doping;

[0081] 3. For example Figure 10 As shown, using RIE to target P - The upper center of the silicon-based trench layer 11 is longitudinally etched to form a buried trench. The width and height of the buried trench are the same as those of the T-type P to be grown in the next step. + Si 1-x Ge x The small-diameter sections of layer 12 have the same dimensions;

[0082] 4. For example Figure 11 As shown, T-type Si was grown sequentially from the bottom to the top of the buried tank using ultra-high vacuum chemical vapor deposition (UHVCVD). 1-x Ge x The small diameter segment of layer 12, and in Si 1-x Ge x The upper end of the small diameter section of layer 12 and P - Si was grown on the upper end of the silicon-based channel layer 11 using the same method. 1-x Ge x The large diameter section of layer 12, Si 1-x Ge x The doping type of layer 12 is the same as that of silicon-based channel layer 11;

[0083] 5. For example Figure 12 As shown, using RIE from top to bottom, T-type Si 1-x Ge x Layer 12, silicon-based channel layer 11, and silicon-based epitaxial layer 10 are etched on both sides to form T-type source region 1, channel region 2, and drain region 3;

[0084] 6. For example Figure 13 As shown, an HfO2 gate dielectric layer 4 and a ferroelectric layer 5 are sequentially deposited on both sides of the device using atomic layer deposition (ALD).

[0085] 7. For example Figure 14 As shown, Al metal is deposited on the drain region 3, the ferroelectric layer 5 and the source region 1 to form the contact between the drain 8, the gate 6 and the source 7.

[0086] In this embodiment, taking an N-type dual-gate tunneling field-effect transistor as an example, the doping concentration of the P-type source region 1 is 1×10⁻⁶. 20 cm -3The source region 1 has a large-diameter segment with a length of 10 nm and a thickness of 30 nm, and a small-diameter segment with a length of 40 nm and a thickness of 10 nm, using Si with x = 0.9. 0.1 Ge 0.9 Materials; the doping concentration of N-type drain region 3 is 1×10⁻⁶. 18 cm -3 The drain region 3 has a length (Ld) of 10 nm and a thickness of 30 nm, and is made of silicon (Si). The doping concentration of the P-type channel region 2 is 1 × 10⁻⁶. 15 cm -3 The thin end of a single channel region has a length of 40 nm and a thickness of 10 nm, while the thick end has a length of 30 nm and a thickness of 30 nm. The N-type dopant is arsenic (As), and the P-type dopant is boron (B). The ferroelectric layer 5 has a thickness of 4 nm, and the α, β, and γ parameters of the ferroelectric material are -9.32 × 10⁻⁶. 10 cm / F, 3.86×10 18 cm 5 / FC 2 6.48×10 28 cm 9 / FC 4 The gate 6 work function is set to 4.45 eV.

[0087] like Figure 2 As shown, this is a dual-gate heterojunction tunneling field-effect transistor in the prior art, wherein the source region 01 and the channel region 02 are P-type boron doped with doping concentrations of 1×10⁻⁶. 20 cm -3 and 1×10 15 cm -3 Drain region 03 is doped with N-type arsenic at a concentration of 1×10⁻⁶. 16 cm -3 Source region 1 is Si 0.1 Ge 0.9 Materials: Both channel region 02 and drain region 03 are made of silicon. Source region 01 has a length of 10 nm and a thickness of 30 nm; channel region 02 has a length of 70 nm and a thickness of 30 nm; drain region 03 has a length (L... d The thickness of the gate oxide layer is 10nm and 30nm; the high-k gate oxide layer 04 on both sides of the channel region 02 is made of HfO2 with a thickness of 2nm, and the work function of the gate 06 is set to 4.45eV.

[0088] like Figure 3 The figure shows a comparison of the transfer characteristic curves of the embodiment of the present invention and the existing dual-gate heterojunction tunneling field-effect transistor in the gate voltage range of 0V to 1V. Figure 3It can be observed that, compared with conventional dual-gate heterojunction field-effect transistors in the prior art, the embodiments using the structure of the present invention have higher on-state current and lower off-state current. In addition, the subthreshold swing (SS) of the embodiments of the present invention is also significantly better than that of conventional dual-gate heterojunction tunneling field-effect transistors in the prior art.

[0089] As shown in Figures 4(a) and 4(b), the energy band structure of the dual-gate heterojunction tunneling field-effect transistor of the present invention and the prior art are compared under the on-state condition, along the longitudinal center of the high-k gate oxide layer, from the lateral source region 1 to the channel region 2 to the source region 1, and along the contact surface between the channel region and the source region, from the longitudinal direction, from the source region to the channel region to the drain region. As can be seen from Figures 4(a) and 4(b), due to the negative capacitance Si of the present invention... 1-x Ge x The / Si heterojunction structure of this invention features a smaller effective tunneling distance. Therefore, compared to conventional dual-gate heterojunction tunneling field-effect transistors in the prior art, the electron band tunneling rate of this invention is significantly improved in the on-state, effectively increasing the on-state current of the device.

[0090] like Figure 5 As shown, the diagram compares the transverse electric field of the dual-gate heterojunction tunneling field-effect transistor in the present invention with that of the prior art under the on-state condition, along the longitudinal center of the high-k gate oxide layer. Due to the negative capacitance heterojunction tunneling field-effect transistor structure of the present invention, the electric field of the embodiment of the present invention can reach as high as 2.8 MV / cm in the on-state, which greatly improves the electron band tunneling rate and further enhances the on-state current.

[0091] like Figure 6 As shown, the ferroelectric material used in this embodiment of the invention undergoes a negative capacitance characteristic test in the circuit to test whether the ferroelectric material has a negative capacitance characteristic. The test results are as follows. Figure 7 As shown, since C = dQ / dV, where Q is the charge and V is the voltage, refer to... Figure 7 The "S" curve and QV curve show negative capacitance characteristics in the voltage range of -0.5V to 0.5V, so it can be used in tunneling field-effect transistors.

[0092] Furthermore, taking the N-type T-source-NCHJTFET as an example: when the embodiment of the present invention is in operation (drain voltage = 1V, gate voltage = 1V), the on-state current of the T-source-NCHJTFET can reach 1.21 × 10⁻⁶. -3 The current-to-ampere ratio (A / μm) is about five orders of magnitude higher than that of a T-source-HJTFET without a ferroelectric layer, and the off-state current is only 1.84 × 10⁻⁶. -17A / μm. Furthermore, the device's minimum SS is only 7.527mV / dec, approximately 70% lower than that of a traditional TFET. These electrical characteristics ensure the device possesses excellent operating performance, meeting the requirements of next-generation devices.

Claims

1. A T-type source region negative capacitance heterojunction tunneling field-effect transistor based on a dual-gate TFET, characterized in that: It includes a T-shaped source region (1) and a channel region (2), a drain region (3), a silicon-based epitaxial layer (10), and a substrate (9) connected sequentially from top to bottom; The upper middle part of the channel area (2) is provided with a burial groove, which divides the channel area (2) into the thick end of the channel area and two thin ends of the channel area. The thickness of the leak area (3) is equal to the thickness of the thick end of the channel area. The small-diameter section structure of the source region (1) is adapted to the structure of the burial trench, and the thickness of the large-diameter section of the source region (1) is equal to the thickness of the thick end of the trench region; the small-diameter section of the source region (1) is set in the burial trench. The source region (1) and the channel region (2) are covered with high-k gate oxide layers (4) on both the left and right sides, and ferroelectric layers (5) are provided at the left end of the left high-k gate oxide layer (4) and the right end of the right high-k gate oxide layer (4). A source electrode (7) is provided at the upper end of the source region (1), a drain electrode (8) is provided below the drain region (3), and a gate electrode (6) is provided at the left end of the left ferroelectric layer (5) and the right end of the right ferroelectric layer (5). The source region (1) is P-type doped or N-type doped, the channel region (2) has the same doping type as the source region (1), and the drain region (3) has the opposite doping type to the source region (1). The source region (1) adopts Si 1-x Ge x In the fabrication process, the channel region (2) and the drain region (3) are fabricated using silicon, thereby forming Si between the source region (1) and the channel region (2). 1-x Ge x / Si tunneling heterojunction, where x represents the germanium content in SiGe, 0 < x < 1.

2. The T-type source region negative capacitance heterojunction tunneling field-effect transistor based on a dual-gate TFET according to claim 1, characterized in that: The high-k gate oxide layer (4) is prepared using a high-k dielectric material, which is HfO2.

3. The T-type source region negative capacitance heterojunction tunneling field-effect transistor based on a dual-gate TFET according to claim 2, characterized in that: The ferroelectric layer (5) is prepared using a ferroelectric material, which is HfSiO.

4. The T-type source region negative capacitance heterojunction tunneling field-effect transistor based on a dual-gate TFET according to claim 3, characterized in that: The parameter α of the ferroelectric material is -9.32 × 10⁻⁶. 10 cm / F; β is 3.86 × 10 18 cm 5 / FC 2 γ is 6.48 × 10 28 cm 9 / FC 4 .

5. The T-type source region negative capacitance heterojunction tunneling field-effect transistor based on a dual-gate TFET according to any one of claims 1-4, characterized in that: The source region (1) has a large diameter segment with a length of 10 nm, a small diameter segment with a length of 40 nm, and a thickness of 10 nm. The thin end of a single channel region has a length of 40 nm and a thickness of 10 nm, while the thick end of the channel region has a length of 30 nm and a thickness of 30 nm. The length of the drain region (3) is 10 nm; The thickness of the high-k gate oxide layer (4) is 2 nm; The thickness of the ferroelectric layer (5) is 4 nm.

6. The T-type source region negative capacitance heterojunction tunneling field-effect transistor based on a dual-gate TFET according to claim 5, characterized in that: The doping concentration of the source region (1) is 1×10 19 cm -3 ~1×10 20 cm -3 ; The doping concentration of the channel region (2) is 1×10 15 cm -3 ~1×10 16 cm -3 ; The doping concentration of the drain region (3) is 1×10⁻⁶. 17 cm -3 ~1×10 18 cm -3 .

7. The T-type source region negative capacitance heterojunction tunneling field-effect transistor based on a dual-gate TFET according to claim 6, characterized in that: The metal work function of the gate (6) is 4.45 eV.

8. The T-type source region negative capacitance heterojunction tunneling field-effect transistor based on a dual-gate TFET according to claim 7, characterized in that: The N-type dopant is arsenic or phosphorus, and the P-type dopant is boron.

9. A method for fabricating a T-type source region negative capacitance heterojunction tunneling field-effect transistor based on a dual-gate TFET as described in any one of claims 1-8, characterized in that, Includes the following steps: Step 1: Grow a silicon-based epitaxial layer (10) on top of the substrate (9); Step 2: Grow a silicon-based channel layer (11) above the silicon-based epitaxial layer (10), wherein the silicon-based epitaxial layer (10) and the silicon-based channel layer (11) have opposite doping types; Step 3: Vertically etch the middle part of the upper end of the silicon-based trench layer (11) to form a buried trench; Step 4: Grow T-type Si sequentially from the bottom to the top inside the embedding trench. 1-x Ge x The small diameter segment of layer (12) and Si 1-x Ge x The large diameter end of layer (12), Si 1-x Ge x The doping type of layer (12) is the same as that of silicon-based channel layer (11); Step 5: Arrange the T-type Si from top to bottom 1-x Ge x The left and right sides of the silicon-based epitaxial layer (12), the silicon-based channel layer (11), and the silicon-based epitaxial layer (10) are etched to form a T-type source region (1), a channel region (2), and a drain region (3); Step 6: Deposit a high-k gate dielectric layer (4) and a ferroelectric layer (5) on the left and right sides of the source region (1) and the channel region (2) respectively; Step 7: Deposit source (7), gate (6) and drain (8) in source region (1), ferroelectric layer (5) and drain region (3) respectively to complete the fabrication of transistor.

10. The method for fabricating a T-type source region negative capacitance heterojunction tunneling field-effect transistor based on a dual-gate TFET according to claim 9, characterized in that: In step 1, a silicon-based epitaxial layer (10) is grown on the substrate (9) using chemical vapor phase epitaxy. In step 2, a silicon-based channel layer (11) is grown above the silicon-based epitaxial layer (10) using chemical vapor phase epitaxy. In steps 3 and 5, etching is performed using reactive ion etching. In step 4, T-type Si is grown using ultra-high vacuum chemical vapor deposition. 1-x Ge x The small diameter segment of layer (12) and Si 1- x Ge x The large diameter end of layer (12); In step 6, a high-k gate dielectric layer (4) and a ferroelectric layer (5) are deposited sequentially using atomic layer deposition.

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