RC-IGBT active region front surface structure

Abstract

The present application relates to a kind of semiconductor power devices, specifically RC-IGBT active area front structure.It includes semiconductor substrate with first conductive type, active area of semiconductor substrate front contains multiple side-by-side arrangement strip cell.Its characteristics are, the cell contains not less than two adjacent first trench of connected gate and a second trench of not connected gate, the active area of semiconductor substrate has the first injection area of first conductive type on front, the depth of first injection area does not exceed the depth of first trench and second trench;There is gate-controlled transistor structure between two adjacent first trenches.The first contact hole is opened above the second trench, the depth of first contact hole is greater than the depth of first injection area, width is greater than the width of second trench, and there is the second injection area of first conductive type below first contact hole.RC-IGBT of the front structure is used, and the performance of IGBT low conduction voltage drop, FRD is superior.

Description

Technical Field

[0001] This invention relates to a semiconductor power device, specifically an RC-IGBT active region front structure. Background Technology

[0002] Reverse-conducting insulated-gate bipolar transistors (RC-IGBTs) integrate an IGBT and a fast recovery diode (FRD) onto a single chip, reducing the application area and lowering costs. RC-IGBTs with a distributed diode structure can better utilize chip area and increase power density. However, because this structure shares the entire front substrate with both the IGBT and FRD, there is a trade-off between the FRD's performance and the IGBT's performance. In practical applications, both IGBTs and FRDs require low conduction losses, low switching losses, and a softer switching process. Therefore, achieving a superior parameter trade-off between the IGBT and FRD in RC-IGBTs is a significant challenge. To achieve better IGBT and FRD matching performance, this solution proposes an active region front structure for the RC-IGBT. The performance parameters of the FRD are adjusted independently in the micro-trench design of the IGBT, ensuring a low on-state voltage drop for the IGBT while simultaneously controlling the FRD's performance parameters. Summary of the Invention

[0003] The technical problem to be solved by this invention is to improve the active region front structure of an RC-IGBT, which results in a low on-state voltage drop and superior FRD performance of the RC-IGBT using this front structure.

[0004] To solve the above problems, the following technical solutions are provided:

[0005] The active region front structure of the RC-IGBT of the present invention includes a semiconductor substrate having a first conductivity type, and the active region on the front side of the semiconductor substrate contains a plurality of strip-shaped cells arranged side by side. The cells are characterized in that each cell contains at least two adjacent first trenches connected to gates and one second trench not connected to a gate; the active region on the front side of the semiconductor substrate has a first injection region of a second conductivity type, the depth of which does not exceed the depth of the first trench and the second trench; a gate-controlled transistor structure is located between two adjacent first trenches. A first contact hole is formed above the second trench, the depth of which is greater than the depth of the first injection region and the width of which is greater than the width of the second trench; a second injection region of the first conductivity type is located below the first contact hole.

[0006] The first contact hole contains a first oxide layer, the upper surface of which is higher than the junction depth of the first injection zone.

[0007] The gate-controlled transistor structure includes a first injection region located between two first trenches, a third injection region of a first conductivity type above the first injection region, and a second contact hole penetrating the third injection region above the first injection region between the two first trenches, which is connected to the emitter.

[0008] The concentration in the second injection region is lower than that in the fourth injection region, and the diffusion depth of the second injection region is 1-10 μm.

[0009] The second trench is not connected to the gate, and a third contact hole is opened on the first oxide layer to connect the conductive polysilicon of the second trench to the emitter.

[0010] The second trench is not connected to the gate and is a floating electrode trench.

[0011] The above approach has the following advantages:

[0012] Because the cell of the active region front structure of the RC-IGBT of this invention contains at least two adjacent first trenches connected to the gate and one second trench not connected to the gate, the active region front of the semiconductor substrate has a first injection region of the second conductivity type. The depth of the first injection region does not exceed the depth of the first trench and the second trench. There is a gate-controlled transistor structure between two adjacent first trenches. A first contact hole is formed above the second trench, and a second injection region of the first conductivity type is formed below the first contact hole. Using a second trench (non-gate trench) can not only reduce the device channel density and improve the device short-circuit capability, but also enhance the carrier injection effect through micro-trench design and reduce IGBT conduction loss. At the same time, the upper half of the second trench is etched away (i.e., the first contact hole structure) and replaced with the anode metal contact of the FRD. A second injection region is formed at the bottom of the first contact hole to increase the minority carrier lifetime control of the FRD. The FRD parameter performance can be controlled by adjusting the first contact width and the injection concentration and depth of the first conductivity type of the second injection region to achieve ideal FRD conduction voltage drop, turn-off loss and reverse recovery loss. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the front structure of the active region of the RC-IGBT of the present invention (Embodiment 1);

[0014] Figure 2 This is a schematic diagram of the front structure of the active region of the RC-IGBT of the present invention under the structure of Embodiment 2;

[0015] Figure 3 This is a flowchart illustrating the fabrication process of the front-side structure of the active region of the RC-IGBT of the present invention. Detailed Implementation

[0016] In the context of "first conductivity type" and "second conductivity type," for N-type RC-IGBT devices, the first conductivity type refers to N-type, and the second conductivity type refers to P-type; for P-type RC-IGBT devices, the types referred to by the first and second conductivity types are exactly the opposite of those for N-type semiconductor devices. The following examples all use N-type RC-IGBT devices in conjunction with the appendix. Figure 1-3 The present invention will be described in further detail below.

[0017] Example 1

[0018] like Figure 1 As shown, the active region front structure of the RC-IGBT in this embodiment includes an N-type semiconductor substrate. The active region on the front of the semiconductor substrate contains multiple strip-shaped cells arranged side by side. Each cell contains at least two adjacent first trenches 101 connected to the gate and one second trench 102 not connected to the gate. Both the first trench 101 and the second trench 102 are filled with conductive polysilicon, and an oxide layer separates the trenches from the polysilicon. The second trench 102 can not only reduce the device channel density and improve the device short-circuit capability, but also enhance the carrier injection effect through micro-trench design, thereby reducing IGBT conduction losses. The active region front of the semiconductor substrate has a P-injection region, the depth of which does not exceed the depth of the first trench 101 and the second trench 102.

[0019] like Figure 1 As shown, a gate-controlled transistor (GMT) structure is located between two adjacent first trenches 102. The GMT structure includes a P-injection region 104 located between the two first trenches 101. The depth of the P-injection region 104 does not exceed the depth of the first trenches 101 and the second trench 102, ensuring the gate-controlled transistor is turned on. An N-injection region 103 is located on the front side of the P-injection region 104. A second contact hole 105 penetrates the N-injection region 103 at the top of the P-injection region 104 between the two first trenches 101, connecting to the emitter. The N-injection region 103 has a conventional injection depth of approximately 0.5 μm.

[0020] like Figure 1 As shown, a first contact hole 107 with a width of S1 and a depth of D1 is formed above the second trench 102. To effectively reduce the P-injection region area and decrease the FRD anode emission efficiency, the depth of the first contact hole 107 is greater than the depth of the P-injection region, and the width of the first contact hole 107 is greater than the total width of the second trench 102 (including the thickness of the gate oxide layer 109 of the second trench 102). Below the first contact hole 107 is an N-injection region 110 with a diffusion depth of 1-10 μm. The concentration of the N-injection region 110 is greater than the concentration of the N-injection region 103, thereby enhancing the minority carrier lifetime control of the FRD.

[0021] like Figure 1As shown, a first oxide layer 108 is deposited in the first contact hole 107. The upper surface of the first oxide layer 108 is higher than the junction depth of the P injection region, thereby preventing the contact hole 107 from directly contacting the drift region 111.

[0022] like Figure 1 As shown, in this embodiment, the second trench 102 is not connected to the gate, and a third contact hole is opened on the first oxide layer 108 to connect the conductive polysilicon of the second trench to the emitter.

[0023] In practical design, the thickness S2 of the P-injection region between the first trench 101 and the second trench 102 can be changed by adjusting the width S1 of the first contact 107 hole, and the concentration and depth of the N-injection region 110 can be adjusted to control the minority carrier lifetime of the FRD, thereby achieving ideal FRD on-state voltage drop, turn-off loss, and reverse recovery loss. The relationship between the S2 value and the concentration and depth of the N-injection region 110 and the FRD minority carrier lifetime is prior art and will not be elaborated here.

[0024] Example 2

[0025] like Figure 2 As shown, the active region front structure of the RC-IGBT in this embodiment includes an N-type semiconductor substrate. The active region on the front of the semiconductor substrate contains multiple strip-shaped cells arranged side by side. Each cell contains at least two adjacent first trenches 201 connected to the gate and one second trench 202 not connected to the gate. Both the first trench 201 and the second trench 202 are filled with conductive polysilicon, and an oxide layer separates the trenches from the polysilicon. The second trench 202 can not only reduce the device channel density and improve the device short-circuit capability, but also enhance the carrier injection effect through micro-trench design, thereby reducing IGBT conduction losses. The active region front of the semiconductor substrate has a P-injection region, the depth of which does not exceed the depth of the first trench 201 and the second trench 202.

[0026] like Figure 2 As shown, a gate-controlled transistor (GMT) structure exists between two adjacent first trenches 202. The GMT structure includes a P-injection region 204 located between the two first trenches 201. The depth of the P-injection region 204 does not exceed the depth of the first trenches 201 and the second trench 202, ensuring the gate-controlled transistor is turned on. An N-injection region 203 is located on the front side of the P-injection region 204. A second contact hole 205 penetrates the N-injection region 203 at the top of the P-injection region 204, connecting to the emitter. The N-injection region 203 has a conventional injection depth of approximately 0.5 μm.

[0027] like Figure 2As shown, a first contact hole 207 with a width of S1 and a depth of D1 is formed above the second trench 202. To effectively reduce the P-injection region area and decrease the FRD anode emission efficiency, the depth of the first contact hole 207 is greater than the depth of the P-injection region, and the width of the first contact hole 207 is greater than the total width of the second trench 202 (including the thickness of the gate oxide layer 209 of the second trench 202). Below the first contact hole 207 is an N-injection region 210 with a diffusion depth of 1-10 μm. The concentration of the N-injection region 210 is greater than the concentration of the N-injection region 203, thereby enhancing the minority carrier lifetime control of the FRD.

[0028] like Figure 2 As shown, a first oxide layer 208 is deposited in the first contact hole 207. The upper surface of the first oxide layer 208 is higher than the junction depth of the P injection region, thereby preventing the contact hole 207 from directly contacting the drift region 211.

[0029] like Figure 2 As shown, in this embodiment, the second trench 202 is not connected to the gate and is a floating electrode trench.

[0030] In practical design, the thickness S2 of the P-injection region between the first trench 201 and the second trench 202 can be changed by adjusting the width S1 of the first contact 207 hole, and the concentration and depth of the N-injection region 210 can be adjusted to control the minority carrier lifetime of the FRD, thereby achieving ideal FRD on-state voltage drop, turn-off loss, and reverse recovery loss. The relationship between the S2 value and the concentration and depth of the N-injection region 210 and the FRD minority carrier lifetime is prior art and will not be elaborated here.

[0031] like Figure 3 As shown, the fabrication process of the active region front structure of the RC-IGBT of the present invention is as follows: First, a semiconductor substrate; second, forming a first trench and a second trench on the front side of the semiconductor substrate; third, forming a gate oxide layer on the sidewalls of the first trench and the second trench by oxidation; fourth, filling the first trench and the second trench with conductive polysilicon; fifth, forming a first contact hole; sixth, forming an N-implantation region below the first contact hole; seventh, forming a P-implantation region; eighth, forming an N-implantation region between two adjacent first trenches; ninth, depositing interlayer dielectric to form a second contact hole and a third contact hole (if it is the structure of Embodiment 2, only the second contact hole needs to be formed); finally, metal deposition is performed.

Claims

1. A front-side structure of an RC-IGBT active region, comprising a semiconductor substrate having a first conductivity type, wherein the active region on the front side of the semiconductor substrate contains a plurality of strip-shaped cells arranged side-by-side; characterized in that, The cell contains at least two adjacent first trenches connected to gates and one second trench not connected to gates. The active region of the semiconductor substrate has a first injection region of the second conductivity type on the front side. The depth of the first injection region does not exceed the depth of the first trench and the second trench. There is a gate-controlled transistor structure between two adjacent first trenches. A first contact hole is provided above the second trench. The depth of the first contact hole is greater than the depth of the first injection region and the width is greater than the width of the second trench. There is a second injection region of the first conductivity type below the first contact hole.

2. The RC-IGBT active region front structure as described in claim 1, characterized in that, A first oxide layer is deposited inside the first contact hole, and the upper surface of the first oxide layer is higher than the junction depth of the first injection zone.

3. The RC-IGBT active region front structure as described in claim 2, characterized in that, The gate-controlled transistor structure includes a first injection region located between two first trenches, a third injection region of a first conductivity type above the first injection region, and a second contact hole penetrating the third injection region above the first injection region between the two first trenches, which is connected to the emitter.

4. The RC-IGBT active region front structure as described in claim 3, characterized in that, The concentration in the second injection region is lower than that in the fourth injection region, and the diffusion depth of the second injection region is 1-10 μm.

5. The RC-IGBT active region front structure as described in any one of claims 2 to 4, characterized in that, The second trench is not connected to the gate, and a third contact hole is opened on the first oxide layer to connect the conductive polysilicon of the second trench to the emitter.

6. The RC-IGBT active region front structure as described in any one of claims 2 to 4, characterized in that, The second trench is not connected to the gate and is a floating electrode trench.

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