trench gate transistor assembly

Abstract

This invention provides a trench gate transistor assembly, comprising: a substrate and a transistor formed on the substrate. The transistor includes a rectifier region, at least one active portion, and a plurality of superjunctions. The rectifier region has at least one rectifier structure composed of a Schottky diode. The at least one active portion is located on at least one side of the rectifier region along a second direction, and the at least one active portion and the at least one rectifier structure are arranged along the second direction. The superjunction structures are distributed along a first direction intersecting the second direction. By arranging the superjunctions, active portions, and rectifier structures in directions that intersect each other, the assembly structure can have greater adjustment flexibility.

Description

Technical Field

[0001] This invention relates to a semiconductor component, and more particularly to a trench gate transistor component. Background Technology

[0002] With the increasing demands for high power, high frequency, high heat resistance, and low power consumption in semiconductor power devices, traditional silicon-based power devices are gradually failing to meet these performance requirements. Therefore, silicon carbide (SiC), with its wide bandgap (WBG), high electron mobility, high thermal conductivity, and low impedance, has attracted considerable attention in recent years. Among these, trench gate power MOSFETs (MOSFETs) made of silicon carbide have become the mainstream high-frequency, low-voltage power devices due to their ability to reduce on-state resistance and improve edge termination characteristics through the trench.

[0003] Taking a vertical N-channel trench MOSFET as an example, to increase the breakdown voltage and reduce the on-resistance of this trench MOSFET, methods such as increasing the gate length to reduce on-resistance or increasing the ion doping concentration of the N-type drift region are generally used. To further improve the breakdown voltage and reduce on-resistance, the N-type drift region used to withstand the breakdown voltage can be replaced with a highly doped P / N-type pillar-shaped doped region with different dopant carriers. This forms a P / N superjunction, improving the device's characteristics. By adjusting the pitch between the P / N pillar-shaped doped regions, the channel density can be increased, improving the channel impedance and achieving different breakdown voltages. However, because the P / N superjunction and the device's channel layer typically extend in the same direction, the channel density is limited by the pre-planned, oriented P-pillars and cannot be arbitrarily adjusted. Summary of the Invention

[0004] The purpose of this invention is to provide a trench gate transistor assembly having multiple superjunctions, wherein the distribution direction of the superjunctions is orthogonal to the distribution direction of the active portion.

[0005] The trench gate transistor assembly of the present invention includes a substrate and a transistor formed on the substrate, wherein the substrate is first-type doped silicon carbide and the transistor is mainly an epitaxial layer whose constituent material is a semiconductor material.

[0006] The transistor includes a rectifier region, at least one active part, and multiple superjunctions.

[0007] The rectifier region has at least one rectifier structure consisting of a Schottky diode.

[0008] The at least one active part is located on at least one side of the rectification region along the second direction, and is arranged and distributed with the at least one rectification structure along the second direction.

[0009] The super-facets are distributed along a first direction that intersects with the second direction.

[0010] The transistor further includes, on the substrate, a first doped region having a first type of doping and a doping concentration less than that of the substrate, a well region located on the top surface of the first doped region and having a second type of doping, a second doped region extending downward from the top surface of the well region to the first doped region, the first doped region and the second doped region having the same type of doping and the same doping concentration, and a plurality of third doped regions extending downward from the top surface of the well region to the first doped region and extending along the second direction into long columnar shapes, the well region and the third doped region having the same type of doping, the doping concentration of the well region being greater than that of the third doped region, and the third doped regions being arranged parallel to each other along a first direction intersecting the second direction, the second doped region defining the rectifier region, and the third doped regions arranged along the first direction and the first doped region jointly defining the super junction, the at least one active part having at least one source, the at least one source extending downward from the top surface of the well region without exceeding the well region and located on at least one side of the second doped region along the second direction.

[0011] Preferably, in the trench gate transistor assembly of the present invention, the transistor has a plurality of active portions, each active portion having a source and a trench gate structure, the active portions being distributed on opposite sides of the rectifier region along the second direction, and each trench gate structure being adjacent to the side of a corresponding source.

[0012] Preferably, in the trench gate transistor assembly of the present invention, a trench gate structure is respectively sandwiched between the opposite sides of the rectifier region along the second direction and the adjacent source electrode, and the trench gate structure is respectively connected to the adjacent rectifier region and the source electrode along the opposite sides of the second direction.

[0013] Preferably, in the trench gate transistor assembly of the present invention, the trench gate structure is not present between the two sides of the rectifier region and the adjacent source.

[0014] Preferably, in the trench gate transistor assembly of the present invention, each trench gate structure has a gate trench extending downward from the top surface of the active portion and along the first direction, with a depth exceeding the well region and adjacent to the side of the source electrode, an insulating layer formed on the inner surface of the gate trench, and a gate electrode filling the gate trench and covering the insulating layer. The trench gate transistor assembly further includes a dielectric insulating layer covering the transistor and a conductive unit formed on the dielectric insulating layer. The conductive unit has a plurality of gate electrode lines, each gate electrode line being electrically connected to the gate electrode filling the gate trench, such that the gate electrode lines are spaced apart along the second direction.

[0015] Preferably, in the trench gate transistor assembly of the present invention, the insulating layer of the trench gate structure is selected from nitride, oxide, or oxynitride, and the bottom of the insulating layer of the trench gate structure has a maximum thickness and a thickness not less than [amount missing].

[0016] Preferably, in the trench gate transistor assembly of the present invention, the transistor is mainly an epitaxial layer made of silicon carbide, and further includes a trench contact electrode, a peripheral region located outside the rectifier region and the active part, the trench contact electrode having at least one first trench formed downward from the top surface of the rectifier region, with a depth not greater than the well region and extending along the first direction, multiple second trenches formed downward from the top surface of the active part, with a depth not greater than the well region and extending along the first direction, and multiple third trenches formed downward from the top surface of the peripheral region, with a depth not greater than the well region and extending along the first direction, and multiple metal layers respectively filling the at least one first trench, the second trench and the third trench and forming ohmic contact with the semiconductor material, the conductive unit also having multiple contact electrode lines, each contact electrode line being connected to the corresponding metal layer, and the contact electrode lines being distributed alternately with the gate electrode lines along the second direction.

[0017] Preferably, in the trench gate transistor assembly of the present invention, the transistor further includes a plurality of heavily doped regions, each corresponding to the bottom of the gate trench, the at least one first trench, the second trench, and the second trench, and being second-type doped.

[0018] Preferably, in the trench gate transistor assembly of the present invention, the conductive unit further has a plurality of conductive plugs passing through the dielectric insulating layer, the contact electrode line is electrically connected to the metal layer through the conductive plugs, and the gate electrode line is electrically connected to the gate electrode through the conductive plugs.

[0019] The beneficial effects of the present invention are as follows: by using structural design, the active part and the rectifier structure of the transistor are arranged along the second direction, and the super junction in the transistor structure is distributed along the first direction that intersects with the second direction, so that the distribution direction of the super junction intersects with the distribution direction of the active part and the rectifier structure, thereby forming a three-dimensional distribution of the active part and the super junction. This avoids the disadvantage of the existing active parts and super junctions distributed in the same direction (coplanar) affecting each other, so that the component structure can have greater adjustment flexibility. Attached Figure Description

[0020] Figure 1 This is a three-dimensional schematic diagram illustrating an embodiment of the trench gate transistor assembly of the present invention;

[0021] Figure 2 It is along Figure 1 A cross-sectional view of section line II-II, for illustrative purposes. Figure 1 ;

[0022] Figure 3 It is along Figure 1 A cross-sectional view of section III-III, for illustrative purposes. Figure 1 ;

[0023] Figure 4 It is along Figure 1 A cross-sectional view of section IV-IV, for illustrative purposes. Figure 1 ;

[0024] Figure 5 This is a structural diagram to illustrate the structure formed after step A;

[0025] Figure 6 This is a structural diagram to illustrate the structure formed after step B;

[0026] Figure 7 This is a structural diagram to illustrate the structure formed after step C;

[0027] Figure 8 This is a structural diagram to illustrate the structure formed after step D;

[0028] Figure 9 This is a cross-sectional structural diagram, showing the structure along... Figure 8 The cross-sectional structure of the AA section line illustrates the structure formed after step E;

[0029] Figure 10 This is a sectional structural diagram, which is based on the continuation of... Figure 9 The cross-sectional structure will be further explained to illustrate the structure formed in step F;

[0030] Figure 11 This is a sectional structural diagram, which is based on the continuation of... Figure 10The cross-sectional structure will be further explained, showing the structure formed through step G;

[0031] Figure 12 This is a sectional structural diagram, which is based on the continuation of... Figure 11 The cross-sectional structure will be further described, showing the structure formed in step H;

[0032] Figure 13 This is a sectional structural diagram, which is based on the continuation of... Figure 12 The cross-sectional structure will be further described, showing the structure formed in step I; and

[0033] Figure 14 This is a sectional structural diagram, which is based on the continuation of... Figure 13 The cross-sectional structure will be further explained, showing the structure formed through step K. Detailed Implementation

[0034] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0035] See also Figures 1 to 4 An embodiment of the trench gate transistor assembly of the present invention includes a substrate 2, a drain electrode 3, a transistor 4, a dielectric insulating layer 5, and a conductive unit 6. Wherein, Figure 1 It is a three-dimensional view, which omits the dielectric insulating layer 5 and the conductive unit 6 located above the transistor 4; Figure 2-4 To separate along Figure 1 The cross-sectional view is shown at the positions of the secant lines II-II, III-III, and IV-IV, and the cross-sectional view includes the dielectric insulating layer 5 and the conductive unit 6 located above the transistor 4.

[0036] The substrate 2 is made of silicon carbide and has a high concentration of type I doping.

[0037] The drain electrode 3 is formed on one surface of the substrate 2 and is in ohmic contact with the substrate 2.

[0038] The transistor 4 is an epitaxial layer made of semiconductor material, formed on the surface of the substrate 2 opposite to the drain electrode 3. It includes a rectifier region RA, multiple active portions A, and multiple superjunctions SJ. The rectifier region RA has at least one rectifier structure SD made of Schottky diodes. The active portions A are located on opposite sides of the rectifier region RA along a second direction Y. The active portions A and the rectifier structure SD are arranged along the second direction Y, and the superjunctions SJ are distributed along a first direction X intersecting the second direction Y.

[0039] In detail, the transistor 4 includes a first doped region 41 formed on the substrate 2, having a first type of doping and a doping concentration less than that of the substrate 2; a well region 42 located on the top surface of the first doped region 41 and having a second type of doping; a second doped region 43 extending downward from the top surface of the well region 42 to the first doped region 41; and a plurality of third doped regions 44 extending downward from the top surface of the well region 42 to the first doped region 41 and extending into a columnar shape along the second direction Y, wherein the third doped regions 44 are arranged parallel to each other along the first direction X. The first doped region 41 and the second doped region 43 are doped with the same type of doping and have the same doping concentration; the well region 42 and the third doped region 44 are doped with the same type of doping, and the doping concentration of the well region 42 is greater than that of the third doped region 44.

[0040] It should be noted that the aforementioned first type of doping is a first conductivity type doping, and the second type of doping is a second conductivity type doping with the opposite electrical properties to the first conductivity type doping. For example, the first type of doping is N-type doping, and the second type of doping is P-type doping, and vice versa. The trench gate transistor component of the present invention can be NMOS or PMOS, without particular limitation. In this embodiment, the first type of doping is N-type doping and the second type of doping is P-type doping as an example; the substrate 2 is N-type doped silicon carbide; the first doping region 41 and the second doping region 43 are N-type doped silicon carbide, and the well region 42 and the third doping region 44 are P-type doped silicon carbide, but in actual implementation, it is not limited to this.

[0041] The aforementioned second doped region 43 defines the rectifier region RA and the peripheral region PA; the rectifier region RA defines an active region AA on each of its two opposite sides along the second direction Y, and the peripheral region PA is defined around the rectifier region RA and the active region AA. The rectifier region RA has at least one rectifier structure SD composed of Schottky diodes, each active region AA has at least one active part A, and the active part A and the rectifier structure SD are arranged along the second direction Y; the elongated columnar third doped region 44 extends to the first doped region 41, forming multiple columnar regions that are staggered in the first doped region 41, and the third doped region 44 arranged along the first direction and the first doped region 41 together define a super junction SJ that is orthogonal to the arrangement direction of the active part A and the rectifier structure SD.

[0042] Specifically, each active region A has a source S and a trench gate structure TG. The source S extends downward from the top surface of the well region 42 and has a depth less than the well region 42. The source S and the first doped region 41 are homo-doped, but the doping concentration is greater than that of the first doped region 41. The trench gate structure TG is adjacent to the side of one of the corresponding source S and has a gate trench 101 extending downward from the top surface of the active region A along the first direction X, with a depth exceeding the well region 42 and adjacent to the side of the source S; an insulating layer 102 formed on the inner surface of the gate trench 101; and a gate electrode 103 filling the gate trench 101 and covering the insulating layer 102. The insulating layer 102 can be selected from nitrides, oxides, or oxynitrides, such as silicon nitride, silicon oxide, or silicon oxynitride, and the gate electrode 103 can be polysilicon. In practice, the two sides of the rectifier region RA do not have a trench gate structure between them and the adjacent source S.

[0043] In addition, the transistor 4 also includes multiple trench contact electrodes TC and multiple heavily doped portions HD.

[0044] The trench-type contact electrode TC has a first trench 201 formed downward from the top surface of the rectifier region RA, with a depth not greater than the well region 42 and extending across the peripheral region PA in the first direction X; a second trench 301 formed downward from the top surface of the active region AA, with a depth not greater than the well region 42 and extending across the source electrode S to the peripheral region PA in the first direction X; multiple third trenches 401 formed downward from the top surface of the peripheral region PA, with a depth not greater than the well region 42, extending across the first direction X and parallel to the first trench 201; and multiple conductive metals 202, 302, and 402 respectively corresponding to filling the first trench 201, the second trench 301, and the third trench 401. The aforementioned conductive metal 202 formed in the rectification region RA and the second doped region 43 are in a Schottky contact, forming the rectification structure SD composed of a Schottky diode; the conductive metal 302 located in the active region AA is used to provide the source S with external electrical connection.

[0045] The heavily doped portion HD is a type II doped portion (P-type doped portion), which is located below the gate trench 101, the first trench 201, the second trench 301 and the third trench 401 respectively and is adjacent to the bottom of the corresponding trench.

[0046] The dielectric insulating layer 5 covers the top surface of the transistor 4 and is made of an insulating material with a low dielectric constant, such as silicon phosphosilicate glass (PSG) or borosilicate glass (BPSG).

[0047] The conductive unit 6 is disposed on the dielectric insulating layer 5 and has multiple contact electrode lines 61, multiple gate electrode lines (not shown), and multiple conductive plugs 62.

[0048] The conductive plug 62 penetrates the dielectric insulating layer 5 and is connected to the gate trench 101 and the conductive metals 202, 302, and 402 respectively. Each gate electrode line is electrically connected to the gate electrode 103 filling the gate trench 101 through a corresponding conductive plug 62, so that the gate electrode lines are spaced apart along the second direction Y. Each contact electrode line 61 is also connected to the conductive metals 202, 302, and 402 through a corresponding conductive plug 62, so that the contact electrode lines 61 are spaced apart and staggered with the gate electrode lines along the second direction Y. The trench gate transistor assembly can be electrically connected to the outside through the conductive unit 6.

[0049] In some embodiments, the bottom of the insulating layer 102 of each trench gate structure TG has a maximum thickness, and the thickness is not less than [amount missing]. By maximizing the thickness of the bottom of the insulating layer 102, the breakdown of the gate oxide layer caused by electric field concentration at the bottom of the trench gate structure TG can be avoided, thereby improving the breakdown voltage of the component.

[0050] Because the quality of the oxide layer on SiC substrates is difficult to control, there are often too many defects, resulting in high channel impedance. While increasing the trench density can effectively improve channel impedance, existing P / N superjunctions and the channel layer of the device extend in the same direction. Therefore, the adjustment of trench density is limited by the P-pillars and cannot be adjusted arbitrarily. The trench gate transistor device of this invention utilizes the arrangement of the active portion A of the transistor 4 and the rectifier structure SD along the second direction Y, and the superjunction SJ in the transistor 4 structure is distributed along the first direction X, which is orthogonal to the second direction Y. This ensures that the distribution direction of the superjunction SJ and the active portion A are orthogonal to each other. Therefore, the adjustment of the width of the superjunction SJ and the adjustment of the channel width of the active portion A can be independent and do not affect each other. This avoids the disadvantage of existing active portions and superjunctions distributed in a coplanar direction affecting each other, and allows for greater adjustment flexibility in the device structure.

[0051] Furthermore, because the distribution direction of the superjunction SJ of the present invention is orthogonal to that of the active portion A, the heavily doped portion HD located at the bottom of the gate trench 101 can be more easily connected to the superjunction SJ, thereby reducing the edge electric field at the bottom of the gate trench 101 and the capacitance between the gate and drain (C). gdIn addition, the heavily doped portion HD in SiC can withstand a higher collapse junction electric field, protecting the oxide layer at the bottom of the gate trench 101 and reducing gate reliability problems caused by the sharp electric field at the bottom of the gate trench 101. Furthermore, by integrating the rectifier structure SD into the structure of the transistor 4, the power consumption of the recovery time of the trench gate transistor assembly during forward conduction and turn-off can be reduced, thus achieving the purpose of the present invention.

[0052] The method for manufacturing this embodiment of the trench gate transistor assembly is described below.

[0053] See Figure 5 First, step A is performed, where an N-type doped silicon carbide epitaxial layer with a lower doping concentration than that of the silicon carbide substrate is epitaxially formed on the silicon carbide substrate with a high concentration of N-type doping. That is, the first doped region 41 is formed on the substrate 2, and the thickness of the first doped region 41 is about 5 to 100 μm.

[0054] Next, refer to Figure 6 In step B, using a patterned photomask formed on the top surface of the first doped region 41, multiple P-type doped third doped regions 44 are formed downwards from the top surface of the first doped region 41 by ion implantation. The third doped regions 44 extend into long columnar shapes along the second direction Y and are arranged parallel to each other along the first direction X. The depth of the third doped regions 44 is approximately 2 to 50 μm.

[0055] See Figure 7 Then, in step C, another patterned photomask is formed to cover the third doped region 44 and a portion of the first doped region 41. From the top surface of the first doped region 41 not covered by the patterned photomask, well regions 42 with P-type doping are formed in an ion-distributed manner on the third doped region 44. The doping concentration of the well regions 42 is greater than that of the third doped region 44, and their depth is between 0.2 and 3 μm. The undoped well regions 42 form the second doped region 43, while the exposed first doped region 41 forms the second doped region 43.

[0056] See Figure 8 Next, step D is performed, whereby multiple sources S with N-type doping and a depth not exceeding that of the well region 42 are formed downwards from the top surface of the well region 42 located on both sides of the second doped region 43 along the second direction Y, using a patterned photomask and ion implantation method. The depth of the source S is approximately 0.05 to 1 μm.

[0057] Next, refer to the following: Figure 9 Proceed to step E. Wherein, Figure 9 Therefore, along Figure 8The cross-sectional structure of the AA secant line will be explained, and the position of the AA secant line is equivalent to... Figure 1 The position of the secant line between IV and IV.

[0058] Step E involves using an etching method to form, from the top surface of the well region 42 adjacent to both sides of each source S, a gate trench 101 extending downward along the first direction X and exceeding the depth of the well region 42; a first trench 201 formed downward from the top surface of the second doped region 43 (rectifier region RA) and not greater than the depth of the well region 42 and extending along the first direction X; a second trench 301 formed downward from the top surface of each source S and not greater than the depth of the well region 42 and extending horizontally along the first direction X; and multiple third trenches 401 located outside the second trenches 301, formed downward from the top surface of the third doped region 44 and the well region 42, and not greater than the depth of the well region 42 and extending along the first direction X. The gate trench 101 is parallel to the first trench 201, the second trench 301, and the third trench 401, and the width of the gate trench 101 is greater than the width of the first trench 201, the second trench 301, and the third trench 401.

[0059] Then, refer to the following: Figure 10 ,in, Figure 10 Therefore, to continue Figure 9 The cross-sectional structure will be further described. In step F, the semiconductor material below each corresponding trench (gate trench 101, first trench 201, second trench 301, third trench 401) is ion-doped and then annealed to form a heavily doped portion HD adjacent to the bottom of the trench (gate trench 101, first trench 201, second trench 301, third trench 401) and having P-type doping, and the doping concentration of the heavily doped portion HD is greater than that of the well region 42.

[0060] Next, refer to Figure 11 ,in, Figure 11 Therefore, to continue Figure 10 The cross-sectional structure will be described further. In step G, an insulating layer made of insulating material is deposited on the surface of the trench and then annealed to obtain the insulating layer 102.

[0061] It should be noted that the depth of the gate trench 101 and the thickness of the insulating layer 102 formed in steps E and G are different depending on the voltage withstand capability of the power component to be manufactured, because the insulating material (e.g., high dielectric insulating materials commonly used in semiconductors, such as silicon nitride (Si3N4), silicon oxide (SiO2), or silicon oxynitride (SiON)) varies. xThe selection of the gate trench 101 and the relationship between the depth of the insulating layer 102 and the withstand voltage of the power component are well known to those skilled in the art, and therefore will not be elaborated further.

[0062] Next, refer to Figure 12 Proceed to step H. Figure 12 Therefore, to continue Figure 11 The cross-sectional structure will be further described in this step H. Polysilicon covering the insulating layer 102 is filled into the gate trench 101 to form the gate electrode 103, yielding a semi-finished product.

[0063] See also Figure 13 Proceed to step I. Figure 13 Therefore, to continue Figure 12 The cross-sectional structure will be further explained to illustrate the structure formed in step I. A dielectric insulating layer 5 is formed on the top surface of the semi-finished product. Perforations are formed by etching downwards on the dielectric insulating layer 5 at positions corresponding to the gate trench 101, the first trench 201, the second trench 301, and the third trench 401, removing the insulating material filling the first trench 201, the second trench 301, and the third trench 401. Metal layers are deposited through these perforations in the first trench 201, the second trench 301, and the third trench 401 to form conductive metals 302 and 402 that form ohmic contacts with the semiconductor material of the semi-finished product, and conductive metal 202 that forms a Schottky contact with the semiconductor material. Conductive plugs 62 are filled in the perforations and connected to the conductive metals 202, 302, and 402 and the gate electrode 103, respectively.

[0064] Finally, see Figure 14 In step K, the contact electrode line 61 and the gate electrode line (not shown) connected to the conductive plug 62 are formed on the dielectric insulating layer 5, and the drain electrode 3, which is in ohmic contact with the substrate 2, is formed on the surface of the substrate 2 opposite to the dielectric insulating layer 5. This process yields a product as shown in the figure. Figure 1 The trench gate transistor assembly shown is shown.

[0065] In summary, the trench gate transistor assembly of this invention utilizes the fact that the distribution directions of the active portion A and the rectifier structure SD of the transistor 4 are orthogonal to the superjunction SJ in the structure. Therefore, the adjustment of the width of the superjunction SJ and the adjustment of the channel width of the active portion A can be independent and do not affect each other, thus avoiding the disadvantage of mutual interference between the active portion and the superjunction distributed in the coplanar direction in existing designs. This allows for greater adjustment flexibility in the assembly structure. Furthermore, by integrating the rectifier structure SD into the structure of the transistor 4, the power consumption during the recovery time of the trench gate transistor assembly during forward conduction and shutdown can be reduced, thus effectively achieving the objectives of this invention.

[0066] However, the above description is merely an embodiment of the present invention and should not be construed as limiting the scope of the present invention. Any simple equivalent changes and modifications made in accordance with the scope of the claims and the contents of the specification shall still fall within the scope of the present invention.

Claims

1. A trench gate transistor assembly, comprising a substrate and a transistor formed on the substrate, wherein the substrate is type-first doped silicon carbide, and the transistor is primarily an epitaxial layer composed of a semiconductor material, characterized in that: The transistor includes: The rectifier region has at least one rectifier structure composed of Schottky diodes; At least one active component is located on at least one side of the rectifying region along a second direction, and is arranged and distributed with the rectifying structure along the second direction; and Multiple super-facets are distributed along a first direction intersecting the second direction. The transistor also includes: The first doped region is formed on the substrate and is a type I doped region with a doping concentration lower than that of the substrate. The well region is located on the top surface of the first doped region and has type II doping; The second doped region extends downwards from the top of the well region to connect with the first doped region, and is doped of the same type and has the same doping concentration as the first doped region; and Multiple third doped regions extend downward from the top surface of the well region to the first doped region and extend into long columnar shapes along the second direction. They are doped with the same type as the well region, and the doping concentration of the well region is greater than that of the third doped region. The third doped regions are arranged parallel to each other along the first direction that intersects the second direction. The second doped region defines the rectifier region, and the third doped region arranged along the first direction, together with the first doped region, defines the super junction. The at least one active part has at least one source electrode, which extends downward from the top of the well region without exceeding the well region, and is located on at least one side of the second doped region along the second direction.

2. The trench gate transistor assembly according to claim 1, characterized in that: The transistor has multiple active units, each active unit having a source and a trench gate structure. The active units are respectively distributed on opposite sides of the rectifier region along the second direction, and each trench gate structure is adjacent to the side of one of the corresponding sources.

3. The trench gate transistor assembly according to claim 2, characterized in that: A trench gate structure is sandwiched between the two opposite sides of the rectifier region along the second direction and the adjacent source electrode, and the trench gate structure is connected to the adjacent rectifier region and the source electrode along the two opposite sides of the second direction.

4. The trench gate transistor assembly according to claim 2, characterized in that: The two sides of the rectifier region do not have the trench gate structure between them and the adjacent source.

5. The trench gate transistor assembly according to claim 2, characterized in that: Each trench gate structure has a gate trench extending downward from the top surface of the active portion along the first direction, with a depth exceeding the well region and adjacent to the side of the source electrode, an insulating layer formed on the inner surface of the gate trench, and a gate electrode filling the gate trench and covering the insulating layer. The trench gate transistor assembly also includes a dielectric insulating layer covering the transistor and a conductive unit formed on the dielectric insulating layer. The conductive unit has a plurality of gate electrode lines, each gate electrode line being electrically connected to the gate electrode filling the gate trench, and the gate electrode lines being spaced apart along the second direction.

6. The trench gate transistor assembly according to claim 5, characterized in that: The insulating layer of the trench gate structure is selected from nitrides, oxides, or oxynitrides, and the bottom of the insulating layer of the trench gate structure has a maximum thickness and the thickness is not less than [amount missing].

7. The trench gate transistor assembly according to claim 5, characterized in that: The transistor is mainly an epitaxial layer made of silicon carbide, and also includes a trench contact electrode, a peripheral region located outside the rectifier region and the active part. The trench contact electrode has at least one first trench formed downward from the top surface of the rectifier region, with a depth no greater than the well region and extending along the first direction; multiple second trenches formed downward from the top surface of the active part, with a depth no greater than the well region and extending along the first direction; multiple third trenches formed downward from the top surface of the peripheral region, with a depth no greater than the well region and extending along the first direction; and multiple metal layers respectively filling the at least one first trench, the second trench and the third trench and forming ohmic contact with the semiconductor material. The conductive unit also has multiple contact electrode lines, each contact electrode line being connected to the corresponding metal layer, and the contact electrode lines are distributed alternately with the gate electrode lines along the second direction.

8. The trench gate transistor assembly according to claim 7, characterized in that: The transistor also includes a plurality of heavily doped regions, each corresponding to the bottom of the gate trench, the at least one first trench, the second trench, and the third trench, and being type II doped.

9. The trench gate transistor assembly according to claim 7, characterized in that: The conductive unit also has a plurality of conductive plugs passing through the dielectric insulating layer. The contact electrode line is electrically connected to the metal layer through the conductive plugs, and the gate electrode line is electrically connected to the gate electrode through the conductive plugs.

Images