A transistor and a method of manufacturing the same

Abstract

The application discloses a transistor and a manufacturing method thereof, and relates to the technical field of semiconductors, which is used for improving the conduction uniformity between different layer nanostructures included in a channel region while inhibiting the parasitic channel leakage, and is beneficial to improving the electrical performance of the transistor. The transistor comprises a semiconductor substrate, an active structure, a dielectric structure and a gate stack structure. The active structure is formed on the semiconductor substrate. The active structure comprises a source region, a drain region and a channel region between the source region and the drain region. The channel region comprises at least two layers of nanostructures along the thickness direction of the semiconductor substrate. In the channel region, the width of the nanostructure located at the bottom layer is greater than the width of the remaining nanostructures. The dielectric structure is formed between the semiconductor substrate and the active structure. The dielectric structure is in contact with the nanostructure located at the bottom layer. The gate stack structure is formed on the surface of the nanostructure located at the bottom layer which is not in contact with the dielectric structure and surrounds the outer periphery of the remaining nanostructures.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a transistor and a method for manufacturing the same. Background Technology

[0002] Compared to planar transistors, fin field-effect transistors and gate-around transistors have stronger gate control capabilities and can suppress short-channel effects.

[0003] However, existing manufacturing methods make it difficult to suppress parasitic channel leakage current in transistors while ensuring high conduction uniformity among different layers of nanostructures in the channel region of the transistor, which is not conducive to improving the electrical performance of the transistor. Summary of the Invention

[0004] The purpose of this invention is to provide a transistor and its manufacturing method, which can improve the conduction uniformity between different layers of nanostructures in the channel region while suppressing parasitic channel leakage current, thereby improving the electrical performance of the transistor.

[0005] To achieve the above objectives, the present invention provides a transistor comprising: a semiconductor substrate, an active structure, a dielectric structure, and a gate stack structure. The active structure is formed on the semiconductor substrate. The active structure includes a source region, a drain region, and a channel region located between the source and drain regions. Along the thickness direction of the semiconductor substrate, the channel region includes at least two layers of nanostructures. In the channel region, the width of the bottom nanostructure is greater than the width of the remaining nanostructures. The dielectric structure is formed between the semiconductor substrate and the active structure. The dielectric structure is in contact with the bottom nanostructure. The gate stack structure is formed on the surface of the bottom nanostructure that is not in contact with the dielectric structure and surrounds the outer periphery of the remaining nanostructures.

[0006] In the above-described technical solution, the dielectric structure of the transistor is formed between the semiconductor substrate and the active structure. In this case, the dielectric structure isolates the source, drain, and channel regions of the active structure from the semiconductor substrate. Because the dielectric structure is a non-conductive insulating structure, when an appropriate voltage is applied to the gate stack structure, the presence of the dielectric structure allows the source and drain regions to conduct only through the channel region, without conducting with the semiconductor substrate located beneath the dielectric structure. This solves the problems of parasitic channel leakage and source-drain leakage. Furthermore, since the dielectric structure is a film layer subsequently formed on the semiconductor substrate and does not constitute part of the semiconductor substrate, in the above case, during transistor manufacturing, other suitable semiconductor substrates, such as silicon substrates or germanium-silicon substrates, which are less expensive than silicon-on-insulator substrates, can be used. This solves the parasitic channel and source-drain leakage problems while also reducing the manufacturing cost of the transistor. Meanwhile, the dielectric structure solves the problems of parasitic channels and source-drain leakage through its own insulation properties. It does not require the use of anti-penetration injection process to treat the fin structure of the transistor. This can prevent problems such as reduced carrier migration rate in the channel region and damage to the fin structure by high-speed ions caused by the injection process, which is beneficial to improving the working performance of the transistor.

[0007] Secondly, in the channel region of the active structure, the width of the bottom nanostructure is greater than that of the other nanostructures. Therefore, all other things being equal, the conduction area of ​​the bottom nanostructure is greater than that of the other nanostructures. Although the voltage applied to the ends of the upper nanostructure along its length is greater than that applied to the ends of the bottom nanostructure along its length, increasing the conduction area of ​​the bottom nanostructure increases its conduction current. This facilitates higher conduction uniformity between the bottom nanostructure and the other nanostructures, improving the transistor's driving performance.

[0008] Furthermore, the dielectric structure contacts the underlying nanostructure, and the gate stack structure is formed on the surface of the underlying nanostructure that is not in contact with the dielectric structure, and surrounds the periphery of the remaining nanostructures. Thus, the gate stack structure and the underlying nanostructure form a FinFET-like architecture, while the gate stack structure and the remaining nanostructures form a ring-gate architecture. This not only improves the structural reliability of the channel region by allowing direct contact between the underlying nanostructure and the dielectric structure when the channel region includes multiple nanostructures, but also enhances the control of the channel region by the gate stack structure within the transistor through the ring-gate architecture formed by the gate stack structure and the remaining nanostructures, suppressing short-channel effects and further improving the transistor's electrical performance.

[0009] Secondly, the present invention also provides a method for manufacturing a transistor, the method comprising: first, providing a semiconductor substrate; next, forming a dielectric structure and an active structure on the semiconductor substrate. The active structure includes a source region, a drain region, and a channel region located between the source and drain regions. Along the thickness direction of the semiconductor substrate, the channel region includes at least two layers of nanostructures. In the channel region, the width of the bottom nanostructure is greater than the width of the remaining nanostructures. A dielectric structure is formed between the semiconductor substrate and the active structure and in contact with the bottom nanostructure. Next, a gate stack structure is formed. The gate stack structure is formed on the surface of the bottom nanostructure that is not in contact with the dielectric structure and surrounds the periphery of the remaining nanostructures.

[0010] The beneficial effects of the second aspect and its various implementations in this invention can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here. Attached Figure Description

[0011] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0012] Figure 1 A schematic diagram of the transistor's structure during the manufacturing process provided in this embodiment of the invention. Figure 1 ;

[0013] Figure 2 A schematic diagram of the transistor's structure during the manufacturing process provided in this embodiment of the invention. Figure 2 ;

[0014] Figure 3 A schematic diagram of the transistor's structure during the manufacturing process provided in this embodiment of the invention. Figure 3 ;

[0015] Figure 4 A schematic diagram of the transistor's structure during the manufacturing process provided in this embodiment of the invention. Figure 4 ;

[0016] Figure 5 A schematic diagram of the transistor's structure during the manufacturing process provided in this embodiment of the invention. Figure 5 ;

[0017] Figure 6 A schematic diagram of the transistor's structure during the manufacturing process provided in this embodiment of the invention. Figure 6 ;

[0018] Figure 7 A schematic diagram of the transistor's structure during the manufacturing process provided in this embodiment of the invention. Figure 7 ;

[0019] Figure 8 Parts (1) and (2) in the figure are schematic diagrams of the transistors provided in the embodiments of the present invention during the manufacturing process. Figure 8 and indication Figure 9 ;

[0020] Figure 9 Parts (1) and (2) in the figure are schematic diagrams of the transistors provided in the embodiments of the present invention during the manufacturing process. Figure 10 and indication Figure 10 one;

[0021] Figure 10 Parts (1) and (2) in the figure are schematic diagrams of the transistors provided in the embodiments of the present invention during the manufacturing process. Figure 10 Two-suppose diagram Figure 10 three;

[0022] Figure 11 Parts (1) and (2) in the figure are schematic diagrams of the transistors provided in the embodiments of the present invention during the manufacturing process. Figure 10 Four symbols Figure 10 five;

[0023] Figure 12 Parts (1) and (2) in the figure are schematic diagrams of the transistors provided in the embodiments of the present invention during the manufacturing process. Figure 10 Six Harmony Diagram Figure 10 seven;

[0024] Figure 13 Parts (1) and (2) in the figure are schematic diagrams of the transistors provided in the embodiments of the present invention during the manufacturing process. Figure 10 Eight and symbol Figure 10 Nine;

[0025] Figure 14 Parts (1) and (2) in the figure are schematic diagrams of the transistors provided in the embodiments of the present invention during the manufacturing process. Figure 2 Ten and symbol Figure 2 eleven;

[0026] Figure 15 Parts (1) and (2) in the figure are schematic diagrams of the transistors provided in the embodiments of the present invention during the manufacturing process. Figure 2 Twelve and symbol Figure 2 Thirteen;

[0027] Figure 16 A schematic diagram of the transistor's structure during the manufacturing process provided in this embodiment of the invention. Figure 2 fourteen;

[0028] Figure 17 A schematic diagram of the transistor's structure during the manufacturing process provided in this embodiment of the invention. Figure 2 fifteen;

[0029] Figure 18 A schematic diagram of the transistor's structure during the manufacturing process provided in this embodiment of the invention. Figure 2 sixteen;

[0030] Figure 19 A schematic diagram of the transistor's structure during the manufacturing process provided in this embodiment of the invention. Figure 2 Seventeen;

[0031] Figure 20 A schematic diagram of the transistor's structure during the manufacturing process provided in this embodiment of the invention. Figure 2 eighteen;

[0032] Figure 21 A schematic diagram of the transistor's structure during the manufacturing process provided in this embodiment of the invention. Figure 2 nineteen;

[0033] Figure 22 Parts (1) and (2) in the figure are schematic diagrams of the transistors provided in the embodiments of the present invention during the manufacturing process. Figure 3 Ten and symbol Figure 3 eleven.

[0034] Reference numerals: 11 Semiconductor substrate, 12 Layer to be oxidized, 13 Channel layer, 14 Sacrificial layer, 15 Third fin structure, 16 Third protective layer, 17 First fin structure, 18 First protective layer, 19 Second protective layer, 20 Dielectric structure, 21 Shallow trench isolation structure, 22 Second fin structure, 23 Sacrificial gate, 24 Gate sidewall, 25 Semiconductor structure, 26 Source region, 27 Drain region, 28 Interlayer dielectric layer, 29 Channel region, 30 Nanostructure, 31 Gate stack structure. Detailed Implementation

[0035] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0036] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0037] In the context of this disclosure, when a layer / element is referred to as being "on top of" another layer / element, the layer / element may be directly on top of the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on top of" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0038] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0039] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0040] Compared to planar transistors, fin field-effect transistors and gate-around transistors have stronger gate control capabilities and can suppress short-channel effects, resulting in higher operating performance.

[0041] For gate-around transistors (GMT-A), parasitic channel leakage is a problem during actual operation. To address this issue, those skilled in the art often employ two methods: First, using a semiconductor substrate with a buried oxide layer, such as a silicon-on-insulator (SiI) substrate. Since the buried oxide layer is a non-conductive insulating layer, it can prevent parasitic channel leakage. Second, using a punch-through injection process to suppress parasitic channel leakage. Specifically, during the fabrication of the GMT-A, after forming a fin structure and a shallow trench isolation structure on the substrate, a punch-through injection process is used to inject impurity ions with a conductivity type opposite to the impurities doped in the source and drain regions into the fin structure. This forms a barrier layer in the lower middle part of the fin structure, thereby using the highly doped barrier layer to suppress parasitic channels.

[0042] Secondly, when the gate-around transistor (GMT) manufactured using existing methods includes a channel region comprising multiple nanostructures spaced along the thickness direction of the semiconductor substrate, the driving performance of the GMT is poor. Specifically, in a GMT, the source electrically connected to the source region is formed at the top of the source region, and the drain electrically connected to the drain region is formed at the top of the drain region. Therefore, along the thickness direction close to the semiconductor substrate, the spacing between each nanostructure and the source and drain is greater than the spacing between another nanostructure located above it and the source and drain. Consequently, when the GMT is in the on-state, the transmission path between the source and drain through the upper nanostructure is shorter, while the transmission path through the lower nanostructure is longer. Since the transmission path is proportional to the on-resistance, the on-resistance of each nanostructure is greater than the on-resistance of the other nanostructure located above it. Under the influence of the on-resistance, the conduction uniformity between the nanostructures is poor, which in turn leads to a deterioration in the driving performance of the GMT.

[0043] In summary, existing manufacturing methods cannot effectively suppress parasitic channel leakage current in transistors while ensuring high conduction uniformity among different layers of nanostructures in the channel region of the manufactured transistor, which is detrimental to improving the electrical performance of transistors.

[0044] To address the aforementioned technical problems, embodiments of the present invention provide a transistor and a method for manufacturing the same. In the transistor provided by these embodiments, a dielectric structure is formed between a semiconductor substrate and an active structure to prevent parasitic channels and source-drain leakage. Furthermore, the bottom-layer nanostructure in the channel region is in contact with the dielectric structure, and the width of the bottom-layer nanostructure is greater than the width of the other nanostructures, thereby achieving higher conduction uniformity between the bottom-layer nanostructure and the other nanostructures, and improving the transistor's driving performance.

[0045] like Figure 21 as well as Figure 22 As shown in sections (1) and (2) of the present invention, in a first aspect, the transistor provided in the embodiments of the present invention includes: a semiconductor substrate 11, an active structure, a dielectric structure 20, and a gate stack structure 31. The active structure is formed on the semiconductor substrate 11. The active structure includes a source region 26, a drain region 27, and a channel region 29 located between the source region 26 and the drain region 27. Along the thickness direction of the semiconductor substrate 11, the channel region 29 includes at least two layers of nanostructures 30. In the channel region 29, the width of the bottom nanostructure 30 is greater than the width of the remaining nanostructures 30. The dielectric structure 20 is formed between the semiconductor substrate 11 and the active structure. The dielectric structure 20 is in contact with the bottom nanostructure 30. The gate stack structure 31 is formed on the surface of the bottom nanostructure 30 that is not in contact with the dielectric structure 20 and surrounds the outer periphery of the remaining nanostructures 30.

[0046] Specifically, the aforementioned semiconductor substrate can be any semiconductor material such as silicon substrate or germanium-silicon substrate, and it should be a low-cost semiconductor substrate. The semiconductor substrate can have an active region and an isolation region. The extent of these active and isolation regions can be determined based on the actual application scenario and is not specifically limited here.

[0047] For the aforementioned dielectric structure, the material of the dielectric structure can be an insulating material such as silicon oxide or germanium oxide. Based on this, such as Figure 21 As shown, the dielectric structure 20 is formed between the semiconductor substrate 11 and the active structure. In this case, the dielectric structure 20 isolates the source region 26, drain region 27, and channel region 29 of the active structure from the semiconductor substrate 11. Because the dielectric structure 20 is a non-conductive insulating structure, when an appropriate voltage is applied to the gate stack structure 31, the presence of the dielectric structure 20 allows the source region 26 and drain region 27 to conduct only through the channel region 29, without conducting with the semiconductor substrate 11 located beneath the dielectric structure 20. This solves the problems of parasitic channel leakage and source-drain leakage. Furthermore, since the dielectric structure 20 is a film layer subsequently formed on the semiconductor substrate 11 and does not constitute part of the semiconductor substrate 11, in the above case, during transistor manufacturing, other suitable semiconductor substrates 11, such as silicon substrates or germanium-silicon substrates, which have lower costs than silicon-on-insulator substrates, can be used. This solves the parasitic channel and source-drain leakage problems while also reducing the manufacturing cost of the transistor. Meanwhile, the dielectric structure 20 solves the problems of parasitic channel and source-drain leakage through its own insulation properties. It does not require the use of anti-penetration injection process to treat the fin structure of the transistor. This can prevent the reduction of carrier migration rate in the channel region 29 and damage to the fin structure by high-speed ions caused by the injection process, which is beneficial to improving the working performance of the transistor.

[0048] In practical applications, dielectric structures are formed on the active regions of a semiconductor substrate. Additionally, such as... Figures 1 to 21 As shown, the dielectric structure 20 can be obtained by selectively oxidizing the patterned layer 12 formed on the semiconductor substrate 11. Furthermore, the material of the layer 12 to be oxidized is the same as the material of the sacrificial layer 14; therefore, in this case, the material of the dielectric structure 20 is an oxide of the material of the sacrificial layer 14.

[0049] The thickness of the dielectric structure can be determined based on the actual application scenario, and no specific limitation is made here. Secondly, the width of the dielectric structure (the width direction of the dielectric structure is parallel to the width direction of the gate stack structure) can be equal to the width of the underlying nanostructure; or, as... Figure 22As shown in sections (1) and (2), the width of the dielectric structure 20 can also be smaller than the width of the nanostructure 30 located at the bottom layer. Specifically, in the actual manufacturing process, when the materials used to manufacture the oxide layer and the sacrificial layer of the dielectric structure 20 are both germanium-silicon or germanium, and the materials of the channel region 29 and the semiconductor substrate 11 are silicon, as shown in sections (1) and (2), the width of the dielectric structure 20 can also be smaller than the width of the nanostructure 30 located at the bottom layer. Figures 9 to 13 As shown in sections (1) and (2), during the etching of the bottom channel layer 13, the oxide layer 12, and part of the semiconductor substrate 11, the etchant used to etch the channel layer 13 and the semiconductor substrate 11 also affects the oxide layer 12, causing the width of the oxide layer 12 after patterning to be smaller than the width of the bottom channel layer 13, and consequently, the width of the dielectric structure to be smaller than the width of the nanostructure located at the bottom. If a highly selective etchant is used, it is advantageous to make the width of the dielectric structure equal to the width of the nanostructure located at the bottom.

[0050] For the aforementioned active structure, the source and drain regions can be directly formed on the dielectric structure. Alternatively, as... Figure 21 As shown, the transistor provided in this embodiment of the invention also includes a semiconductor structure 25 integrally formed with the underlying nanostructure 30. This semiconductor structure 25 is located between the source region 26 and the dielectric structure 20, and between the drain region 27 and the dielectric structure 20. In other words, the source region 26 and the drain region 27 are formed on the semiconductor structure 25. In this case, as... Figure 17 and Figure 18 As shown, when the transistor includes the aforementioned semiconductor structure 25 and the source region 26 and drain region 27 are formed using a source-drain epitaxial growth method, after removing the portion of the second fin structure located above the bottom channel layer 13, not only can at least the remaining portion of the channel layer 13 be used as a seed layer for growing the source region 26 and drain region 27, but the semiconductor structure 25 can also be used as a seed layer for growing the source region 26 and drain region 27, thereby reducing defects in the source region 26 and drain region 27 and improving the transistor yield. The material and specifications of the semiconductor structure 25 can be determined based on the material and specifications of the channel region, and are not specifically limited here.

[0051] The materials for the source and drain regions can be any semiconductor material, such as silicon, silicon germanium, or germanium. The source and drain regions can be made of the same or different materials. For example, both the source and drain regions can be made of silicon, silicon germanium, or germanium. Another example is that the source region can be made of silicon, and the drain region can be made of silicon germanium.

[0052] The aforementioned active structure includes a channel region comprising at least two nanostructure layers. For example, Figure 21 as well as Figure 22As shown in sections (1) and (2), the bottom nanostructure 30 is in contact with the dielectric structure 20, and the remaining nanostructures 30 included in the channel region 29 are spaced apart above the bottom nanostructure 30 along the thickness direction of the semiconductor substrate 11. At this time, the gate stack structure 31 is formed on the surface of the bottom nanostructure 30 that is not in contact with the dielectric structure 20 and surrounds the outer periphery of the remaining nanostructures 30. It can be seen that the gate stack structure 31 and the bottom nanostructure 30 form a FinFET-like architecture, while the gate stack structure 31 and the remaining nanostructures 30 form a ring gate architecture. At this time, not only can the structural reliability of the channel region 29 be improved by the direct contact between the bottom nanostructure 30 and the dielectric structure 20 when the channel region 29 includes multiple nanostructures 30, but also the ring gate architecture formed by the gate stack structure 31 and the remaining nanostructures 30 can improve the control capability of the gate stack structure 31 of the transistor over the channel region 29, suppress the short-channel effect, and further improve the electrical performance of the transistor.

[0053] Specifically, the exact number of nanostructure layers included in the channel region can be determined based on actual needs, and is not specifically limited here. As for the specifications of the nanostructures included in the channel region, such as... Figure 22 As shown in parts (1) and (2), the width of the bottom nanostructure 30 is greater than the width of the other nanostructures 30. Therefore, under the same conditions, the conduction area of ​​the bottom nanostructure 30 is greater than that of the other nanostructures 30. Although the voltage applied to the ends of the upper nanostructure 30 along its length is greater than that applied to the ends of the bottom nanostructure 30 along its length in the direction close to the semiconductor substrate 11, increasing the conduction area of ​​the bottom nanostructure 30 can increase its conduction current. This facilitates higher conduction uniformity between the bottom nanostructure 30 and the other nanostructures 30, thereby improving the driving performance of the transistor.

[0054] Among them, such as Figure 22 As shown in part (2), in the channel region 29, except for the nanostructure 30 located at the bottom layer, the widths of the remaining nanostructures 30 are equal; at this time, as Figure 2 As shown, a single patterning step is sufficient to obtain the first fin structure 17 for fabricating the remaining nanostructures 30, thereby reducing the fabrication difficulty of the channel region and simplifying the channel region fabrication process. Alternatively, as... Figure 22As shown in part (1), the width of the different layers of nanostructures 30 included in the channel region 29 gradually increases along the direction close to the semiconductor substrate 11; at this time, it is advantageous to make the conduction area of ​​the different layers of nanostructures 30 included in the channel region 29 gradually increase along the direction close to the semiconductor substrate 11, which is advantageous to make the nanostructures 30 at different heights have conduction currents of equal magnitude, and further improve the conduction uniformity between different nanostructures 30.

[0055] In practical applications, such as Figure 22 As shown in sections (1) and (2), the central axes of the different layers of nanostructures 30 included in the channel region 29 can coincide. In this case, the length of the two sidewalls of each nanostructure 30 located on the bottom nanostructure 30 along the length direction is equal to the length of the two sidewalls of the bottom nanostructure 30 along the length direction. Alternatively, the central axes of the different layers of nanostructures included in the channel region can also be parallel to each other, but not coincident. In this case, during the actual manufacturing process, if the spacing between other structures located on both sides of the channel layer along the length direction and the channel layer is not equal during the patterning process of the channel layer used to manufacture the nanostructure, the etching agent may etch the channel layer to different degrees along the length direction, resulting in the central axes of the nanostructures 30 formed based on different channel layers not coinciding.

[0056] In addition, such as Figure 21 As shown, the heights of the different nanostructures 30 can be the same. Alternatively, the height of the nanostructure at the bottom layer can be greater than the height of the other nanostructures; in this case, only the height of the nanostructure at the bottom layer can be greater than the height of the other nanostructures, and the heights of the other nanostructures can be the same. Alternatively, the heights of the different nanostructures can gradually increase along the thickness direction close to the semiconductor substrate; in this case, it is beneficial to increase the conduction area of ​​the nanostructure at the bottom layer, and it is more beneficial to make the nanostructures at different heights have equal conduction currents, further improving the conduction uniformity between different nanostructures.

[0057] The specific width and height of the different nanostructures included in the channel region can be determined based on the height of each nanostructure layer and the actual application scenario; no specific limitations are made here. Furthermore, the channel region can be made of silicon, silicon-germanium, or group III-V semiconductor materials, etc. For example, the channel region can be made of silicon.

[0058] For the above-mentioned gate stack structure, such as Figure 21 and Figure 22As shown in sections (1) and (2), the gate stack may include a gate dielectric layer and a gate formed at least around the periphery of each nanostructure 30 through gaps. The gate dielectric layer may also be formed above the portion of the semiconductor substrate 11 that exposes the gate formation region. Specifically, the gate dielectric layer may be made of insulating materials with low dielectric constants, such as silicon oxide or silicon nitride, or insulating materials with high dielectric constants, such as HfO2, ZrO2, TiO2, or Al2O3. The gate may be made of conductive materials such as doped polycrystalline silicon, TiN, TaN, or TiSiN. The thickness of the gate dielectric layer and the gate can be set according to actual needs and is not specifically limited here.

[0059] In some cases, such as Figure 21 and Figure 22 As shown in sections (1) and (2) of the present invention, the transistor provided in this embodiment may further include a shallow trench isolation structure 21, a gate sidewall 24, and an interlayer dielectric layer 28. The shallow trench isolation structure 21 is formed at least on the isolation region of the semiconductor substrate 11. The shallow trench isolation structure 21 is not integrally formed with the dielectric structure 20, and the top height of the shallow trench isolation structure 21 can be any height less than or equal to the top height of the dielectric structure 20, as long as it can be applied to the transistor provided in this embodiment. Furthermore, the material of the shallow trench isolation structure 21 can be an insulating material such as SiN, Si3N4, SiO2, or SiCO. It should be understood that when other transistors or conductive structures are formed on the semiconductor substrate 11, forming the shallow trench isolation structure 21 on the isolation region of the semiconductor substrate 11 can isolate the transistor provided in this embodiment from the source region 26 or drain region 27 of other transistors and other conductive structures, preventing electrical connection between them and improving the reliability between the transistor formed on the semiconductor substrate 11 and other structures. Furthermore, the aforementioned interlayer dielectric layer 28 covers the semiconductor substrate 11, and its top is flush with the top of the gate stack structure 31. It should be understood that during the manufacturing process of the transistors provided in the embodiments of the present invention, such as... Figure 20 As shown, the presence of the interlayer dielectric layer 28 protects the source region 26 and drain region 27 from etching and cleaning operations during the etching of the sacrificial gate and sacrificial layer. Specifically, the material of the interlayer dielectric layer 28 can be an insulating material such as SiO2 or SiN. Regarding the gate sidewall 24, as... Figure 21 As shown, a gate sidewall 24 is formed between the interlayer dielectric layer 28 and the gate stack structure 31. The presence of the gate sidewall 24 facilitates the formation of the gate stack structure 31 of the transistor and isolates the gate stack structure 31 from the subsequently formed conductive structure. The gate sidewall 24 is made of an insulating material. Specifically, the material and thickness of the gate sidewall 24 can be designed according to the actual application scenario, and are not specifically limited here.

[0060] Secondly, embodiments of the present invention provide a method for manufacturing a transistor. The following will describe, based on... Figures 1 to 22 The illustrated perspective view or cross-sectional view describes the manufacturing process. Specifically, the method for manufacturing this transistor includes the following steps:

[0061] First, a semiconductor substrate is provided. The specific structure of the semiconductor substrate can be referred to in the previous text, and will not be repeated here.

[0062] Next, as Figure 20 As shown, a dielectric structure 20 and an active structure are formed on a semiconductor substrate 11. The active structure includes a source region 26, a drain region 27, and a channel region 29 located between the source region 26 and the drain region 27. Along the thickness direction of the semiconductor substrate 11, the channel region 29 includes at least two layers of nanostructures 30. In the channel region 29, the width of the bottom nanostructure 30 is greater than the width of the other nanostructures 30. The dielectric structure 20 is formed between the semiconductor substrate 11 and the active structure and is in contact with the bottom nanostructure 30.

[0063] In actual manufacturing, an oxide layer for creating a dielectric structure can be formed on a semiconductor substrate before forming the channel layer and sacrificial layer used to create the active structure. Based on this, after appropriate patterning, the dielectric structure can be formed by selectively oxidizing the oxide layer. The material of the oxide layer can be the same as the sacrificial layer; in this case, the channel layer, sacrificial layer, and oxide layer only need to be formed from two different semiconductor materials, reducing the difficulty of subsequent selective processing. Of course, the material of the oxide layer can also be different from the material of the sacrificial layer.

[0064] The formation process of the dielectric structure will be divided into two types based on whether a corresponding protective layer is present to protect the underlying channel layer during selective oxidation of the patterned layer to be oxidized:

[0065] The first method: The above-mentioned formation of a dielectric structure on a semiconductor substrate may include the following steps: Figure 1 As shown, a layer 12 to be oxidized is formed on a semiconductor substrate 11, and a channel layer 13 and a sacrificial layer 14 are alternately stacked on the layer 12 to be oxidized. The channel layer 13, located at the bottom, is in contact with the layer 12 to be oxidized, and the material of the sacrificial layer 14 is the same as that of the layer 12 to be oxidized. Next, as... Figure 2 and Figure 7 As shown, the remaining channel layers 13 and sacrificial layers 14 located on the bottom channel layer 13 are patterned to form a first fin structure 17 on the channel layer 13. Next, as... Figure 8 As shown in part (1), a first protective layer 18 is formed covering the outer periphery of the first fin structure 17. Figure 9As shown in section (1), under the masking effect of the first protective layer 18, at least the channel layer 13 and the layer to be oxidized 12 located at the bottom layer are etched. Next, as... Figure 13 As shown in sections (1) and (2), the remaining portion of the oxide layer to be oxidized is selectively oxidized to form a dielectric structure 20. Then, as... Figure 14 As shown in parts (1) and (2) of the diagram, the first protective layer is removed.

[0066] In the actual manufacturing process, such as Figure 1 As shown, the aforementioned oxide layer 12, channel layer 13, and sacrificial layer 14 can be formed using processes such as epitaxy. The channel layer 13 can be made of a semiconductor material such as silicon. The oxide layer 12 and sacrificial layer 14 can be semiconductor materials that have a certain etching selectivity ratio with the channel layer 13 and can achieve selective oxidation with the channel layer 13. For example, the materials of the sacrificial layer 14 and the oxide layer 12 are Si. 1-x Ge x 0.2≤x≤1. For example: the materials of sacrificial layer 14 and the layer to be oxidized 12 are Si. 0.2 Ge 0.8 Si 0.3 Ge 0.7 Si 0.4 Ge 0.6 or Si 0.5 Ge 0.5 Then, photolithography and etching processes can be used to form a mask layer on the alternately stacked channel layer 13 and sacrificial layer 14. Then, as... Figure 2 As shown, under the masking effect of the same mask layer, the remaining channel layers 13 and sacrificial layer 14 on the bottom channel layer 13 are patterned. At this time, the width of each channel layer 13 included in the first fin structure 17 is the same. Correspondingly, the width of the nanostructure 30 fabricated based on each channel layer 13 included in the first fin structure 17 is also equal.

[0067] Or, such as Figure 1 As shown, when at least three channel layers 13 are formed on the layer to be oxidized 12, the above-described patterning process of the remaining channel layers 13 and sacrificial layer 14 on the bottom channel layer 13 to form a first fin structure on the channel layer 13 may further include the step of: Figure 3As shown, the target layer is patterned using photolithography and etching processes to form a third fin structure 15. The target layer is the unpatterned channel layer 13 and / or sacrificial layer 14, currently located at the top layer. For example, when four channel layers and three sacrificial layers are formed on the layer to be oxidized, the number of channel layers and sacrificial layers is ordered in ascending order along the direction closest to the semiconductor substrate. In this case, during the first operation, the target layer can be either the channel layer in the first layer or both the channel layer and the sacrificial layer in the first layer. During the second operation, if the target layer was the channel layer in the first operation, the target layer for the second operation can be either the sacrificial layer in the first layer or both the sacrificial layer and the channel layer. If the target layer was both the channel layer and the sacrificial layer in the first operation, the target layer for the second operation can be either the channel layer in the second layer or both the channel layer and the sacrificial layer. Next, as... Figure 4 As shown, a third protective layer 16 covering the outer periphery of the third fin structure can be formed using processes such as deposition and etching. The material of this third protective layer 16 can be silicon nitride, etc. Along the width direction of the gate stack structure 31, the thickness of the third protective layer 16 can be determined based on the width difference between each pair of adjacent nanostructure layers. Then, as... Figures 5 to 7 As shown, the above operation is repeated until the first fin structure 17 is formed. The number of repetitions of the above operation can be determined based on the number of other channel layers 13 and sacrificial layers 14 located on the bottom channel layer 13, and the target layer object at each operation. For example, if four channel layers 13 and three sacrificial layers 14 are formed on the layer to be oxidized 12, and the target layer object at each operation is the unpatterned channel layer 13 and sacrificial layer 14 currently located on the top layer, the operation is performed three times.

[0068] After forming the first fin structure using at least the two methods described above, a first protective layer covering the outer periphery of the first fin structure can be formed using processes such as deposition and etching. The material of this first protective layer can be silicon nitride or similar materials. Along the width direction of the gate stack structure, the thickness of this first protective layer can be determined based on the difference between the width of the bottom nanostructure and the width of the penultimate nanostructure. Then, a dry etching or wet etching process can be used to etch only the oxide layer and the bottom channel layer. Alternatively, as... Figure 9 As shown in part (1), etching may also be performed only on the oxide layer 12, the channel layer 13 located at the bottom layer, and a portion of the semiconductor substrate 11. Next, the remaining portion of the oxide layer is selectively oxidized to form a dielectric structure 20. Then, as... Figure 14As shown in parts (1) and (2), the first protective layer can be removed by dry etching or wet etching processes.

[0069] If a third protective layer is formed during the formation of the first fin-like structure, then the third protective layer also needs to be removed after the first protective layer is removed. Alternatively, the third protective layer can be removed after the first fin-like structure is formed but before the first protective layer is formed.

[0070] The second method involves forming a dielectric structure on a semiconductor substrate, including: such as Figure 1 As shown, a layer 12 to be oxidized is formed on a semiconductor substrate 11, and a channel layer 13 and a sacrificial layer 14 are alternately stacked on the layer 12. The channel layer 13, located at the bottom, is in contact with the layer 12 to be oxidized. The material of the sacrificial layer 14 is the same as that of the layer 12 to be oxidized. Next, as... Figures 2 to 7 As shown, the remaining channel layers 13 and sacrificial layers 14 located on the bottom channel layer 13 are patterned to form a first fin structure 17 on the channel layer 13. Next, as... Figure 8 As shown in parts (1) and (2), a first protective layer 18 is formed covering the outer periphery of the first fin structure 17. Then, as... Figure 10 As shown in sections (1) and (2), the trench layer 13 located at the bottom layer is etched under the masking effect of the first protective layer 18. Next, as... Figure 11 As shown in portions (1) and (2) of the diagram, a second protective layer 19 is formed covering the sidewalls of the first protective layer 18 and the remaining portion of the channel layer 13 located at the bottom layer. Next, as... Figure 12 As shown in sections (1) and (2), under the masking effect of the first protective layer 18 and the second protective layer 19, at least the layer to be oxidized 12 is etched. Next, the remaining portion of the layer to be oxidized is selectively oxidized to form a dielectric structure 20. As... Figure 14 As shown in parts (1) and (2) of the diagram, the first and second protective layers are removed.

[0071] In the actual manufacturing process, before etching the bottom channel layer, the manufacturing process for the second method is the same as that for the first method, and will not be repeated here. The difference between the second and first methods in forming the first protective layer is that, under the masking effect of the first protective layer, the second method only etches the bottom channel layer, so that the width of the patterned bottom channel layer is greater than the width of the other channel layers. Then, deposition and etching processes are used, such as... Figure 11As shown in parts (1) and (2) of the diagram, a second protective layer 19 is formed covering the sidewalls of the first protective layer 18 and the remaining portion of the bottom channel layer 13. The material of this second protective layer 19 can be silicon nitride or similar materials. The manufacturing method provided in this embodiment of the invention does not limit the thickness of the second protective layer 19, as long as it can protect the bottom channel layer 13 during the subsequent selective oxidation treatment of the oxide layer 12. Then, as... Figure 12 As shown in parts (1) and (2), dry etching or wet etching processes can be used to etch at least the oxide layer 12 under the masking effect of the first protective layer 18 and the second protective layer 19. Next, the remaining portion of the oxide layer is selectively oxidized to form a dielectric structure 20. Then, as... Figure 14 As shown in parts (1) and (2), the first and second protective layers can be removed by dry etching or wet etching processes.

[0072] Among them, such as Figure 14 As shown in sections (1) and (2), after selective oxidation, the structure formed on the dielectric structure 20 is a second fin structure 22. This second fin structure 22 includes all the channel layers and sacrificial layers after patterning. In the above case, as... Figure 15 As shown in sections (1) and (2) above, a shallow trench isolation structure 21 can be formed on the isolation region of the semiconductor substrate 11 using at least deposition and etching processes. The material and top height of the shallow trench isolation structure 21 can be referred to above.

[0073] For example, forming an active structure on a semiconductor substrate as described above may include the following steps:

[0074] like Figure 16 As shown, processes such as deposition and etching can be used to form the sacrificial gate 23 and gate sidewall 24 spanning the second fin structure. The gate sidewall 24 is located on both sides of the sacrificial gate 23 along its length. The material of the sacrificial gate 23 can be polysilicon or similar materials. The material of the gate sidewall 24 can be found in the previous text.

[0075] Next, as Figure 17 As shown, at least a portion of the second fin structure is patterned under the masking effect of the sacrificial gate 23 and the gate sidewall 24, and along the direction close to the semiconductor substrate 11.

[0076] Specifically, such as Figure 17As shown, under the masking effect of the sacrificial gate 23 and the gate sidewall 24, and along the direction close to the semiconductor substrate 11, only the portion of the channel layer 13 located at the bottom layer of the second fin structure is patterned. Semiconductor structures 25 are formed on both sides of the channel layer 13 located at the bottom layer along the length direction of the gate stack structure.

[0077] Alternatively, the portion of the second fin structure exposed outside the sacrificial gate and gate sidewalls can be completely removed. In this case, both sides of the dielectric structure along its length are exposed.

[0078] Next, as Figure 18 As shown, epitaxial growth and other processes can be used to form source region 26 and drain region 27 on both sides of the second fin structure along its length.

[0079] It should be noted that, as Figure 17 and Figure 18 As shown, if the semiconductor structure 25 is retained after the second fin structure is patterned, then when forming the source region 26 and the drain region 27, not only can the remaining part of the channel layer be used as the epitaxial seed layer, but the retained semiconductor structure 25 can also be used as the epitaxial seed layer to improve the formation quality of the source region 26 and the drain region 27.

[0080] Next, as Figure 19 As shown, an interlayer dielectric layer 28 can be formed on the semiconductor substrate 11 using processes such as deposition and planarization. The top of the interlayer dielectric layer 28 is flush with the top of the sacrificial gate 23. The material of the interlayer dielectric layer 28 can be referred to above.

[0081] Then, as Figure 20 As shown, dry etching or wet etching processes can be used to remove the sacrificial gate and the exposed portion of each sacrificial layer, so that the exposed portion of each channel layer forms the corresponding nanostructure 30, thereby obtaining the active structure.

[0082] Next, as Figure 21 as well as Figure 22 As shown in sections (1) and (2) above, the gate stack structure 31 can be formed using processes such as atomic layer deposition. This gate stack structure 31 is formed on the surface of the bottom nanostructure 30 that is not in contact with the dielectric structure 20, and surrounds the outer periphery of the remaining nanostructures 30. Specific information regarding the structure and materials of this gate stack structure 31 can be found above and will not be repeated here.

[0083] It should be noted that the above-described active structure and gate stack structure can be formed in various ways. How the above-described active structure and gate stack structure are formed is not the main feature of this invention; therefore, this specification only provides a brief description to enable those skilled in the art to easily implement this invention. Those skilled in the art can certainly conceive of other ways to fabricate the above-described active structure and gate stack structure.

[0084] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0085] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0086] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A transistor, characterized in that, include: Semiconductor substrate, An active structure is formed on the semiconductor substrate; the active structure includes a source region, a drain region, and a channel region located between the source region and the drain region; Along the thickness direction of the semiconductor substrate, the channel region includes at least two layers of nanostructures; in the channel region, the width of the bottom nanostructure is greater than the width of the remaining nanostructures; A dielectric structure is formed between the semiconductor substrate and the active structure; the dielectric structure is in contact with the nanostructure located on the underlying layer; A gate stack structure is formed on the surface of the bottom nanostructure that is not in contact with the dielectric structure and surrounds the outer periphery of the remaining nanostructures; The transistor also includes a semiconductor structure integrally formed with the underlying nanostructure; the semiconductor structure is located between the source region and the dielectric structure, and between the drain region and the dielectric structure.

2. The transistor according to claim 1, characterized in that, In the channel region, except for the nanostructure located at the bottom layer, the widths of the remaining nanostructures are equal; or, Along the direction close to the semiconductor substrate, the width of the different layers of nanostructures included in the channel region gradually increases.

3. The transistor according to claim 2, characterized in that, The central axes of the different layers of nanostructures in the channel region coincide.

4. The transistor according to claim 1, characterized in that, The width of the dielectric structure is smaller than the width of the nanostructure located at the bottom layer.

5. A method for manufacturing a transistor, characterized in that, include: Provide a semiconductor substrate; A dielectric structure, an active structure, and a semiconductor structure are formed on the semiconductor substrate; the active structure includes a source region, a drain region, and a channel region located between the source region and the drain region; along the thickness direction of the semiconductor substrate, the channel region includes at least two nanostructures; in the channel region, the width of the bottom nanostructure is greater than the width of the remaining nanostructures; the dielectric structure is formed between the semiconductor substrate and the active structure and is in contact with the bottom nanostructure; The semiconductor structure is integrally formed with the underlying nanostructure; The semiconductor structure is located between the source region and the dielectric structure, and between the drain region and the dielectric structure; A gate stack structure is formed; the gate stack structure is formed on the surface of the bottom nanostructure that is not in contact with the dielectric structure and surrounds the outer periphery of the remaining nanostructures.

6. The method for manufacturing a transistor according to claim 5, characterized in that, Forming the dielectric structure on the semiconductor substrate includes: An oxide layer is formed on the semiconductor substrate, and a channel layer and a sacrificial layer are alternately stacked on the oxide layer; the channel layer at the bottom layer is in contact with the oxide layer; the material of the sacrificial layer is the same as that of the oxide layer. The remaining channel layers and the sacrificial layer located on the bottom channel layer are patterned to form a first fin structure on the channel layer; A first protective layer is formed covering the outer periphery of the first fin-like structure; Under the masking effect of the first protective layer, at least the channel layer and the layer to be oxidized located at the bottom layer are etched; The remaining portion of the layer to be oxidized is selectively oxidized to form the dielectric structure. Remove the first protective layer.

7. The method for manufacturing a transistor according to claim 5, characterized in that, Forming the dielectric structure on the semiconductor substrate includes: An oxide layer is formed on the semiconductor substrate, and a channel layer and a sacrificial layer are alternately stacked on the oxide layer; the channel layer at the bottom layer is in contact with the oxide layer; the material of the sacrificial layer is the same as that of the oxide layer. The remaining channel layers and the sacrificial layer located on the bottom channel layer are patterned to form a first fin structure on the channel layer; A first protective layer is formed covering the outer periphery of the first fin-like structure; Under the masking effect of the first protective layer, the channel layer located at the bottom layer is etched; A second protective layer is formed over the sidewalls of the first protective layer and the remaining portion of the channel layer located at the bottom layer; Under the masking effect of the first and second protective layers, at least the layer to be oxidized is etched; The remaining portion of the layer to be oxidized is selectively oxidized to form the dielectric structure. Remove the first protective layer and the second protective layer.

8. The method for manufacturing a transistor according to claim 6 or 7, characterized in that, The sacrificial layer and the layer to be oxidized are made of Si. 1-x Ge x , 0.2≤x≤1; and / or, The channel layer is made of Si.

9. The method for manufacturing a transistor according to claim 6 or 7, characterized in that, After the selective oxidation treatment, the structure formed on the dielectric structure is a second fin-like structure; An active structure is formed on the semiconductor substrate, including: A sacrificial gate and a gate sidewall are formed across the second fin structure; the gate sidewall is located on both sides of the sacrificial gate along its length. Under the masking effect of the sacrificial gate and gate sidewall, and along the direction close to the semiconductor substrate, at least a portion of the second fin structure is patterned. The source region and the drain region are formed on both sides of the second fin structure along its length. The sacrificial gate and the exposed portion of each sacrificial layer are removed so that the exposed portion of each channel layer forms a corresponding layer nanostructure.

10. The method for manufacturing a transistor according to claim 9, characterized in that, The patterning of at least a portion of the second fin structure under the masking action of the sacrificial gate and gate sidewalls, and along a direction close to the semiconductor substrate, includes: Under the masking effect of the sacrificial gate and gate sidewalls, and along the direction close to the semiconductor substrate, the portion of the channel layer located on the bottom layer of the second fin structure is patterned; wherein, along the length direction of the gate stack structure, the two side edge portions of the channel layer located on the bottom layer form semiconductor structures.

11. The method for manufacturing a transistor according to claim 6 or 7, characterized in that, The step of patterning the remaining channel layers and the sacrificial layer located on the bottom channel layer to form a first fin-like structure on the channel layers includes: Under the masking effect of the same mask layer, the remaining channel layers and the sacrificial layer located on the bottom channel layer are patterned.

12. The method for manufacturing a transistor according to claim 6 or 7, characterized in that, At least three channel layers are formed on the layer to be oxidized; The step of patterning the remaining channel layers and the sacrificial layer located on the bottom channel layer to form a first fin-like structure on the channel layers includes: The target layer is patterned to form a third fin structure; the target layer is the unpatterned channel layer and / or the sacrificial layer that is currently on top. A third protective layer is formed covering the outer periphery of the third fin-like structure; Repeat the above operation until the first fin-like structure is formed.

Images