An error amplifier and LED control circuit

Abstract

This invention provides an error amplifier and an LED control circuit. The amplifier includes an input stage circuit, a current bias circuit, a voltage bias circuit, an amplification stage circuit, and an output stage circuit. The input stage circuit increases the voltage input values ​​at the voltage sampling terminal and the reference voltage terminal. The current bias circuit generates a bias current. The voltage bias circuit converts the bias current into a bias voltage. The output terminal of the amplification stage circuit is connected to the output stage circuit to amplify the error between the sampled voltage output from the voltage sampling terminal and the reference voltage, and outputs an amplified error voltage through the output stage circuit. This invention increases the voltage input values ​​at the voltage sampling terminal and the reference voltage terminal through the input stage circuit, thereby increasing the voltage input range of the error amplifier, preventing the input voltage at the voltage sampling terminal from being too low and affecting the normal operation of the amplifier, and improving the application scenarios of the amplifier.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to an error amplifier and an LED control circuit. Background Technology

[0002] An error amplifier is an amplifier used to amplify output errors. It has two input terminals: one connected to the reference voltage and the other connected to the output voltage of the feedback point. When there is a difference between the output voltage of the feedback point and the reference voltage, the error amplifier amplifies this difference and then clamps the output voltage of the feedback point to match the reference voltage through the feedback control loop of the subsequent stage.

[0003] In existing technologies, the input terminal of the error amplifier directly samples the output voltage of the feedback point. When the output voltage of the feedback point is very low, the error amplifier cannot work properly, which affects the application scenarios and working accuracy of the error amplifier. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides an error amplifier and an LED control circuit, which solves the problem that the error amplifier in the prior art suffers from excessively low input voltage, affecting normal operation.

[0005] In a first aspect, the present invention provides an error amplifier, the amplifier comprising: an input stage circuit, a current bias circuit, a voltage bias circuit, an amplification stage circuit, and an output stage circuit; a first input terminal of the input stage circuit is connected to a voltage sampling terminal, and a second input terminal of the input stage circuit is connected to a reference voltage terminal, for increasing the voltage input values ​​of the voltage sampling terminal and the reference voltage terminal; the current bias circuit is used to generate a bias current; the input terminal of the voltage bias circuit is connected to the output terminal of the current bias circuit, for converting the bias current into a bias voltage; the input terminal of the amplification stage circuit is connected to the output terminal of the input stage circuit, the voltage bias terminal of the amplification stage is connected to the output terminal of the voltage bias circuit, and the output terminal of the amplification stage circuit is connected to the output stage circuit for amplifying the error between the sampled voltage output from the voltage sampling terminal and the reference voltage, and outputting an amplified error voltage through the output stage circuit.

[0006] Optionally, the input stage circuit includes: a first transistor, a second transistor, a third transistor, and a fourth transistor; the base of the first transistor is connected to the voltage sampling terminal, the emitter of the first transistor is connected to the base of the third transistor, and the collector of the third transistor is the first output terminal of the input stage circuit; the base of the second transistor is connected to the reference voltage terminal, the emitter of the second transistor is connected to the base of the fourth transistor, and the collector of the fourth transistor is the second output terminal of the input stage circuit; the emitters of the first transistor, the second transistor, the third transistor, and the fourth transistor are respectively connected to the output terminal of the current bias circuit, and the collectors of the first transistor, the second transistor, the third transistor, and the fourth transistor are respectively grounded.

[0007] Optionally, the input stage circuit further includes: a fifth transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor; the emitter of the fifth transistor is connected to the current bias circuit, the base of the fifth transistor, the drain of the first NMOS transistor, the gate of the first NMOS transistor, and the gate of the second NMOS transistor are respectively connected to the gate of the third NMOS transistor, the drain of the second NMOS transistor is connected to the base of the first transistor, and the gate of the third NMOS transistor is connected to the base of the second transistor; the collector of the fifth transistor, the source of the first NMOS transistor, the source of the second NMOS transistor, and the source of the third NMOS transistor are respectively grounded.

[0008] Optionally, the voltage biasing circuit includes: a first resistor, a fourth NMOS transistor, and a fifth NMOS transistor; the drain of the fourth NMOS transistor is connected to the output terminal of the current biasing circuit through the first resistor, and the gate of the fourth NMOS transistor is the first output terminal of the voltage biasing circuit; the drain of the fifth NMOS transistor is connected to the source of the fourth NMOS transistor, the gate of the fifth NMOS transistor is connected to the drain of the fourth NMOS transistor, and the source of the fifth NMOS transistor is grounded; wherein, the gate of the fifth NMOS transistor is the second output terminal of the voltage biasing circuit.

[0009] Optionally, the amplification stage circuit includes: a first PMOS transistor, a second PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor; the drain of the first PMOS transistor and the drain of the second PMOS transistor are respectively connected to an external power supply, and the gate and source of the first PMOS transistor are respectively connected to the gate of the second PMOS transistor; the gate of the sixth NMOS transistor and the gate of the seventh NMOS transistor are respectively connected to the first output terminal of the voltage bias circuit, and the drain of the sixth NMOS transistor is connected to the source of the first PMOS transistor. The source of the sixth NMOS transistor is connected to the collector of the fourth transistor, the source of the seventh NMOS transistor is connected to the collector of the third transistor, and the drain of the seventh NMOS transistor is connected to the source of the second PMOS transistor. The gates of the eighth and ninth NMOS transistors are respectively connected to the second output terminal of the voltage bias circuit. The drain of the eighth NMOS transistor is connected to the source of the sixth NMOS transistor, and the drain of the ninth NMOS transistor is connected to the source of the seventh NMOS transistor. The sources of the eighth and ninth NMOS transistors are grounded.

[0010] Optionally, the output stage circuit includes: a tenth NMOS transistor and a second resistor; the gate of the tenth NMOS transistor is connected to the drain of the seventh NMOS transistor, the drain of the tenth NMOS transistor is connected to an external power supply, and the source of the tenth NMOS transistor is grounded through the second resistor.

[0011] Optionally, the current biasing circuit includes: a constant current source, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor; the output terminal of the constant current source is connected to the gate and source of the third PMOS transistor; the gates of the fourth, fifth, sixth, seventh, and eighth PMOS transistors are respectively connected to the gate of the third PMOS transistor; the drains of the third, fourth, fifth, sixth, seventh, and eighth PMOS transistors are respectively connected to the power supply output terminal; and the sources of the fourth, fifth, sixth, seventh, and eighth PMOS transistors respectively output bias current.

[0012] Secondly, the present invention provides an LED control circuit, the control circuit comprising: an error amplifier, a reference voltage generator, a ramp signal generation module, a PWM generator, a current limiting comparator, a logic control module, and a constant current generation module; the ramp signal generation module is used to output a first current and also to generate a ramp signal of a preset frequency; the first input terminal of the error amplifier is connected to the output terminal of the constant current generation module, and the second input terminal of the error amplifier is connected to the first output terminal of the reference voltage generator, for amplifying the error between the output voltage of the constant current generation module and the reference voltage output by the reference voltage generator to obtain an error amplified signal; the first input terminal of the PWM generator is connected to the output terminal of the error amplifier, and the second input terminal of the PWM generator is connected to the first output terminal of the ramp signal generation module, for comparing the error amplified signal with the ramp signal. The current limiting comparator is connected to the first input terminal of the current limiting comparator and the second output terminal of the reference voltage generator. The second input terminal of the current limiting comparator is connected to the first output terminal of the ramp signal generation module. The ramp signal is compared with the current limiting reference voltage to obtain the current limiting comparison result. The input terminal of the logic control module is connected to the output terminal of the current limiting comparator and the output terminal of the PWM generator. The logic control module generates a logic control signal based on the current limiting comparison result output by the current limiting comparator and the PWM signal. The first input terminal of the constant current generation module is connected to the second output terminal of the ramp signal generation module. The second input terminal of the constant current generation module is connected to the output terminal of the logic control module. The output terminal of the constant current generation module is connected to an LED. The constant current generation module generates a constant second current from the first current based on the logic control signal.

[0013] Optionally, the ramp signal generation module includes: an oscillator, a ramp compensator, a superimposed converter, a current sampling generator, and a third resistor; the oscillator is used to generate a frequency signal; the first input terminal of the current sampling generator is connected to the power output terminal, and the second input terminal of the current sampling generator is connected to the first input terminal of the current sampling generator through the third resistor, for sampling the voltage across the third resistor to obtain a sampled current; the input terminal of the ramp compensator is connected to the output terminal of the oscillator, for generating a ramp compensation signal; the input terminal of the superimposed converter is connected to the output terminal of the ramp compensator and the output terminal of the current sampling generator, respectively, for superimposing the sampled current and the ramp compensation signal to generate the ramp signal of the preset frequency; wherein, the output terminal of the superimposed converter is the first output terminal of the ramp signal generation module, and the second input terminal of the current generator is the second output terminal of the ramp signal generation module.

[0014] Optionally, the constant current generation module includes: a driving unit, a MOSFET, an inductor, a capacitor, a diode, and a fourth resistor; the input terminal of the driving unit is connected to the output terminal of the logic control module, the output terminal of the driving unit is connected to the gate of the MOSFET, the drain of the MOSFET is connected to the second output terminal of the ramp signal generation module, the source of the MOSFET is connected to the first terminal of the inductor and the cathode of the diode, the second terminal of the inductor is connected to the first terminal of the capacitor and the anode of the LED, the second terminal of the capacitor and the anode of the diode are grounded, the first terminal of the fourth resistor is connected to the cathode of the LED, and the second terminal of the fourth resistor is grounded.

[0015] Compared with the prior art, the present invention has the following beneficial effects:

[0016] The error amplifier in this invention receives the sampling voltage output from the voltage sampling terminal and the reference voltage output from the reference voltage terminal through the input stage circuit. It generates a differential signal based on the bias current, the sampling voltage, and the reference voltage. The differential signal is then amplified by the amplification stage circuit, and the amplified error voltage is output to the subsequent stage circuit through the output stage circuit. In this invention, the voltage input values ​​at the voltage sampling terminal and the reference voltage terminal are increased by the input stage circuit, thereby increasing the voltage input range of the error amplifier, preventing the input voltage at the voltage sampling terminal from being too low and affecting the normal operation of the amplifier, and improving the application scenarios of the amplifier. Attached Figure Description

[0017] Figure 1 A schematic diagram of the structure of an error amplifier provided in an embodiment of the present invention;

[0018] Figure 2 A circuit diagram of an error amplifier provided for an embodiment of the present invention;

[0019] Figure 3 This is a current diagram of an LED control circuit provided in an embodiment of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] In the examples of this invention, functional units with the same reference numerals have the same and similar structures and functions.

[0022] In a first aspect, the present invention provides an error amplifier, specifically including the following embodiments:

[0023] Example 1

[0024] Figure 1 A schematic diagram of an error amplifier provided in an embodiment of the present invention is shown below. Figure 1 As shown, the amplifier 100 includes:

[0025] Input stage circuit 110, current bias circuit 120, voltage bias circuit 130, amplifier stage circuit 140, and output stage circuit 150;

[0026] The first input terminal of the input stage circuit 110 is connected to the voltage sampling terminal, and the second input terminal of the input stage circuit 110 is connected to the reference voltage terminal, which is used to increase the voltage input value of the voltage sampling terminal and the reference voltage terminal.

[0027] The current bias circuit 120 is used to generate a bias current;

[0028] The input terminal of the voltage bias circuit 130 is connected to the output terminal of the current bias circuit 120, and is used to convert the bias current into a bias voltage.

[0029] The input terminal of the amplifier stage circuit 140 is connected to the output terminal of the input stage circuit 110, the voltage bias terminal of the amplifier stage is connected to the output terminal of the voltage bias circuit 130, and the output terminal of the amplifier stage circuit 140 is connected to the output stage circuit 150 to amplify the error between the sampled voltage and the reference voltage output by the voltage sampling terminal, and output the error amplified voltage through the output stage circuit 150.

[0030] It should be noted that, in this embodiment, the error amplifier receives the sampling voltage output from the voltage sampling terminal and the reference voltage output from the reference voltage terminal through the input stage circuit, and generates a differential signal based on the bias current, the sampling voltage, and the reference voltage. The differential signal is then amplified by the amplification stage circuit, and the amplified error voltage is output to the subsequent stage circuit through the output stage circuit. In this embodiment, the voltage input values ​​of the voltage sampling terminal and the reference voltage terminal are increased by the input stage circuit, thereby increasing the voltage input range of the error amplifier, preventing the input voltage of the voltage sampling terminal from being too low and affecting the normal operation of the amplifier, and improving the application scenarios of the amplifier.

[0031] Example 2

[0032] Figure 2 A circuit diagram of an error amplifier provided in an embodiment of the present invention is shown below. Figure 2As shown, in this embodiment, the input stage circuit includes: a first transistor Q1, a second transistor Q2, a third transistor Q3, and a fourth transistor Q4; the base of the first transistor Q1 is connected to the voltage sampling terminal, the emitter of the first transistor Q1 is connected to the base of the third transistor Q3, and the collector of the third transistor Q3 is the first output terminal of the input stage circuit; the base of the second transistor Q2 is connected to the reference voltage terminal, and the emitter of the second transistor Q2 is connected to the base of the third transistor Q3. The base of the fourth transistor Q4 is connected, and the collector of the fourth transistor Q4 is the second output terminal of the input stage circuit; the emitters of the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 are respectively connected to the output terminal of the current bias circuit, and the collectors of the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 are respectively grounded.

[0033] It should be noted that the error amplifier in this embodiment does not directly sample the output voltage. Instead, it connects to the voltage sampling terminal and the reference voltage terminal via transistors Q1 and Q2, respectively, which can raise the VBE voltage and increase the input voltage range of the error amplifier. Furthermore, by using PNP transistors Q3 and Q4 as the input pair, the input offset voltage can be reduced, thereby improving the voltage sampling accuracy.

[0034] In this embodiment, the input stage circuit further includes: a fifth transistor Q5, a first NMOS transistor MN1, a second NMOS transistor MN2, and a third NMOS transistor MN3; the emitter of the fifth transistor Q5 is connected to the current bias circuit, the base of the fifth transistor Q5, the drain of the first NMOS transistor MN1, the gate of the first NMOS transistor MN1, and the gate of the second NMOS transistor MN2 are respectively connected to the gate of the third NMOS transistor, the drain of the second NMOS transistor MN2 is connected to the base of the first transistor Q1, and the gate of the third NMOS transistor MN3 is connected to the base of the second transistor Q2; the collector of the fifth transistor Q5, the source of the first NMOS transistor MN1, the source of the second NMOS transistor MN2, and the source of the third NMOS transistor MN3 are respectively grounded.

[0035] It should be noted that in this embodiment, there will be base current in the first transistor Q1 and the second transistor Q2. In order to eliminate the influence of base current on sampling accuracy, the first NMOS transistor MN1, the second NMOS transistor MN2 and the third NMOS transistor MN3 are connected to the base of the transistor respectively, so that the base current can be released to ground through the MOS transistor and the influence of base current on sampling accuracy can be eliminated.

[0036] In this embodiment, the voltage biasing circuit includes: a first resistor R1, a fourth NMOS transistor MN4, and a fifth NMOS transistor MN5; the drain of the fourth NMOS transistor MN4 is connected to the output terminal of the current biasing circuit through the first resistor R1, and the gate of the fourth NMOS transistor MN4 is the first output terminal of the voltage biasing circuit; the drain of the fifth NMOS transistor MN5 is connected to the source of the fourth NMOS transistor MN4, the gate of the fifth NMOS transistor MN5 is connected to the drain of the fourth NMOS transistor MN4, and the source of the fifth NMOS transistor MN5 is grounded; wherein, the gate of the fifth NMOS transistor MN5 is the second output terminal of the voltage biasing circuit.

[0037] In this embodiment, the amplification stage circuit includes: a first PMOS transistor MP1, a second PMOS transistor MP2, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, and a ninth NMOS transistor MN9; the drains of the first PMOS transistor MP1 and the second PMOS transistor MP2 are respectively connected to an external power supply, and the gates and sources of the first PMOS transistor MP1 are respectively connected to the gates of the second PMOS transistor MP2; the gates of the sixth NMOS transistor MN6 and the seventh NMOS transistor MN7 are respectively connected to the first output terminal of the voltage bias circuit, and the drain of the sixth NMOS transistor MN6 is connected to the first output terminal of the first PMOS transistor MP1. The sources of the sixth NMOS transistor MN6 are connected to the collector of the fourth transistor Q4, the source of the seventh NMOS transistor MN7 is connected to the collector of the third transistor Q3, and the drain of the seventh NMOS transistor MN7 is connected to the source of the second PMOS transistor MP2. The gates of the eighth NMOS transistor MN8 and the ninth NMOS transistor MN9 are respectively connected to the second output terminal of the voltage bias circuit. The drain of the eighth NMOS transistor MN8 is connected to the source of the sixth NMOS transistor MN6, and the drain of the ninth NMOS transistor MN9 is connected to the source of the seventh NMOS transistor MN7. The sources of the eighth NMOS transistor MN8 and the ninth NMOS transistor MN9 are grounded.

[0038] In this embodiment, the output stage circuit includes: a tenth NMOS transistor MN10 and a second resistor R2; the gate of the tenth NMOS transistor MN10 is connected to the drain of the seventh NMOS transistor MN7, the drain of the tenth NMOS transistor MN10 is connected to an external power supply, and the source of the tenth NMOS transistor MN10 is grounded through the second resistor R2.

[0039] In this embodiment, the current bias circuit includes: a constant current source, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, and an eighth PMOS transistor MP8; the output terminal of the constant current source is connected to the gate and source of the third PMOS transistor MP3, and the gates of the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the seventh PMOS transistor MP7, and the eighth PMOS transistor MP8 are... The drain of the third PMOS transistor MP3 is not connected to the gate of the fourth PMOS transistor MP4, the drain of the fifth PMOS transistor MP5, the drain of the sixth PMOS transistor MP6, the drain of the seventh PMOS transistor MP7, and the drain of the eighth PMOS transistor MP8 are respectively connected to the power output terminal. The source of the fourth PMOS transistor MP4, the source of the fifth PMOS transistor MP5, the source of the sixth PMOS transistor MP6, the source of the seventh PMOS transistor MP7, and the source of the eighth PMOS transistor MP8 respectively output bias current.

[0040] As can be seen, the error amplifier in this embodiment does not directly sample the output voltage. Instead, it raises the VBE voltage by one step through transistors Q1 and Q2, increasing the input voltage range of the error amplifier. However, the base current of Q1 and Q2 will affect the sampling accuracy. Therefore, the structure of MN1, MN2, and MN3 is used to eliminate the influence of the base current on the sampling accuracy. The input pair transistors Q3 and Q4 are PNP transistors to reduce the input offset voltage. A folded cascode structure is used to increase the DC gain of the error amplifier. The error amplifier amplifies the difference between the FB voltage and the VREF voltage, and outputs the voltage VO to the next stage circuit, the PWM generator. Therefore, the error amplifier in this embodiment improves the output voltage sampling accuracy, reduces the error amplifier offset voltage, increases the DC gain of the error amplifier, and improves the output constant current accuracy.

[0041] Secondly, the present invention provides an LED control circuit, specifically including the following embodiments:

[0042] Example 3

[0043] Figure 3 A current diagram of an LED control circuit provided in an embodiment of the present invention is shown below. Figure 3 As shown, the LED control circuit includes:

[0044] The error amplifier EA, reference voltage generator REF, ramp signal generation module 210, PWM generator EB, current limiting comparator ED, logic control module LG, and constant current generation module 220 described in Embodiment 1 or Embodiment 2;

[0045] The ramp signal generation module 210 is used to output a first current and also to generate a ramp signal of a preset frequency.

[0046] The first input terminal of the error amplifier EA is connected to the output terminal of the constant current generation module 220, and the second input terminal of the error amplifier EA is connected to the first output terminal of the reference voltage generator REF. It is used to amplify the error between the output voltage of the constant current generation module 220 and the reference voltage output by the reference voltage generator REF to obtain an error amplification signal.

[0047] The first input terminal of the PWM generator EB is connected to the output terminal of the error amplifier EA, and the second input terminal of the PWM generator EB is connected to the first output terminal of the ramp signal generation module 210. It is used to compare the error amplification signal and the ramp signal, and generate a PWM signal based on the comparison result.

[0048] The first input terminal of the current limiting comparator ED is connected to the second output terminal of the reference voltage generator REF, and the second input terminal of the current limiting comparator ED is connected to the first output terminal of the ramp signal generation module 210, which is used to compare the ramp signal with the current limiting reference voltage to obtain the current limiting comparison result.

[0049] The input terminal of the logic control module LG is connected to the output terminal of the current limiting comparator ED and the output terminal of the PWM generator EB, respectively, and is used to generate a logic control signal based on the current limiting comparison result output by the current limiting comparator ED and the PWM signal.

[0050] The first input terminal of the constant current generation module 220 is connected to the second output terminal of the ramp signal generation module 210, the second input terminal of the constant current generation module 220 is connected to the output terminal of the logic control module LG, and the output terminal of the constant current generation module 220 is connected to the LED, which is used to generate a constant second current from the first current according to the logic control signal.

[0051] It should be noted that the working process of the LED control circuit in this embodiment is as follows: the error amplifier EA amplifies the output voltage of the constant current generation module 220 and the reference voltage output by the reference voltage generator REF to obtain an error amplification signal; the PWM generator EB compares the error amplification signal with the ramp signal and generates a PWM signal based on the comparison result; the logic control module LG generates a logic control signal based on the current limiting comparison result output by the current limiting comparator ED and the PWM signal, so that the constant current generation module 220 generates a constant second current from the first current according to the logic control signal, thereby driving the LED to emit light stably.

[0052] It should be further explained that, in order to drive the LED to emit light stably, the LED control circuit samples the PWM pulse width modulation output to maintain a constant current. PWM pulse width modulation adjusts the output voltage by changing the pulse duty cycle while keeping the pulse frequency constant. The error amplifier EA amplifies the error between the output signal and the reference voltage, and then compares the output voltage of the error amplifier EA with the ramp signal to obtain the duty cycle signal. Finally, when the loop stabilizes, the output voltage of the error amplifier EA remains basically unchanged, the duty cycle remains unchanged, and the output voltage is stable, thus ensuring a constant current flowing through the LED and achieving the purpose of stable driving. The error amplifier EA plays a very important role in the LED control circuit. By using the error amplifier EA in Embodiment 1 or Embodiment 2, a more accurate constant current can be obtained.

[0053] In this embodiment, the ramp signal generation module 210 includes: an oscillator OSC, a ramp compensator RAMP, a superimposed converter DA, a current sampling generator EC, and a third resistor R3; the oscillator OSC is used to generate a frequency signal; the first input terminal of the current sampling generator EC is connected to the power output terminal, and the second input terminal of the current sampling generator EC is connected to the first input terminal of the current sampling generator EC through the third resistor R3, for sampling the voltage across the third resistor R3 to obtain a sampled current; the input terminal of the ramp compensator RAMP is connected to the output terminal of the oscillator OSC, for generating a ramp compensation signal; the input terminal of the superimposed converter DA is connected to the output terminal of the ramp compensator RAMP and the output terminal of the current sampling generator EC, respectively, for superimposing the sampled current and the ramp compensation signal to generate a ramp signal of the preset frequency;

[0054] Wherein, the output terminal of the superimposed unit DA is the first output terminal of the ramp signal generation module 210, and the second input terminal of the current generator is the second output terminal of the ramp signal generation module 210.

[0055] In this embodiment, the constant current generation module 220 includes: a driving unit DR, a MOSFET M1, an inductor L, a capacitor C, a diode D1, and a fourth resistor R4. The input terminal of the driving unit DR is connected to the output terminal of the logic control module LG, the output terminal of the driving unit DR is connected to the gate of the MOSFET M1, the drain of the MOSFET M1 is connected to the second output terminal of the ramp signal generation module 210, the source of the MOSFET M1 is connected to the first terminal of the inductor L and the cathode of the diode D1, the second terminal of the inductor L is connected to the first terminal of the capacitor C and the anode of the LED, the second terminal of the capacitor C and the anode of the diode D1 are grounded, the first terminal of the fourth resistor R4 is connected to the cathode of the LED, and the second terminal of the fourth resistor R4 is grounded. Figure 3 The drive unit DR also includes a power module (not shown), so the drive unit DR and the source of the MOSFET are connected to a floating ground.

[0056] It should be noted that in this embodiment, the output current Iout = Vfb / R4. If Vfb is stable, a constant output current can be obtained. An error amplifier is used to determine the voltage Vfb = Vref. The PWM generator compares the amplifier output voltage with the ramp voltage to generate a PWM signal. The current limiting comparator compares the ramp signal VSLOPE with the current limiting voltage reference, limiting the maximum current cycle by cycle. An oscillator generates a frequency signal. A ramp compensator generates a ramp compensation signal for ramp compensation, avoiding subharmonic oscillations. An overlay unit adds the current sample and ramp compensation to generate a ramp signal of the preset frequency, which is used to generate the PWM signal and the current limiting circuit. The logic control module controls the switching of the power transistor based on the oscillation signal, the current limiting signal, and the PWM signal.

[0057] In this embodiment, the driving unit drives the MOS transistor to turn on or off according to the control signal output by the logic control module, thereby causing the LC oscillation circuit composed of inductor and capacitor to oscillate, so that the current flowing through the LED remains constant.

[0058] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0059] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. An error amplifier, characterized in that, The amplifier includes: The current bias circuit includes a constant current source unit and a current mirror unit; the constant current source unit is used to generate a reference current, and the current mirror unit mirrors the reference current to generate a bias current. The input stage circuit has a first input terminal connected to a voltage sampling terminal and a second input terminal connected to a reference voltage terminal. The input stage circuit includes a voltage boosting unit and a differential input unit. The voltage boosting unit boosts the sampling voltage output from the voltage sampling terminal and the reference voltage output from the reference voltage terminal according to the bias current. The differential input unit compares the boosted voltages to generate a differential signal. The input stage circuit specifically includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor; The base of the first transistor is connected to the voltage sampling terminal, the emitter of the first transistor is connected to the base of the third transistor, and the collector of the third transistor is the first output terminal of the input stage circuit. The base of the second transistor is connected to the reference voltage terminal, the emitter of the second transistor is connected to the base of the fourth transistor, and the collector of the fourth transistor is the second output terminal of the input stage circuit. The emitters of the first transistor, the second transistor, the third transistor, and the fourth transistor are respectively connected to the output terminal of the current bias circuit, and the collectors of the first transistor, the second transistor, the third transistor, and the fourth transistor are respectively grounded. The emitter of the fifth transistor is connected to the current bias circuit. The base of the fifth transistor, the drain of the first NMOS transistor, the gate of the first NMOS transistor, and the gate of the second NMOS transistor are respectively connected to the gate of the third NMOS transistor. The drain of the second NMOS transistor is connected to the base of the first transistor. The gate of the third NMOS transistor is connected to the base of the second transistor. The collector of the fifth transistor, the source of the first NMOS transistor, the source of the second NMOS transistor, and the source of the third NMOS transistor are respectively grounded. A voltage bias circuit, whose input terminal is connected to the output terminal of the current bias circuit, receives the bias current, performs voltage conversion to generate a bias voltage, and is used to provide operating bias for the amplifier stage circuit. An amplifier stage circuit has its input terminal connected to the output terminal of the input stage circuit, and its voltage bias terminal connected to the output terminal of the voltage bias circuit; the amplifier stage circuit amplifies the differential signal through a folded common-source common-gate structure to obtain an error amplified signal; The output stage circuit has its input terminal connected to the output terminal of the amplifier stage circuit. It receives the error amplification signal, performs current-to-voltage conversion, and outputs the error amplification voltage.

2. An error amplifier as described in claim 1, characterized in that, The voltage biasing circuit includes: First resistor, fourth NMOS transistor, and fifth NMOS transistor; The drain of the fourth NMOS transistor is connected to the output terminal of the current bias circuit through the first resistor, and the gate of the fourth NMOS transistor is the first output terminal of the voltage bias circuit. The drain of the fifth NMOS transistor is connected to the source of the fourth NMOS transistor, the gate of the fifth NMOS transistor is connected to the drain of the fourth NMOS transistor, and the source of the fifth NMOS transistor is grounded; wherein, the gate of the fifth NMOS transistor is the second output terminal of the voltage bias circuit.

3. An error amplifier as described in claim 1, characterized in that, The amplifier stage circuit includes: The first PMOS transistor, the second PMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, and the ninth NMOS transistor; The drain of the first PMOS transistor and the drain of the second PMOS transistor are respectively connected to an external power supply, and the gate of the first PMOS transistor and the source of the first PMOS transistor are respectively connected to the gate of the second PMOS transistor. The gates of the sixth NMOS transistor and the seventh NMOS transistor are respectively connected to the first output terminal of the voltage bias circuit. The drain of the sixth NMOS transistor is connected to the source of the first PMOS transistor. The source of the sixth NMOS transistor is connected to the collector of the fourth transistor. The source of the seventh NMOS transistor is connected to the collector of the third transistor. The drain of the seventh NMOS transistor is connected to the source of the second PMOS transistor. The gates of the eighth NMOS transistor and the ninth NMOS transistor are respectively connected to the second output terminal of the voltage bias circuit. The drain of the eighth NMOS transistor is connected to the source of the sixth NMOS transistor, and the drain of the ninth NMOS transistor is connected to the source of the seventh NMOS transistor. The sources of the eighth and ninth NMOS transistors are grounded.

4. An error amplifier as described in claim 3, characterized in that, The output stage circuit includes: The tenth NMOS transistor and the second resistor; The gate of the tenth NMOS transistor is connected to the drain of the seventh NMOS transistor, the drain of the tenth NMOS transistor is connected to an external power supply, and the source of the tenth NMOS transistor is grounded through the second resistor.

5. An error amplifier as described in claim 1, characterized in that, The current biasing circuit includes: Constant current source, third PMOS transistor, fourth PMOS transistor, fifth PMOS transistor, sixth PMOS transistor, seventh PMOS transistor and eighth PMOS transistor; The output terminal of the constant current source is connected to the gate and source of the third PMOS transistor. The gates of the fourth, fifth, sixth, seventh, and eighth PMOS transistors are connected to the gate of the third PMOS transistor. The drains of the third, fourth, fifth, sixth, seventh, and eighth PMOS transistors are connected to the power supply output terminal. The sources of the fourth, fifth, sixth, seventh, and eighth PMOS transistors output bias currents.

6. An LED control circuit, characterized in that, The control circuit includes: The error amplifier, reference voltage generator, ramp signal generation module, PWM generator, current limiting comparator, logic control module, and constant current generation module as described in any one of claims 1-5; The ramp signal generation module is used to output a first current and also to generate a ramp signal of a preset frequency. The first input terminal of the error amplifier is connected to the output terminal of the constant current generation module, and the second input terminal of the error amplifier is connected to the first output terminal of the reference voltage generator. The error amplifier is used to amplify the error between the output voltage of the constant current generation module and the reference voltage output by the reference voltage generator to obtain an error amplification signal. The first input terminal of the PWM generator is connected to the output terminal of the error amplifier, and the second input terminal of the PWM generator is connected to the first output terminal of the ramp signal generation module. The PWM generator is used to compare the error amplifier signal with the ramp signal and generate a PWM signal based on the comparison result. The first input terminal of the current limiting comparator is connected to the second output terminal of the reference voltage generator, and the second input terminal of the current limiting comparator is connected to the first output terminal of the ramp signal generation module, which is used to compare the ramp signal with the current limiting reference voltage to obtain the current limiting comparison result. The input terminal of the logic control module is connected to the output terminal of the current limiting comparator and the output terminal of the PWM generator, respectively, and is used to generate a logic control signal based on the current limiting comparison result output by the current limiting comparator and the PWM signal. The first input terminal of the constant current generation module is connected to the second output terminal of the ramp signal generation module, the second input terminal of the constant current generation module is connected to the output terminal of the logic control module, and the output terminal of the constant current generation module is connected to the LED, which is used to generate a constant second current from the first current according to the logic control signal.

7. The LED control circuit as described in claim 6, characterized in that, The ramp signal generation module includes: Oscillator, slope compensator, superposition unit, current sampling generator, and third resistor; The oscillator is used to generate a frequency signal; The first input terminal of the current sampling generator is connected to the power output terminal, and the second input terminal of the current sampling generator is connected to the first input terminal of the current sampling generator through the third resistor, for sampling the voltage across the third resistor to obtain the sampling current; The input terminal of the ramp compensator is connected to the output terminal of the oscillator to generate a ramp compensation signal. The input terminal of the superimposed unit is connected to the output terminal of the ramp compensator and the output terminal of the current sampling generator, respectively, for superimposing the sampled current and the ramp compensation signal to generate the ramp signal of the preset frequency. Wherein, the output terminal of the superimposed unit is the first output terminal of the ramp signal generation module, and the second input terminal of the current sampling generator is the second output terminal of the ramp signal generation module.

8. The LED control circuit as described in claim 6, characterized in that, The constant current generation module includes: The drive unit, power MOSFET, inductor, capacitor, diode, and fourth resistor; The input terminal of the driving unit is connected to the output terminal of the logic control module. The output terminal of the driving unit is connected to the gate of the power MOSFET. The drain of the MOSFET is connected to the second output terminal of the ramp signal generation module. The source of the power MOSFET is connected to the first terminal of the inductor and the cathode of the diode. The second terminal of the inductor is connected to the first terminal of the capacitor and the anode of the LED. The second terminal of the capacitor and the anode of the diode are grounded. The first terminal of the fourth resistor is connected to the cathode of the LED. The second terminal of the fourth resistor is grounded.

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