Multiple power domain disorder opening anti-fuse circuit

Abstract

The application is suitable for the field of integrated circuit technology, and provides a multi-power-domain disorder opening anti-fuse circuit, which comprises a logic module, a driving switch module and a fuse fusing and reading module.The driving switch module is electrically connected with the logic module and the fuse fusing and reading module.The logic module is electrically connected with a first power domain and a second power domain.The driving switch module is electrically connected with a third power domain.The fuse fusing and reading module is electrically connected with the first power domain, the second power domain and the third power domain.The logic module, the driving switch module and the fuse fusing and reading module are all used for grounding.In the process of opening the first power domain, the second power domain and the third power domain in any order, the logic module is used for outputting a first logic signal to the driving switch module.The driving switch module is used for prohibiting sending a fusing signal to the fuse fusing and reading module according to the first logic signal.The application solves the problem that the fuse may be mistakenly fused when the opening sequence of the multi-power domain is random.

Description

Technical Field

[0001] This application belongs to the field of integrated circuit technology, and in particular relates to a multi-power domain disorder turn-on anti-fuse circuit. Background Technology

[0002] As integrated circuits become increasingly dense and feature sizes shrink, their design complexity increases, leading to higher costs for production redesigns. Fuse tuning technology provides a solution to address issues such as drift in chip manufacturing process parameters and changes in output drive. No redesign is required after production; only a single fuse programming operation during mid-testing is needed, saving on expensive mask redesign costs and reducing production cycle time associated with redesigns.

[0003] Currently, a fuse circuit is used to program the fuse in one go. However, this fuse circuit requires power from multiple power domains. When the power domains are turned on in a random order, the fuse may blow accidentally, making the fuse blowing uncontrollable. Summary of the Invention

[0004] This application provides a multi-power domain disordered start-up anti-fuse circuit, which can solve the problem of accidental fuse blowing when the start-up sequence of multiple power domains is random.

[0005] This application provides a multi-power-domain disordered activation anti-fuse circuit, including a logic module, a drive switch module, and a fuse blowing and reading module. The drive switch module is electrically connected to the logic module and the fuse blowing and reading module respectively. The logic module is used to be electrically connected to a first power domain and a second power domain, the drive switch module is used to be electrically connected to a third power domain, and the fuse blowing and reading module is used to be electrically connected to the first power domain, the second power domain, and the third power domain. The logic module, the drive switch module, and the fuse blowing and reading module are all grounded.

[0006] During the process of the first power domain, the second power domain, and the third power domain being turned on in any order, the logic module is used to output a first logic signal to the drive switch module; the drive switch module is used to prevent the sending of a fuse breaking signal to the fuse breaking and reading module according to the first logic signal, wherein the fuse breaking signal is used to instruct the fuse breaking and reading module to break the fuse.

[0007] In one possible implementation, the logic module includes a logic unit and a pull-down unit; the pull-down unit is electrically connected to the logic unit and the drive switch module respectively; the logic unit is used to be electrically connected to the first power domain and the second power domain; and both the logic unit and the pull-down unit are grounded.

[0008] During the process of the first power domain, the second power domain, and the third power domain being turned on in any order, the logic unit is used to output the first logic signal under the action of the pull-down unit.

[0009] In one possible implementation, the logic unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a seventeenth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a fifth resistor; the sources and substrates of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor are all electrically connected to the first power domain; the gate of the first PMOS transistor is electrically connected to the gate of the fourth PMOS transistor, the drain of the fifth PMOS transistor, the drain of the sixth NMOS transistor, and the gate of the second NMOS transistor; the drain of the first PMOS transistor is electrically connected to the drain of the second PMOS transistor, the gate of the third PMOS transistor, and the drain of the first NMOS transistor; the gate of the second PMOS transistor is grounded; and the third PMOS transistor... The drain of the first NMOS transistor is electrically connected to the drain of the third NMOS transistor, the drain of the fourth PMOS transistor, the gate of the fifth PMOS transistor, the gate of the sixth NMOS transistor, the pull-down unit, and the drive switch module, respectively. The source and substrate of the sixth NMOS transistor are both grounded. The gate of the first NMOS transistor is electrically connected to the first terminal of the fifth resistor, the gate of the seventeenth PMOS transistor, and the gate of the fifth NMOS transistor, respectively. The source of the first NMOS transistor is electrically connected to the drain of the second NMOS transistor. The gate of the third NMOS transistor is electrically connected to the drain of the seventeenth PMOS transistor and the drain of the fifth NMOS transistor, respectively. The source and substrate of the seventeenth PMOS transistor are both electrically connected to the second power domain. The second terminal of the fifth resistor, the substrate of the first NMOS transistor, the source and substrate of the second NMOS transistor, the source and substrate of the third NMOS transistor, and the source and substrate of the fifth NMOS transistor are all grounded.

[0010] In one possible implementation, the pull-down unit includes a first resistor; a first end of the first resistor is electrically connected to both the logic unit and the drive switch module, and a second end of the first resistor is grounded.

[0011] In one possible implementation, the drive switch module includes a first inverter, a second inverter, a third inverter, and a first switch unit; the second inverter is electrically connected to the first inverter and the third inverter respectively; the first inverter is electrically connected to the logic module; the third inverter is electrically connected to the first switch unit; the first switch unit is electrically connected to the fuse blowing and reading module; the first inverter, the second inverter, the third inverter, and the first switch unit are all used to be electrically connected to the third power domain; and the first inverter, the second inverter, and the third inverter are all used to be grounded.

[0012] During the process of the first power domain, the second power domain, and the third power domain being turned on in any order, the first inverter, the second inverter, and the third inverter sequentially invert the first logic signal output by the logic module to obtain the second logic signal; the first switching unit is used to prevent the sending of the fuse blowing and reading signal to the fuse blowing and reading module according to the second logic signal.

[0013] In one possible implementation, the first switching unit includes a ninth PMOS transistor; the source and substrate of the ninth PMOS transistor are both electrically connected to the third power domain, the gate of the ninth PMOS transistor is electrically connected to the third inverter, and the drain of the ninth PMOS transistor is electrically connected to the fuse blowout and readout module.

[0014] In one possible implementation, the fuse blowing and reading module includes a first filtering unit, a second filtering unit, a pull-up unit, a second switching unit, a third switching unit, a fuse blowing and reading unit, and a signal conversion unit. The second switching unit is electrically connected to the pull-up unit, the third switching unit, and the first filtering unit, respectively. The second filtering unit is electrically connected to the pull-up unit. The fuse blowing and reading unit is electrically connected to the drive switching module, the third switching unit, and the signal conversion unit, respectively. The first filtering unit is used to be electrically connected to the third power domain. The second filtering unit and the fuse blowing and reading unit are both used to be electrically connected to the first power domain. The signal conversion unit is used to be electrically connected to the second power domain. The first filtering unit, the second filtering unit, the second switching unit, the third switching unit, and the signal conversion unit are all grounded.

[0015] In one possible implementation, the pull-up unit includes a tenth PMOS transistor, an eleventh PMOS transistor, a tenth NMOS transistor, and an eleventh NMOS transistor; the source and substrate of the tenth PMOS transistor and the eleventh PMOS transistor are both electrically connected to the second filter unit; the gate of the tenth PMOS transistor is electrically connected to the gate of the eleventh PMOS transistor, the drain of the tenth NMOS transistor, the gate of the eleventh NMOS transistor, and the drain of the eleventh NMOS transistor, respectively; the drain of the tenth PMOS transistor is electrically connected to the gate of the tenth NMOS transistor; the source and substrate of the tenth NMOS transistor and the eleventh NMOS transistor are both grounded; and the drain of the eleventh PMOS transistor is electrically connected to the second switching unit and the third switching unit, respectively.

[0016] In one possible implementation, the fuse-breaking and readout unit includes a twelfth PMOS transistor, a thirteenth PMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fourth resistor, a first fuse, and a second fuse. The sources and substrates of the twelfth and thirteenth PMOS transistors are both electrically connected to the first power domain. The gates of the twelfth and thirteenth PMOS transistors are both used to receive a bias voltage. The drain of the twelfth PMOS transistor is connected to the drain of the thirteenth NMOS transistor, the gate of the thirteenth NMOS transistor, and the gate of the fourteenth NMOS transistor, respectively. The gate is electrically connected, the drain of the thirteenth PMOS transistor is electrically connected to the first end of the fourth resistor and the drain of the fourteenth NMOS transistor, the second end of the fourth resistor is electrically connected to the signal conversion unit, the substrates of the thirteenth NMOS transistor and the fourteenth NMOS transistor are both grounded, the source of the thirteenth NMOS transistor is electrically connected to the first end of the first fuse, the source of the fourteenth NMOS transistor is electrically connected to the drive switch module and the first end of the second fuse, and the second ends of the first fuse and the second fuse are both electrically connected to the third switch unit.

[0017] In one possible implementation, the signal conversion unit includes a fourth inverter, a fifth inverter, and a sixth inverter; the fifth inverter is electrically connected to the fourth inverter and the sixth inverter respectively; the fourth inverter is electrically connected to the fuse blowing and reading unit; and the fourth inverter, the fifth inverter, and the sixth inverter are all electrically connected between the second power domain and ground.

[0018] The beneficial effects of the embodiments in this application compared with the prior art are:

[0019] This application provides a multi-power-domain disordered activation anti-fuse circuit, including a logic module, a drive switch module, and a fuse blowing and reading module. The drive switch module is electrically connected to both the logic module and the fuse blowing and reading module. The logic module is used to connect to a first power domain and a second power domain. The drive switch module is used to connect to a third power domain. The fuse blowing and reading module is used to connect to the first, second, and third power domains. All three modules—logic module, drive switch module, and fuse blowing and reading module—are grounded.

[0020] During the process of the first power domain, the second power domain, and the third power domain being turned on in any order, the logic module is used to output a first logic signal to the drive switch module. The drive switch module is used to disable the sending of a fuse-breaking signal to the fuse-breaking and reading module according to the first logic signal. The fuse-breaking signal is used to instruct the fuse-breaking and reading module to blow the fuse.

[0021] As can be seen from the above, during the process of the first power domain, the second power domain, and the third power domain being turned on in any order, the logic module always outputs a first logic signal to the drive switch module. The drive switch module, based on the first logic signal, prohibits sending a fuse-breaking signal to the fuse-breaking and read-out module, thus disabling write operations to the fuse. Therefore, the fuse-breaking and read-out module will not blow the fuse. Thus, the multi-power domain disorderly turn-on anti-fuse fuse circuit provided in this application embodiment solves the problem of accidental fuse blowing when the turn-on order of multiple power domains is random, making fuse blowing controllable. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of a multi-power domain disordered start-up anti-fuse circuit provided in an embodiment of this application;

[0024] Figure 2 This is a schematic diagram of a multi-power domain disordered start-up anti-fuse circuit provided in another embodiment of this application;

[0025] Figure 3 This is a schematic diagram of a multi-power domain disordered start-up anti-fuse circuit provided in another embodiment of this application;

[0026] Figure 4 This is a schematic diagram of a multi-power domain disordered start-up anti-fuse circuit provided in another embodiment of this application;

[0027] Figure 5 This is a schematic diagram of a multi-power domain disordered start-up anti-fuse circuit provided in another embodiment of this application;

[0028] Figure 6 This is a circuit connection diagram of a multi-power domain disordered start-up anti-fuse circuit provided in an embodiment of this application.

[0029] In the diagram: 10, Logic Module; 101, Logic Unit; 102, Pull-down Unit; 20, Driver Switch Module; 201, First Inverter; 202, Second Inverter; 203, Third Inverter; 204, First Switch Unit; 30, Fuse Blowing and Reading Module; 301, First Filter Unit; 302, Second Filter Unit; 303, Second Switch Unit; 304, Pull-up Unit; 305, Third Switch Unit; 306, Fuse Blowing and Reading Unit; 307, Signal Conversion Unit; 3071, Fourth Inverter; 3072, Fifth Inverter; 3073, Sixth Inverter. Detailed Implementation

[0030] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0031] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0032] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0033] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [the described condition or event] is detected," or "in response to detection of [the described condition or event]."

[0034] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0035] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0036] Existing fuse circuits are used to perform a single programming (i.e., write) operation on the fuse. When using fuse circuits, multiple power supply domains are required for power supply. When the opening sequence of multiple power supply domains is random, the fuse may be accidentally blown (i.e., the write operation on the fuse is accidentally enabled), which makes the fuse blowing (i.e., the write operation on the fuse) uncontrollable.

[0037] To address the aforementioned problems, embodiments of this application provide a multi-power-domain disorder-activated anti-fuse circuit, such as... Figure 1 As shown, the multi-power-domain disordered activation anti-fuse circuit includes a logic module 10, a drive switch module 20, and a fuse blowing and reading module 30. The drive switch module 20 is electrically connected to both the logic module 10 and the fuse blowing and reading module 30. The logic module 10 is used to electrically connect to the first and second power domains. The drive switch module 20 is used to electrically connect to the third power domain. The fuse blowing and reading module 30 is used to electrically connect to the first, second, and third power domains. All three modules—logic module 10, drive switch module 20, and fuse blowing and reading module 30—are grounded.

[0038] Specifically, when using a multi-power-domain unordered opening anti-fuse circuit, power needs to be supplied to the circuit. During the process of opening the first, second, and third power domains in any order (i.e., the opening order of the first, second, and third power domains is no longer considered), logic module 10 outputs a first logic signal to drive switch module 20. This first logic signal is a low-level signal. Drive switch module 20, based on the first logic signal, prohibits sending a fuse-breaking signal to fuse-breaking and reading module 30, i.e., disables write operations to the fuse, and fuse-breaking and reading module 30 will not blow the fuse. The fuse-breaking signal is used to instruct fuse-breaking and reading module 30 to blow the fuse.

[0039] As can be seen from the above, during the process of the first power domain, the second power domain, and the third power domain being turned on in any order, the logic module 10 always outputs a first logic signal to the drive switch module 20. The drive switch module 20, based on the first logic signal, prohibits sending a fuse-breaking signal to the fuse-breaking and read module 30, thus disabling write operations to the fuse. Therefore, the fuse-breaking and read module 30 will not blow the fuse. In other words, during the process of the first power domain, the second power domain, and the third power domain being turned on in any order, the multi-power domain disorderly turn-on anti-fuse fuse circuit always disables write operations to the fuse. In summary, the multi-power domain disorderly turn-on anti-fuse fuse circuit provided in this application embodiment solves the problem of accidental fuse blowing when the multi-power domain turn-on order is random.

[0040] After the multi-power domain disorder-activated anti-fuse circuit is powered on, it performs a write operation or a read operation on the fuse based on the received enable signal, making the fuse blowing controllable. Specifically, logic module 10 receives the enable signal. When the enable signal is low, logic module 10 outputs a low-level signal to drive switch module 20. Drive switch module 20, based on the low-level signal, prevents the sending of a fuse blowing signal to fuse blowing and reading module 30, thus disabling write operations on the fuse, and fuse blowing and reading module 30 will not blow the fuse. At this time, the multi-power domain disorder-activated anti-fuse circuit initiates a read operation on the fuse. When the fuse is not blown, fuse blowing and reading module 30 outputs a high-level signal, thus achieving the storage of the information "1". When the fuse is blown, the fuse blowing and reading module 30 outputs a low-level signal. That is, when the fuse is blown, the multi-power domain disorderly opening anti-fuse circuit outputs a low-level signal, thereby realizing the storage of "0" information.

[0041] When the enable signal is high, logic module 10 outputs a high-level signal to drive switch module 20. Drive switch module 20 turns on according to the high-level signal output by logic module 10, that is, it initiates the write operation to the fuse, and outputs a fuse-breaking signal to fuse-breaking and read module 30. Fuse-breaking and read module 30 blows the fuse according to the fuse-breaking signal output by drive switch module 20, realizing one write operation of the fuse, that is, one programming.

[0042] It should be noted that the voltage of the first power supply domain is 3.3V. The voltage of the second power supply domain is 1.2V. The voltage of the third power supply domain is 2.5V.

[0043] like Figure 2As shown, logic module 10 includes logic unit 101 and pull-down unit 102. Pull-down unit 102 is electrically connected to logic unit 101 and drive switch module 20, respectively. Logic unit 101 is used for electrical connection to a first power domain and a second power domain. Both logic unit 101 and pull-down unit 102 are grounded.

[0044] Specifically, when using the multi-power domain disordered opening anti-fuse circuit, it is necessary to supply power to the multi-power domain disordered opening anti-fuse circuit. During the process of the first power domain, the second power domain and the third power domain being opened in any order, the logic unit 101 is used to output the first logic signal under the action of the pull-down unit 102.

[0045] After the multi-power domain disorder-activated anti-fuse circuit is powered on, logic unit 101 performs corresponding operations based on the received enable signal. When the enable signal is low, logic unit 101 outputs a low-level signal to drive switch module 20. Drive switch module 20, based on the low-level signal output by logic unit 101, prohibits sending a fuse-breaking signal to fuse-breaking and read module 30, i.e., disables the write operation to the fuse, and fuse-breaking and read module 30 will not blow the fuse. At this time, the multi-power domain disorder-activated anti-fuse circuit enables the read operation of the fuse. When the enable signal is high, logic unit 101 outputs a high-level signal to drive switch module 20. Drive switch module 20, based on the high-level signal output by logic unit 101, conducts, i.e., enables the write operation to the fuse, and outputs a fuse-breaking signal to fuse-breaking and read module 30. The fuse blowing and reading module 30 blows the fuse according to the fuse blowing signal output by the drive switch module 20, thereby realizing a one-time write operation of the fuse.

[0046] For example, such as Figure 6As shown, logic unit 101 includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a seventeenth PMOS transistor P17, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fifth NMOS transistor N5, a sixth NMOS transistor N6, and a fifth resistor R5. The sources and substrates of the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3, the fourth PMOS transistor P4, and the fifth PMOS transistor P5 are all used for electrical connection to the first power supply domain to receive a 3.3V voltage. The gate of the first PMOS transistor P1 is electrically connected to the gate of the fourth PMOS transistor P4, the drain of the fifth PMOS transistor P5, the drain of the sixth NMOS transistor N6, and the gate of the second NMOS transistor N2. These gates are connected to fback. The drain of the first PMOS transistor P1 is electrically connected to the drain of the second PMOS transistor P2, the gate of the third PMOS transistor P3, and the drain of the first NMOS transistor N1. These gates are connected to net1. The gate of the second PMOS transistor P2 is used to ground VSS. The drain of the third PMOS transistor P3 is electrically connected to the drain of the third NMOS transistor N3, the drain of the fourth PMOS transistor P4, the gate of the fifth PMOS transistor P5, the gate of the sixth NMOS transistor N6, the pull-down unit 102, and the drive switch module 20, respectively. The drains of the third PMOS transistor P3, the third NMOS transistor N3, the fourth PMOS transistor P4, the gate of the fifth PMOS transistor P5, the gate of the sixth NMOS transistor N6, the pull-down unit 102, and the drive switch module 20 are connected to out1. The source and substrate of the sixth NMOS transistor N6 are both grounded to VSS. The gate of the first NMOS transistor N1 is electrically connected to the first terminal of the fifth resistor R5, the gate of the seventeenth PMOS transistor P17, and the gate of the fifth NMOS transistor N5, respectively. The source of the first NMOS transistor N1 is electrically connected to the drain of the second NMOS transistor N2, and the source of the first NMOS transistor N1 and the drain of the second NMOS transistor N2 are connected to net2. The gate of the third NMOS transistor N3 is electrically connected to the drain of the seventeenth PMOS transistor P17 and the drain of the fifth NMOS transistor N5, respectively. The gate of the third NMOS transistor N3, the drain of the seventeenth PMOS transistor P17, and the drain of the fifth NMOS transistor N5 are connected to net3. The source and substrate of the seventeenth PMOS transistor P17 are both used to be electrically connected to the second power supply domain to receive a 1.2V voltage.The second terminal of the fifth resistor R5, the substrate of the first NMOS transistor N1, the source and substrate of the second NMOS transistor N2, the source and substrate of the third NMOS transistor N3, and the source and substrate of the fifth NMOS transistor N5 are all used to ground VSS. The first terminal of the fifth resistor R5 is used to receive the enable signal E. It should be noted that the gate oxide layers of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the sixth NMOS transistor are thick gate oxide layers, while the gate oxide layers of the seventeenth PMOS transistor and the fifth NMOS transistor are thin gate oxide layers.

[0047] Specifically, when using a multi-power-domain out-of-order turn-on anti-fuse circuit, power needs to be supplied to the circuit. When the first power domain turns on first, followed by the second and third power domains, the potential on out1 is pulled low by the pull-down unit 102. Therefore, the fifth PMOS transistor P5 turns on and outputs a high-level signal to the gates of the fourth PMOS transistor P4, the first PMOS transistor P1, and the second NMOS transistor N2. Then, the fourth PMOS transistor P4 and the first PMOS transistor P1 turn off, and the second NMOS transistor N2 turns on. Since the second power domain is not turned on, the first NMOS transistor N1 is turned off by the pull-down action of the fifth resistor R5 before the enable signal arrives, thus eliminating the pull-down current in the branch containing the first NMOS transistor N1. The gate of the second PMOS transistor P2 is grounded to VSS, turning it on and enabling a weak pull-up. This allows it to output a high-level signal to the gate of the third PMOS transistor P3, turning it off. Thus, both the third and fourth PMOS transistors P3 and P4 are off, leaving out1 without pull-up capability. Therefore, whether the third NMOS transistor N3 is on or off will not affect the pull-down unit 102's ability to pull down the potential on out1 to a low level. In other words, regardless of whether the second power domain is on (when the second power domain is on, the pull-down effect of the fifth resistor R5 causes the input of the inverter composed of the seventeenth PMOS transistor P17 and the fifth NMOS transistor N5 to be a low-level signal and the output to be a high-level signal, thereby turning on the third NMOS transistor N3; when the second power domain is not on, the gate of the third NMOS transistor N3 is floating, resulting in pull-down leakage and providing pull-down functionality), the logic unit 101 will not output the first logic signal, which is a low-level signal. Therefore, in terms of the turn-on order of the first power domain and the second power domain, regardless of whether the second power domain is turned on first or last, there is no pull-up capability at out1. The potential on out1 will be pulled down to a low level signal under the action of the pull-down unit 102, that is, the logic unit 101 outputs the first logic signal.

[0048] When the third power domain is turned on first and the first power domain is turned on later, since the first power domain is not turned on, regardless of whether the second power domain is turned on, there is neither pull-up nor pull-down capability at out1. The potential on out1 will be pulled down to a low level signal under the action of the pull-down unit 102, that is, the logic unit 101 outputs the first logic signal.

[0049] Therefore, during the process of the first power domain, the second power domain, and the third power domain being turned on in any order, the logic unit 101 always outputs the first logic signal under the action of the pull-down unit 102. The drive switch module 20 prohibits sending the fuse breaking and reading module 30 to the fuse breaking and reading module 30 according to the first logic signal, that is, it closes the write operation to the fuse, and the fuse breaking and reading module 30 will not blow the fuse.

[0050] After the multi-power domain disordered start-up anti-fuse circuit is powered on, the first terminal of the fifth resistor R5, the gate of the first NMOS transistor N1, the gate of the seventeenth PMOS transistor P17, and the gate of the fifth NMOS transistor N5 all operate accordingly based on the received enable signal E. When the enable signal E is low, the inverter formed by the seventeenth PMOS transistor P17 and the fifth NMOS transistor N5 outputs a high-level signal of 1.2V, turning on the third NMOS transistor N3 and simultaneously turning off the first NMOS transistor N1, thus eliminating the pull-down current in the branch containing the first NMOS transistor N1. Since the gate of the second PMOS transistor P2 is grounded to VSS, the second PMOS transistor P2 is turned on, and under the weak pull-up effect of the second PMOS transistor P2, the third PMOS transistor P3 is turned off. Because the third NMOS transistor N3 is larger, its pull-down capability is greater than that of the fourth PMOS transistor P4. Therefore, regardless of whether the fourth PMOS transistor P4 is on or off, the conduction of the third NMOS transistor N3 will force the OUT1 node to a low-level signal. The inverter composed of the fifth PMOS transistor P5 and the sixth NMOS transistor N6 detects a low-level signal on OUT1 and outputs a high-level signal, causing the fourth PMOS transistor P4 to turn off and the second NMOS transistor N2 to turn on. Since both the third PMOS transistor P3 and the fourth PMOS transistor P4 are off, the conduction of the third NMOS transistor N3 maintains a stable low-level signal on OUT1. The third PMOS transistor P3, the fourth PMOS transistor P4, the fifth PMOS transistor P5, the third NMOS transistor N3, and the sixth NMOS transistor N6 form a latch structure, keeping the potential on OUT1 at a stable low level. The drive switch module 20, based on the low-level signal output by the logic unit 101, prohibits the sending of a fuse-breaking signal to the fuse-breaking and read module 30, thus disabling write operations to the fuse. At this time, the multi-power domain disorder-activated anti-fuse circuit enables read operations on the fuse.

[0051] When the enable signal E is high, the inverter composed of the seventeenth PMOS transistor P17 and the fifth NMOS transistor N5 outputs a low-level signal, turning off the third NMOS transistor N3 and simultaneously turning on the first NMOS transistor N1, thus providing a pull-down current in the branch containing the first NMOS transistor N1. Under the pull-down effect of the pull-down unit 102, the inverter composed of the fifth PMOS transistor P5 and the sixth NMOS transistor N6 detects that the OUT1 node is low and outputs a high-level signal, turning off the fourth PMOS transistor P4 and the first PMOS transistor P17. When the first NMOS transistor (N1) is turned off, the second NMOS transistor (N2) turns on. This conduction of the first NMOS transistor (N1) and the second NMOS transistor (N2) provides pull-down current to their respective branches. Although the second PMOS transistor (P2) still provides a weak pull-up current, its pull-up capability is much smaller than the pull-down capability of the first NMOS transistor (N1) and the second NMOS transistor (N2). This causes the third PMOS transistor (P3) to turn on. The pull-up capability of the third PMOS transistor (P3) is greater than the pull-down capability of the pull-down unit 102. Therefore, the potential on out1 is converted from a low-level signal to a high-level signal. The inverter composed of the fifth PMOS transistor (P5) and the sixth NMOS transistor (P6) detects a high-level signal at the OUT1 node and outputs a low-level signal, thus turning on the first PMOS transistor (P1) and the fourth PMOS transistor (P4), and turning off the second NMOS transistor (N2). The turn-off of the second NMOS transistor (N2) means that its branch has no pull-down capability. Under the pull-up action of the first PMOS transistor (P1) and the second PMOS transistor (P2), the third PMOS transistor (P3) turns off. The pull-up capability of the fourth PMOS transistor P4 is greater than the pull-down capability of the pull-down unit 102, so the potential on out1 is a high-level signal. The latch structure composed of the fourth PMOS transistor P4, the third NMOS transistor N3, the fifth PMOS transistor P5, and the sixth PMOS transistor P6 keeps the potential on out1 a stable high-level signal. The drive switch module 20 turns on according to the high-level signal output by the logic unit 101, that is, it initiates the write operation to the fuse, and outputs a fuse-breaking signal to the fuse-breaking and read module 30. The fuse-breaking and read module 30 blows the fuse according to the fuse-breaking signal output by the drive switch module 20, that is, it realizes the fuse write operation.

[0052] It should be noted that logic unit 101 can also be replaced by other units that implement its function, and is not limited to this.

[0053] For example, such as Figure 6 As shown, the pull-down unit 102 includes a first resistor R1. The first end of the first resistor R1 is electrically connected to both the logic unit 101 and the drive switch module 20. The first end of the first resistor R1, the logic unit 101, and the drive switch module 20 are connected to out1. The second end of the first resistor R1 is used to ground VSS. According to... Figure 6As shown, the first end of the first resistor R1 is electrically connected to the drain of the third PMOS transistor P3, the drain of the fourth PMOS transistor P4, the drain of the third NMOS transistor N3, the gate of the fifth PMOS transistor P5, the gate of the sixth PMOS transistor P6, and the drive switch module 20, respectively. The first end of the first resistor R1, the drain of the third PMOS transistor P3, the drain of the fourth PMOS transistor P4, the drain of the third NMOS transistor N3, the gate of the fifth PMOS transistor P5, the gate of the sixth PMOS transistor P6, and the drive switch module 20 are connected to out1.

[0054] Specifically, during the process of turning on the first power domain, the second power domain, and the third power domain in any order, the OUT1 node is pulled down to a low level signal under the action of the first resistor R1, so that the logic unit 101 always outputs the first logic signal.

[0055] It should be noted that the drop-down unit 102 can also be replaced by other units that perform its function, and is not limited to this.

[0056] like Figure 3 As shown, the drive switch module 20 includes a first inverter 201, a second inverter 202, a third inverter 203, and a first switch unit 204. The second inverter 202 is electrically connected to both the first inverter 201 and the third inverter 203. The first inverter 201 is electrically connected to the logic module 10. The third inverter 203 is electrically connected to the first switch unit 204. The first switch unit 204 is electrically connected to the fuse blowing and reading module 30. The first inverter 201, second inverter 202, third inverter 203, and first switch unit 204 are all used for electrical connection to a third power domain. The first inverter 201, second inverter 202, and third inverter 203 are all used for grounding. Figure 3 It can be seen that the first inverter 201 is electrically connected to the logic unit 101 and the pull-down unit 102 respectively.

[0057] Specifically, during the process of turning on the first power domain, the second power domain, and the third power domain in any order, the first inverter 201, the second inverter 202, and the third inverter 203 sequentially invert the first logic signal output by the logic module 10 to obtain the second logic signal, which is a high-level signal. The first switching unit 204 is used to prevent the sending of a fuse-breaking signal to the fuse-breaking and reading module 30 according to the second logic signal, that is, to close the write operation to the fuse, and the fuse-breaking and reading module 30 will not blow the fuse.

[0058] After the multi-power domain disorder-activated anti-fuse circuit is powered on, the logic module 10 performs corresponding operations based on the received enable signal. When the enable signal is low, the logic module 10 outputs a low-level signal. The first inverter 201, the second inverter 202, and the third inverter 203 sequentially invert the low-level signal output by the logic module 10 to obtain a high-level signal. The first switching unit 204, based on the high-level signal, prohibits the sending of a fuse-breaking signal to the fuse-breaking and reading module 30, thus disabling the write operation to the fuse. At this time, the multi-power domain disorder-activated anti-fuse circuit enables the reading operation of the fuse.

[0059] When the enable signal is high, logic module 10 outputs a high-level signal. First inverter 201, second inverter 202, and third inverter 203 sequentially invert the high-level signal output by logic module 10 to obtain a low-level signal. First switching unit 204 conducts based on the low-level signal, thus initiating a write operation to the fuse and outputting a fuse-breaking signal to fuse-breaking and read module 30. Fuse-breaking and read module 30 blows the fuse based on the fuse-breaking signal output by first switching unit 204, thus completing the write operation to the fuse.

[0060] For example, such as Figure 6 As shown, the first inverter 201 includes a sixth PMOS transistor P6 and a seventh NMOS transistor N7. The source and substrate of the sixth PMOS transistor P6 are both electrically connected to the third power supply domain to receive a 2.5V voltage. The gates of the sixth PMOS transistor P6 and the seventh NMOS transistor N7 are respectively electrically connected to the first terminal of the first resistor R1, the gate of the fifth PMOS transistor P5, the gate of the sixth NMOS transistor N6, the drain of the third PMOS transistor P3, the drain of the fourth PMOS transistor P4, and the drain of the third NMOS transistor N3. The gates of the sixth PMOS transistor P6, the seventh NMOS transistor N7, the first terminal of the first resistor R1, the gate of the fifth PMOS transistor P5, the gate of the sixth NMOS transistor N6, the drain of the third PMOS transistor P3, the drain of the fourth PMOS transistor P4, and the third NMOS transistor N3 are connected to out1. The drain of the sixth PMOS transistor P6 is electrically connected to the drain of the second inverter 202 and the drain of the seventh NMOS transistor N7, respectively. The drains of the sixth PMOS transistor P6, the second inverter 202, and the seventh NMOS transistor N7 are connected to out2. The source and substrate of the seventh NMOS transistor N7 are both used to ground VSS.

[0061] It should be noted that the first inverter 201 can also be replaced by other units that perform its function, and is not limited to this.

[0062] For example, such as Figure 6As shown, the second inverter 202 includes a seventh PMOS transistor P7 and an eighth NMOS transistor N8. The gate of the seventh PMOS transistor P7 is electrically connected to the gate of the eighth NMOS transistor N8, the drain of the sixth PMOS transistor P6, and the drain of the seventh NMOS transistor N7, respectively. These three transistors are connected to out2. The drain of the seventh PMOS transistor P7 is electrically connected to the drain of the eighth NMOS transistor N8 and the third inverter 203, respectively. These three transistors are connected to out3. The source and substrate of the seventh PMOS transistor P7 are both used for electrical connection to the third power domain to receive a 2.5V voltage. The source and substrate of the eighth NMOS transistor N8 are both used to ground VSS.

[0063] It should be noted that the second inverter 202 can also be replaced by other units that perform its function, and is not limited to this.

[0064] For example, such as Figure 6 As shown, the third inverter 203 includes an eighth PMOS transistor P8 and a ninth NMOS transistor N9. The gate of the eighth PMOS transistor P8 is electrically connected to the gate of the ninth NMOS transistor N9, the drain of the seventh PMOS transistor P7, and the drain of the eighth NMOS transistor N8, respectively. The gates of the eighth PMOS transistor P8, the ninth NMOS transistor N9, the drains of the seventh PMOS transistor P7, and the drain of the eighth NMOS transistor N8 are connected to out3. The drain of the eighth PMOS transistor P8 is electrically connected to the first switching unit 204 and the drain of the ninth NMOS transistor N9, respectively. The drains of the eighth PMOS transistor P8, the first switching unit 204, and the ninth NMOS transistor N9 are connected to out4. The source and substrate of the eighth PMOS transistor P8 are both used to be electrically connected to the third power domain to receive a 2.5V voltage. The source and substrate of the ninth NMOS transistor N9 are both used to ground VSS.

[0065] It should be noted that the third inverter 203 can also be replaced by other units that perform its function, and is not limited to this.

[0066] For example, such as Figure 6 As shown, the first switching unit 204 includes a ninth PMOS transistor P9. The source and substrate of the ninth PMOS transistor P9 are both electrically connected to the third power domain to receive a 2.5V voltage. The gate of the ninth PMOS transistor P9 is electrically connected to the third inverter 203, and the gate of the ninth PMOS transistor P9 and the third inverter 203 are connected to out4. The drain of the ninth PMOS transistor P9, after a fuse is fused, is electrically connected to the read module 30, and the drain of the ninth PMOS transistor P9, after a fuse is fused, is connected to drive on the read module 30. According to... Figure 6As shown, the gate of the ninth PMOS transistor P9 is electrically connected to the drain of the eighth PMOS transistor P8 and the drain of the ninth NMOS transistor N9 in the third inverter 203. The gate of the ninth PMOS transistor P9, the drain of the eighth PMOS transistor P8, and the drain of the ninth NMOS transistor N9 are connected to out4.

[0067] Specifically, during the process of turning on the first power domain, the second power domain, and the third power domain in any order, the third inverter 203 outputs a second logic signal, which is a high-level signal. The ninth PMOS transistor P9 is turned off according to the second logic signal, preventing the sending of a fuse-breaking signal to the fuse-breaking and read module 30, that is, disabling the write operation to the fuse, and the fuse-breaking and read module 30 will not blow the fuse.

[0068] After the multi-power domain disorder-activated anti-fuse circuit is powered on, logic module 10 receives an enable signal. When the enable signal is low, the third inverter 203 outputs a high-level signal. The ninth PMOS transistor P9 is turned off according to the high-level signal output by the third inverter 203, preventing the transmission of a fuse-breaking signal to the fuse-breaking and read module 30, thus disabling write operations to the fuse. At this time, the multi-power domain disorder-activated anti-fuse circuit enables read operations on the fuse.

[0069] When the enable signal is high, the third inverter 203 outputs a low-level signal. The ninth PMOS transistor P9 turns on according to the low-level signal output by the third inverter 203, thus initiating a write operation to the fuse and outputting a fuse-breaking signal to the fuse-breaking and read module 30. The fuse-breaking and read module 30 then blows the fuse according to the fuse-breaking signal output by the ninth PMOS transistor P9, thus realizing the write operation to the fuse. It should be noted that the ninth PMOS transistor P9 is large; when the fuse is a polysilicon fuse, a fuse-breaking current of approximately 40mA is required during the write operation. Due to the relatively large gate capacitance load of the ninth PMOS transistor P9, this application employs a three-stage inverter to enable the ninth PMOS transistor P9 to turn on and off quickly.

[0070] It should be noted that the first switch unit 204 can also be replaced by other units that perform its function, and is not limited to this.

[0071] like Figure 4As shown, the fuse blowing and reading module 30 includes a first filtering unit 301, a second filtering unit 302, a pull-up unit 304, a second switching unit 303, a third switching unit 305, a fuse blowing and reading unit 306, and a signal conversion unit 307. The second switching unit 303 is electrically connected to the pull-up unit 304, the third switching unit 305, and the first filtering unit 301. The second filtering unit 302 is electrically connected to the pull-up unit 304. The fuse blowing and reading unit 306 is electrically connected to the drive switching module 20, the third switching unit 305, and the signal conversion unit 307. The first filtering unit 301 is used for electrical connection to the third power domain, and the second filtering unit 302 and the fuse blowing and reading unit 306 are both used for electrical connection to the first power domain. The signal conversion unit 307 is used for electrical connection to the second power domain. The first filtering unit 301, the second filtering unit 302, the second switching unit 303, the third switching unit 305, and the signal conversion unit 307 are all grounded. Figure 4 It can be seen that the fuse blowing and reading unit 306 is electrically connected to the first switching unit 204, the third switching unit 305 and the signal conversion unit 307, respectively.

[0072] Specifically, during the process of turning on the first power domain, the second power domain, and the third power domain in any order, the first switching unit 204, according to the first logic signal, prohibits sending a fuse-breaking signal to the fuse-breaking and reading module 30, that is, it closes the write operation to the fuse. The fuse-breaking and reading unit 306 does not receive a fuse-breaking signal, therefore the fuse will not blow. Specifically, during the turn-on process of the first power domain, the voltage rises from low to high. When a suitable voltage is reached, the fuse-breaking and reading unit 306 begins the reading operation, but at this time, the read data is not stored.

[0073] When the third power domain is enabled, the first filter unit 301 filters the 2.5V voltage and outputs a low-level signal to the second switch unit 303. The second switch unit 303 is turned off according to the low-level signal output by the first filter unit 301, meaning that the second switch unit 303 is always in the off state when the third power domain is enabled. When the first power domain is enabled, the second filter unit 302 filters the 3.3V voltage, providing a low-noise voltage for the pull-up unit 304. The pull-up unit 304 outputs a high-level signal to the third switch unit 305 according to the voltage provided by the second filter unit 302. The third switch unit 305 is turned on according to the high-level signal output by the pull-up unit 304, meaning that the third switch unit 305 is always in the on state when the first power domain is enabled, thus providing path current for fuse read and write operations.

[0074] After the multi-power domain disorder-activated anti-fuse circuit is powered on, it performs a write operation or a read operation on the fuse based on the received enable signal. When the enable signal is low, the first switching unit 204 disables the sending of a fuse-breaking signal to the fuse-breaking and reading module 30 according to the first logic signal, thus closing the write operation on the fuse. At this time, the multi-power domain disorder-activated anti-fuse circuit enables the read operation on the fuse. When the fuse is not blown, the fuse-breaking and reading unit 306 outputs a low-level signal to the signal conversion unit 307. The signal conversion unit 307 converts the low-level signal output by the fuse-breaking and reading unit 306 into a high-level signal, realizing the storage of the information "1". When the fuse is blown, the fuse-breaking and reading unit 306 outputs a high-level signal to the signal conversion unit 307. The signal conversion unit 307 converts the high-level signal output by the fuse blowing and reading unit 306 into a low-level signal to realize the storage of "0" information.

[0075] When the enable signal is high, the first switching unit 204 is turned on and outputs a fuse-breaking signal to the fuse-breaking and reading unit 306. The fuse-breaking and reading unit 306 blows the fuse according to the fuse-breaking signal output by the first switching unit 204, thereby realizing the write operation on the fuse.

[0076] For example, such as Figure 6 As shown, the first filter unit 301 includes a first capacitor C1 and a second resistor R2. The first terminal of the first capacitor C1 is electrically connected to the third power supply domain to receive a 2.5V voltage. The second terminal of the first capacitor C1 is electrically connected to the second switching unit 303 and the first terminal of the second resistor R2. The second terminal of the first capacitor C1, the second switching unit 303, and the first terminal of the second resistor R2 are connected to rc1. The second terminal of the second resistor R2 is grounded to VSS. The first filter unit 301 provides a relatively clean low-level signal to the second switching unit 303.

[0077] It should be noted that the first filter unit 301 can also be replaced by other units that perform its function, and is not limited to this.

[0078] For example, such as Figure 6 As shown, the second filter unit 302 includes a second capacitor C2, a third capacitor C3, and a third resistor R3. The first terminals of both the second capacitor C2 and the third resistor R3 are electrically connected to the first power supply domain to receive a 3.3V voltage. The second terminal of the third resistor R3 is electrically connected to both the first terminal of the third capacitor C3 and the pull-up unit 304. The second terminal of the third resistor R3, the first terminal of the third capacitor C3, and the pull-up unit 304 are connected to rc2. The second terminals of both the second capacitor C2 and the third capacitor C3 are grounded to VSS.

[0079] It should be noted that the second filter unit 302 can also be replaced by other units that perform its function, and is not limited to this.

[0080] For example, such as Figure 6 As shown, the second switching unit 303 includes a twelfth NMOS transistor N12. The gate of the twelfth NMOS transistor N12 is electrically connected to the second terminal of the first capacitor C1 and the first terminal of the second resistor R2, respectively. The gate of the twelfth NMOS transistor N12, the second terminal of the first capacitor C1, and the first terminal of the second resistor R2 are connected to rc1. The drain of the twelfth NMOS transistor N12 is electrically connected to the pull-up unit 304 and the third switching unit 305, respectively. The drain of the twelfth NMOS transistor N12, the pull-up unit 304, and the third switching unit 305 are connected to tiehi1. The source and substrate of the twelfth NMOS transistor N12 are both used to ground VSS.

[0081] Specifically, when the third power domain is turned on, the first filter unit 301 outputs a low-level signal. The twelfth NMOS transistor N12 is turned off according to the low-level signal output by the first filter unit 301, that is, when the third power domain is turned on, the twelfth NMOS transistor N12 is always in the off state.

[0082] It should be noted that the second switch unit 303 can also be replaced by other units that perform its function, and is not limited to this.

[0083] For example, such as Figure 6 As shown, the third switching unit 305 includes a fifteenth NMOS transistor N15. The gate of the fifteenth NMOS transistor N15 is electrically connected to the pull-up unit 304 and the drain of the twelfth NMOS transistor N12, respectively. The gate of the fifteenth NMOS transistor N15, the pull-up unit 304, and the drain of the twelfth NMOS transistor N12 are connected to tiehi1. The drain of the fifteenth NMOS transistor N15 is electrically connected to the read unit 306 via a fuse. The drain of the fifteenth NMOS transistor N15 is connected to the sink via a fuse. The source and substrate of the fifteenth NMOS transistor N15 are both used to ground VSS.

[0084] Specifically, when the first power domain is turned on, the pull-up unit 304 outputs a high-level signal to the gate of the fifteenth NMOS transistor N15, turning on the fifteenth NMOS transistor N15. That is, when the first power domain is turned on, the fifteenth NMOS transistor N15 is always in the on state, thereby providing path current for the fuse read and write operations.

[0085] It should be noted that the third switch unit 305 can also be replaced by other units that perform its function, and is not limited to this.

[0086] For example, such as Figure 6As shown, the pull-up unit 304 includes a tenth PMOS transistor P10, an eleventh PMOS transistor P11, a tenth NMOS transistor N10, and an eleventh NMOS transistor N11. The sources and substrates of the tenth PMOS transistor P10 and the eleventh PMOS transistor P11 are electrically connected to the second filter unit 302. The sources and substrates of the tenth PMOS transistor P10 and the eleventh PMOS transistor P11, as well as the second filter unit 302, are connected to rc2. The gate of the tenth PMOS transistor P10 is electrically connected to the gate of the eleventh PMOS transistor P11, the drain of the tenth NMOS transistor N10, the gate of the eleventh NMOS transistor N11, and the drain of the eleventh NMOS transistor N11. The gates of the tenth PMOS transistor P10, the eleventh PMOS transistor P11, the tenth NMOS transistor N10, the eleventh NMOS transistor N11, and the drain of the eleventh NMOS transistor N11 are connected to tielow. The drain of the tenth PMOS transistor P10 is electrically connected to the gate of the tenth NMOS transistor N10, and the drain of the tenth PMOS transistor P10 is connected to the gate of the tenth NMOS transistor N10 on tiehi. The sources and substrates of the tenth NMOS transistor N10 and the eleventh NMOS transistor N11 are both used to ground VSS. The drain of the eleventh PMOS transistor P11 is electrically connected to the second switching unit 303 and the third switching unit 305, respectively. The drain of the eleventh PMOS transistor P11, the second switching unit 303, and the third switching unit 305 are connected on tiehi1. According to Figure 6 It can be seen that the sources and substrates of the tenth PMOS transistor P10 and the eleventh PMOS transistor P11 are electrically connected to the second terminal of the third resistor R3 and the first terminal of the third capacitor C3 in the second filter unit 302. The sources and substrates of the tenth PMOS transistor P10 and the eleventh PMOS transistor P11, the second terminal of the third resistor R3 and the first terminal of the third capacitor C3 are connected to rc2. The drain of the eleventh PMOS transistor P11 is electrically connected to the drain of the twelfth NMOS transistor N12 and the gate of the fifteenth NMOS transistor N15, respectively. The drain of the eleventh PMOS transistor P11, the drain of the twelfth NMOS transistor N12 and the gate of the fifteenth NMOS transistor N15 are connected to tiehi1.

[0087] Specifically, the pull-up unit composed of the tenth PMOS transistor P10, the eleventh PMOS transistor P11, the tenth NMOS transistor N10, and the eleventh NMOS transistor N11 is mainly used to provide a high-level signal to the gate of the fifteenth NMOS transistor N15, so that the fifteenth NMOS transistor N15 is always in the conducting state after the first power domain is turned on.

[0088] It should be noted that the pull-up unit 304 can also be replaced by other units that perform its function, and is not limited to this.

[0089] For example, such as Figure 6As shown, the fuse-breaking and readout unit 306 includes a twelfth PMOS transistor P12, a thirteenth PMOS transistor P13, a thirteenth NMOS transistor N13, a fourteenth NMOS transistor N14, a fourth resistor R4, a first fuse FUSE1, and a second fuse FUSE2. The sources and substrates of the twelfth PMOS transistor P12 and the thirteenth PMOS transistor P13 are both electrically connected to the first power domain to receive a 3.3V voltage. The gates of the twelfth PMOS transistor P12 and the thirteenth PMOS transistor P13 are both used to receive a bias voltage, and their gates are connected to READN. The drain of the twelfth PMOS transistor P12 is electrically connected to the drain and gate of the thirteenth NMOS transistor N13 and the gate of the fourteenth NMOS transistor N14, respectively. The drains of the twelfth PMOS transistor P12, the thirteenth NMOS transistor N13, the gates of the thirteenth NMOS transistor N13 and the gate of the fourteenth NMOS transistor N14 are connected to bia1. The drain of the thirteenth PMOS transistor P13 is electrically connected to the first terminal of the fourth resistor R4 and the drain of the fourteenth NMOS transistor N14, respectively. The drains of the thirteenth PMOS transistor P13, the first terminal of the fourth resistor R4, and the drain of the fourteenth NMOS transistor N14 are connected to bia2. The second terminal of the fourth resistor R4 is electrically connected to the signal conversion unit 307, and the second terminal of the fourth resistor R4 is connected to the signal conversion unit 307 on fs. The substrates of both the thirteenth NMOS transistor N13 and the fourteenth NMOS transistor N14 are used to ground VSS. The source of the thirteenth NMOS transistor N13 is electrically connected to the first terminal of the first fuse FUSE1, and the source of the thirteenth NMOS transistor N13 and the first terminal of the first fuse FUSE1 are connected to drive0. The source of the fourteenth NMOS transistor N14 is electrically connected to the first terminal of the drive switch module 20 and the second fuse FUSE2, respectively, and the source of the fourteenth NMOS transistor N14, the drive switch module 20, and the first terminal of the second fuse FUSE2 are connected to drive0. The second terminals of the first fuse FUSE1 and the second terminal of the second fuse FUSE2 are both electrically connected to the third switch unit 305, and the second terminals of the first fuse FUSE1, the second terminal of the second fuse FUSE2, and the third switch unit 305 are connected to the sink. Figure 6 As shown, the source of the fourteenth NMOS transistor N14 is electrically connected to the drain of the ninth PMOS transistor P9 and the first terminal of the second fuse FUSE2. The source of the fourteenth NMOS transistor N14, the drain of the ninth PMOS transistor P9, and the first terminal of the second fuse FUSE2 are connected to the drive. The second terminal of the first fuse FUSE1 and the second terminal of the second fuse FUSE2 are both electrically connected to the drain of the fifteenth NMOS transistor N15. The second terminal of the first fuse FUSE1, the second terminal of the second fuse FUSE2, and the drain of the fifteenth NMOS transistor N15 are connected to the sink.

[0090] Specifically, during the process of turning on the first power domain, the second power domain, and the third power domain in any order, the fuse blowing and reading unit 306 does not receive a fuse blowing signal, and therefore will not blow the fuse. Specifically, during the turn-on process of the first power domain, the voltage rises from low to high. When a suitable voltage is reached, the fuse blowing and reading unit 306 begins the reading operation, but at this time, it does not store the read data.

[0091] After the multi-power domain disorder-activated anti-fuse circuit is powered on, it performs a write operation or a read operation on the fuse based on the received enable signal E. When the enable signal E is low, the ninth PMOS transistor P9 is turned off, preventing the sending of a fuse-breaking signal to the fuse-breaking and read unit 306, thus disabling the write operation on the fuse. At this time, the multi-power domain disorder-activated anti-fuse circuit enables the read operation on the fuse. Under the action of the bias voltage, the twelfth PMOS transistor P12 and the thirteenth PMOS transistor P13 are turned on, which in turn turns on the thirteenth NMOS transistor N13 and the fourteenth NMOS transistor N14. The fifteenth NMOS transistor is also in a conducting state. When the fuse is not blown, the second terminal of the fourth resistor R4 outputs a low-level signal, which is processed by the signal conversion unit 307 and outputs a high-level signal, realizing the storage of the information "1". When the fuse is blown, the second terminal of the fourth resistor R4 outputs a high-level signal, which is then processed by the signal conversion unit 307 and outputs a low-level signal to realize the storage of the information "0".

[0092] When the enable signal E is high, the ninth PMOS transistor P9 turns on and outputs a fuse-breaking signal to the second fuse FUSE2. Because the ninth PMOS transistor P9 is large, it can provide approximately 40mA of current. When the fuse is a polysilicon fuse, its breaking current is approximately 30mA. Therefore, when the ninth PMOS transistor P9 turns on, it can melt the polysilicon fuse, thus enabling a write operation on the fuse.

[0093] It should be noted that the thirteenth NMOS transistor N13 and the fourteenth NMOS transistor N14 form a current sink, ensuring that the current flowing through the first fuse FUSE1 is equal to the current flowing through the second fuse FUSE2. The thirteenth NMOS transistor N13 and the fourteenth NMOS transistor N14 have a small width-to-length ratio; when they are turned on, they output a current of approximately 5uA, which is not enough to blow the fuses. The bias voltage is used to prevent fluctuations in the current in the branch containing the thirteenth NMOS transistor N13 and the branch containing the fourteenth NMOS transistor N14.

[0094] It should be noted that the fuse blowing and reading unit 306 can also be replaced by other units that perform its function, and is not limited to this.

[0095] like Figure 5 As shown, the signal conversion unit 307 includes a fourth inverter 3071, a fifth inverter 3072, and a sixth inverter 3073. The fifth inverter 3072 is electrically connected to both the fourth inverter 3071 and the sixth inverter 3073. The fourth inverter 3071 is electrically connected to the fuse-blown readout unit 306. The fourth inverter 3071, fifth inverter 3072, and sixth inverter 3073 are all electrically connected between the second power domain and ground.

[0096] Specifically, when reading the fuse, the signal conversion unit 307 converts the signal output by the fuse blowing and reading unit 306. When the fuse is not blown, the fuse blowing and reading unit 306 outputs a low-level signal. The fourth inverter 3071, the fifth inverter 3072, and the sixth inverter 3073 sequentially invert the low-level signal output by the fuse blowing and reading unit 306, outputting a high-level signal to store the information "1". When the fuse is blown, the fuse blowing and reading unit 306 outputs a high-level signal. The fourth inverter 3071, the fifth inverter 3072, and the sixth inverter 3073 sequentially invert the high-level signal output by the fuse blowing and reading unit 306, outputting a low-level signal to store the information "0".

[0097] For example, such as Figure 6 As shown, the fourth inverter 3071 includes a fourteenth PMOS transistor P14 and a sixteenth NMOS transistor N16. The source and substrate of the fourteenth PMOS transistor P14 are both electrically connected to the second power supply domain to receive a 1.2V voltage. The gate of the fourteenth PMOS transistor P14 is electrically connected to the gate of the sixteenth NMOS transistor N16 and the second terminal of the fourth resistor R4, respectively. The gates of the fourteenth PMOS transistor P14, the sixteenth NMOS transistor N16, and the second terminal of the fourth resistor R4 are connected to fs. The drain of the fourteenth PMOS transistor P14 is electrically connected to the drain of the fifth inverter 3072 and the drain of the sixteenth NMOS transistor N16, respectively. The drains of the fourteenth PMOS transistor P14, the fifth inverter 3072, and the sixteenth NMOS transistor N16 are connected to fs1. The source and substrate of the sixteenth NMOS transistor N16 are both grounded to VSS. It should be noted that the gate oxide layers of the fourteenth PMOS transistor P14 and the sixteenth NMOS transistor N16 are thick gate oxide layers, which can withstand a voltage of 3.3V.

[0098] It should be noted that the fourth inverter 3071 can also be replaced by other units that perform its function, and is not limited to this.

[0099] For example, such as Figure 6As shown, the fifth inverter 3072 includes a fifteenth PMOS transistor P15 and a seventeenth NMOS transistor P17. The source and substrate of the fifteenth PMOS transistor P15 are both electrically connected to the second power domain to receive a 1.2V voltage. The gate of the fifteenth PMOS transistor P15 is electrically connected to the gate of the seventeenth NMOS transistor P17, the drain of the fourteenth PMOS transistor P14, and the drain of the sixteenth NMOS transistor N16, respectively. The gates of the fifteenth PMOS transistor P15, the seventeenth NMOS transistor P17, the fourteenth PMOS transistor P14, and the sixteenth NMOS transistor N16 are connected to fs1. The drain of the fifteenth PMOS transistor P15 is electrically connected to the drain of the seventeenth NMOS transistor P17 and the sixth inverter 3073, respectively. The drains of the fifteenth PMOS transistor P15, the seventeenth NMOS transistor P17, and the sixth inverter 3073 are connected to fs2. The source and substrate of the seventeenth NMOS transistor P17 are both used for grounding VSS. It should be noted that the gate oxide layers of the fifteenth PMOS transistor P15 and the seventeenth NMOS transistor P17 are thin gate oxide layers.

[0100] It should be noted that the fifth inverter 3072 can also be replaced by other units that perform its function, and is not limited to this.

[0101] For example, such as Figure 6 As shown, the sixth inverter 3073 includes a sixteenth PMOS transistor P16 and an eighteenth NMOS transistor N18. The source and substrate of the sixteenth PMOS transistor P16 are both electrically connected to the second power supply domain to receive a 1.2V voltage. The gate of the sixteenth PMOS transistor P16 is electrically connected to the gate of the eighteenth NMOS transistor N18, the drain of the fifteenth PMOS transistor P15, and the drain of the seventeenth NMOS transistor P17, respectively. The gates of the sixteenth PMOS transistor P16, N18, and P15, and the drains of P17 are connected to fs2. The drain of the sixteenth PMOS transistor P16 is electrically connected to the drain of the eighteenth NMOS transistor N18, and these two drains are connected to Y. The drains of the sixteenth PMOS transistor P16 and N18 serve as output ports. The source and substrate of the eighteenth NMOS transistor N18 are both used for grounding VSS. It should be noted that the gate oxide layers of the sixteenth PMOS transistor P16 and the eighteenth NMOS transistor N18 are thin gate oxide layers.

[0102] It should be noted that the sixth inverter 3073 can also be replaced by other units that perform its function, and is not limited to this.

[0103] The multi-power domain disordered start-up anti-fuse circuit provided in this application embodiment is used for polysilicon fuses, metal fuses, etc. It should be noted that the current for melting polysilicon fuses and metal fuses is different, and the size of the corresponding switching transistor needs to be adjusted according to their respective melting currents.

[0104] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0105] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A multi-power-domain disordered turn-on anti-fuse circuit, characterized in that, It includes a logic module, a drive switch module, and a fuse blowing and reading module; the drive switch module is electrically connected to the logic module and the fuse blowing and reading module respectively; the logic module is used to be electrically connected to a first power domain and a second power domain; the drive switch module is used to be electrically connected to a third power domain; the fuse blowing and reading module is used to be electrically connected to the first power domain, the second power domain, and the third power domain; the logic module, the drive switch module, and the fuse blowing and reading module are all grounded. During the process of the first power domain, the second power domain, and the third power domain being turned on in any order, the logic module is used to output a first logic signal to the drive switch module; the drive switch module is used to prevent the sending of a fuse breaking signal to the fuse breaking and reading module according to the first logic signal, wherein the fuse breaking signal is used to instruct the fuse breaking and reading module to break the fuse; The logic module includes a logic unit and a pull-down unit; the pull-down unit is electrically connected to the logic unit and the drive switch module respectively; the logic unit is used to be electrically connected to the first power domain and the second power domain; both the logic unit and the pull-down unit are used to be grounded. During the process of the first power domain, the second power domain and the third power domain being turned on in any order, the logic unit is used to output the first logic signal under the action of the pull-down unit; The drive switch module includes a first inverter, a second inverter, a third inverter, and a first switch unit; the second inverter is electrically connected to the first inverter and the third inverter respectively; the first inverter is electrically connected to the logic module; the third inverter is electrically connected to the first switch unit; the first switch unit is electrically connected to the fuse blowing and reading module; the first inverter, the second inverter, the third inverter, and the first switch unit are all used to be electrically connected to the third power domain; the first inverter, the second inverter, and the third inverter are all used to be grounded. During the process of the first power domain, the second power domain, and the third power domain being turned on in any order, the first inverter, the second inverter, and the third inverter sequentially invert the first logic signal output by the logic module to obtain the second logic signal; the first switching unit is used to prevent the sending of the fuse blowing and reading signal to the fuse blowing and reading module according to the second logic signal.

2. The multi-power domain disordered start-up anti-fuse circuit according to claim 1, characterized in that, The logic unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a seventeenth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a fifth resistor. The sources and substrates of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor are all electrically connected to the first power domain. The gate of the first PMOS transistor is electrically connected to the gate of the fourth PMOS transistor, the drain of the fifth PMOS transistor, the drain of the sixth NMOS transistor, and the gate of the second NMOS transistor. The drain of the first PMOS transistor is electrically connected to the drain of the second PMOS transistor, the gate of the third PMOS transistor, and the drain of the first NMOS transistor. The gate of the second PMOS transistor is grounded, and the drain of the third PMOS transistor is... The drain of the third NMOS transistor, the drain of the fourth PMOS transistor, the gate of the fifth PMOS transistor, the gate of the sixth NMOS transistor, the pull-down unit, and the drive switch module are electrically connected. The source and substrate of the sixth NMOS transistor are both grounded. The gate of the first NMOS transistor is electrically connected to the first terminal of the fifth resistor, the gate of the seventeenth PMOS transistor, and the gate of the fifth NMOS transistor, respectively. The source of the first NMOS transistor is electrically connected to the drain of the second NMOS transistor. The gate of the third NMOS transistor is electrically connected to the drain of the seventeenth PMOS transistor and the drain of the fifth NMOS transistor, respectively. The source and substrate of the seventeenth PMOS transistor are both electrically connected to the second power domain. The second terminal of the fifth resistor, the substrate of the first NMOS transistor, the source and substrate of the second NMOS transistor, the source and substrate of the third NMOS transistor, and the source and substrate of the fifth NMOS transistor are all grounded.

3. The multi-power domain disordered start-up anti-fuse circuit according to claim 1, characterized in that, The pull-down unit includes a first resistor; the first end of the first resistor is electrically connected to the logic unit and the drive switch module respectively, and the second end of the first resistor is used for grounding.

4. The multi-power domain disordered start-up anti-fuse circuit according to claim 1, characterized in that, The first switching unit includes a ninth PMOS transistor; the source and substrate of the ninth PMOS transistor are both used to be electrically connected to the third power domain, the gate of the ninth PMOS transistor is electrically connected to the third inverter, and the drain of the ninth PMOS transistor is electrically connected to the fuse blown and read module.

5. The multi-power domain disordered start-up anti-fuse circuit according to claim 1, characterized in that, The fuse blowing and reading module includes a first filtering unit, a second filtering unit, a pull-up unit, a second switching unit, a third switching unit, a fuse blowing and reading unit, and a signal conversion unit. The second switching unit is electrically connected to the pull-up unit, the third switching unit, and the first filtering unit, respectively. The second filtering unit is electrically connected to the pull-up unit. The fuse blowing and reading unit is electrically connected to the drive switching module, the third switching unit, and the signal conversion unit, respectively. The first filtering unit is used to be electrically connected to the third power domain. The second filtering unit and the fuse blowing and reading unit are both used to be electrically connected to the first power domain. The signal conversion unit is used to be electrically connected to the second power domain. The first filtering unit, the second filtering unit, the second switching unit, the third switching unit, and the signal conversion unit are all grounded.

6. The multi-power domain disordered start-up anti-fuse circuit according to claim 5, characterized in that, The pull-up unit includes a tenth PMOS transistor, an eleventh PMOS transistor, a tenth NMOS transistor, and an eleventh NMOS transistor. The source and substrate of the tenth PMOS transistor and the eleventh PMOS transistor are electrically connected to the second filter unit. The gate of the tenth PMOS transistor is electrically connected to the gate of the eleventh PMOS transistor, the drain of the tenth NMOS transistor, the gate of the eleventh NMOS transistor, and the drain of the eleventh NMOS transistor, respectively. The drain of the tenth PMOS transistor is electrically connected to the gate of the tenth NMOS transistor. The source and substrate of the tenth NMOS transistor and the eleventh NMOS transistor are both grounded. The drain of the eleventh PMOS transistor is electrically connected to the second switching unit and the third switching unit, respectively.

7. The multi-power domain disordered start-up anti-fuse circuit according to claim 6, characterized in that, The fuse-breaking and readout unit includes a twelfth PMOS transistor, a thirteenth PMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fourth resistor, a first fuse, and a second fuse. The sources and substrates of the twelfth and thirteenth PMOS transistors are both electrically connected to the first power domain. The gates of the twelfth and thirteenth PMOS transistors are both used to receive bias voltage. The drain of the twelfth PMOS transistor is electrically connected to the drain, gate, and gate of the thirteenth NMOS transistor, respectively. The drain of the thirteenth PMOS transistor is electrically connected to the first terminal of the fourth resistor and the drain of the fourteenth NMOS transistor, respectively. The second terminal of the fourth resistor is electrically connected to the signal conversion unit. The substrates of the thirteenth NMOS transistor and the fourteenth NMOS transistor are both grounded. The source of the thirteenth NMOS transistor is electrically connected to the first terminal of the first fuse. The source of the fourteenth NMOS transistor is electrically connected to the drive switch module and the first terminal of the second fuse, respectively. The second terminals of the first fuse and the second fuse are both electrically connected to the third switch unit.

8. The multi-power domain disordered start-up anti-fuse circuit according to claim 7, characterized in that, The signal conversion unit includes a fourth inverter, a fifth inverter, and a sixth inverter; the fifth inverter is electrically connected to the fourth inverter and the sixth inverter respectively, the fourth inverter is electrically connected to the fuse blowing and reading unit, and the fourth inverter, the fifth inverter, and the sixth inverter are all electrically connected between the second power domain and ground.

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