Stacked 2t1c-dram memory device based on heterogeneous integration and method of manufacturing the same
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-05-18
- Publication Date
- 2026-08-11
AI Technical Summary
随着晶体管特征尺寸的减小，存储阵列集成密度提高的同时晶体管的栅极对沟道的控制能力减弱，漏致势垒降低等短沟道效应加大了器件的闭电流，DRAM存储节点内的电荷通过以接入晶体管的亚阈值泄漏为主的各种泄漏通道逐渐排出，导致DRAM单元的保留时间减少，且由于其数据的读取路和写入路为同一条晶体管，读取过程会破坏节点内的存储数据，是一种破坏性读取，因此需要不断进行数据刷新和回写操作
[0050]本发明还提供集成电路芯片，该芯片上至少有一个半导体器件为所述的2T1C-DRAM。
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Figure CN116744675B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor device technology, specifically relating to dynamic random access memory devices and their manufacturing methods. Background Technology
[0002] Dynamic Random Access Memory (DRAM) devices are the primary memory in current computer architectures, mainly composed of a MOSFET transistor and a capacitor. The transistor is responsible for both charging and reading the capacitor. As transistor feature sizes decrease and memory array integration density increases, the gate's control over the channel weakens. Short-channel effects, such as drain-induced barrier reduction, increase the device's shut-off current. Charge within DRAM memory nodes gradually drains through various leakage channels, primarily subthreshold leakage from the transistor, leading to reduced DRAM cell retention time. Furthermore, since the read and write paths share the same transistor, the read process can corrupt the stored data within the node, constituting a destructive read, thus requiring continuous data refresh and write-back operations. 2T-DRAM and 3T-DRAM topologies, building upon 1T1C-DRAM, introduce dedicated read transistors to separate the write and read paths, improving data stability. However, this increases the area of each memory cell, and the short data retention time due to shut-off current persists. Therefore, DRAM development has consistently faced the challenge of reducing leakage current and power consumption while simultaneously increasing integration density. Summary of the Invention
[0003] The purpose of this invention is to provide a stacked 2T1C dynamic random access memory device with excellent electrical performance, which can reduce leakage current, increase data retention time within the storage node, and reduce the area of the storage cell, and the same method for its fabrication.
[0004] The stacked 2T1C dynamic random access memory (DRAM) device provided by this invention is an improvement on the traditional 2T1C DRAM based on MoS2-Si heterogeneous integration. It features a vertically stacked structure of two heterogeneous transistors; the two source metal layers and the intermediate dielectric naturally form a MIM capacitor structure, thereby increasing the integration density of DRAM and mitigating its short retention time. By vertically stacking MoS2-FETs with a large bandgap as write transistors on silicon-based read transistors, the leakage current of the write transistors is reduced, the data retention time within the memory node is increased, and the area of the memory cell is reduced. This invention's memory device not only possesses excellent electrical performance and broad application prospects, but its process is also based on traditional CMOS, making the process simple and mature, and applicable to the field of high-performance memory.
[0005] Specifically, the present invention provides a stacked 2T1C-DRAM memory device based on MoS2-Si heterogeneous integration, the structure of which is described below. Figure 1 As shown, it includes:
[0006] Si substrate 1;
[0007] Buried oxide layer 2 formed on Si substrate 1;
[0008] Source electrode 6, channel region 3, and drain electrode 7 are arranged from left to right on the buried oxide layer 2;
[0009] The first gate oxide layer 4, the gate 5, and the first gate metal 9 are formed sequentially from bottom to top on the channel region 3;
[0010] Sidewalls 8 are formed on both sides of the first gate oxide layer 4, the gate 5, and the first gate metal 9;
[0011] A first source metal 10 is formed on the source 6 and outside the left sidewall 8, and a MIM dielectric layer 16 is formed on the first source metal 10;
[0012] The first drain metal 11 is formed on the source electrode 7 and outside the right sidewall 8;
[0013] An isolation layer 12 is formed on the first drain metal 11, the right sidewall 8, and the first gate metal 9 (right side portion);
[0014] A second gate oxide layer 14 and a MoS2 active region 15 are sequentially formed on the isolation layer 12; the second gate oxide layer 14 contains a second gate metal 13, and the second gate metal 13 is on the isolation layer 12.
[0015] The second drain metal 18 is formed on the active region 15 of MoS2;
[0016] A second source metal 17 is formed on the MIM dielectric layer 16 and the first gate metal 9 (left side).
[0017] Furthermore, among which:
[0018] The substrate 1 is undoped or weakly doped; the channel region 3 is undoped or weakly n-type doped; and the source 6 and drain 7 are weakly n-type doped or strongly n-type doped.
[0019] The doping concentration of the channel region 3 and / or the substrate 1 is weaker than that of the source 6 and / or the drain 7.
[0020] The doping concentration of the substrate 1 is 10. 15 Up to 10 19 cm -2 between.
[0021] The doping concentration of the channel region 3 is 10.15 Up to 10 19 cm -2 between.
[0022] The doping concentration of the source 6 and drain 7 is 10. 15 Up to 10 21 cm -2 between.
[0023] The first gate oxide layer 4 is one or more of silicon dioxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, tantalum oxide, strontium oxide, and iridium oxide, and its thickness ranges from 1 to 30 nm.
[0024] The gate 5 is a polycrystalline silicon or metal, or a composite layer of polycrystalline silicon and metal, with a thickness ranging from 10nm to 500nm.
[0025] The sidewall 8 is made of one or more of the following materials: silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, tantalum oxide, strontium oxide, and iridium oxide.
[0026] The first gate metal (9), the first source metal (10), the first drain metal (11), the second gate metal (13), the second source metal (17), and the second drain metal (18) are one or more of aluminum, nickel, titanium, gold, and metal silicide, and their thickness ranges from 10nm to 200nm.
[0027] The isolation layer 12, the second gate oxide layer 14, and the MIM dielectric layer 16 are one or more of silicon dioxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, tantalum oxide, strontium oxide, and iridium oxide, with a thickness ranging from 10 to 1000 nm.
[0028] This invention also provides a method for fabricating the 2T1C memory device, comprising the following steps:
[0029] S1. Initial SOI die settings;
[0030] S2. Deposit the first gate oxide layer 4 and deposit the gate material thereon;
[0031] S3. Photolithography and etching are performed to form the gate pattern;
[0032] S4. Using gate 5 as a mask template, source 6 and drain 7 are formed by ion implantation;
[0033] S5. Deposit the sidewall dielectric of the gate 5 and etch it to form the sidewalls 8 on both sides of the gate 5;
[0034] S6. Deposit metal and anneal to form a first gate metal 9, a first source metal 10 and a first drain metal 11;
[0035] S7. Deposited oxide isolation layer 12;
[0036] S8. Deposit metal contacts and anneal to form the second gate metal 13;
[0037] S9. Deposit the second gate oxide layer 14;
[0038] S10. Synthesize MoS2 and form the MoS2 active region 15 by photolithography;
[0039] S11. Photolithography and etching are performed to form the MIM dielectric layer 16;
[0040] S12. Deposit metal, photolithography and annealing to form the second source metal 17 and the second drain metal 18.
[0041] Preferably, steps S2, S7, and S9 further include: the oxide layer is deposited by one or more of thermal oxidation, chemical vapor deposition, and atomic layer deposition methods.
[0042] Step S3 further includes: photolithography to open the window of the gate pattern, and then using photoresist as a mask to perform etching to form the gate pattern. The etching in step S3 is either dry etching or wet etching. The dry etching uses fluorine-based or halogen gas, and the wet etching is wet etching.
[0043] Step S4 further includes: using arsenic or phosphorus during ion implantation at a dose of 10. 12 cm -2 Up to 10 16 cm -2 The energy ranges from 1 keV to 50 keV.
[0044] Step S5 further includes: using one or more of chemical vapor deposition and atomic layer deposition as the deposition method, and using one or more of reactive ion etching with vertical orientation and dry etching with fluorine-based gas as the etching method.
[0045] Steps S6, S8, and S12 further include: photolithography and opening a deposition window, performing metal deposition using photoresist as a mask, followed by stripping and annealing to form metal contacts, with the annealing temperature between 300 and 1000 degrees Celsius, and the metal deposition method being one or more of electron beam evaporation deposition and magnetron sputtering.
[0046] Step S10 further includes: the synthesis and growth of MoS2 is carried out by one or more of mechanical exfoliation, chemical exfoliation, and chemical vapor deposition, wherein the mechanical exfoliation is carried out by one or more of transparent tape method and wafer anodic bonding method; and the chemical exfoliation is carried out by one or more of ion intercalation and solvent-based exfoliation.
[0047] Step S11 further includes: photolithography and opening a window, etching the oxide layer using photoresist as a mask, and using one or more of the following etching methods: vertically oriented reactive ion etching and dry etching with fluorine-based gas.
[0048] Step S12 further includes: performing isotropic metal deposition, followed by photolithography to form source metal 2 and drain metal 2, with an annealing temperature between 300 degrees and 1000 degrees, wherein the metal deposition method is one or more of electron beam evaporation coating and magnetron sputtering, and the etching method is one or more of reactive ion etching with vertical orientation and dry etching with fluorine-based gas.
[0049] The dynamic random access memory (DRAM) device provided by this invention has a lower layer consisting of an NMOS transistor built on a silicon-on-insulator (SOI) substrate, which functions as a read transistor, and an upper layer consisting of a MoS2-MOSFET, which functions as a write transistor. The source metals of the two transistors and the dielectric layer between them together constitute a MIM capacitor, while the source metal of the MoS2-FET is directly connected to the gate metal of the SOI-FET. By replacing the write transistor of the silicon-based 2T1C-DRAM with a MoS2-FET and stacking them vertically on top of the read transistor to form a stacked structure, this invention reduces the area of the memory cell. Furthermore, due to the larger bandgap of MoS2, the write transistor's turn-off current is reduced, thus improving the data storage time of the memory cell.
[0050] The present invention also provides an integrated circuit chip, wherein at least one semiconductor device on the chip is the 2T1C-DRAM described above.
[0051] The beneficial effects of this invention are as follows.
[0052] The two transistors in the stacked 2T1C dynamic random access memory device based on MoS2-Si heterogeneous integration of this invention are stacked, with the write transistor built on MoS2, which has a relatively large bandgap. By vertically stacking MoS2 material with a larger bandgap onto silicon-based transistors for use as write transistors, the area of a single memory cell is reduced to the area of a single transistor while retaining non-destructive read characteristics, and the data retention time is improved. The stacked 2T1C-DRAM memory device is manufactured using traditional CMOS technology, which is simple, mature, and applicable to high-performance memory applications. Attached Figure Description
[0053] Figure 1 This is a structural diagram of Embodiment 1 of the DRAM memory device of the present invention.
[0054] Figures 2a-2m This is a flowchart illustrating the fabrication process of Embodiment 1 of the DRAM memory device of the present invention.
[0055] Figures 3a-3c Other embodiments of the DRAM memory device of the present invention are shown. Among them, (a) is the device structure corresponding to embodiment 2, (b) is the device structure corresponding to embodiment 3, and (c) is the device structure corresponding to embodiment 4.
[0056] In the figure, the labels are as follows: 1 is Si substrate, 2 is buried oxide layer, 3 is channel region, 4 is first gate oxide layer, 5 is gate, 6 is source, 7 is drain, 8 is sidewall, 9 is first gate metal, 10 is first source metal, 11 is first drain metal, 12 is isolation layer, 13 is second gate metal, 14 is second gate oxide layer, 15 is MoS2 active region, 16 is MIM dielectric layer, 17 is second source metal, and 18 is second drain metal. Detailed Implementation
[0057] The present invention will now be further described in conjunction with embodiments and accompanying drawings.
[0058] In this invention, the write transistor required for 2T1C-DRAM is a MoS2-FET with a larger upper bandgap and lower turn-off current, the read transistor is a lower SOI-FET, and the capacitor is a MIM capacitor composed of the source metal of the two transistors and the insulating dielectric in between.
[0059] Based on the same working principle, the structure of the device can be different. Example 1 (corresponding to...) Figure 1 The device structure and process flow shown in Figure 2), Example 2 (corresponding to Figure 3a Device structure diagram), Example 3 (corresponding to) Figure 3b Device structure diagram), Example 4 (corresponding to) Figure 3c (Diagram of device structure).
[0060] Example 1 (corresponding) Figure 1 (The device structure and the process flow shown in Figure 2).
[0061] A stacked 2T1C-DRAM memory device based on MoS2-Si heterogeneous integration includes: a Si substrate, a buried oxide layer, a channel region, a first gate oxide layer 1, a gate, a source, a drain, a sidewall, a first gate metal 1, a first source metal 1, a first drain metal 1, an isolation layer, a second gate metal 2, a second gate oxide layer 2, a MoS2 active region, a MIM dielectric layer, a second source metal 2, and a second drain metal 2.
[0062] (1) As shown in Figure 2(a), the initial SOI die has a substrate doping concentration between 0 and 10. 19 cm -2 Between 0 and 10, the doping concentration of its SOI active region is between 0 and 10. 19 cm -2 between.
[0063] (2) A gate oxide layer 1 is deposited on the SOI die, and a gate material is deposited thereon. Subsequently, photolithography and etching are performed to form a gate pattern. Etching is performed using either dry etching or wet etching. Dry etching uses fluorine-based or halogen gas, while wet etching is a wet etching process. The gate oxide layer is generally one or more of silicon dioxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, tantalum oxide, strontium oxide, and iridium oxide, with a thickness ranging from 1 to 30 nm. The deposited gate material is polysilicon, metal, or a composite layer of polysilicon and metal, with a thickness ranging from 10 nm to 500 nm.
[0064] (3) Using the gate as a self-aligned mask, the source and drain are formed by ion implantation; arsenic or phosphorus is used for ion implantation, with a dose of 10. 12 cm -2 Up to 10 16 cm -2 Between 1keV and 50keV, the doping concentration of the source and drain electrodes is between 10. 15 Up to 10 21 cm -2 Between these two regions, the doping concentration is greater than that in the channel region and the substrate.
[0065] (4) The sidewall dielectric of the gate is deposited and etched to form the sidewalls on both sides of the gate. The sidewall material is one or more of silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, tantalum oxide, strontium oxide, and iridium oxide. The deposition method is one or more of chemical vapor deposition and atomic layer deposition, and the etching method is one or more of reactive ion etching with vertical orientation and dry etching with fluorine-based gas.
[0066] (5) Photolithography is performed and the deposition window is opened. Metal deposition is performed using photoresist as a mask. Then, the metal is stripped and annealed to form the first gate metal 1, the first source metal 1 and the first drain metal 1. The annealing temperature is between 300 degrees and 1000 degrees. The metal deposition method is one or more of electron beam evaporation coating and magnetron sputtering. The metal material is one or more of aluminum, nickel, titanium, gold and metal silicide. The thickness range is 10nm-200nm.
[0067] (6) Deposit an oxide isolation layer; the deposition method is one or more of thermal oxidation, chemical vapor deposition, and atomic layer deposition, and the oxide layer material is one or more of silicon dioxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, tantalum oxide, strontium oxide, and iridium oxide, with a thickness range of 20-1000 nm.
[0068] (7) Photolithography is performed to open the deposition window, and metal deposition is carried out using photoresist as a mask. The metal is then stripped and annealed to form the second gate metal 2. The annealing temperature is between 300 and 1000 degrees Celsius. The metal deposition method is one or more of electron beam evaporation deposition, magnetron sputtering, and metal contact followed by annealing. The metal material is one or more of aluminum, nickel, titanium, gold, and metal silicides, with a thickness ranging from 10 nm to 200 nm.
[0069] (8) Deposit gate oxide layer 2, the deposition method is one or more of thermal oxidation, chemical vapor deposition, and atomic layer deposition, the oxide layer material is one or more of silicon dioxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, tantalum oxide, strontium oxide, and iridium oxide, and its thickness ranges from 20 to 1000 nm.
[0070] (9) Synthesize MoS2 and form the active region of MoS2 by photolithography (15).
[0071] (10) Photolithography is performed and the window is opened. The first gate metal 1 is exposed by etching using photoresist as a mask, and a MIM dielectric layer is formed at the same time. The etching method is one or more of the following: reactive ion etching with vertical orientation and dry etching with fluorine-based gas.
[0072] (11) Isotropic metal deposition is performed, followed by photolithography and etching to form a second source metal 2 and a second drain metal 2. The annealing temperature is between 300 and 1000 degrees Celsius. The metal deposition method is one or more of electron beam evaporation deposition and magnetron sputtering followed by metal contact and annealing. The metal material is one or more of aluminum, nickel, titanium, gold, and metal silicides, with a thickness ranging from 10 nm to 200 nm. The etching method is one or more of reactive ion etching with vertical orientation and dry etching with fluorine-based gas.
[0073] Example 2 (corresponding) Figure 3a (Diagram of device structure).
[0074] The device structure and process flow of Example 2 are similar to those of Example 1. The difference is that in Example 1, the gate of the upper MoS2 transistor is buried under the oxide layer, while in Example 2, the gate of the upper MoS2 transistor is above the oxide layer. Its structure is similar to that of the standard MOS structure.
[0075] Example 3 (corresponding) Figure 3b (Diagram of device structure).
[0076] Example 3 is similar to Example 1, except that the two FETs stacked vertically in Example 1 have different horizontal coordinates.
[0077] Example 4 (corresponding) Figure 3c(Diagram of device structure).
[0078] Example 4 is similar to Example 1, except that the two FETs stacked vertically in Example 1 have different horizontal coordinates, and the gate of the upper MoS2 transistor in Example 4 is above the oxide layer, and its structure is similar to the standard MOS structure.
[0079] In summary, this invention proposes a stacked 2T1C dynamic random access memory (DRAM) device based on MoS2-Si heterogeneous integration. The device utilizes MoS2, with its wider bandgap, as the channel material for the DRAM write transistor, reducing leakage current dominated by subthreshold current and improving data storage time. Simultaneously, the vertically stacked structure of the two transistors reduces the area of the memory cells, increasing the integration density of the memory array. While retaining non-volatile read performance, it solves the problems of short storage time and low integration density in traditional DRAM. The memory device manufactured by this invention has advantages such as high integration, long storage time, and low power consumption. This invention is based on mature SOI-MOSFET technology, with a simple and mature process, and can be applied to the field of high-performance dynamic memory.
[0080] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.
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Claims
1. A stacked 2T1C-DRAM memory device based on MoS2-Si heterogeneous integration, characterized in that, This is a vertically stacked structure of two heterogeneous transistors; the two source metal layers and the intermediate dielectric naturally form a MIM capacitor structure to improve the integration density of DRAM and mitigate the short retention time of DRAM; by vertically stacking MoS2-FETs with a large bandgap as write transistors on silicon-based read transistors, the leakage current of the write transistors is reduced, the data retention time within the memory node is increased, and the area of the memory cell is reduced; specifically including: Si substrate (1). Buried oxide layer (2) formed on Si substrate (1); Source electrode (6), channel region (3), and drain electrode (7) arranged from left to right on the buried oxygen layer (2); The first gate oxide layer (4), gate (5), and first gate metal (9) are formed sequentially from bottom to top on the channel region (3). Sidewalls (8) are formed on both sides of the first gate oxide layer (4), the gate (5), and the first gate metal (9). A first source metal (10) is formed on the source (6) and outside the left sidewall (8), and a MIM dielectric layer (16) is formed on the first source metal (10). The first drain metal (11) is formed on the source electrode (7) and outside the right sidewall (8). An isolation layer (12) is formed on the first drain metal (11), the right sidewall (8), and the first gate metal (9) (right side portion). A second gate oxide layer (14) and a MoS2 active region (15) are sequentially formed on the isolation layer (12); the second gate oxide layer (14) contains a second gate metal (13), and the second gate metal (13) is on the isolation layer (12); The second drain metal (18) is formed on the active region (15) of MoS2. A second source metal (17) is formed on the left side of the MIM dielectric layer (16) and the first gate metal (9).
2. The stacked 2T1C-DRAM memory device according to claim 1, characterized in that: The substrate (1) is undoped or weakly doped; the channel region (3) is undoped or weakly n-type doped; the source (6) and drain (7) are weakly n-type doped or strongly n-type doped. The doping concentration of the channel region (3) and / or the substrate (1) is weaker than the doping concentration of the source (6) and / or the drain (7); The doping concentration of the substrate (1) is between 0 and 10. 19 cm -2 between; The doping concentration of the channel region (3) is between 0 and 10. 19 cm -2 between; The doping concentration of the source (6) and drain (7) is 10. 15 Up to 10 21 cm -2 between.
3. The stacked 2T1C-DRAM memory device according to claim 1, characterized in that: The first gate oxide layer (4) is one or more of silicon dioxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, tantalum oxide, strontium oxide, and iridium oxide, and its thickness ranges from 1 to 30 nm; The gate (5) is a polycrystalline silicon or metal, or a composite layer of polycrystalline silicon and metal, with a thickness of 10nm-500nm.
4. The stacked 2T1C-DRAM memory device according to claim 1, characterized in that: The sidewall (8) is made of one or more of the following materials: silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, tantalum oxide, strontium oxide, and iridium oxide. The first gate metal (9), the first source metal (10), the first drain metal (11), the second gate metal (13), the second source metal (17), and the second drain metal (18) are one or more of aluminum, nickel, titanium, gold, and metal silicide, and their thickness is 10nm-200nm.
5. The stacked 2T1C-DRAM memory device according to claim 1, characterized in that, The isolation layer (12), the second gate oxide layer (14), and the MIM dielectric layer (16) are one or more of silicon dioxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, tantalum oxide, strontium oxide, and iridium oxide; and their thickness is 10-1000 nm.
6. The method for fabricating a stacked 2T1C-DRAM memory device as described in any one of claims 1-5, characterized in that, The specific steps are as follows: S1. Initial SOI die setup; S2. Deposit a first gate oxide layer (4) and deposit gate material thereon; S3. Photolithography and etching to form the gate pattern; S4. Using the gate (5) as a mask, the source (6) and drain (7) are formed by ion implantation. S5. Deposit the sidewall dielectric of the gate (5) and etch to form the sidewalls (8) on both sides of the gate (5). S6. Deposit metal and anneal to form a first gate metal (9), a first source metal (10) and a first drain metal (11). S7. Deposit oxide isolation layer (12); S8. Deposit metal contacts and anneal to form a second gate metal (13). S9. Deposit the second gate oxide layer (14); S10. Synthesize MoS2 and form the active region of MoS2 by photolithography (15). S11. Photolithography and etching to form a MIM dielectric layer (16). S12. Deposit metal, photolithography and annealing to form a second source metal (17) and a second drain metal (18).
7. The preparation method according to claim 6, characterized in that: Steps S2, S7, and S9 further include: the oxide layer is deposited by one or more of the following methods: thermal oxidation, chemical vapor deposition, and atomic layer deposition. Step S3 further includes: photolithography to open the window of the gate pattern, and then using photoresist as a mask to perform etching to form the gate pattern. The etching in step S3 is either dry etching or wet etching. The dry etching uses fluorine-based or halogen gas, and the wet etching is wet etching.
8. The preparation method according to claim 6, characterized in that: Step S4 further includes: using arsenic or phosphorus during ion implantation at a dose of 10. 12 cm -2 Up to 10 16 cm -2 The energy ranges from 1 keV to 50 keV. Step S5 further includes: using one or more of chemical vapor deposition and atomic layer deposition as the deposition method, and using one or more of reactive ion etching with vertical orientation and dry etching with fluorine-based gas as the etching method. Steps S6, S8, and S12 further include: photolithography and opening a deposition window, performing metal deposition using photoresist as a mask, followed by stripping and annealing to form metal contacts, with the annealing temperature between 300 and 1000 degrees Celsius, and the metal deposition method being one or more of electron beam evaporation deposition and magnetron sputtering.
9. The preparation method according to claim 6, characterized in that: Step S10 further includes: the synthesis and growth of MoS2 employs one or more of mechanical exfoliation, chemical exfoliation, and chemical vapor deposition; the mechanical exfoliation employs one or more of transparent tape method and wafer anodic bonding method; the chemical exfoliation employs one or more of ion intercalation and solvent-based exfoliation. Step S11 further includes: photolithography and opening a window, etching the oxide layer using photoresist as a mask, and using one or more of the following etching methods: vertically oriented reactive ion etching and dry etching with fluorine-based gas. Step S12 further includes: performing isotropic metal deposition, followed by photolithography to form source metal 2 and drain metal 2, with an annealing temperature between 300 degrees and 1000 degrees, wherein the metal deposition method is one or more of electron beam evaporation coating and magnetron sputtering, and the etching method is one or more of reactive ion etching with vertical orientation and dry etching with fluorine-based gas.
10. An integrated circuit chip, characterized in that, At least one semiconductor device on the chip is a 2T1C-DRAM memory device as described in any one of claims 1-5.