Semiconductor structure and method of forming the same

Abstract

The present disclosure relates to the technical field of semiconductor technology, and discloses a semiconductor structure and a forming method thereof. The forming method comprises the following steps: providing a substrate, the substrate comprising an array region and a peripheral region which are adjacently distributed; forming an insulating layer covering the surface of the array region and the peripheral region; forming a protective layer on at least the surface of the insulating layer located in the peripheral region; forming a stacked film layer covering the surface of the structure formed by the insulating layer and the protective layer, the stacked film layer comprising a first sacrificial layer, a middle support layer, a second sacrificial layer and a top support layer which are sequentially and adjacently distributed; etching the stacked film layer, the protective layer and the insulating layer to form a plurality of capacitive holes which are adjacently distributed, and the orthographic projection of the capacitive holes on the substrate is located in the array region; forming a lower electrode layer in the capacitive holes; etching and removing the first sacrificial layer and the second sacrificial layer, and the etching rate of the first sacrificial layer and the second sacrificial layer is greater than the etching rate of the protective layer. The forming method can reduce structural defects and improve product yield.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and a method for forming the same. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is widely used in mobile devices such as smartphones and tablets due to its advantages such as small size, high integration, and high transfer speed. The capacitor structure is one of the important structures in DRAM, mainly used to store electrical charge. However, structural defects are prone to occur during the manufacturing process of the capacitor structure, resulting in a low product yield.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] In view of this, the present disclosure provides a semiconductor structure and a method for forming the same, which can reduce structural defects and improve product yield.

[0005] According to one aspect of this disclosure, a method for forming a semiconductor structure is provided, comprising:

[0006] A substrate is provided, the substrate comprising an array region and a peripheral region distributed adjacent to each other;

[0007] An insulating layer is formed covering the surfaces of the array region and the peripheral region;

[0008] A protective layer is formed at least on the surface of the insulating layer located in the peripheral region;

[0009] A stacked film layer is formed to cover the surface of the structure jointly constituted by the insulating layer and the protective layer, the stacked film layer comprising a first sacrificial layer, a middle support layer, a second sacrificial layer and a top support layer stacked in sequence;

[0010] The stacked film layer, the protective layer, and the insulating layer are etched to form a plurality of spaced capacitor holes, the orthogonal projection of the capacitor holes on the substrate being located in the array region;

[0011] A lower electrode layer is formed within the capacitor hole;

[0012] The first sacrificial layer and the second sacrificial layer are removed by etching, and the etching rates of the first sacrificial layer and the second sacrificial layer are both greater than the etching rate of the protective layer.

[0013] In one exemplary embodiment of this disclosure, the etch rate ratio of the first sacrificial layer and the second sacrificial layer to the protective layer is 1:0.3.

[0014] In one exemplary embodiment of this disclosure, the etching to remove the first sacrificial layer and the second sacrificial layer includes:

[0015] A first opening is formed within the top support layer to expose the second sacrificial layer;

[0016] The second sacrificial layer is removed through the first opening to expose the surface of the central support layer;

[0017] The central support layer is etched to form a second opening exposing the first sacrificial layer, wherein the etch rate of the central support layer is greater than or equal to the etch rate of the protective layer;

[0018] The first sacrificial layer is removed through the second opening.

[0019] In one exemplary embodiment of this disclosure, the middle support layer is made of a different material than the protective layer, and the middle support layer is made of the same material as the insulating layer.

[0020] In one exemplary embodiment of this disclosure, the first sacrificial layer and the second sacrificial layer are both made of silicon oxide, the middle support layer is made of silicon nitride, and the protective layer is made of carbon, amorphous carbon, amorphous carbon, or diamond-like carbon.

[0021] In one exemplary embodiment of this disclosure, the middle support layer is made of the same material as the protective layer.

[0022] In one exemplary embodiment of this disclosure, both the central support layer and the protective layer are made of silicon nitride.

[0023] In one exemplary embodiment of this disclosure, the forming method further includes:

[0024] After removing the first sacrificial layer and the second sacrificial layer, the protective layer located in the peripheral area is removed.

[0025] In one exemplary embodiment of this disclosure, the forming method further includes:

[0026] A capacitor dielectric layer is formed on the surface of the structure jointly formed by the lower electrode layer, the insulating layer, the middle support layer located in the array region, and the top support layer located in the array region;

[0027] An upper electrode layer is formed on the surface of the capacitor dielectric layer.

[0028] According to one aspect of this disclosure, a semiconductor structure is provided, said semiconductor structure being formed by the method for forming a semiconductor structure according to any one of the preceding claims.

[0029] The semiconductor structure and its formation method disclosed herein, because a protective layer is formed on the surface of the peripheral region, and the etching rates of both the first and second sacrificial layers are greater than the etching rate of the protective layer, can protect the insulating layer within the peripheral region during the etching process of removing the first and second sacrificial layers. This reduces the probability of damage to the insulating layer within the peripheral region, and consequently reduces the probability of damage to the circuit structure beneath the insulating layer during the etching process of the first and second sacrificial layers, helping to reduce structural defects and thus improve product yield. Furthermore, during the removal of the first and second sacrificial layers, the middle support layer provides lateral support to the middle of the lower electrode layer, and the top support layer provides lateral support to the top of the lower electrode layer, helping to reduce the probability of the lower electrode layer collapsing and further improving product yield.

[0030] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0031] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0032] Figure 1 This is a schematic diagram of a semiconductor structure in related technologies.

[0033] Figure 2 This is a flowchart of a method for forming a semiconductor structure according to an embodiment of this disclosure.

[0034] Figure 3 This is a schematic diagram of the substrate, insulating layer, protective layer, stacked film layers and first mask layer in an embodiment of this disclosure.

[0035] Figure 4 This is a schematic diagram of the capacitor hole in an embodiment of this disclosure.

[0036] Figure 5 This is a top view of the capacitor hole in an embodiment of this disclosure.

[0037] Figure 6 This is a schematic diagram of the first mask layer after removal in an embodiment of this disclosure.

[0038] Figure 7 This is a schematic diagram after step S160 is completed in an embodiment of this disclosure.

[0039] Figure 8 This is a schematic diagram after step S170 is completed in an embodiment of this disclosure.

[0040] Figure 9 This is a schematic diagram after step S210 is completed in an embodiment of this disclosure.

[0041] Figure 10 This is a schematic diagram after step S230 is completed in an embodiment of this disclosure.

[0042] Figure 11 This is a schematic diagram after step S180 is completed in an embodiment of this disclosure.

[0043] Figure 12 This is a schematic diagram after step S190 is completed in an embodiment of this disclosure.

[0044] Figure 13 This is a schematic diagram after step S200 is completed in an embodiment of this disclosure.

[0045] Explanation of reference numerals in the attached figures:

[0046] 100, Substrate; 200, Support layer; 300, Capacitor via; 400, Lower electrode layer; A, Array region; B, Peripheral region; 1, Substrate; 11, Storage node contact plug; 2, Insulating layer; 3, Protective layer; 4, Stacked film layers; 41, First sacrificial layer; 42, Middle support layer; 421, Second opening; 43, Second sacrificial layer; 44, Top support layer; 441, First opening; 101, Capacitor via; 5, Capacitor structure; 51, Lower electrode layer; 510, Particle; 52, Capacitor dielectric layer; 53, Upper electrode layer; 6, First mask layer; 61, Polysilicon layer; 62, Silicon oxide layer; 601, First mask pattern; 7, Second mask layer; 71, Silicon nitride layer; 72, Hard mask layer; 701, Second mask pattern; a, Array region; b, Peripheral region. Detailed Implementation

[0047] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0048] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0049] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0050] The capacitor structure fabrication process includes: forming multiple alternately distributed support layers 200 and sacrificial layers on a substrate 100; etching each support layer 200 and each sacrificial layer to form capacitor holes 300; forming a lower electrode layer 400 of the capacitor structure within the capacitor holes 300; and removing the sacrificial layer by wet etching. However, during the etching process to form the capacitor holes 300, due to the influence of the fabrication process, the size of the capacitor holes 300 located at the junction of the array region A and the peripheral region B of the substrate 100 is relatively small. During the subsequent deposition of the lower electrode layer 400 of the capacitor structure, the small-sized capacitor holes 300 are easily sealed prematurely, preventing the deposition of the lower electrode layer 400 inside. During the subsequent wet etching process to remove the sacrificial layer, the etching solution easily penetrates into the peripheral region B through the small-sized capacitor holes 300, damaging the circuit structure within the peripheral region B and leading to structural defects (such as…). Figure 1 (As shown).

[0051] Based on this, embodiments of the present disclosure provide a method for forming a semiconductor structure. Figure 2 A flowchart illustrating the method for forming the semiconductor structure of this disclosure is shown below. Figure 2 As shown, the forming method includes steps S110-S170, wherein:

[0052] Step S110: Provide a substrate, the substrate comprising adjacent array regions and peripheral regions;

[0053] Step S120: Form an insulating layer covering the surfaces of the array region and the peripheral region;

[0054] Step S130: A protective layer is formed at least on the surface of the insulating layer located in the peripheral region;

[0055] Step S140: Form a stacked film layer covering the surface of the structure jointly formed by the insulating layer and the protective layer, wherein the stacked film layer includes a first sacrificial layer, a middle support layer, a second sacrificial layer and a top support layer stacked in sequence.

[0056] Step S150: Etch the stacked film layer, the protective layer and the insulating layer to form a plurality of spaced capacitor holes, the orthogonal projection of the capacitor holes on the substrate being located in the array region;

[0057] Step S160: A lower electrode layer is formed inside the capacitor hole;

[0058] Step S170: Etch away the first sacrificial layer and the second sacrificial layer, wherein the etching rates of the first sacrificial layer and the second sacrificial layer are both greater than the etching rate of the protective layer.

[0059] The semiconductor structure formation method disclosed herein, since a protective layer is formed on the surface of the peripheral region, and the etching rates of both the first and second sacrificial layers are greater than the etching rate of the protective layer, allows the protective layer to protect the insulating layer within the peripheral region during the etching process of removing the first and second sacrificial layers. This reduces the probability of damage to the insulating layer within the peripheral region, thereby reducing the probability of damage to the circuit structure beneath the insulating layer during the etching process of the first and second sacrificial layers. This helps to reduce structural defects and improve product yield. Furthermore, during the removal of the first and second sacrificial layers, a middle support layer provides lateral support to the middle of the lower electrode layer, and a top support layer provides lateral support to the top of the lower electrode layer. This helps to reduce the probability of the lower electrode layer collapsing, further improving product yield.

[0060] The steps and specific details of the semiconductor structure formation method disclosed herein are described in detail below:

[0061] like Figure 2 As shown, in step S110, a substrate is provided, the substrate including adjacent array regions and peripheral regions.

[0062] like Figure 3 As shown, the substrate 1 can be a flat plate structure, which can be rectangular, circular, elliptical, polygonal or irregular shape, and its material can be a semiconductor material, for example, silicon, but not limited to silicon or other semiconductor materials. No special limitation is made on the shape and material of the substrate 1 here.

[0063] Please continue reading Figure 3As shown, substrate 1 may include an array region a and a peripheral region b. The array region a and the peripheral region b may be distributed adjacent to each other, and the peripheral region b may surround the outer perimeter of the array region a. For example, the array region a may be a circular region, a rectangular region, or an irregularly shaped region; of course, it may also be a region of other shapes, without special limitation here. The peripheral region b may be a ring-shaped region and may surround the outer perimeter of the array region a. It may be a circular ring region, a rectangular ring region, or a ring region of other shapes, which will not be listed here.

[0064] Array region a can be used to form capacitor arrays, transistor arrays, word line structures and bit line structures connecting transistors and capacitors, while peripheral region b can be used to form word line contact plugs. The word line contact plugs can connect to word line drivers, sense amplifiers, row decoders and column decoders, as well as special-function control circuits located in peripheral region b. The control circuits can control the word lines and bit lines to realize the storage and reading functions of transistors and capacitors. In some embodiments of this disclosure, array region a may have multiple spaced storage node contact plugs 11.

[0065] like Figure 2 As shown, in step S120, an insulating layer 2 is formed covering the surfaces of the array region a and the peripheral region b.

[0066] Please continue reading Figure 3 As shown, the insulating layer 2 can be made of insulating materials, such as silicon nitride and / or silicon oxide. The insulating layer 2 can be a single-layer structure or a composite structure composed of multiple layers; no special limitation is made here. For example, the insulating layer 2 may include a first sub-film layer and a second sub-film layer. The first sub-film layer can at least cover the surface of each control circuit in the peripheral region b; the second sub-film layer can cover the first sub-film layer and can also simultaneously cover the surface of the array region a, filling the gaps between the contact plugs 11 of each storage node. For example, the material of the first sub-film layer can be silicon oxide, and the material of the second sub-film layer can be silicon nitride. The first and second sub-film layers can be formed sequentially by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, other methods can also be used to form the first and second sub-film layers; no special limitation is made here regarding the formation method of the first and second sub-film layers.

[0067] like Figure 2 As shown, in step S130, a protective layer 3 is formed at least on the surface of the insulating layer 2 located in the peripheral region b.

[0068] The protective layer 3 can be made of an insulating material, such as carbon, silicon nitride, amorphous carbon, amorphous carbon, or diamond-like carbon. The protective layer 3 can at least cover the surface of the insulating layer 2 located in the peripheral region b, and can protect the insulating layer 2 on the surface of the peripheral region b from damage in subsequent processes.

[0069] Please refer to some embodiments of this disclosure. Figure 3 As shown, for ease of fabrication, the protective layer 3 can simultaneously cover the surface of the insulating layer 2 located in array region a. For example, the protective layer 3 can be formed on the surface of the insulating layer 2 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, other methods can also be used to form the protective layer 3, and no specific limitation is made here. The orthogonal projection of the protective layer 3 onto the substrate 1 can simultaneously cover array region a and peripheral region b.

[0070] like Figure 2 As shown, in step S140, a stacked film layer 4 is formed covering the surface of the structure jointly formed by the insulating layer 2 and the protective layer 3. The stacked film layer 4 includes a first sacrificial layer 41, a middle support layer 42, a second sacrificial layer 43 and a top support layer 44, which are stacked in sequence.

[0071] Please continue reading Figure 3 As shown, the stacked film layer 4 may include a first sacrificial layer 41, a middle support layer 42, a second sacrificial layer 43, and a top support layer 44, which are sequentially stacked along a direction perpendicular to the substrate 1; wherein: when the protective layer 3 is only located in the peripheral region b, the first sacrificial layer 41 may cover the surface of the structure jointly formed by the protective layer 3 and the insulating layer 2; when the protective layer 3 is formed on both the array region a and the peripheral region b, the first sacrificial layer 41 may cover the surface of the protective layer 3.

[0072] In some embodiments of this disclosure, the first sacrificial layer 41 and the second sacrificial layer 43 may be made of the same material; for example, both the first sacrificial layer 41 and the second sacrificial layer 43 may be made of silicon oxide. The middle support layer 42 and the top support layer 44 may be made of the same material, and / or the middle support layer 42 and the protective layer 3 may be made of the same material. For example, the middle support layer 42, the top support layer 44, and the protective layer 3 may all be made of silicon nitride.

[0073] In some other embodiments of this disclosure, the material of the central support layer 42 is different from that of the protective layer 3, and the material of the central support layer 42 is the same as that of the insulating layer 2. For example, the materials of the central support layer 42 and the insulating layer 2 are both silicon nitride, and the material of the protective layer 3 is carbon, amorphous carbon, amorphous carbon or diamond-like carbon.

[0074] For example, a first sacrificial layer 41, a middle support layer 42, a second sacrificial layer 43, and a top support layer 44 can be sequentially formed on the surface of the structure jointly formed by the insulating layer 2 and the protective layer 3 by means of chemical phase deposition, physical vapor deposition, or atomic layer deposition. Of course, the first sacrificial layer 41, the middle support layer 42, the second sacrificial layer 43, and the top support layer 44 can also be formed by other means. No special limitation is made here on the formation method of the first sacrificial layer 41, the middle support layer 42, the second sacrificial layer 43, and the top support layer 44.

[0075] like Figure 2 As shown, in step S150, the stacked film layer 4, the protective layer 3 and the insulating layer 2 are etched to form a plurality of spaced capacitor holes 101, the orthogonal projection of the capacitor holes 101 on the substrate 1 being located in the array region a.

[0076] Please continue reading Figure 3 As shown, a first mask layer 6 can be formed on the surface of the stacked film layer 4. The first mask layer 6 can be a single-layer film structure or a composite film structure formed by multiple film layers, without special limitation. For example, the first mask layer 6 can be a composite film structure composed of multiple film layers, such as a polysilicon layer 61 and a silicon oxide layer 62 located on top of the polysilicon layer 61. The first mask layer 6 can be etched to form a plurality of spaced first mask patterns 601 within the first mask layer 6. The orthogonal projection of the first mask patterns 601 on the substrate 1 is located within the array region a and can expose the surface of the stacked film layer 4 (e.g., the top support layer 44), that is, the first mask patterns 601 can be through-holes penetrating the first mask layer 6. In the direction parallel to the substrate 1, the cross-section of the first mask pattern 601 can be circular, elliptical, rectangular, polygonal, or irregular, without special limitation. It should be noted that during the etching process to form the first mask pattern 601, the cross-sectional area of ​​the first mask pattern 601 near the peripheral area b may be relatively small due to the influence of the manufacturing process.

[0077] like Figure 4As shown, a first mask layer 6 with a first mask pattern 601 can be used as a mask to etch the stacked film layer 4, protective layer 3, and insulating layer 2 to form a plurality of spaced capacitor holes 101. The number of capacitor holes 101 is equal to the number of storage node contact plugs 11, and each capacitor hole 101 can expose each storage node contact plug 11 in a corresponding manner. It should be noted that when the surface of the insulating layer 2 of the array region a does not have a protective layer 3, the capacitor holes 101 can pass through the top support layer 44, the second sacrificial layer 43, the middle support layer 42, the first sacrificial layer 41, and the insulating layer 2 covering the surface of the storage node contact plug 11, thereby exposing the storage node contact plug 11; when the surface of the insulating layer 2 of the array region a has a protective layer 3, the capacitor holes 101 can pass through the top support layer 44, the second sacrificial layer 43, the middle support layer 42, the first sacrificial layer 41, the protective layer 3, and the insulating layer 2 covering the surface of the storage node contact plug 11, thereby exposing the storage node contact plug 11.

[0078] It should be noted that, as Figure 5 As shown, since the cross-sectional area of ​​the first mask pattern 601 near the peripheral region b in the first mask layer 6 is relatively small, the cross-sectional area of ​​the capacitor hole 101 near the peripheral region b in the capacitor hole 101 formed by using it as a mask is relatively small, that is, the aperture of the capacitor hole 101 near the peripheral region b is relatively small.

[0079] In some embodiments of this disclosure, such as Figure 6 As shown, after the capacitor hole 101 is formed, the first mask layer 6 can be removed by etching or other means, thereby exposing the surface of the top support layer 44; after removing the first mask layer 6, the surface of the top support layer 44 can be cleaned to reduce residue.

[0080] like Figure 2 As shown, in step S160, a lower electrode layer 51 is formed within the capacitor hole 101.

[0081] A conformal lower electrode layer 51 covering the capacitor hole 101 can be formed within the capacitor hole 101 by methods such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The lower electrode layer 51 can be contacted and connected to the storage node contact plug 11 at the bottom of the capacitor hole 101, so as to input the charge stored in the lower electrode layer 51 to the storage node contact plug 11, thereby realizing charge storage. In some embodiments of this disclosure, the material of the lower electrode layer 51 can be a material with good conductivity, for example, titanium nitride. Of course, other materials that can be used as electrodes can also be used, and the material of the lower electrode layer 51 is not specifically limited here. For example, for ease of fabrication, a lower electrode layer 51 can be deposited on the surface of the top support layer 44. In this case, the lower electrode layer 51 can cover the surface of the top support layer 44 and conformally cover the inner wall of each capacitor hole 101. Subsequently, the lower electrode layer 51 can be etched back or polished to disconnect the lower electrode layers 51 in different capacitor holes 101 from each other and make the ends of the lower electrode layers 51 in each capacitor hole 101 flush with the surface of the top support layer 44 away from the substrate 1.

[0082] It should be noted that during the formation of the lower electrode layer 51, because the aperture of the capacitor holes 101 near the peripheral region b is relatively small, the capacitor holes 101 with smaller apertures are easily insufficiently cleaned during the cleaning of the top support layer 44, and residual particles 510 are inevitable on their tops. During the deposition of the lower electrode layer 51, these capacitor holes 101 are prone to premature sealing, and the lower electrode layer 51 cannot be deposited inside them. In this embodiment of the present disclosure, the structure after completing step S160 is as follows: Figure 7 As shown.

[0083] like Figure 2 As shown, in step S170, the first sacrificial layer 41 and the second sacrificial layer 43 are etched away, and the etching rates of the first sacrificial layer 41 and the second sacrificial layer 43 are both greater than the etching rate of the protective layer 3.

[0084] After forming the lower electrode layer 51, the first sacrificial layer 41 and the second sacrificial layer 43 can be removed to facilitate the formation of a double-sided capacitor. For example, the first sacrificial layer 41 and the second sacrificial layer 43 can be etched separately using a wet etching process to remove them. During this process, the etching rate ratio of the first sacrificial layer 41 and the second sacrificial layer 43 to the protective layer 3 is 1:0.3, resulting in minimal consumption or damage to the protective layer 3 during the etching of the first sacrificial layer 41 and the second sacrificial layer 43. In this embodiment, the structure after step S170 is as follows... Figure 8 As shown.

[0085] For example, when both the first sacrificial layer 41 and the second sacrificial layer 43 are made of silicon oxide, hydrofluoric acid or ammonium fluoride solution can be used to wet-etch the first sacrificial layer 41 and the second sacrificial layer 43. During this process, the etching solution may penetrate to the surface of the peripheral region b through the capacitor hole 101 not covered by the lower electrode layer 51. At this time, the insulating layer 2 in the peripheral region b can be protected by the protective layer 3, which can reduce the probability of the insulating layer 2 in the peripheral region b being damaged by the etching solution, thereby reducing the probability of damaging the circuit structure below the insulating layer 2 during the etching of the first sacrificial layer 41 and the second sacrificial layer 43, helping to reduce structural defects and thus improve product yield.

[0086] In one exemplary embodiment of this disclosure, etching away the first sacrificial layer 41 and the second sacrificial layer 43 may include steps S210-S240, wherein:

[0087] Step S210: A first opening 441 is formed in the top support layer 44 to expose the second sacrificial layer 43.

[0088] After the lower electrode layer 51 is formed, a second mask layer 7 can be formed on the surface of the top support layer 44 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The second mask layer 7 can be a single-layer structure or a composite film structure composed of multiple layers. Its material can be at least one of polymer, carbon, silicon oxide, silicon nitride, polycrystalline silicon, and silicon oxynitride. Of course, other materials can also be used, which will not be listed here. In some embodiments, the second mask layer 7 can be multilayered, which may include a silicon nitride layer 71 and a hard mask layer 72. The silicon nitride layer 71 can be formed on the surface of the top support layer 44, and the hard mask layer 72 can be located on the surface of the silicon nitride layer 71 away from the top support layer 44.

[0089] A photoresist layer can be formed on the surface of the second mask layer 7 by spin coating or other methods. The photoresist layer can be made of photoresist. The photoresist layer can be exposed and developed to form multiple spaced-apart development areas. The orthographic projection of the development areas on the substrate 1 is located in the array area a, and the orthographic projection of the development areas on the substrate 1 at least partially overlaps with the orthographic projection of the top support layer 44 on the substrate 1. The second mask layer 7 can be etched in the development areas to form multiple spaced-apart second mask patterns 701.

[0090] The second mask layer 7, which may have a second mask pattern 701, can be used as a mask to perform dry etching on the top support layer 44, thereby forming a plurality of first openings 441 exposing the second sacrificial layer 43. For example, the top support layer 44 can be dry etched to form a plurality of spaced-apart first openings 441 within the top support layer 44. In the direction parallel to the substrate 1, the shape of the first opening 441 may be circular, elliptical, rectangular, polygonal, or irregular; no particular limitation is made to the shape of the first opening 441 here. In the embodiments of this disclosure, the structure after step S210 is as follows: Figure 9 As shown.

[0091] Step S220: Remove the second sacrificial layer 43 through the first opening 441 to expose the surface of the central support layer 42.

[0092] like Figure 10 As shown, the second sacrificial layer 43 can be wet-etched through the first opening 441 to remove it. During the etching of the second sacrificial layer 43, the etching solution may penetrate into the peripheral region b through the capacitor hole 101 that is not filled by the lower electrode layer 51 near the peripheral region b. During this process, since the surface of the peripheral region b is covered with a protective layer 3, and the etching rate of the protective layer 3 is less than that of the second sacrificial layer 43, the etching solution consumes the protective layer 3 more slowly. The protective layer 3 can protect the insulating layer 2 below it from damage, and the circuit structure below the insulating layer 2 will not be damaged by the etching solution, which helps to improve the product yield.

[0093] Step S230: Etch the central support layer 42 to form a second opening 421 exposing the first sacrificial layer 41, wherein the etching rate of the central support layer 42 is greater than or equal to the etching rate of the protective layer 3.

[0094] Please continue reading Figure 10 As shown, after removing the second sacrificial layer 43, the exposed central support layer 42 can be etched to form a second opening 421 exposing the first sacrificial layer 41. For example, the central support layer 42 can be dry-etched to form a plurality of second openings 421 penetrating the central support layer 42, wherein the orthographic projection of the second opening 421 on the substrate 1 at least partially coincides with the orthographic projection of the first opening 441 on the substrate 1. In the direction parallel to the substrate 1, the shape of the second opening 421 can be circular, elliptical, rectangular, polygonal, or irregular; no specific limitation is made here on the specific shape of the second opening 421.

[0095] In some embodiments of this disclosure, the material of the protective layer 3 is the same as that of the central support layer 42, and the thickness of the protective layer 3 may be greater than that of the central support layer 42. During the dry etching of the central support layer 42, even if the etching gas diffuses to the peripheral region b, thereby consuming or damaging part of the film structure on the peripheral region b, the consumed or damaged part is the protective layer 3 on the surface of the peripheral region b. Provided that the protective layer 3 is not completely consumed, the insulating layer 2 and the circuit structure below the protective layer 3 will not be damaged.

[0096] Step S240: Remove the first sacrificial layer 41 through the second opening 421.

[0097] Please continue reading Figure 8 As shown, the first sacrificial layer 41 can be wet-etched through the second opening 421 to remove it. During the etching process of removing the first sacrificial layer 41, the etching solution may also penetrate into the peripheral region b through the capacitor hole 101 that is not filled by the lower electrode layer 51 near the peripheral region b. During this process, the insulating layer 2 below it can still be protected from damage by the protective layer 3, and the circuit structure below the insulating layer 2 will not be damaged by the etching solution, which helps to improve the product yield.

[0098] In one exemplary embodiment of this disclosure, the method for forming the semiconductor structure of this disclosure may further include:

[0099] Step S180: After removing the first sacrificial layer 41 and the second sacrificial layer 43, the protective layer 3 located in the peripheral area b is removed.

[0100] After removing the first sacrificial layer 41, the protective layer 3 located in the peripheral region b can be removed, thereby exposing the surface of the insulating layer 2 in the peripheral region b, so as to facilitate the subsequent formation of word line contact plugs penetrating the insulating layer 2 on the peripheral region b. For example, the protective layer 3 located in the peripheral region b can be removed by a dry etching process. The etching gas for dry etching can be set according to the specific material of the protective layer 3, as long as the protective layer 3 can be removed without damaging (or with minimal damage) other surrounding structures. In the embodiments of this disclosure, the structure after completing step S180 is as follows: Figure 11 As shown.

[0101] It should be noted that when a protective layer 3 is also formed on array region a, the protective layer 3 on array region a can be retained. The remaining protective layer 3 and insulating layer 2 on array region a can serve as the bottom support layer of the lower electrode layer 51. The bottom of the lower electrode layer 51 can be supported by the remaining protective layer 3 and insulating layer 2 on array region a, which helps to further reduce the probability of the lower electrode layer 51 collapsing and improve product yield.

[0102] In an exemplary embodiment of this disclosure, the method for forming the semiconductor structure may further include steps S190 and S200, wherein:

[0103] In step S190, a capacitor dielectric layer 52 is formed on the surface of the structure jointly formed by the lower electrode layer 51, the insulating layer 2, the middle support layer 42 located in the array region a, and the top support layer 44 located in the array region a.

[0104] After removing the protective layer 3, a conformally shaped capacitor dielectric layer 52 is formed on the surface of the structure consisting of the lower electrode layer 51, the bottom support layer, the remaining middle support layer 42, and the remaining top support layer 44 using chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The capacitor dielectric layer 52 can be a single-layer film structure made of the same material, or a mixed-layer film structure made of different materials. For example, it may include materials with a high dielectric constant, such as alumina, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, tantalum oxide, niobium oxide, strontium oxide, or mixtures thereof. Other materials are also possible, but will not be listed here. The structure after step S190 in this embodiment is as follows: Figure 12 As shown.

[0105] In step S200, an upper electrode layer 53 is formed on the surface of the capacitor dielectric layer 52.

[0106] The upper electrode layer 53 can be formed on the surface of the capacitor dielectric layer 52 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, other processes can also be used to form the upper electrode layer 53, and no specific limitations are made here. The material of the upper electrode layer 53 can be titanium nitride, or other materials, which will not be listed here. The lower electrode layer 51, the capacitor dielectric layer 52, and the upper electrode layer 53 together constitute the capacitor structure 5. In this embodiment, the structure after step S200 is as follows: Figure 13 As shown.

[0107] It should be noted that although the steps of the semiconductor structure formation method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0108] This disclosure also provides a semiconductor structure that can be formed by the semiconductor structure formation method in any of the above embodiments.

[0109] The specific details and manufacturing processes of each part of the above semiconductor structure have been described in detail in the corresponding semiconductor structure formation methods, so they will not be repeated here.

[0110] For example, the semiconductor structure can be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. Of course, it can also be other storage devices, which will not be listed here.

[0111] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising an array region and a peripheral region distributed adjacent to each other; An insulating layer is formed covering the surfaces of the array region and the peripheral region; A protective layer is formed at least on the surface of the insulating layer located in the peripheral region; A stacked film layer is formed to cover the surface of the structure jointly constituted by the insulating layer and the protective layer, the stacked film layer comprising a first sacrificial layer, a middle support layer, a second sacrificial layer and a top support layer stacked in sequence; The stacked film layer, the protective layer, and the insulating layer are etched to form a plurality of spaced capacitor holes, the orthogonal projection of the capacitor holes on the substrate being located in the array region; A lower electrode layer is formed within the capacitor hole; The first sacrificial layer and the second sacrificial layer are removed by etching, and the etching rates of the first sacrificial layer and the second sacrificial layer are both greater than the etching rate of the protective layer.

2. The forming method according to claim 1, characterized in that, The etch rate ratio of the first sacrificial layer and the second sacrificial layer to the protective layer is 1:0.

3.

3. The forming method according to claim 1, characterized in that, The etching process removes the first sacrificial layer and the second sacrificial layer, including: A first opening is formed within the top support layer to expose the second sacrificial layer; The second sacrificial layer is removed through the first opening to expose the surface of the central support layer; The central support layer is etched to form a second opening exposing the first sacrificial layer, wherein the etch rate of the central support layer is greater than or equal to the etch rate of the protective layer; The first sacrificial layer is removed through the second opening.

4. The forming method according to claim 3, characterized in that, The middle support layer is made of a different material than the protective layer, and the middle support layer is made of the same material as the insulating layer.

5. The forming method according to claim 4, characterized in that, The first sacrificial layer and the second sacrificial layer are both made of silicon oxide, the middle support layer is made of silicon nitride, and the protective layer is made of carbon, amorphous carbon, amorphous carbon, or diamond-like carbon.

6. The forming method according to claim 1, characterized in that, The middle support layer is made of the same material as the protective layer.

7. The forming method according to claim 6, characterized in that, Both the central support layer and the protective layer are made of silicon nitride.

8. The forming method according to any one of claims 1-7, characterized in that, The forming method further includes: After removing the first sacrificial layer and the second sacrificial layer, the protective layer located in the peripheral area is removed.

9. The forming method according to claim 8, characterized in that, The forming method further includes: A capacitor dielectric layer is formed on the surface of the structure jointly formed by the lower electrode layer, the insulating layer, the middle support layer located in the array region, and the top support layer located in the array region; An upper electrode layer is formed on the surface of the capacitor dielectric layer.

10. A semiconductor structure, characterized in that, The semiconductor structure is formed by the method for forming the semiconductor structure according to any one of claims 1-9.

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