Method of manufacturing charge-trapping non-volatile memory device

Abstract

A manufacturing method of a charge-trapping nonvolatile memory device is disclosed. In the process of manufacturing the nonvolatile memory device, a barrier layer of a storage element can be effectively protected from contamination or thinning. In addition, in the semiconductor substrate, since a well region of a logic element region and a well region of a memory element region are not simultaneously manufactured, a nonvolatile memory cell having a small size can be designed in the memory element region, and a threshold voltage of a charge-trapping transistor can be accurately controlled.

Description

Technical Field

[0001] This invention relates to a method for manufacturing a nonvolatile memory apparatus, and more particularly to a method for manufacturing a charge-trapping nonvolatile memory apparatus. Background Technology

[0002] As is well known, non-volatile memory devices can retain data even after power is lost, and therefore are widely used in electronic products. Generally, a non-volatile memory device includes peripheral circuitry and a memory cell array, both fabricated on the same semiconductor substrate. For example, the peripheral circuitry includes bitline drivers, word line drivers, source line drivers, and control units, etc. The memory cell array consists of multiple non-volatile memory cells.

[0003] When manufacturing non-volatile memory devices, designers divide the layout area of ​​a semiconductor substrate into a logic device area and a memory device area. Components manufactured in the logic device area can form the peripheral circuitry of the non-volatile memory device, while components manufactured in the memory device area can form a memory cell array.

[0004] Furthermore, the elements in the logic element area can be further divided into input / output devices (IO devices) and core devices. The elements in the memory element area can be further divided into switching devices and storage devices, and each non-volatile memory cell includes both switching devices and storage devices.

[0005] In addition, core components can be called low-voltage devices (LV devices), such as low-voltage P-type transistors (LV P-type transistors) and low-voltage N-type transistors (LV N-type transistors). Input / output components can be called high-voltage devices (HV devices), such as high-voltage P-type transistors (HVP-type transistors) and high-voltage N-type transistors (HV N-type transistors). Low-voltage devices can withstand lower voltage stress, while high-voltage devices can withstand higher voltage stress.

[0006] Because the aforementioned I / O components, core components, switching components, and memory components all have different circuit structures, integrating the peripheral circuitry with the memory cell array onto the same semiconductor substrate is a challenging task. Summary of the Invention

[0007] This invention relates to a method for manufacturing a charge-capturing non-volatile memory device, comprising the following steps: (A) forming a pad oxide layer on a surface of a semiconductor substrate, and forming a plurality of isolation structures within the semiconductor substrate; wherein the isolation structures divide the semiconductor substrate into a memory element region and a logic element region, and further divide the logic element region into an input / output element region and a core element region; (B) forming a first photoresist layer covering the logic element region, and forming a first photoresist layer on the semiconductor substrate within the memory element region. (C) A first type-1 well region is formed below the surface; (D) The first photoresist layer and at least a portion of the pad oxide layer are removed, and a stacked layer is formed covering the logic element region and the memory element region; wherein the stacked layer includes a bottom oxide layer, a trapping layer, a barrier layer and a protective layer; (E) A second photoresist layer is formed covering a portion of the stacked layer in the memory element region, and the protective layer, the barrier layer and the trapping layer not covered by the second photoresist layer are removed; (I) The second photoresist layer is removed. (F) A second first-type well region, a first second-type well region, and a first deep first-type well region are formed under the semiconductor substrate of the core element region, and a third first-type well region, a second second-type well region, and a second deep first-type well region are formed under the semiconductor substrate of the input / output element region, wherein the first second-type well region is located within the first deep first-type well region, and the second second-type well region is located within the second deep first-type well region; (G) The third photoresist layer is removed, and a portion of the bottom oxide layer not covered by the protective layer is removed; (H) The protective layer on the stacked layer is removed, and an input / output gate oxide layer is formed on the semiconductor substrate of the memory element region, the input / output gate oxide layer is formed on the semiconductor substrate of the input / output element region, and a core gate oxide layer is formed on the semiconductor substrate of the core element region; (I) A gate layer is formed, covering the memory element region and the logic element region; and (J) A plurality of gate structures are formed and a plurality of doped regions are formed. Furthermore, a first gate structure is located on the first first-type well region, and a first second-type doped region and a second second-type doped region are formed in the first first-type well regions on both sides of the first gate structure; and a second gate structure is located on the first first-type well region, and a second second-type doped region and a third second-type doped region are formed in the first first-type well regions on both sides of the second gate structure. Furthermore, a third gate structure is formed on the second first-type well region, and a fourth second-type doped region and a fifth second-type doped region form both sides of the third gate structure and are located in the second first-type well region; and a fourth gate structure is formed on the first second-type well region, and a first first-type doped region and a second first-type doped region form both sides of the fourth gate structure and are located in the first second-type well region.Furthermore, a fifth gate structure is formed on the third first type well region, a sixth second type doped region and a seventh second type doped region form both sides of the fifth gate structure and are located within the third first type well region; and a sixth gate structure is formed on the second second type well region, a third first type doped region and a fourth first type doped region form both sides of the sixth gate structure and are located within the second second type well region.

[0008] To provide a better understanding of the above and other aspects of the present invention, preferred embodiments are described below in detail with reference to the accompanying drawings: Attached Figure Description

[0009] Figures 1A to 1I This is a flowchart illustrating the manufacturing method of a charge-capturing non-volatile memory device according to the first embodiment of the present invention.

[0010] Figures 2A to 2L This is a flowchart illustrating the manufacturing method of a charge-capturing non-volatile memory device according to a second embodiment of the present invention.

[0011] Figures 3A to 3C A schematic diagram illustrating an example of a process sequence swap for the second embodiment;

[0012] Figures 4A to 4C A schematic diagram illustrating another example of the process sequence exchange for the second embodiment;

[0013] Figures 5A to 5F This is a flowchart illustrating the manufacturing method of a charge-capturing non-volatile memory device according to a third embodiment of the present invention.

[0014] Figures 6A to 6L A flowchart illustrating the manufacturing method of a charge-capturing non-volatile memory device according to a fourth embodiment of the present invention; and

[0015] Figures 7A to 7F This is a flowchart illustrating the manufacturing method of a charge-capturing non-volatile memory device according to the fifth embodiment of the present invention.

[0016] Symbol Explanation

[0017] 102,103,104,105,106,107,202,203,204,205,206,207,502,503,504,505,506,507,602,603,604,605,606,607,702,703,704,705,706,707: Isolation Structure

[0018] 110, 210, 510, 610, 710: Pad oxide layer

[0019] 111,211,511,611,711: Bottom oxide layer

[0020] 112,212,512,612,712: Capture Layer

[0021] 113,213,513,613,713: Barrier layer

[0022] 117,122,132,209,217,218,222,512,517,518,612,617,618,622,632,712,717,718: Photoresist layer

[0023] 120, 220, 620: Input and output gate oxide layers

[0024] 124,224,624: Core gate oxide layer

[0025] 130, 230, 630: Gate layer

[0026] 136,236,636: Spacer wall

[0027] 141,142,143,144,147,241,242,243,244,247,641,642,643,644,647: p-doped regions

[0028] 145, 148, 245, 248, 645, 648: n-doped regions

[0029] 151,152,154,155,157,158,251,252,254,255,257,258,651,652,654,655,657,658: Gate structure

[0030] 214, 514, 614, 714: Protective layer Detailed Implementation

[0031] This invention discloses a method for manufacturing a non-volatile memory device, which can simultaneously fabricate a core device, an I / O device, a switching device, and a storage device on a semiconductor substrate.

[0032] In other words, using the manufacturing process disclosed in this invention, all components required for peripheral circuits and memory cell arrays can be fabricated on a semiconductor substrate to form a non-volatile memory device. Furthermore, the non-volatile memory cell manufactured by this invention is a charge-trapping non-volatile memory cell. Therefore, the non-volatile memory device completed by the manufacturing method disclosed in this invention is a charge-trapping non-volatile memory device.

[0033] Please refer to Figures 1A to 1I The diagram shown is a flowchart of a method for manufacturing a charge-capturing non-volatile memory device according to a first embodiment of the present invention.

[0034] like Figure 1A As shown, an isolation structure formation process is performed. First, a pad oxide layer 110 is formed on the surface of a semiconductor substrate Psub, and multiple isolation structures 102 to 107 are formed within the semiconductor substrate Psub. The semiconductor substrate Psub is a P-type substrate, and the isolation structures 102 to 107 are shallow trench isolation structures (STI structures).

[0035] For example, during the fabrication process of forming the isolation structure, a pad oxide layer 110 and a pad silicon nitride layer (not shown) are sequentially formed on the surface of the semiconductor substrate Psub. Next, after forming the isolation structures 102 to 107 in the semiconductor substrate Psub, an etching process is performed to remove the pad silicon nitride layer (not shown), leaving only the pad oxide layer 110 on the surface of the semiconductor substrate Psub.

[0036] like Figure 1A As shown, on the surface of the semiconductor substrate Psub, the area between isolation structure 102 and isolation structure 106 is a logic device area, and the area between isolation structure 106 and isolation structure 107 is a memory device area. Components fabricated in the logic device area can form the peripheral circuitry of a non-volatile memory device. Components fabricated in the memory device area can form a memory cell array of a non-volatile memory device. In other words, non-volatile memory cells composed of switching elements and storage elements are fabricated in the memory device area.

[0037] Furthermore, the logic element area can be further divided into an input / output element area and a core element area. For example... Figure 1A As shown, the area between isolation structure 102 and isolation structure 104 is the input / output device area, and the area between isolation structure 104 and isolation structure 106 is the core device area. The input / output devices include high-voltage metal-oxide-semiconductor half-p-type transistors (HV P-type transistors) and high-voltage N-type transistors (HV N-type transistors). The core device includes low-voltage metal-oxide-semiconductor half-p-type transistors (LV P-type transistors) and low-voltage N-type transistors (LV N-type transistors).

[0038] According to an embodiment of the present invention, a high-voltage N-type transistor (HV N-type transistor) is fabricated between isolation structure 102 and isolation structure 103. A high-voltage P-type transistor (HV P-type transistor) is fabricated between isolation structure 103 and isolation structure 104. A low-voltage N-type transistor (LV N-type transistor) is fabricated between isolation structure 104 and isolation structure 105. A low-voltage P-type transistor (LV P-type transistor) is fabricated between isolation structure 105 and isolation structure 106.

[0039] like Figure 1B As shown, a multi-stage ion implantation process is performed to form an N-well NW1 beneath the surface of the semiconductor substrate Psub in the memory element region, and N-wells NW2 and NW3, P-wells PW1 and PW2, and deep N-wells DNW1 and DNW2 beneath the surface of the semiconductor substrate Psub in the logic element region. Following this, an etching process is performed to remove the pad oxide layer 110.

[0040] like Figure 1BAs shown, an N-type well region NW1 is formed below the surface of the semiconductor substrate Psub between isolation structures 106 and 107. An N-type well region NW2 is formed below the surface of the semiconductor substrate Psub between isolation structures 105 and 106. A P-type well region PW1 and a deep N-type well region DNW1 are formed below the surface of the semiconductor substrate Psub between isolation structures 104 and 105, with the P-type well region PW1 located within the deep N-type well region DNW1. An N-type well region NW3 is formed below the surface of the semiconductor substrate Psub between isolation structures 103 and 104. A P-type well region PW2 and a deep N-type well region DNW2 are formed below the surface of the semiconductor substrate Psub between isolation structures 102 and 103, with the P-type well region PW2 located within the deep N-type well region DNW2.

[0041] like Figure 1C As shown, a stack layer is formed on the surface of a semiconductor substrate Psub. The stack layer includes a bottom oxide layer 111, a trapping layer 112, and a blocking layer 113. Then, a photoresist layer 117 is formed within the memory element region, covering a portion of the stack layer. For example, the trapping layer 112 may be made of silicon nitride, and the bottom oxide layer 111 and the blocking layer 113 may be made of silicon dioxide.

[0042] like Figure 1D As shown, an etching process is performed to remove the bottom oxide layer 111, the trapping layer 112, and the blocking layer 113 that are not covered by the photoresist layer 117. Next, the photoresist layer 117 is removed, and an input / output gate oxide layer (IO gate oxide layer) 120 is formed on the exposed semiconductor substrate Psub surface.

[0043] like Figure 1E As shown, a photoresist layer 122 is formed to cover the memory element region and the input / output element region. Next, an etching process is performed to remove the input / output gate oxide layer 120 on the surface of the semiconductor substrate Psub in the core element region.

[0044] like Figure 1F As shown, the photoresist layer 122 is removed, and a core gate oxide layer 124 is formed on the surface of the semiconductor substrate Psub in the core element region. The thickness of the core gate oxide layer 124 is less than the thickness of the input / output gate oxide layer 120.

[0045] Next, the gate structure formation process and the doping process are performed. These processes are compatible with CMOS fabrication processes, and will be briefly described below.

[0046] like Figure 1G As shown, a gate layer 130 is formed, covering the logic element region and the memory element region. That is, the gate layer 130 covers the input / output gate oxide layer 120, the core gate oxide layer 124, and the barrier layer 113. Next, a photoresist layer 132 is formed on the gate layer 130. For example, the material of the gate layer can be polysilicon.

[0047] like Figure 1H As shown, an etching process is performed to remove the gate layer 130, input / output gate oxide layer 120, core gate oxide layer 124, bottom oxide layer 111, trapping layer 112, and barrier layer 113 that are not covered by the photoresist layer 132. Next, the photoresist layer 132 is removed.

[0048] After that, as Figure 1I As shown, in the input / output device region, a spacer wall 136 is formed on the sidewall of the input / output gate oxide layer 120 and the gate layer 130. Therefore, the input / output gate oxide layer 120, the gate layer 130 and the spacer wall 136 can become the gate structures 157 and 158 of the input / output device (IO device).

[0049] Similarly, in the core device region, a spacer wall 136 is formed on the sidewalls of the core gate oxide layer 124 and the gate layer 130, so the core gate oxide layer 124, the gate layer 130 and the spacer wall 136 can become the gate structures 154 and 155 of the core device.

[0050] Similarly, in the memory element region, spacer walls 136 are formed on the sidewalls of the input / output gate oxide layer 120 and the gate layer 130, and spacer walls 136 are also formed on the sidewalls of the bottom oxide layer 111, the trap layer 112, the barrier layer 113, and the gate layer 130. Therefore, the input / output gate oxide layer 120, the gate layer 130, and the spacer walls 136 can form the gate structure 152 of a switching device, and the bottom oxide layer 111, the trap layer 112, the barrier layer 113, the gate layer 130, and the spacer walls 136 can form the gate structure 151 of a storage device.

[0051] Furthermore, after the doping fabrication process, in the input / output device region, the gate structure 158 is formed on the P-type well region PW2, and two n-doped regions 148 are formed in the P-type well regions PW2 on both sides of the gate structure 158. Therefore, the P-type well region PW2, the two n-doped regions 148, and the gate structure 158 form a high-voltage N-type transistor M. N_HV Furthermore, the gate structure 157 is formed on the N-type well region NW3, and two p-doped regions 147 are formed within the N-type well regions NW3 on both sides of the gate structure 157. Therefore, the N-type well region NW3, the two p-doped regions 147, and the gate structure 157 form a high-voltage P-type transistor M. P_HV .

[0052] In the core component region, the gate structure 155 is formed on the P-type well region PW1, and two n-doped regions 145 are formed in the P-type well regions PW1 on both sides of the gate structure 155. Therefore, the P-type well region PW1, the two n-doped regions 145, and the gate structure 155 form a low-voltage N-type transistor M. N_LV Furthermore, the gate structure 154 is formed on the N-type well region NW2, and two p-doped regions 144 are formed in the N-type well regions NW2 on both sides of the gate structure 154. Therefore, the N-type well region NW2, the two p-doped regions 144, and the gate structure 154 form a low-voltage P-type transistor M. P_LV .

[0053] In the memory element region, a gate structure 152 is formed on an N-type well region NW1, and two p-doped regions 142 and 143 are formed in the N-type well regions NW1 on both sides of the gate structure 152. Therefore, the N-type well region NW1, the two p-doped regions 142 and 143, and the gate structure 152 form a switching element M. P_SW Furthermore, the gate structure 151 is formed on the N-type well region NW1, and two p-doped regions 141 and 142 are formed in the N-type well regions NW1 on both sides of the gate structure 151. Therefore, the N-type well region NW1, the two p-doped regions 141 and 142, and the gate structure 151 form the memory element M. P_STORAGE .

[0054] Of course, the doping fabrication process described above may also include: a lightly doped drain region fabrication process (LDD process) and / or a halo implantation process, etc. That is, the doped regions 141-148 may selectively include a lightly doped drain region (LDD region) and / or a halo region. In other embodiments, the positions of the two gate structures 151 and 152 of the memory element region can also be interchanged. For example, the gate structure 151 of the memory element is located between the two p-doped regions 142 and 143, and the gate structure 152 of the switching element is located between the two p-doped regions 141 and 142.

[0055] Furthermore, in the subsequent line-conducting process, core components within the logic element area (e.g., low-voltage P-type transistors) can be connected. P_LV With low-voltage N-type transistor M N_LV ) and input / output components (e.g., high-voltage P-type transistor M) P_HV With high voltage N-type transistor M N_HV This can be used to form peripheral circuits. Simultaneously, it can also connect to the switching elements M within the memory element area. P_SW With storage element M P_STORAGE These are used to form a memory cell array. Combining peripheral circuitry with the memory cell array creates the non-volatile memory device of this invention.

[0056] According to a first embodiment of the present invention, the storage element M P_STORAGE The gate structure 151 includes a bottom oxide layer 111, a trapping layer 112, and a blocking layer 113. The bottom oxide layer 111 and the blocking layer 113 can be made of silicon dioxide, and the trapping layer 112 can be made of silicon nitride. Therefore, the gate structure 151 is an (oxide / nitride / oxide, abbreviated as ONO) gate structure, and the memory element M... P_STORAGE This is a charge-trapping transistor with an ONO gate structure. In other words, it combines the switching element M. P_SW With storage element M P_STORAGE This can form a charge-capture non-volatile memory cell, and the non-volatile memory device of the present invention is a charge-capture non-volatile memory device.

[0057] However, the manufacturing method of the first embodiment still has some minor drawbacks. For example, during the manufacturing process of the non-volatile memory device of the first embodiment, the characteristics of the charge-capturing non-volatile memory cell may be compromised. This will be explained below.

[0058] Because of the storage element M in the memory element area P_STORAGE The gate structure 151 is an ONO gate structure. For example... Figure 1C and Figure 1E As shown, in storage element M P_STORAGE During the manufacturing process, photoresist layers 117 and 122 are formed multiple times on the surface of the barrier layer 113. During the removal of the photoresist layers 117 and 122 and the cleaning process, the surface of the barrier layer 113 may become contaminated by particles or eroded, causing it to thin and potentially affecting the memory element M. P_STORAGE Its properties are destroyed.

[0059] In addition, such as Figure 1B As shown, since the logic element region and the memory element region undergo ion implantation processes simultaneously, three N-type well regions NW1, NW2, and NW3 are simultaneously formed beneath the Psub surface of the semiconductor substrate in both regions. Because it is not possible to perform ion implantation separately for the memory element region, this may cause issues with the memory element M... P_STORAGE In other words, the threshold voltage shift of a charge-capture transistor cannot be precisely controlled. Furthermore, because the logic element area and the memory element area are fabricated using ion implantation processes simultaneously, the size of non-volatile memory cells cannot be further reduced due to process rules.

[0060] To overcome the aforementioned shortcomings, the present invention further modifies the process of the first embodiment. For example, a protective layer is designed above the barrier layer to prevent contamination of the barrier layer or alteration of its thickness during manufacturing. Furthermore, the present invention designs different ion implantation processes to form the wells of the memory element region and the wells of the logic element region, respectively, thereby reducing the size of the non-volatile memory cell.

[0061] Please refer to Figures 2A to 2L The diagram shown is a flowchart of a method for manufacturing a charge-capturing non-volatile memory device according to a second embodiment of the present invention.

[0062] like Figure 2AAs shown, an isolation structure formation process is performed, in which a pad oxide layer 210 is formed on the surface of a semiconductor substrate Psub, and multiple isolation structures 202-207 are formed within the semiconductor substrate Psub. The semiconductor substrate Psub is a P-type substrate, and the isolation structures 202-207 are shallow trench isolation structures.

[0063] like Figure 2A As shown, on the surface of the semiconductor substrate Psub, the area between isolation structures 202 and 206 is a logic element area, and the area between isolation structures 206 and 207 is a memory element area. Furthermore, the logic element area can be further divided into an input / output element area and a core element area. For example... Figure 2A As shown, the area between isolation structure 202 and isolation structure 204 is the input / output component area, and the area between isolation structure 204 and isolation structure 206 is the core component area.

[0064] In this embodiment, a high-voltage N-type transistor (HV N-type transistor) will be fabricated between isolation structure 202 and isolation structure 203. A high-voltage P-type transistor (HV P-type transistor) will be fabricated between isolation structure 203 and isolation structure 204. A low-voltage N-type transistor (LV N-type transistor) will be fabricated between isolation structure 204 and isolation structure 205. A low-voltage P-type transistor (LV P-type transistor) will be fabricated between isolation structure 205 and isolation structure 206.

[0065] like Figure 2B As shown, a photoresist layer 209 is formed to cover the logic element region. Next, an ion implantation process is performed to form an N-type well region NW1 below the surface of the semiconductor substrate Psub in the memory element region. Afterward, an etching process is performed to remove the pad oxide layer 210 in the memory element region, while retaining the pad oxide layer 210 in the logic element region.

[0066] Next, as Figure 2C As shown, the photoresist layer 209 is first removed, and a stack layer is formed. The stack layer includes: a bottom oxide layer 211, a trapping layer 212, a blocking layer 213, and a protective layer 214. The trapping layer 212 and the protective layer 214 can be made of silicon nitride, while the bottom oxide layer 211 and the blocking layer 213 can be made of silicon dioxide.

[0067] like Figure 2CAs shown, in the memory element region, a stacked layer covers the surface of the semiconductor substrate Psub. In the logic element region, the stacked layer covers the pad oxide layer 210. That is, in the memory element region, a bottom oxide layer 211 covers the surface of the semiconductor substrate Psub, and sequentially covers a trapping layer 212, a barrier layer 213, and a protective layer 214. In the logic element region, the bottom oxide layer 211 covers the pad oxide layer 210, and sequentially covers a trapping layer 212, a barrier layer 213, and a protective layer 214.

[0068] like Figure 2D As shown, a photoresist layer 217 is formed within the memory element region, covering a portion of the stacked layers in the memory element region. Subsequently, an etching process is performed to remove the trapping layer 212, the blocking layer 213, and the protective layer 214 that are not covered by the photoresist layer 217, leaving only the bottom oxide layer 211.

[0069] like Figure 2E As shown, after removing the photoresist layer 217, a photoresist layer 218 is formed to cover the memory element region. Next, multiple ion implantation processes are performed to form N-type well regions NW2 and NW3, P-type well regions PW1 and PW2, and deep N-type well regions DNW1 and DNW2 below the surface of the semiconductor substrate Psub in the logic element region. The two P-type well regions PW1 and PW2 are located within the two deep N-type well regions DNW1 and DNW2, respectively.

[0070] like Figure 2E As shown, an N-type well region NW2 is formed below the surface of the semiconductor substrate Psub between isolation structures 205 and 206. A P-type well region PW1 and a deep N-type well region DNW1 are formed below the surface of the semiconductor substrate Psub between isolation structures 204 and 205, with the P-type well region PW1 located within the deep N-type well region DNW1. An N-type well region NW3 is formed below the surface of the semiconductor substrate Psub between isolation structures 203 and 204. A P-type well region PW2 and a deep N-type well region DNW2 are formed below the surface of the semiconductor substrate Psub between isolation structures 202 and 203, with the P-type well region PW2 located within the deep N-type well region DNW2.

[0071] In the second embodiment, the N-type well region NW1 in the memory element region is formed first, followed by the N-type well regions NW2 and NW3 in the logic element region. That is, the N-type well region NW1 in the memory element region and the NW2 and NW3 in the logic element region are not formed simultaneously. Furthermore, even if the stacked layer needs to be formed in a high-temperature environment, since the stacked layer is formed first and the N-type well regions NW2 and NW3 in the logic element region are formed later, the N-type well regions NW2 and NW3 are not affected by the high temperature.

[0072] like Figure 2F As shown, the photoresist layer 218 is removed, and an etching process is performed to remove the bottom oxide layer 211 and the pad oxide layer 210 that are not covered by the stacked layers.

[0073] like Figure 2G As shown, the protective layer 214 in the memory element area is first removed, and then an input / output gate oxide layer (IO gate oxide layer) 220 is formed on the surface of the semiconductor substrate Psub.

[0074] like Figure 2H As shown, a photoresist layer 222 is formed to cover the memory element region and the input / output element region. Next, an etching process is performed to remove the input / output gate oxide layer 220 on the surface of the semiconductor substrate Psub in the core element region.

[0075] like Figure 2I As shown, the photoresist layer 222 is removed, and a core gate oxide layer 224 is formed on the surface of the semiconductor substrate Psub in the core element region. The thickness of the core gate oxide layer 224 is less than the thickness of the input / output gate oxide layer 220.

[0076] Next, the gate structure formation process and the doping process are carried out.

[0077] like Figure 2J As shown, a gate layer 230 is formed, covering the logic element region and the memory element region. That is, the gate layer 230 covers the input / output gate oxide layer 220, the core gate oxide layer 224, and the barrier layer 213. Next, a photoresist layer 232 is formed on the gate layer 230. The material of the gate layer can be polysilicon.

[0078] like Figure 2KAs shown, an etching process is performed to remove the gate layer 230, input / output gate oxide layer 220, core gate oxide layer 224, bottom oxide layer 211, trapping layer 212, and barrier layer 213 that are not covered by the photoresist layer 232. Next, the photoresist layer 232 is removed.

[0079] like Figure 2L As shown, in the input / output device region, a spacer 236 is formed on the sidewall of the input / output gate oxide layer 220 and the gate layer 230. Therefore, the input / output gate oxide layer 220, the gate layer 230 and the spacer 236 can become the gate structures 257 and 258 of the input / output device (IO device).

[0080] Similarly, in the core device region, a spacer 236 is formed on the sidewalls of the core gate oxide layer 224 and the gate layer 230. Therefore, the core gate oxide layer 224, the gate layer 230 and the spacer 236 can become the gate structures 254 and 255 of the core device.

[0081] Similarly, in the memory element region, spacer walls 236 are formed on the sidewalls of the input / output gate oxide layer 220 and the gate layer 230, and spacer walls 236 are also formed on the sidewalls of the bottom oxide layer 211, the trap layer 212, the barrier layer 213, and the gate layer 230. Therefore, the input / output gate oxide layer 220, the gate layer 230, and the spacer walls 236 can form the gate structure 252 of a switching device, and the bottom oxide layer 211, the trap layer 212, the barrier layer 213, the gate layer 230, and the spacer walls 236 can form the gate structure 251 of a storage device.

[0082] Furthermore, after the doping fabrication process, in the input / output device region, the gate structure 258 is formed on the P-type well region PW2, and two n-doped regions 248 are formed in the P-type well regions PW2 on both sides of the gate structure 258. Therefore, the P-type well region PW2, the two n-doped regions 248, and the gate structure 258 form a high-voltage N-type transistor M. N_HV Furthermore, the gate structure 257 is formed on the N-type well region NW3, and two p-doped regions 247 are formed within the N-type well regions NW3 on both sides of the gate structure 257. Therefore, the N-type well region NW3, the two p-doped regions 247, and the gate structure 257 form a high-voltage P-type transistor M. P_HV .

[0083] In the core component region, the gate structure 255 is formed on the P-type well region PW1, and two n-doped regions 245 are formed in the P-type well regions PW1 on both sides of the gate structure 255. Therefore, the P-type well region PW1, the two n-doped regions 245, and the gate structure 255 form a low-voltage N-type transistor M. N_LV Furthermore, the gate structure 254 is formed on the N-type well region NW2, and two p-doped regions 244 are formed in the N-type well regions NW2 on both sides of the gate structure 254. Therefore, the N-type well region NW2, the two p-doped regions 244, and the gate structure 254 form a low-voltage P-type transistor M. P_LV .

[0084] In the memory element region, a gate structure 252 is formed on an N-type well region NW1, and two p-doped regions 242 and 243 are formed within the N-type well regions NW1 on both sides of the gate structure 252. Therefore, the N-type well region NW1, the two p-doped regions 242 and 243, and the gate structure 252 form a switching element M. P_SW Furthermore, the gate structure 251 is formed on the N-type well region NW1, and two p-doped regions 241 and 242 are formed in the N-type well regions NW1 on both sides of the gate structure 251. Therefore, the N-type well region NW1, the two p-doped regions 241 and 242, and the gate structure 251 form the memory element M. P_STORAGE .

[0085] Of course, the doping fabrication process described above may also include a lightly doped drain region fabrication process (LDD process) and / or a halo implantation process, etc. That is to say, doped regions 241 to 248 may selectively include a lightly doped drain region (LDD region) and / or a halo region.

[0086] Furthermore, in the subsequent line-conducting process, core components within the logic element area (e.g., low-voltage P-type transistors) can be connected. P_LV With low-voltage N-type transistor M N_LV ) and input / output components (e.g., high-voltage P-type transistor M) P_HV With high voltage N-type transistor M N_HV This can be used to form peripheral circuits. Simultaneously, it can also connect to the switching elements M within the memory element area. P_SW With storage element M P_STORAGE These are used to form a memory cell array. Combining peripheral circuitry with the memory cell array creates the non-volatile memory device of this invention.

[0087] According to a second embodiment of the present invention, the storage element MP_STORAGE The gate structure 251 includes a bottom oxide layer 211, a trapping layer 212, and a blocking layer 213. The bottom oxide layer 211 and the blocking layer 213 can be made of silicon dioxide, and the trapping layer 212 can be made of silicon nitride. Therefore, the gate structure 251 is an (oxide / nitride / oxide, abbreviated as ONO) gate structure, and the memory element M... P_STORAGE This is a charge-trapping transistor with an ONO gate structure. In other words, it combines the switching element M. P_SW With storage element M P_STORAGE This can form a charge-capture non-volatile memory cell, and the non-volatile memory device of the present invention is a charge-capture non-volatile memory device.

[0088] Clearly, during the manufacturing process of the non-volatile memory device of the second embodiment, the barrier layer 213 is covered by the protective layer 214. Therefore, contamination or thinning of the barrier layer 213 during manufacturing can be prevented. Furthermore, since the well regions of the logic element region and the memory element region are not fabricated simultaneously, smaller non-volatile memory cells can be designed in the memory element region, and the threshold voltage of the charge-trapping transistor can be precisely controlled.

[0089] Furthermore, the manufacturing process in the second embodiment can be modified according to actual needs. For example, Figure 2F After the structure is completed, Figures 2G to 2I The order of the manufacturing process can be changed. That is, the order of the three steps—removing the protective layer 214, forming the input / output gate layer 220, and forming the core gate layer 224—can be interchanged.

[0090] Please refer to Figures 3A to 3C This is an example of a change in the manufacturing process sequence of the second embodiment. In this example, the change... Figure 2G , Figure 2H and Figure 2I Production process sequence. Figure 2F Under the structure, such as Figure 3A As shown, an input / output gate layer 220 is formed on the surface of the semiconductor substrate Psub. Next, as... Figure 3B As shown, after removing the protective layer 214, a photoresist layer 222 is formed to cover the memory device region and the input / output device region. Next, an etching process is performed to remove the input / output gate oxide layer 220 on the surface of the semiconductor substrate Psub in the core device region. Then, as... Figure 3CAs shown, the photoresist layer 222 is removed, and a core gate oxide layer 224 is formed on the surface of the semiconductor substrate Psub in the core element region. Wherein, Figure 3C The structure is similar to Figure 2I Therefore, subsequent actions can be based on... Figures 2J to 2L The manufacturing process for the non-volatile memory device of the second embodiment of the present invention will be described in detail here.

[0091] Please refer to Figures 4A to 4C This is another example of a change in the manufacturing process sequence of the second embodiment. In this other example, the process sequence is also changed. Figure 2G , Figure 2H and Figure 2I Production process sequence. Figure 2F Under the structure, such as Figure 4A As shown, an input / output gate layer 220 is formed on the surface of the semiconductor substrate Psub. Next, as... Figure 4B As shown, a photoresist layer 222 is formed covering the memory device region and the input / output device region. Next, an etching process is performed to remove the input / output gate oxide layer 220 on the surface of the semiconductor substrate Psub in the core device region. Then, as... Figure 4C As shown, the photoresist layer 222 and the protective layer 214 are removed sequentially, and a core gate oxide layer 224 is formed on the surface of the semiconductor substrate Psub in the core component region. Among these, Figure 4C The structure is similar to Figure 2I Therefore, subsequent actions can be based on... Figures 2J to 2L The manufacturing process for the non-volatile memory device of the second embodiment of the present invention will be described in detail here.

[0092] Please refer to Figures 5A to 5F The diagram shown is a flowchart of a method for manufacturing a charge-capturing non-volatile memory device according to a third embodiment of the present invention.

[0093] like Figure 5A As shown, an isolation structure formation process is performed, in which a pad oxide layer 510 is formed on the surface of a semiconductor substrate Psub, and multiple isolation structures 502-507 are formed within the semiconductor substrate Psub. The semiconductor substrate Psub is a P-type substrate, and the isolation structures 502-507 are shallow trench isolation structures.

[0094] like Figure 5A As shown, on the surface of the semiconductor substrate Psub, the area between isolation structures 502 and 506 is a logic element area, and the area between isolation structures 506 and 507 is a memory element area. Furthermore, the logic element area can be further divided into an input / output element area and a core element area. For example... Figure 5AAs shown, the area between isolation structure 502 and isolation structure 504 is the input / output component area, and the area between isolation structure 504 and isolation structure 506 is the core component area.

[0095] like Figure 5B As shown, a photoresist layer 512 is formed to cover the logic element region. Next, an ion implantation process is performed to form an N-type well region NW1 below the surface of the semiconductor substrate Psub in the memory element region. Afterward, the photoresist layer 512 is removed, and then all pad oxide layers 510 are removed.

[0096] Next, as Figure 5C As shown, a stacked layer is formed on the surface of a semiconductor substrate Psub. The stacked layer includes: a bottom oxide layer 511, a trapping layer 512, a blocking layer 513, and a protective layer 514. The trapping layer 512 and the protective layer 514 can be made of silicon nitride, and the bottom oxide layer 511 and the blocking layer 513 can be made of silicon dioxide. That is, the bottom oxide layer 511 covers the surface of the semiconductor substrate Psub, and the trapping layer 512, the blocking layer 513, and the protective layer 514 are sequentially covered thereon.

[0097] like Figure 5D As shown, a photoresist layer 517 is formed within the memory element region, covering a portion of the stacked layers. Subsequently, an etching process is performed to remove the capture layer 512, barrier layer 513, and protective layer 514 that are not covered by the photoresist layer 517, leaving only the bottom oxide layer 511.

[0098] like Figure 5E As shown, after removing the photoresist layer 517, a photoresist layer 518 is formed to cover the memory element region. Next, multiple ion implantation processes are performed to form N-type well regions NW2 and NW3, P-type well regions PW1 and PW2, and deep N-type well regions DNW1 and DNW2 below the surface of the semiconductor substrate Psub in the logic element region. The two P-type well regions PW1 and PW2 are located within the two deep N-type well regions DNW1 and DNW2, respectively.

[0099] like Figure 5EAs shown, an N-type well region NW2 is formed below the surface of the semiconductor substrate Psub between isolation structures 505 and 506. A P-type well region PW1 and a deep N-type well region DNW1 are formed below the surface of the semiconductor substrate Psub between isolation structures 504 and 505, with the P-type well region PW1 located within the deep N-type well region DNW1. An N-type well region NW3 is formed below the surface of the semiconductor substrate Psub between isolation structures 503 and 504. A P-type well region PW2 and a deep N-type well region DNW2 are formed below the surface of the semiconductor substrate Psub between isolation structures 502 and 503, with the P-type well region PW2 located within the deep N-type well region DNW2.

[0100] In the third embodiment, the N-type well region NW1 in the memory element region is formed first, and the N-type well regions NW2 and NW3 in the logic element region are formed later. That is to say, the N-type well region NW1 in the memory element region and the NW2 and NW3 in the logic element region are not formed simultaneously.

[0101] like Figure 5F As shown, the photoresist layer 518 is removed, and an etching process is performed to remove the bottom oxide layer 511. Additionally, Figure 5F The structure is the same as Figure 2F Therefore, according to the second embodiment, Figures 2G to 2L The manufacturing process of the non-volatile memory device of the third embodiment of the present invention is used to complete the manufacturing process, which will not be described in detail here.

[0102] Of course, the manufacturing process of the third embodiment can also be changed according to actual needs. For example, refer to... Figures 3A to 3C or Figures 4A to 4C To modify the order of the manufacturing process steps and complete the non-volatile memory device of the third embodiment of the present invention.

[0103] In the first, second, and third embodiments described above, the switching element M within the memory element region... P_SW The gate structure includes input and output gate oxide layers, a gate layer, and spacers. (Referring to the second embodiment) Figure 2L For example, the switching element M P_SW The gate structure 252 includes an input / output gate oxide layer 220, a gate layer 230, and a spacer 236. In the following embodiments, the switching element M P_SW The gate structure may be made of other materials.

[0104] Please refer to Figures 6A to 6L The diagram shown is a flowchart of a method for manufacturing a charge-capturing non-volatile memory device according to a fourth embodiment of the present invention.

[0105] like Figure 6AAs shown, an isolation structure formation process is performed, in which a pad oxide layer 610 is formed on the surface of a semiconductor substrate Psub, and multiple isolation structures 602-607 are formed within the semiconductor substrate Psub. The semiconductor substrate Psub is a P-type substrate, and the isolation structures 602-607 are shallow trench isolation structures.

[0106] like Figure 6A As shown, on the surface of the semiconductor substrate Psub, the area between isolation structures 602 and 606 is a logic element area, and the area between isolation structures 606 and 607 is a memory element area. Furthermore, the logic element area can be further divided into an input / output element area and a core element area. For example... Figure 6A As shown, the area between isolation structure 602 and isolation structure 604 is the input / output component area, and the area between isolation structure 604 and isolation structure 606 is the core component area.

[0107] like Figure 6B As shown, a photoresist layer 612 is formed to cover the logic element region. Next, an ion implantation process is performed to form an N-type well region NW1 below the surface of the semiconductor substrate Psub in the memory element region. Afterward, an etching process is performed to remove the pad oxide layer 610 in the memory element region, while retaining the pad oxide layer 610 in the logic element region.

[0108] like Figure 6C As shown, the photoresist layer 612 is removed, forming a stacked layer. The stacked layer includes: a bottom oxide layer 611, a trapping layer 612, a blocking layer 613, and a protective layer 614. The trapping layer 612 and the protective layer 614 can be made of silicon nitride, while the bottom oxide layer 611 and the blocking layer 613 can be made of silicon dioxide.

[0109] like Figure 6C As shown, in the memory element region, a stacked layer covers the surface of the semiconductor substrate Psub. In the logic element region, the stacked layer covers the pad oxide layer 610. That is, in the memory element region, a bottom oxide layer 611 covers the surface of the semiconductor substrate Psub, and sequentially covers a trapping layer 612, a barrier layer 613, and a protective layer 614. In the logic element region, the bottom oxide layer 611 covers the pad oxide layer 610, and sequentially covers a trapping layer 612, a barrier layer 613, and a protective layer 614.

[0110] like Figure 6DAs shown, a photoresist layer 617 is formed within the memory element region, covering a portion of the stacked layers in the memory element region. Subsequently, an etching process is performed to remove the trapping layer 612, the blocking layer 613, and the protective layer 614 that are not covered by the photoresist layer 617, leaving only the bottom oxide layer 611.

[0111] like Figure 6E As shown, after removing the photoresist layer 617, a photoresist layer 618 is formed to cover the memory element region. Next, multiple ion implantation processes are performed to form N-type well regions NW2 and NW3, P-type well regions PW1 and PW2, and deep N-type well regions DNW1 and DNW2 below the surface of the semiconductor substrate Psub in the logic element region. The two P-type well regions PW1 and PW2 are located within the two deep N-type well regions DNW1 and DNW2, respectively.

[0112] like Figure 6E As shown, an N-type well region NW2 is formed below the surface of the semiconductor substrate Psub between isolation structures 605 and 606. A P-type well region PW1 and a deep N-type well region DNW1 are formed below the surface of the semiconductor substrate Psub between isolation structures 604 and 605, with the P-type well region PW1 located within the deep N-type well region DNW1. An N-type well region NW3 is formed below the surface of the semiconductor substrate Psub between isolation structures 603 and 604. A P-type well region PW2 and a deep N-type well region DNW2 are formed below the surface of the semiconductor substrate Psub between isolation structures 602 and 603, with the P-type well region PW2 located within the deep N-type well region DNW2.

[0113] In the fourth embodiment, the N-type well region NW1 in the memory element region is formed first, and the N-type well regions NW2 and NW3 in the logic element region are formed later. That is to say, the N-type well region NW1 in the memory element region and the NW2 and NW3 in the logic element region are not formed simultaneously.

[0114] like Figure 6F As shown, the photoresist layer 618 is removed, and an etching process is performed to remove the bottom oxide layer 611 and the pad oxide layer 610 that are not covered by the stacked layers.

[0115] like Figure 6G As shown, the protective layer 614 in the memory element area is first removed, and then an input / output gate oxide layer 620 is formed on the surface of the semiconductor substrate Psub.

[0116] like Figure 6HAs shown, a photoresist layer 622 is formed covering the input / output device region and a portion of the barrier layer 613 within the memory device region. Next, an etching process is performed to remove the input / output gate oxide layer 620 on the surface of the semiconductor substrate Psub in the core device region, and to remove the barrier layer 613 and the input / output gate oxide layer 620 in the memory device region that are not covered by the photoresist layer 622. In this embodiment, the second photoresist layer 622 covers at least half of the stacked layers in the memory device region.

[0117] like Figure 6I As shown, the photoresist layer 622 is removed, and a core gate oxide layer 624 is formed on the surface of the semiconductor substrate Psub in the core element region. The thickness of the core gate oxide layer 624 is less than the thickness of the input / output gate oxide layer 620. Additionally, in the memory element region, a barrier layer 613 covers a portion of the capture layer 612, while the remaining portion of the capture layer 612 is exposed and not covered.

[0118] Next, the gate structure formation process and the doping process are carried out.

[0119] like Figure 6J As shown, a gate layer 630 is formed, covering the logic element region and the memory element region. That is, the gate layer 630 covers the input / output gate oxide layer 620, the core gate oxide layer 624, the trapping layer 612, and the barrier layer 613. Next, a photoresist layer 632 is formed on the gate layer 630. The material of the gate layer can be polysilicon.

[0120] like Figure 6K As shown, an etching process is performed to remove the gate layer 630, input / output gate oxide layer 620, core gate oxide layer 624, bottom oxide layer 611, trapping layer 612, and barrier layer 613 that are not covered by the photoresist layer 632. Next, the photoresist layer 632 is removed.

[0121] After that, as Figure 6L As shown, in the input / output device region, a spacer 636 is formed on the sidewall of the input / output gate oxide layer 620 and the gate layer 630. Therefore, the input / output gate oxide layer 620, the gate layer 630 and the spacer 636 can become the gate structures 657 and 658 of the input / output device (IO device).

[0122] Similarly, in the core device region, a spacer wall 636 is formed on the sidewalls of the core gate oxide layer 624 and the gate layer 630. Therefore, the core gate oxide layer 624, the gate layer 630 and the spacer wall 636 can become the gate structures 654 and 655 of the core device.

[0123] Similarly, in the memory element region, spacer walls 636 are formed on the sidewalls of the bottom oxide layer 611, the capture layer 612, and the gate layer 630, and spacer walls 636 are also formed on the sidewalls of the bottom oxide layer 611, the capture layer 612, the barrier layer 613, and the gate layer 630. Therefore, the bottom oxide layer 611, the capture layer 612, the gate layer 630, and the spacer walls 636 can form the gate structure 652 of the switching device, and the bottom oxide layer 611, the capture layer 612, the barrier layer 613, the gate layer 630, and the spacer walls 636 can form the gate structure 651 of the storage device.

[0124] Furthermore, after the doping fabrication process, in the input / output device region, the gate structure 658 is formed on the P-type well region PW2, and two n-doped regions 648 are formed in the P-type well regions PW2 on both sides of the gate structure 658. Therefore, the P-type well region PW2, the two n-doped regions 648, and the gate structure 658 form a high-voltage N-type transistor M. N_HV Furthermore, the gate structure 657 is formed on the N-type well region NW3, and two p-doped regions 647 are formed in the N-type well regions NW3 on both sides of the gate structure 657. Therefore, the N-type well region NW3, the two p-doped regions 647, and the gate structure 657 form a high-voltage P-type transistor M. P_HV .

[0125] In the core component region, the gate structure 655 is formed on the P-type well region PW1, and two n-doped regions 645 are formed in the P-type well regions PW1 on both sides of the gate structure 655. Therefore, the P-type well region PW1, the two n-doped regions 645, and the gate structure 655 form a low-voltage N-type transistor M. N_LV Furthermore, the gate structure 654 is formed on the N-type well region NW2, and two p-doped regions 644 are formed within the N-type well regions NW2 on both sides of the gate structure 654. Therefore, the N-type well region NW2, the two p-doped regions 644, and the gate structure 654 form a low-voltage P-type transistor M. P_LV .

[0126] In the memory element region, a gate structure 652 is formed on an N-type well region NW1, and two p-doped regions 642 and 643 are formed within the N-type well regions NW1 on both sides of the gate structure 652. Therefore, the N-type well region NW1, the two p-doped regions 642 and 643, and the gate structure 652 form a switching element M. P_SW Furthermore, the gate structure 651 is formed on the N-type well region NW1, and two p-doped regions 641 and 642 are formed in the N-type well regions NW1 on both sides of the gate structure 651. Therefore, the N-type well region NW1, the two p-doped regions 641 and 642, and the gate structure 651 form the memory element M. P_STORAGE .

[0127] Of course, the doping fabrication process described above may also include a lightly doped drain region (LDD) fabrication process and / or a halo implantation process, etc. That is to say, the doped regions 641 to 648 may selectively include a lightly doped drain region (LDD region) and / or a halo region.

[0128] Furthermore, in the subsequent line-conducting process, core components within the logic element area (e.g., low-voltage P-type transistors) can be connected. P_LV With low-voltage N-type transistor M N_LV ) and input / output components (e.g., high-voltage P-type transistor M) P_HV With high voltage N-type transistor M N_HV This can be used to form peripheral circuits. Simultaneously, it can also connect to the switching elements M within the memory element area. P_SW With storage element M P_STORAGE These are used to form a memory cell array. Combining peripheral circuitry with the memory cell array creates the non-volatile memory device of this invention.

[0129] Compared to Figure 2L The second embodiment is a non-volatile memory device and Figure 6L The fourth embodiment of the non-volatile memory device differs in the switching element M. P_SW The gate structure is the same for all components. Figure 2L In the middle, the switching element M P_SW The gate structure 252 includes: input and output gate oxide layer 220, gate layer 230 and spacer 236. Figure 6L In the middle, the switching element M P_SW The gate structure 652 includes: a bottom oxide layer 611, a trapping layer 612, a gate layer 630, and a spacer 636.

[0130] Similarly, in the process of manufacturing the non-volatile memory device of the fourth embodiment, the barrier layer 613 is covered by the protective layer 614. Therefore, it is possible to prevent the barrier layer 613 from being contaminated or thinned during the manufacturing process. In addition, since the well regions of the logic element region and the memory element region are not fabricated simultaneously, smaller non-volatile memory cells can be designed in the memory element region, and the threshold voltage of the charge-trapping transistor can be precisely controlled.

[0131] Furthermore, in the manufacturing process of the fourth embodiment, Figure 6F and Figure 6G The fabrication process includes first removing the protective layer 614, and then forming the input / output gate layer 620. Similarly, in the fourth embodiment, the order of these two steps can be reversed according to actual needs. For example, in one example, the input / output gate layer 620 can be formed first, and then the protective layer 614 can be removed.

[0132] Please refer to Figures 7A to 7F The diagram shown is a flowchart of a method for manufacturing a charge-capturing non-volatile memory device according to a fifth embodiment of the present invention.

[0133] like Figure 7A As shown, an isolation structure formation process is performed, in which a pad oxide layer 710 is formed on the surface of a semiconductor substrate Psub, and multiple isolation structures 702-707 are formed within the semiconductor substrate Psub. The semiconductor substrate Psub is a P-type substrate, and the isolation structures 702-707 are shallow trench isolation structures.

[0134] like Figure 7A As shown, on the surface of the semiconductor substrate Psub, the area between isolation structures 702 and 706 is a logic element area, and the area between isolation structures 706 and 707 is a memory element area. Furthermore, the logic element area can be further divided into an input / output element area and a core element area. For example... Figure 7A As shown, the area between isolation structure 702 and isolation structure 704 is the input / output component area, and the area between isolation structure 704 and isolation structure 706 is the core component area.

[0135] like Figure 7B As shown, a photoresist layer 712 is formed to cover the logic element region. Next, an ion implantation process is performed to form an N-type well region NW1 below the surface of the semiconductor substrate Psub in the memory element region. Afterward, the photoresist layer 712 is removed, and an etching process is performed to remove all pad oxide layers 710.

[0136] Next, as Figure 7CAs shown, a stacked layer is formed on the surface of a semiconductor substrate Psub. The stacked layer includes: a bottom oxide layer 711, a trapping layer 712, a blocking layer 713, and a protective layer 714. The trapping layer 712 and the protective layer 714 can be made of silicon nitride, while the bottom oxide layer 711 and the blocking layer 713 can be made of silicon dioxide. In other words, the bottom oxide layer 711 covers the surface of the semiconductor substrate Psub, and the trapping layer 712, the blocking layer 713, and the protective layer 714 are sequentially covered thereon.

[0137] like Figure 7D As shown, a photoresist layer 717 is formed in the memory element area, covering part of the protective layer 714. Subsequently, an etching process is performed to remove the trapping layer 712, the blocking layer 713, and the protective layer 714 that are not covered by the photoresist layer 717, leaving only the bottom oxide layer 711.

[0138] like Figure 7E As shown, after removing the photoresist layer 717, a photoresist layer 718 is formed to cover the memory element region. Next, multiple ion implantation processes are performed to form N-type well regions NW2 and NW3, P-type well regions PW1 and PW2, and deep N-type well regions DNW1 and DNW2 below the surface of the semiconductor substrate Psub in the logic element region. The two P-type well regions PW1 and PW2 are located within the two deep N-type well regions DNW1 and DNW2, respectively.

[0139] like Figure 7E As shown, an N-type well region NW2 is formed below the surface of the semiconductor substrate Psub between isolation structures 705 and 706. A P-type well region PW1 and a deep N-type well region DNW1 are formed below the surface of the semiconductor substrate Psub between isolation structures 704 and 705, with the P-type well region PW1 located within the deep N-type well region DNW1. An N-type well region NW3 is formed below the surface of the semiconductor substrate Psub between isolation structures 703 and 704. A P-type well region PW1 and a deep N-type well region DNW1 are formed below the surface of the semiconductor substrate Psub between isolation structures 702 and 703, with the P-type well region PW2 located within the deep N-type well region DNW2.

[0140] In the fifth embodiment, the N-type well region NW1 in the memory element region is formed first, and the N-type well regions NW2 and NW3 in the logic element region are formed later. That is to say, the N-type well region NW1 in the memory element region and the NW2 and NW3 in the logic element region are not formed simultaneously.

[0141] like Figure 7F As shown, the photoresist layer 718 is removed, and an etching process is performed to remove the bottom oxide layer 711. Among these steps... Figure 7F The structure is the same as Figure 6F Therefore, according to the fourth embodiment... Figures 6G to 6L The manufacturing process of the non-volatile memory device of the fifth embodiment of the present invention is described in detail below.

[0142] In summary, this invention proposes a method for manufacturing a charge-trapping non-volatile memory device. During the manufacturing process, the barrier layer of the memory element is effectively protected, preventing contamination or thinning. Furthermore, since the well regions of the logic element region and the memory element region are not fabricated simultaneously, smaller non-volatile memory cells can be designed in the memory element region, and the threshold voltage of the charge-trapping transistor can be precisely controlled.

[0143] In summary, although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A method for manufacturing a charge-capturing non-volatile memory device, comprising the following steps: (A) A pad oxide layer is formed on the surface of a semiconductor substrate, and a plurality of isolation structures are formed within the semiconductor substrate; wherein, These isolation structures divide the semiconductor substrate into a memory element area and a logic element area, and further divide the logic element area into an input / output element area and a core element area; (B) A first photoresist layer is formed to cover the logic element region, and a first type-1 well region is formed below the surface of the semiconductor substrate of the memory element region; (C) Remove the first photoresist layer and at least a portion of the pad oxide layer, and form a stacked layer covering the logic element region and the memory element region; wherein the stacked layer includes a bottom oxide layer, a trapping layer, a barrier layer and a protective layer; (D) Form a second photoresist layer covering a portion of the stacked layer in the memory element region, and remove the protective layer, the barrier layer and the trapping layer that are not covered by the second photoresist layer; (E) Remove the second photoresist layer and form a third photoresist layer covering the memory element region; (F) A second first-type well region, a first second-type well region, and a first deep first-type well region are formed under the semiconductor substrate in the core component region, and a third first-type well region, a second second-type well region, and a second deep first-type well region are formed under the semiconductor substrate in the input / output component region, wherein the first second-type well region is located within the first deep first-type well region, and the second second-type well region is located within the second deep first-type well region; (G) Remove the third photoresist layer and remove part of the bottom oxide layer that is not covered by the protective layer; (H) Remove the protective layer on the stacked layer, form an input / output gate oxide layer on the semiconductor substrate of the memory element region, form the input / output gate oxide layer on the semiconductor substrate of the input / output element region, and form a core gate oxide layer on the semiconductor substrate of the core element region. (I) Forming a gate layer covering the memory element region and the logic element region; and (J) Multiple gate structures are formed and multiple doped regions are formed; Wherein, a first gate structure is located on the first first-type well region, a first second-type doped region and a second second-type doped region are formed in the first first-type well regions on both sides of the first gate structure; and a second gate structure is located on the first first-type well region, a second second-type doped region and a third second-type doped region are formed in the first first-type well regions on both sides of the second gate structure; Wherein, a third gate structure is formed on the second first type well region, a fourth second type doped region and a fifth second type doped region form both sides of the third gate structure and are located within the second first type well region; and a fourth gate structure is formed on the first second type well region, a first first type doped region and a second first type doped region form both sides of the fourth gate structure and are located within the first second type well region; The fifth gate structure is formed on the third first type well region, the sixth second type doped region and the seventh second type doped region form the two sides of the fifth gate structure and are located in the third first type well region; and the sixth gate structure is formed on the second second type well region, the third first type doped region and the fourth first type doped region form the two sides of the sixth gate structure and are located in the second second type well region.

2. The manufacturing method as claimed in claim 1, wherein step (C) further comprises: Before removing the pad oxide layer in the logic element area and the memory element area, the first photoresist layer is removed first.

3. The manufacturing method of claim 1, wherein step (H) further comprises the following steps: Remove the protective layer from the stack layer; The input / output gate oxide layer is formed on the surface of the semiconductor substrate; A fourth photoresist layer is formed, covering the memory element region and the input / output element region, and the input / output gate oxide layer in the core element region is removed; as well as The fourth photoresist layer is removed, and the core gate oxide layer is formed on the surface of the semiconductor substrate within the core element region.

4. The manufacturing method as claimed in claim 3, wherein step (H) comprises: Before removing the protective layer on the stacked layer, the input / output gate oxide layer is first formed on the surface of the semiconductor substrate within the memory element region.

5. The manufacturing method of claim 3, wherein step (H) comprises: After removing the fourth photoresist layer and before forming the core gate oxide layer, the protective layer on the stacked layer is removed.

6. The manufacturing method of claim 1, wherein the first gate structure includes the bottom oxide layer, the trapping layer, the blocking layer, the gate layer, and the spacer wall; the second gate structure includes the input / output gate oxide layer, the gate layer, and the spacer wall; each of the third gate structure and the fourth gate structure includes the core gate oxide layer, the gate layer, and the spacer wall; and each of the fifth gate structure and the sixth gate structure includes the input / output gate oxide layer, the gate layer, and the spacer wall.

7. The manufacturing method of claim 6, wherein the first gate structure, the first first-type well region, the first second-type doped region, and the second second-type doped region form a memory element; the second gate structure, the first first-type well region, the second second-type doped region, and the third second-type doped region form a switching element; the third gate structure, the second first-type well region, the fourth second-type doped region, and the fifth second-type doped region form a low-voltage second-type transistor; the fourth gate structure, the first second-type well region, the first first-type doped region, and the second first-type doped region form a low-voltage first-type transistor; the fifth gate structure, the third first-type well region, the sixth second-type doped region, and the seventh second-type doped region form a high-voltage second-type transistor; the sixth gate structure, the second second-type well region, the third first-type doped region, and the fourth first-type doped region form a high-voltage first-type transistor; and the switching element and the memory element constitute a charge-trapping non-volatile memory cell.

8. The manufacturing method of claim 1, wherein the bottom oxide layer and the barrier layer comprise silicon dioxide, the trapping layer comprises silicon nitride, and the gate layer comprises polysilicon.

9. The manufacturing method of claim 1, wherein step (D) comprises: The second photoresist layer is formed to cover at least half of the stacked layers in the memory element region.

10. The manufacturing method of claim 9, wherein step (H) further comprises the following steps: (H1) Remove the protective layer on the stacked layer and form the input / output gate oxide layer on the semiconductor substrate; (H2) Form a fourth photoresist layer covering a portion of the barrier layer in the input / output device region and the memory device region; remove the input / output gate oxide layer in the core device region; remove the portion of the barrier layer and the input / output gate oxide layer in the memory device region not covered by the fourth photoresist layer; and (H3) Remove the fourth photoresist layer and form the core gate oxide layer on the surface of the semiconductor substrate within the core element region.

11. The manufacturing method of claim 10, wherein step (H1) comprises: After forming the input / output gate oxide layer on the semiconductor substrate, the protective layer on the stacked layer is then removed.

12. The manufacturing method of claim 10, wherein the first gate structure includes the bottom oxide layer, the trapping layer, the blocking layer, the gate layer, and the spacer wall; and the second gate structure includes the bottom oxide layer, the trapping layer, the gate layer, and the spacer wall; The third gate structure includes the core gate oxide layer, the gate layer, and the spacer wall; The fourth gate structure includes the core gate oxide layer, the gate layer, and the spacer wall; The fifth gate structure includes the input / output gate oxide layer, the gate layer, and the spacer wall; Furthermore, the sixth gate structure includes the input / output gate oxide layer, the gate layer, and the spacer wall.

13. The manufacturing method of claim 1, wherein step (C) further comprises: After removing the pad oxide layer within the memory element region, the first photoresist layer is removed.

14. The manufacturing method of claim 13, wherein step (C) further comprises: The stacked layer is formed to cover the pad oxide layer within the logic element region and to cover the surface of the semiconductor substrate within the memory element region.

15. The manufacturing method of claim 13, wherein step (G) further comprises: Remove the oxide layer from the pad.

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