Transmitter with extended dynamic range beyond supply rail

Abstract

An apparatus includes a plurality of signal processing stages configured to convert a digital baseband signal to an analog radio frequency signal for transmission. The signal processing stages are configured to be operably coupled to a positive supply voltage and a negative supply voltage. At least one of the plurality of signal processing stages is configured to generate an analog voltage signal that includes a voltage level outside of a voltage range defined by the positive supply voltage and the negative supply voltage.

Description

Background Technology

[0001] This disclosure generally relates to transmitters and sensor nodes implementing transmitters in sensor networks. Wireless sensor networks typically comprise multiple sensor nodes distributed within a given physical environment to work collaboratively, thereby monitoring one or more physical conditions or events occurring in that environment. In a wireless sensor network environment, the power consumption of a sensor node should be limited when it operates and communicates with neighboring sensor nodes or other nodes in the network environment. In this regard, the power consumption of the radio frequency (RF) transmitter or transceiver implemented by the sensor node should be limited to extend the sensor node's limited power supply capacity (e.g., battery capacity). Summary of the Invention

[0002] Exemplary embodiments of this disclosure include an apparatus comprising a plurality of signal processing stages configured to convert digital baseband signals into analog radio frequency signals for transmission. The signal processing stages are configured to be operatively coupled to a positive supply voltage and a negative supply voltage, wherein at least one of the plurality of signal processing stages is configured to generate an analog voltage signal including voltage levels outside a voltage range defined by the positive and negative supply voltages.

[0003] Other embodiments will be described in the following detailed description of exemplary embodiments, which are read in conjunction with the accompanying drawings. Attached Figure Description

[0004] Embodiments of the invention will now be described by way of example only with reference to the accompanying drawings, in which:

[0005] Figure 1 A transmitter according to an exemplary embodiment of the present disclosure is shown schematically.

[0006] Figure 2A A digital-to-analog converter (DAC) circuit and a filter circuit according to exemplary embodiments of the present disclosure are illustrated schematically.

[0007] Figure 2B The illustration schematically depicts an implementation of an exemplary embodiment of the present disclosure. Figure 2A The inverter circuit in the DAC circuit.

[0008] Figure 3 A modulation circuit according to an exemplary embodiment of the present disclosure is schematically shown.

[0009] Figure 4A The diagram shows a voltage waveform generated by a DAC circuit according to an exemplary embodiment of the present disclosure.

[0010] Figure 4BThe filtered voltage waveform generated by the filter circuit according to an exemplary embodiment of the present disclosure is illustrated schematically.

[0011] Figure 5 A DAC circuit and a filter circuit according to another exemplary embodiment of the present invention are schematically shown.

[0012] Figure 6A A multi-channel transmitter according to an exemplary embodiment of the present disclosure is schematically illustrated.

[0013] Figure 6B The diagram schematically illustrates a local oscillator (LO) signal generator circuit according to an exemplary embodiment of the present disclosure, which can be implemented to generate signals for... Figure 6A Different LO signals from a multi-channel transmitter.

[0014] Figure 7 A multi-channel transmitter according to another exemplary embodiment of the present disclosure is schematically illustrated.

[0015] Figure 8 A sensor node for implementing a transmitter according to an exemplary embodiment of the present disclosure is schematically shown.

[0016] Figure 9 A computing system including a network of sensor nodes implementing a transmitter is schematically illustrated according to an exemplary embodiment of the present disclosure.

[0017] Figure 10 An exemplary architecture of a computing node according to an exemplary embodiment of the present disclosure is schematically shown, which can host and execute programs for managing and configuring sensor nodes, including transmitter systems.

[0018] Figure 11 A cloud computing environment is described according to exemplary embodiments of the present disclosure.

[0019] Figure 12 Describes an abstract model layer according to exemplary embodiments of this disclosure. Detailed Implementation

[0020] Exemplary embodiments of this disclosure will now be described in further detail with respect to transmitters having a dynamic range exceeding the voltage supply rails. More specifically, exemplary embodiments of this disclosure include transmitters that include signal processing stages configured to generate analog voltage signals having voltage levels exceeding the supply voltage rails (e.g., a negative supply voltage rail or a positive supply voltage rail). For example, in some embodiments, an ultra-low power transmitter includes multiple signal processing stages configured to convert digital baseband signals into analog radio frequency signals for transmission. The signal processing stages are configured to be operatively coupled to a positive supply voltage and a negative supply voltage, wherein at least one of the multiple signal processing stages is configured to generate an analog voltage signal including a voltage level (e.g., a peak voltage level or an average voltage level) less than the negative supply voltage. In other embodiments, the transmitter includes multiple signal processing stages configured to convert digital baseband signals into analog radio frequency signals for transmission, wherein at least one of the multiple signal processing stages is configured to generate an analog voltage signal including a voltage level (e.g., a peak voltage level or an average voltage level) greater than the positive supply voltage.

[0021] It should be understood that the various features shown in the accompanying drawings are schematic diagrams not drawn to scale. Furthermore, the same or similar reference numerals are used in all the drawings to denote the same or similar features, elements, or structures; therefore, detailed explanations of the same or similar features, elements, or structures will not be repeated for each drawing. Additionally, as used herein, the term "exemplary" means "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" should not be construed as preferred or advantageous over other embodiments or designs.

[0022] Furthermore, it should be understood that the phrase “configured to” used in conjunction with circuits, structures, elements, components, etc., that perform one or more functions or otherwise provide some functions is intended to cover embodiments in which the circuits, structures, elements, components, etc., are implemented in hardware, software, and / or combinations thereof. In implementations that include hardware, the hardware may include discrete circuit elements (e.g., transistors, inverters, etc.), programmable elements (e.g., ASICs, FPGAs, etc.), processing devices (e.g., CPUs, GPUs, etc.), one or more integrated circuits, and / or combinations thereof. Therefore, by way of example only, when a circuit is defined as being configured to provide a particular function, it is intended to cover, but is not limited to, embodiments in which the circuit consists of elements, processing devices, and / or integrated circuits that enable the circuit to perform the particular function when in an operational state (e.g., connected or otherwise deployed in a system, energized, receiving input, and / or generating output), and embodiments in a non-operational state (e.g., not connected or otherwise deployed in a system, not energized, not receiving input, and / or not generating output) or in a partially operational state.

[0023] Figure 1 A transmitter 100 according to an exemplary embodiment of the present disclosure is schematically shown. Specifically, Figure 1 A single-channel transmitter 100 is schematically shown, comprising a baseband signal generator 110, a digital-to-analog converter stage 120 (or DAC stage 120), a filter stage 130, a modulation stage 140, an amplifier driver stage 150, and an impedance matching network 160. The DAC stage 120 includes an input coupled to the output of the baseband signal generator 110. The filter stage 130 includes an input coupled to the output of the DAC stage 120. The modulation stage 140 includes an input coupled to the output of the filter stage 130. The amplifier driver stage 150 includes an input coupled to the output of the modulation stage 140 and an output coupled to the input of the matching network 160. The matching network 160 includes an output connected to the output node of the transmitter 100. In some embodiments, the output of the transmitter 100 is coupled to an antenna system configured to transmit an RF output signal generated by the transmitter 100. In other embodiments, transmitter 100 includes a waveform generator (e.g., an arbitrary waveform generator or a function generator), wherein the output of transmitter 100 is coupled to the input of a sensor device, and wherein the RF output signal generated by transmitter 100 is configured to excite the sensor device.

[0024] like Figure 1 As further shown, the various signal processing stages 120, 130, 140, 150, and 160 of the transmitter 100 include control signal input ports that receive digital control signals from a microcontroller configured to control the operation of the transmitter 100. In some embodiments, some or all of stages 120, 130, 140, 150, and 160 have a configurable hardware framework in which various operating parameters of the stage can be adjusted by the digital control signals. Furthermore, in some embodiments, the active components of the various signal processing stages have control circuitry configured to control the power-on and power-off of circuit blocks in the signal processing stages in response to the digital control signals, thereby selectively activating the circuit blocks of the signal processing stages for different operating modes of the transmitter 100. In some embodiments, as known in the art, the control circuitry for controlling the power-on and power-off of the circuit blocks of the signal processing stages can be implemented using an open-drain circuit topology. In other embodiments, circuit blocks of the signal processing stage can be powered on or off by implementing a switching circuit configured to control the flow of quiescent current (or operating current) of the active components of various circuit blocks, such that a given circuit block can be powered off by cutting off the flowing operating current.

[0025] In the context of the exemplary embodiments discussed herein, RF signals include signals having frequencies ranging from, for example, about 20 kHz to about 300 GHz, such that the energy of an oscillating signal at the RF frequency (e.g., a current signal) can be radiated from a conductor into space as radio waves. In some embodiments, transmitter system 100 includes a quadrature transmitter configured to process quadrature signals (referred to as IQ signals). As known in the art, quadrature signals include in-phase (I) signal components and quadrature-phase (Q) signal components. A pair of quadrature signals have the same frequency but are 90 degrees out of phase. For illustrative purposes, exemplary embodiments of this disclosure will be described in the context of a quadrature transmitter system, although other types of transmitters and modulation techniques may be used to implement the exemplary signal processing circuits and methods discussed herein.

[0026] Figure 1 An exemplary embodiment is illustrated, wherein transmitter 100 includes an RF analog quadrature transmitter. Baseband signal generator 110 is configured to receive baseband data as input (e.g., sensor data) and generate digital quadrature signals I and Q representing the input baseband data. In this process, the baseband data input to baseband signal generator 110 is split into two quadrature digital components, including an in-phase (I) baseband component and a quadrature-phase (Q) baseband component. In some embodiments, baseband signal generator 110 implements digital signal processing techniques based on a combination of hardware and software to generate the digital quadrature baseband signals I and Q.

[0027] In some embodiments, the input baseband data includes digital baseband data generated by another signal processor configured to process the output signal from the sensor device and generate the baseband data. In other embodiments, the functionality of the baseband signal generator 110 can be implemented in a separate digital signal processor performing various functions, including but not limited to digital signal processing of sensor data received from the sensor and generating digital quadrature baseband IQ signals. In this respect, although Figure 1 The exemplary embodiments shown depict a baseband signal generator 110 as a component of transmitter 100; however, it should be understood that in other embodiments, the baseband signal generator 110 is a system component (e.g., a digital signal processor) separate from transmitter 100. In other embodiments where transmitter 100 is implemented as a waveform generator, baseband signal generator 110 generates the necessary digital quadrature baseband IQ signal required to generate an analog waveform (e.g., a sinusoidal voltage waveform) with a target center frequency, which is configured to operate or otherwise excite sensor devices coupled to the output of the transmitter.

[0028] DAC stage 120 is configured to convert a digital baseband signal (e.g., a digital IQ signal output from baseband signal generator 110) into an analog baseband signal having a baseband frequency. DAC stage 120 includes a first DAC circuit 121 and a second DAC circuit 122. The first DAC circuit 121 is configured to convert the digital baseband component I into an analog baseband component I(t) having a baseband frequency, and the second DAC circuit 122 is configured to convert the digital baseband component Q into an analog baseband component Q(t) having the same baseband frequency but with a 90-degree phase shift relative to I(t). DAC stage 120 operates at a given sampling rate (f... S The system generates and outputs analog baseband signals I(t) and Q(t) at a sampling frequency, and in some embodiments, the sampling frequency is in the baseband frequency range of approximately 100 kHz to approximately 100 MHz.

[0029] Based on the Nyquist sampling theorem, with a sampling rate f S The highest fundamental output frequency f that the DAC can generate is O The signal is equal to half the sampling rate or f s / 2 (referred to as the first Nyquist zone). In the frequency domain, when the generating frequency f O When the waveform is a sine wave, the basic baseband frequency f O will be f O The spectral components appear at that point, and there will be additional higher frequency components generated at the output of DAC stage 120, which are called "mirrors" and are functions of f. S and f O For example, higher frequency components are identified as |n×(f S ±f O )|, where n = 1, 2, 3, ... . The mirror image has the same information content as the fundamental spectral components, but at a higher frequency and with a smaller amplitude. For example, a downstream filter stage 130 is used to suppress / reject unwanted mirror images.

[0030] In some embodiments, the first DAC circuit 121 and the second DAC circuit 122 are implemented using a voltage-mode DAC framework in which the analog output is a voltage waveform. More specifically, in some embodiments, a voltage-mode DAC framework is used as described above. Figure 2A The exemplary capacitor-based DAC framework shown implements the first DAC circuit 121 and the second DAC circuit 122, wherein the first DAC circuit 121 and the second DAC circuit 122 are configured to generate analog voltage signals, which include voltage levels (e.g., peak voltage level, average voltage level, etc.) less than the negative supply voltage (or negative supply rail). In other embodiments, such as Figure 5The exemplary capacitor-based DAC framework shown implements a first DAC circuit 121 and a second DAC circuit 122, wherein the first DAC circuit 121 and the second DAC circuit 122 are configured to generate analog voltage signals, which include voltage levels (e.g., peak voltage levels, average voltage levels, etc.) greater than the positive supply voltage (or positive supply rail). This will be discussed in further detail below. Figure 2A and Figure 5 Details of the exemplary DAC circuit shown.

[0031] In some embodiments, the first DAC circuit 121 and the second DAC circuit 122 implement a configurable hardware framework, wherein various operating parameters of the DAC stage 120 can be adjusted via digital control, for example, by digital control signals input to the DAC stage 120. For example, in some embodiments, digital control can be used to adjust DAC operating parameters, including but not limited to sampling rate, analog output gain, etc. In this regard, the first DAC circuit 121 and the second DAC circuit 122 can be configured to have desired gain and sampling frequency to achieve desired RF transmission power and RF transmission frequency, for example, when the transmitter 100 operates in baseband transmit mode, wherein in baseband transmit mode, the modulation stage 140 is inoperable and used to up-convert the baseband frequency to a higher RF transmission frequency, as discussed in further detail below.

[0032] For example, a higher DAC sampling frequency can be used as needed to transmit baseband data and / or relax the filter response of the downstream filter of filter stage 130. In fact, increasing the DAC sampling frequency leads to the possibility of adapting to higher baseband transmission frequencies (i.e., the analog baseband components I(t) and Q(t) have higher baseband frequencies). Additionally, increasing the DAC sampling frequency leads to a higher center frequency f of the baseband components. O and the center frequency f of the higher frequency image S ±f O The increased spacing between the frequencies relaxes the required sharpness of the filter cutoff at the filter's corner frequencies. However, the higher DAC sampling rate leads to increased power consumption. Therefore, a trade-off between power consumption and the lower DAC sampling frequency, along with the sharpness of the filter cutoff at the filter's corner frequencies, must be considered.

[0033] Filter stage 130 is configured to filter the IQ analog signal components output from DAC stage 120, thereby generating filtered analog IQ signals. Filter stage 130 includes a first filter circuit 131 and a second filter circuit 132. The first filter circuit 131 is configured to filter the in-phase analog signal I(t) output from the first DAC circuit 121, and the second filter circuit 132 is configured to filter the quadrature-phase analog signal Q(t) output from the second DAC circuit 122. In some embodiments, the first filter circuit 131 and the second filter circuit 132 include low-pass filters configured to allow the fundamental spectral components of the corresponding analog signals I(t) and Q(t) to pass through while suppressing the mirror components of the corresponding analog signals I(t) and Q(t). In some embodiments, the first filter circuit 131 and the second filter circuit 132 use, for example... Figure 2A or Figure 5 This is implemented using the analog dual-quadratic low-pass filter circuit framework shown. It has the following characteristics: Figure 2A The analog dual-secondary low-pass filter circuit shown is configured to generate a filtered analog voltage signal that includes voltage levels (e.g., average voltage level, peak voltage level, etc.) less than the negative supply voltage VSS, while having... Figure 5 The analog dual-secondary low-pass filter circuit of the architecture shown is configured to generate a filtered analog voltage signal that includes voltage levels (e.g., average voltage level, peak voltage level, etc.) greater than the positive supply voltage VDD. Figure 2A and Figure 5 The details of the exemplary low-pass filter circuit shown will be discussed in further detail below.

[0034] In other embodiments, the first filter circuit 131 and the second filter circuit 132 may be configured as bandpass filters to allow the desired frequency bands of the higher-frequency image components of the respective analog baseband components I(t) and Q(t) to pass through, while suppressing the fundamental spectral components and other image components of the respective analog baseband components I(t) and Q(t). In other embodiments, the first filter circuit 131 and the second filter circuit 132 are configured as high-pass filters, as may be desired for a given application. In some embodiments, the filter stage 130 includes configurable filter circuitry, wherein, for example, the cutoff frequencies of the first filter circuit 131 and the second filter circuit 132 may be adjusted, or wherein the first filter circuit 131 and the second filter circuit 132 may be configured to have different filter types (e.g., low-pass, band-pass, etc.) desired for a given application. For example, in some embodiments, the bandpass filter may be configured using two low-pass filters employing known signal filtering techniques and architectures. In some embodiments, the filter configuration is digitally controlled by digital control signals input to the filter stage 130.

[0035] In some embodiments, modulation stage 140 is configured to perform analog IQ signal modulation (e.g., single-sideband (SSB) modulation) by mixing filtered analog signals I(t) and Q(t) output from filter stage 130 with quadrature LO signals (e.g., in-phase LO signals (LO_I) and quadrature-phase LO signals (LO_Q)) to generate and output an analog RF signal (e.g., a SSB-modulated RF output signal). The local oscillator signals LO_I and LO_Q each have the same LO frequency, but the LO_Q signal is phase-shifted by 90 degrees relative to the LO_I signal. More specifically, modulation stage 140 includes a first mixer circuit 141, a second mixer circuit 142, and a signal combiner circuit 143. The first mixer circuit 141 is configured to mix the filtered analog signal I(t) with the LO_I signal to generate a first RF signal output. The second mixer circuit 142 is configured to mix the filtered analog signal Q(t) with the LO_Q signal to generate a second RF signal output. The first RF signal and the second RF signal output from the first mixer circuit 141 and the second mixer circuit 142 are input to the signal combiner circuit 143 and combined (e.g., added) to generate a single-sideband RF signal output.

[0036] In some embodiments, a quadrature phase shifter circuit is implemented in transmitter 100 to generate quadrature LO_I and LO_Q signals. For example, the quadrature phase shifter circuit is configured to receive an LO signal as input and output quadrature LO signals LO_I and LO_Q based on the LO input signal. In this configuration, the LO_I signal includes the same frequency and phase as the input LO signal, and the LO_Q signal includes the same frequency as the input LO signal but with a 90-degree phase shift. The quadrature phase shifter circuit can be implemented using one of various quadrature phase shifting techniques known to those skilled in the art.

[0037] Modulation stage 140 performs an upconversion modulation process configured to generate an RF analog signal having a center frequency higher than the baseband frequency of the baseband signal output from DAC stage 120. In some embodiments, depending on the application, the LO frequency of modulation stage 140 is in the range of 100 MHz to approximately 10 GHz. More specifically, as understood by those skilled in the art, as a result of the mixing operations of the first mixer 141 and the second mixer 142, the first and second RF signals output from the respective first mixer 141 and second mixer 142 each comprise a double-sideband RF signal. The double-sideband signal comprises an upper sideband (USB) and a lower sideband (LSB), which are positioned equidistantly above and below the LO frequency. The upper sideband comprises a frequency band above the LO frequency, and the lower sideband comprises a frequency band below the LO frequency. The upper and lower sidebands each carry the same information content of the IQ signals. For example, assume that the filtered analog signals I(t) and Q(t) (i.e., the modulated signals) have a center frequency f. M And the LO signal has a frequency f LO The first and second RF signals output from the first mixer 141 and the second mixer 142 will each have an upper sideband of (i) a spectral component, which is centered at (f LO +f M (i) the frequency band, and (ii) the lower sideband of the spectral component, which is centered at (f LO -f M The frequency band.

[0038] In some embodiments, the signal combiner 143 is configured to add a first RF signal and a second RF signal output from the first mixer 141 and the second mixer 142. In this case, the signal combiner 143 outputs a real lower sideband signal as a single-sideband modulated RF signal (with a suppressed carrier) having a frequency f from the modulation signals I(t) and Q(t). M Up-converted to the center frequency (f) of the lower sideband LO -f M The center frequency of ). In other embodiments, the signal combiner 143 is configured to subtract the first RF signal and the second RF signal output from the first mixer 141 and the second mixer 142. In this case, the signal combiner 143 outputs a "real" upper sideband signal as a single-sideband modulated RF signal (with a suppressed carrier) having a frequency f from the modulation signals I(t) and Q(t). M Up-converted to the center frequency (f) of the upper sideband LO +f M The center frequency of ).

[0039] In other embodiments, modulation stage 140 is configured as a double-sideband modulator (with a suppressed carrier). More specifically, modulation stage 140 may be configured to provide double-sideband modulation by maintaining the LO_Q input to the second mixer 142 at a constant zero voltage level (i.e., LO_Q = 0). In this case, the second mixer 142 will have zero output (i.e., no RF signal is output from the second mixer 142), and the output of signal combiner 143 will be the double-sideband RF signal output from the first mixer 141. For example, to illustrate the IQ modulation process performed by modulation stage 140, it is assumed that (i) the in-phase signal is a cosine waveform, (ii) the quadrature-phase signal is a sine waveform, and (iii) the analog baseband components I(t) and Q(t) have a baseband frequency f. M (represented as B), and (iv) the LO_I and LO_Q signals have LO frequency f. LO (denoted as A). Using this exemplary notation, the analog baseband signal I(t) is represented as cos(B), the analog baseband signal Q(t) is represented as sin(B), the LO_I signal is represented as cos(A), and the LO_Q signal is represented as sin(B).

[0040] Based on the product-to-sum trigonometric identity, the first mixer 141 and the second mixer 142 of the modulation stage 140 perform the following operations. The first mixer 141 mixes the analog in-phase baseband signal I(t) with the LO_I signal through the following multiplication process: cos(A)cos(B)=1 / 2[cos(AB)+cos(A+B)]. The second mixer 142 mixes the analog quadrature-phase baseband signal Q(t) with the LO_Q signal through the following multiplication process: sin(A)sin(B)=1 / 2[cos(AB)-cos(A+B)].

[0041] Furthermore, in some embodiments, the signal combiner 143 adds the signals output from the first mixer 141 and the second mixer 142 to generate a single-sideband RF output signal (RF). OUT ) as follows: RF OUT = (1 / 2[cos(AB)+cos(A+B)])+(1 / 2[cos(AB)-cos(A+B)])=cos(AB). In other embodiments, the signal combiner 143 subtracts the signals output from the first mixer 141 and the second mixer 142 to generate a single-sideband RF output signal (RF). OUT ) as follows: RF OUT =(1 / 2[cos(AB)+cos(A+B)])-(1 / 2[cos(AB)-cos(A+B)])=cos(A+B).

[0042] Amplifier driver stage 150 is configured to receive a modulated RF signal output from modulation stage 140, amplify the modulated RF signal to a desired power level, and drive the output of transmitter 100 (e.g., drive an antenna coupled to the output of transmitter 100, or drive a sensor device coupled to the output of transmitter 100). In some embodiments, amplifier driver stage 150 includes a programmable gain, wherein the gain can be expressed as the difference between the input power level (at the input of amplifier driver stage 150) and the output power level (at the output of amplifier driver stage 150), or more specifically, as the ratio of output power to input power. Amplifier driver stage 150 is used to increase the power level of the RF output signal to a level sufficient to transmit the modulated RF signal at a given power level and over a desired transmission distance (wirelessly or wired).

[0043] Impedance matching network 160 is configured to match the source impedance or load impedance of the output of amplifier driver stage 150 to the characteristic impedance of the output load of transmitter 100 (e.g., antenna input, duplexer, etc.). In some embodiments, impedance matching network 160 includes a balun to convert the differential / balanced output of amplifier driver stage 150 to a single / unbalanced output. In some embodiments, the output of impedance matching network 160 is coupled to an antenna system. In other embodiments, the output of impedance matching network 160 is coupled to a sensor device. In some embodiments, the resonant parameters (e.g., impedance and bandwidth) of matching network 160 remain substantially constant, wherein matching network 160 is designed to have a center frequency corresponding to the RF transmission frequency (e.g., 2.4 GHz) of transmitter 100.

[0044] In other embodiments, the matching network 160 is configured with multiple injection points to provide different impedance matching and filtering characteristics. Different injection points can be selected by applying digital control signals to the matching network 160. The matching network 160 can have high-pass and low-pass characteristics, where different injection points can be selected to provide different impedance matching and response characteristics. In some embodiments, the impedance matching network 160 is designed to have a high Q factor, wherein the center frequency of the impedance matching network 160 can be adjusted to provide sufficient impedance matching for different transmission frequencies, which are generated, for example, by changing the sampling frequency of the DAC stage 120 and / or changing the LO frequency of the modulation stage 140 according to a given application.

[0045] Figure 2A A DAC circuit and a filter circuit according to exemplary embodiments of the present disclosure are schematically illustrated. Specifically, Figure 2A The diagram schematically illustrates a circuit block 200 including a DAC circuit 220 and a filter circuit 230 according to an exemplary embodiment of the present disclosure, which can be respectively in... Figure 1 Implemented in the DAC stage 120 and filter stage 130 of the transmitter 100 to generate an analog voltage signal including voltage levels (e.g., average voltage level, peak voltage level, etc.) less than the negative supply voltage (e.g., negative supply rail). Figure 2A As shown, the DAC circuit 220 includes a digital logic interface, a timing control block 222, and a voltage-mode output stage 224. The voltage-mode output stage 224 includes multiple output stages coupled in parallel to the output node N1 of the DAC circuit 220, and an output capacitor C coupled between the output node N1 and the negative supply voltage (e.g., the VSS voltage rail). 10 (or scaling capacitors). Specifically, the voltage-mode output stage 224 includes multiple (n) output stages, each of which includes corresponding inverters 224-0, 224-1, 224-2, ..., 224-(n-1) and corresponding capacitors C0, C1, C2, ..., C... n-1 Capacitors C0, C1, C2, ..., C n-1 They are all connected to output node N1. Figure 2A In one embodiment, the DAC circuit 220 uses inverters 224-0, 224-1, 224-2, ..., 224-(n-1) as drivers for low-power operation.

[0046] The digital logic interface and timing control block 222 includes control circuitry and logic elements to process the input digital baseband signal and output an n-bit data signal (D0, D1, D2, ..., D...) at a given sampling rate of the DAC circuit 220. n-1 Given an n-bit data signal (D0, D1, D2, ..., D...), n-1 The data bits are input to the corresponding inverters 224-0, 224-1, 224-2, ..., 224-(n-1), where the inverters generate output voltages to the corresponding capacitors C0, C1, C2, ..., Cn. n-1 The voltage across the capacitors is used for charging / discharging. In this exemplary embodiment, at any given time, the voltage across the output node N1 includes the voltage across capacitors C0, C1, C2, ..., C1. n-1 The sum of voltages across capacitors C0, C1, C2, ..., C at any given time n-1 The voltage on the output capacitor C 10 Charging / discharging generates an analog voltage waveform at output node N1 over time. Specifically, for an n-bit data signal (D0, D1, D2, ..., D...), ... n-1 ), enable 2 at any given time nOne of a different set of inverters 224-0, 224-1, 224-2, ..., 224-(n-1) (e.g., with a positive input data pulse) is used to generate an output voltage at node N1 representing an n-bit data signal that is applied to the input of inverters 224-0, 224-1, 224-2, ..., 224-(n-1) at a given time.

[0047] In some embodiments, inverters 224-0, 224-1, 224-2, ..., 224-(n-1) are implemented using CMOS inverter circuitry. For example, Figure 2B The illustration schematically depicts an exemplary embodiment of the present disclosure. Figure 2A The CMOS inverter circuit 224-i is implemented in the DAC circuit 220. The CMOS inverter circuit 224-i includes a PMOS transistor 226-1 and an NMOS transistor 226-2 connected in series between a positive power supply voltage node (e.g., the VDD power supply voltage rail) and a negative power supply voltage node (e.g., the VSS power supply voltage rail). The source terminal of the PMOS transistor 226-1 is connected to the VDD power supply voltage rail, and the source terminal of the NMOS transistor 226-2 is connected to the VSS power supply voltage rail. In some embodiments, VDD = 350mV and VSS = 0V. Transistors 226-1 and 226-2 have a common gate terminal for receiving input data bits Di. Transistors 226-1 and 226-2 have a common drain terminal connected to the output node of the inverter circuit 224-i.

[0048] The operation of inverter circuit 224-i is well known. When the input data bit Di has a logic "1" level, NMOS transistor 226-2 is turned on, while PMOS transistor 226-1 is turned off. In this case, the inverter output voltage is pulled to VSS, which is low. When the input data bit Di has a logic "0" level, a complementary situation occurs, where PMOS transistor 226-1 is turned on, and NMOS transistor 226-2 is turned off. In this state, the inverter output voltage is pulled up to VDD, which is high.

[0049] As noted above, at any given time, the voltage across output node N1 includes capacitors C0, C1, C2, ..., C n-1 The sum of the voltages across the capacitors. In some embodiments, capacitors C0, C1, C2, ..., C n-1 This includes binary-weighted capacitance values. In other embodiments, capacitors C0, C1, C2, ..., C... n-1This includes unary-weighted capacitor values. In some embodiments, binary-weighted capacitor values ​​are used when the DAC circuit 220 implements a relatively small number of bits to provide a sufficient range of output voltages. In some embodiments, unary-weighted capacitor values ​​are used when the DAC circuit 220 implements a relatively large number of bits, wherein the unary-weighted capacitor values ​​provide finer resolution and greater linearity in the voltage output levels of the DAC circuit 220.

[0050] It should be understood that DAC circuit 220 provides an exemplary architecture in which the DAC output voltage at output node N1 of DAC circuit 220 may have a voltage level (e.g., average voltage level, peak voltage level, etc.) lower than the negative supply voltage VSS. The following will combine... Figure 4A An exemplary output voltage waveform that can be generated at the output node N1 of the DAC circuit 220 is discussed in further detail. In this regard, the DAC circuit 220 provides an exemplary architecture to extend the useful dynamic range of the DAC circuit 220, wherein the analog voltage waveform output from the DAC circuit 220 sweeps and oscillates below VSS, and thus extends the dynamic range of the transmitter implementing the DAC circuit 220.

[0051] like Figure 2A Further illustrating, filter circuit 230 includes an input directly coupled to the output node N1 of DAC circuit 220. Filter circuit 230 is configured to filter the analog baseband voltage signal generated at the output node N1 of DAC circuit 220, and to generate a filtered analog baseband voltage signal at the output node N3 of filter circuit 230, wherein the filtered analog baseband voltage signal includes voltage levels (e.g., average voltage level, peak voltage level, etc.) less than the negative supply voltage VSS. Figure 2A In an exemplary embodiment, the input of filter circuit 230 is directly coupled (e.g., directly DC coupled) to the output node N1 of DAC circuit 220. Filter circuit 230 is configured to filter the analog voltage waveform that is the output of DAC circuit 220 without requiring DC level shifting of the analog voltage waveform at the input of filter circuit 230.

[0052] Filter circuit 230 includes bias circuit 231, which is configured to generate a bias current I for operating filter circuit 230 at a given operating point. BIAS The bias circuit 231 includes a current mirror circuit, which includes PMOS transistors 232 and 233 and a current source 234. The current source 234 generates a constant reference current I flowing through the PMOS transistor 232. REF This causes the PMOS transistor 232 to generate a current I equal to the reference current. REF Proportional (e.g., a 1:1 ratio or greater) bias current IBIAS The operation of the current mirror circuit 231 is known, and therefore its detailed description is not required to understand the exemplary embodiments described herein.

[0053] Filter circuit 230 includes an analog dual-secondary low-pass filter frame, which includes transistor 235 (e.g., a PMOS transistor), a first resistor R1, a second resistor R2, and a first capacitor C. 11 Second capacitor C 12 Transistor 235 includes a gate terminal, a first source / drain terminal, and a second source / drain terminal. Specifically, in an exemplary embodiment where transistor 235 is a PMOS transistor, the first source / drain terminal includes a source terminal coupled to the feedback path of filter circuit 230, and the second source / drain terminal includes a drain terminal coupled to the negative power supply voltage node VSS. The gate terminal of transistor 235 is coupled to the output node N3 of filter circuit 230.

[0054] like Figure 2A As further shown, the first resistor R1 is coupled between the output node N1 of the DAC circuit 220 and the feedback node N2 of the filter circuit 230. The second resistor R2 is coupled between the feedback node N2 and the output node N3 of the filter circuit 230. The first capacitor C 11 Coupled in the feedback path between feedback node N2 and the first source / drain terminal of transistor 235. Second capacitor C 12 Coupled between the output node N3 of filter circuit 230 and the negative power supply voltage node VSS. The first source / drain terminal (e.g., the source terminal) of transistor 235 is coupled to the output of bias circuit 231, causing the bias current I... BIAS The current flows in the channel of transistor 235 to set the operating point of filter circuit 230.

[0055] It should be understood that Figure 2A The filter circuit 230 provides a novel design for a low-pass second-order Sallen-Key filter (or positive feedback filter) implemented using a single transistor 235, instead of an operational amplifier as typically implemented in conventional Sallen-Key filter and dual-secondary low-pass filter designs. In this respect, compared to conventional dual-secondary low-pass filter circuits, Figure 2A The implementation of the single-transistor dual-secondary low-pass filter circuit 230 in the diagram provides lower power consumption and a smaller coverage area (less footprint). Figure 2A In the filter circuit 230, the first source / drain terminal (e.g., the source terminal) of transistor 235 is connected via a first capacitor C. 11 Connect to feedback node N2 to realize the filter feedback loop.

[0056] Figure 2A The exemplary design of the filter circuit 230 allows for direct DC coupling between the output node N1 of the DAC circuit 220 and the input node of the filter circuit 230. This allows the analog voltage waveform at the input node of the filter circuit 230 to oscillate along the negative power rail VSS, even though the filter circuit 230 is DC biased between the positive VDD and negative VSS power rails. Furthermore, the output node N3 of the filter circuit 230 includes a high-impedance node. Using this filter configuration, the output node N3 of the filter circuit 230 can be supplied to an antenna or sensor device, or it can be up-converted by the modulation stage 140 and then supplied to an antenna or sensor device.

[0057] It should be understood that, such as Figure 2A The exemplary DAC circuit 220 and filter circuit 230 shown can be used to implement Figure 1 The first DAC circuit 121 and the first filter circuit 131 in the DAC stage 120 and filter stage 130 of the transmitter 100 convert the digital in-phase (I) baseband signal into an in-phase analog baseband signal I(t) and perform low-pass filtering on the in-phase analog baseband signal I(t). Similarly, as Figure 2A The exemplary DAC circuit 220 and filter circuit 230 shown can be used to implement Figure 1 The transmitter 100's DAC stage 120 and filter stage 130 contain a second DAC circuit 122 and a second filter circuit 132, which convert the digital quadrature phase (Q) baseband signal into a quadrature phase analog baseband signal Q(t) and perform low-pass filtering on the quadrature phase analog baseband signal Q(t). In this regard, for a single-ended DAC and filter configuration, the transmitter 100's DAC stage 120 and filter stage 130 will be implemented using two of the DAC circuits 220 and two of the filter circuits 230, one DAC circuit 220 and one filter circuit 230 for each I and Q baseband channel.

[0058] On the other hand, for the differential DAC and filter configuration, the first DAC circuit 121 can be used Figure 2A The two DAC circuits 220 shown are used to implement this, with one DAC circuit 220 configured to generate an in-phase analog baseband signal I(t) and the other DAC circuit 220 configured to generate a complementary in-phase analog baseband signal. It is essentially an inverted version of the in-phase analog baseband signal I(t). Similarly, for a differential DAC and filter configuration, the second DAC circuit 122 can be used... Figure 2A The two DAC circuits 220 shown are used to implement this, with one DAC circuit 220 configured to generate an orthogonal phase analog baseband signal Q(t) and the other DAC circuit 220 configured to generate a complementary orthogonal phase analog baseband signal. It is essentially an inverted version of the quadrature phase analog baseband signal Q(t).

[0059] Similarly, for a differential DAC and filter configuration, the first filter circuit 131 of the filter stage 130 of the transmitter 100 can be used Figure 2A The filter circuits 230 shown are implemented in two ways, one of which is configured to filter the in-phase analog baseband signal I(t), and the other is configured to filter complementary in-phase analog baseband signals. Filtering is performed. Furthermore, for differential DAC and filter configurations, the second filter circuit 132 of the filter stage 130 of transmitter 100 can be used... Figure 2A The filter circuits 230 shown are implemented in two ways, one of which is configured to filter the quadrature phase analog baseband signal Q(t), and the other is configured to filter the complementary quadrature phase analog baseband signal. Perform filtering.

[0060] Figure 3 A modulation circuit according to an exemplary embodiment of the present disclosure is schematically illustrated. In some embodiments, Figure 3 Schematic illustration of what can be done Figure 1 The modulation circuit 300 is implemented in the modulation stage 140 of the transmitter 100. Specifically, Figure 3 An exemplary SSB modulation circuit 300, including a dual-balanced Gilbert mixer unit configuration, is schematically shown according to an exemplary embodiment of the present disclosure. Figure 3 An exemplary embodiment of an SSB modulation circuit 300 is shown, the SSB modulation circuit 300 being configured to generate an output voltage waveform V including an average voltage of approximately 0V and a peak voltage less than that of the negative power supply node VSS. OUT It should be understood that, for ease of explanation, Figure 3 An exemplary SSB dual-balanced mixer circuit configuration is schematically shown, wherein a first mixer circuit 141 (I mixer) is shown for a differential DAC and filter configuration, while a second mixer circuit 142 (Q mixer) is not shown. Figure 3 As shown in the diagram. In this regard, Figure 3 An exemplary embodiment of the SSB modulation circuit 300 is shown, wherein the complementary pair I(t) of the in-phase analog baseband signal and And the complementary pair LO_I of the in-phase LO signal and It is input to the modulation circuit 300.

[0061] The modulation circuit 300 includes a DC bias stage 310, a degeneration resistor RD, a baseband signal input and processing stage 320, a mixer stage 330, and a signal output stage 340 (e.g., a signal combiner circuit). The DC bias stage 310 includes PMOS transistors 312 and 314, and degeneration capacitors 316 and 318. PMOS transistor 312 and degeneration capacitor 316 are connected in parallel, and PMOS transistor 314 and degeneration capacitor 318 are connected in parallel. PMOS transistors 312 and 314 include a receiver for a DC bias voltage V. BIAS To generate static DC bias current I in each branch of the modulation circuit 300 BIAS The gate terminal. In some embodiments, a DC bias voltage V equal to zero volts. BIAS (V BIAS =0V) is applied to the gate terminals of transistors 312 and 314. As will be understood by those skilled in the art, the degradation resistor RD is connected across the bias branch of the modulation circuit 300 and is configured to improve the linear operation of the modulation circuit 300.

[0062] The output of the DC bias stage 310 is coupled to the baseband signal input and processing stage 320. The baseband signal input and processing stage 320 includes PMOS transistors 322 and 324. In some embodiments, PMOS transistors 322 and 324 include gate terminals coupled to the output nodes of a complementary pair of filter circuits. For example, for Figure 2A The differential configuration of the DAC circuit 220 and filter circuit 230 shown indicates that the gate terminal of the PMOS transistor 322 is directly coupled to the generated complementary in-phase analog baseband signal. The output node N3 of the filter circuit 230 is directly coupled to the output node N3 of the filter circuit 230 that generates the filtered in-phase analog baseband signal I(t).

[0063] The baseband signal input and the output of processing stage 320 are coupled to the input of mixer stage 330. Mixer stage 330 includes switching PMOS transistors 332, 334, 336, and 338. Switching transistors 332 and 334 have a common source terminal that provides a first input to mixer stage 330, which is connected to the baseband signal input and a first output of processing stage 320 (e.g., the drain terminal of transistor 322). Similarly, switching transistors 336 and 338 have a common source terminal that provides a second input to mixer stage 330, which is connected to the baseband signal input and a second output of processing stage 320 (e.g., the drain terminal of transistor 324).

[0064] like Figure 3As further shown, the in-phase local oscillator signal LO_I is applied to the gate terminals of switching transistors 332 and 338, while the complementary in-phase local oscillator signal... Applications are made to the gate terminals of switching transistors 334 and 336. Furthermore, switching transistors 334 and 338 include a common drain terminal that provides a first output of mixer stage 330, which is connected to a first node N1 of signal output stage 340. Similarly, switching transistors 332 and 336 include a common drain terminal that provides a second output of mixer stage 330, which is connected to a second node N2 of signal output stage 340.

[0065] Signal output stage 340 includes inductors 342 and 346, and capacitors 344 and 348. Inductor 346 and capacitor 348 are connected in parallel between the first node N1 and the negative power supply voltage node VSS. Inductor 342 and capacitor 344 are connected in parallel between the second node N2 and the negative power supply voltage node VSS. Signal output stage 340 generates an output voltage VOUT, such as the differential output voltage Vout on nodes N1 and N2. OUT + and V OUT - The signal output stage 340 includes... Figure 1 An exemplary embodiment of the signal combiner circuit 143 of the modulation stage 140.

[0066] In the complementary pair I(t) of the in-phase analog baseband signal and The baseband signal input and the input of the processing stage 320 are applied, and the in-phase LO signal LO_I and During operation, when the complementary pair is applied to the input of mixer stage 330, switching transistors 334 and 338 of mixer stage 330 generate an output current x_m, which is applied to the first node N1 to drive LC circuits 346 and 348 and thereby generate a voltage V at the first node N1. OUT + Similarly, the switching transistors 332 and 336 of the mixer stage 330 generate an output current x_p, which is applied to the second node N2 to drive the LC circuits 342 and 344, thereby generating a voltage V at the second node N2. OUT _ .

[0067] As noted above, the modulation circuit 300 includes a second Giber mixer unit (e.g., a Q mixer unit, not shown), which includes a DC bias stage 310, a degradation resistor RD, a baseband signal input and processing stage 320, and a copy of a mixer stage 330 for processing and mixing the quadrature-phase analog baseband signal Q(t) and the quadrature-phase local oscillator signal LO_Q. Specifically, the baseband signal input and processing stage 320 for the Q mixer unit will receive the complementary pair Q(t) and the quadrature-phase analog baseband signal LO_Q. As input, and the Q mixer stage will receive the complementary pair LO_Q and quadrature phase LO signals. As input, the two outputs of the Q mixer stage will be coupled to... Figure 3 The nodes N1 and N2 of the signal output stage 340 shown are such that the output current signals x_m of the I and Q mixer units will be combined at the first node N1, while the output current signals x_p of the I and Q mixer units will be combined at the second node N2.

[0068] In other embodiments, Figure 1 The transmitter 100 can be configured to generate an RF output signal having a transmit frequency at the baseband frequency. In this example, the modulation stage 140 (or modulation circuit 300) can be configured to operate with a LO frequency signal (e.g., LO_I) held at a logic "0" level (i.e., LO_I = 0V), while disabling the Q mixer unit, thereby enabling the differentially filtered analog baseband signal I(t) and It can reach the amplifier driver stage 150 through the modulation stage 140 without up-converting to a higher frequency. In this configuration, the complementary pair I(t) of the filtered analog baseband signal and Input to modulation stage 140 ( Figure 1 The first mixer circuit 141, or the modulation circuit 300 () Figure 3 The frequency will not be up-converted to a higher center frequency through the operation of the mixer circuit.

[0069] In other words, in order to enable the baseband operation mode of transmitter 100, Figure 1 The DAC stage 120, filter stage 130, and modulation stage 140 of the transmitter 100 will be configured to bypass the modulation stage 140 by applying a 0V static LO_I signal to the LO input of the first mixer circuit 141 (e.g., Figure 3 The up-conversion operation of the modulation circuit 300 in the middle, in Figure 3 In an exemplary embodiment, this would keep switching transistors 332 and 338 in the ON state and switching transistors 334 and 336 in the OFF state, thereby substantially allowing complementary filtering of the analog baseband signal I(t) and Outputs are made at nodes N1 and N2 of output stage 340. Furthermore, for baseband operation, the Q-processing circuit blocks of signal processing stages 120, 130, and 140 (e.g., the second DAC circuit 122, the second filter circuit 132, and the second mixer circuit 142) can be powered off to save power.

[0070] It should be understood that, such as Figure 2A and Figure 3 The signal processing stage of the DAC circuit 220, filter circuit 230, and modulation circuit 300 shown operates together to generate an analog AC voltage signal having a voltage level that swings below the negative power supply rail VSS. In this respect, although the DAC circuit 220, filter circuit 230, and modulation circuit 300 operate with a static DC bias limited by the positive and negative power supply rails, as... Figure 2A and Figure 3 The circuit configuration of the DAC circuit 220, filter circuit 230, and modulation circuit 300 shown essentially allows the dynamic range of the DAC, filter, and modulation signal processing stages to be extended below the VSS power rail, thereby providing ultra-low power operation for transmitters implementing such signal processing stages.

[0071] For example, Figure 4A The exemplary embodiments shown herein are available from [the present disclosure]. Figure 2A The DAC circuit 220 generates a voltage waveform of 400. Specifically, Figure 4A A simulated voltage waveform 400 is shown, which can be generated by DAC circuit 220 at its output node N1 and directly applied to the input node of filter circuit 230. Voltage waveform 400 includes multiple incremental voltage step transitions that form the analog voltage output signal 400 over time (as shown in nanoseconds (ns)). Figure 4A In the exemplary embodiment shown, the voltage waveform 400 includes a period T of approximately 20 ns, and the voltage level swings from approximately +20 mV to approximately -170 mV, wherein it is assumed that the positive power supply voltage rail VDD is 350 mV and the negative power supply voltage rail VSS is 0 V. Figure 4A The waveform 400 of the DAC output voltage is shown to have a voltage level less than VSS for most of the time. Furthermore, Figure 4A The output voltage waveform 400 is shown to include an average voltage level of approximately -80mV. With a positive supply voltage rail of 350mV, it can be seen that the output voltage of the DAC circuit 220 can have an effective rail-to-rail voltage swing of 350mV - (-170mV) = 520mV, which is significantly greater than the actual rail-to-rail voltage difference of VDD - VSS = 350mV.

[0072] In other words, although the outputs of the inverters 224-0, 224-1, 224-2, ..., 224-(n-1) of the DAC circuit 220 have a rail-to-rail voltage swing limited to VDD-VSS = 350mV, the output node N1 of the DAC circuit 220 includes an isolated capacitor node (isolated from the power supply node (e.g., the VDD node)) used to drive the output capacitors C0, C1, C2, ..., C... n-1 The implementation of inverters 224-0, 224-1, 224-2, ..., 224-(n-1) allows scaling capacitor C at the output node of DAC circuit 220. 10 The voltage on the VSS power rail oscillates below the VSS power rail.

[0073] Furthermore, as noted above, filter circuit 230 is configured for direct DC coupling to the output node N1 of DAC circuit 220 without requiring DC level shifting at the input of filter circuit 230, because filter circuit 230 is configured to receive and filter DAC output voltage waveforms having voltage levels below the negative supply voltage rail VSS. For example, Figure 4B The diagram schematically illustrates a filtered voltage waveform generated by a filter circuit according to an exemplary embodiment of the present disclosure. Specifically, Figure 4B The diagram illustrates the operation of the filter circuit 230 to... Figure 4A The simulated voltage waveform 410 is generated by low-pass filtering the DAC output voltage waveform 400.

[0074] like Figure 4B As shown, the filter voltage waveform 410 comprises a smooth sine wave with the same period T (e.g., approximately 20 ns) as the DAC output voltage waveform 400, but in which the entire filter voltage waveform 410 is below the negative supply voltage rail VSS. Figure 4B An exemplary filtered voltage waveform 410 is shown, which is output from the output node N3 of the filter circuit 230 and directly applied (directly coupled) to... Figure 3 The modulation circuit 300 includes a baseband signal input and processing stage 320. In this regard, Figure 3 The modulation circuit 300 is configured to receive the filtered voltage waveform 410 output from the filter circuit 230 without having to apply a DC level shift between the output node N3 of the filter circuit 230 and the baseband signal input and the input of the processing stage 320.

[0075] In other words, modulation circuit 300 includes a circuit configuration that allows direct coupling to the output node of filter circuit 230 for input and processing of the filtered voltage waveform output from filter circuit 230, wherein the filtered voltage waveform has a voltage level (e.g., peak voltage level, average voltage level, etc.) below the negative supply voltage rail VSS. Modulation circuit 300 utilizes a low bias voltage (e.g., V... BIAS The circuit consists of a stack of PMOS transistors (0V) and a signal output stage 340, wherein the first node N1 and the second node N2 are inductively loaded via inductors 342 and 346 and coupled to the negative supply voltage rail VSS through inductors 342 and 346. This circuit configuration allows the mixer stage 330 to mix the low-voltage (filtered) analog baseband voltage waveform directly applied to the baseband signal input and the input of the processing stage 320 with the local oscillator signal input to the mixer stage 330, while allowing the output voltage VSS on the first node N1 and the second node N2 of the signal output stage 340 to be... OUT It oscillates below the negative supply voltage rail VSS. In some embodiments, the output voltage V at nodes N1 and N2 of signal output stage 340... OUT It will have an average voltage of approximately 0V, and a peak voltage that swings below the negative supply voltage rail VSS.

[0076] Although Figure 2A , Figure 2B and Figure 3 An exemplary embodiment is shown in which the transmitter's signal processing stage is configured to generate a dynamic voltage signal waveform having a voltage level (e.g., peak voltage level, average voltage level, etc.) less than the negative supply voltage rail VSS. However, in other embodiments, the transmitter's signal processing stage may be configured to generate a dynamic voltage signal waveform having a voltage level (e.g., peak voltage level, average voltage level, etc.) greater than the positive supply voltage rail VDD. For example, Figure 5 The diagram schematically illustrates a circuit block 500 including a DAC circuit 520 and a filter circuit 530 according to another exemplary embodiment of the present disclosure, which can... Figure 1 Implemented in the DAC stage 120 and filter stage 130 of the transmitter 100 to effectively extend the dynamic range of the signal processing stage above the VDD power rail.

[0077] Specifically, Figure 5 The voltage-mode DAC circuit 520 is shown, which includes similar components to... Figure 2A The architecture of the voltage-mode DAC circuit 220 is described, but the DAC circuit 520 includes a voltage-mode output stage 524 configured to generate an analog output voltage at the output node N1 of the DAC circuit 520, the analog output voltage having a voltage level exceeding the positive supply voltage rail VDD. Specifically, as... Figure 5As shown, the voltage-mode output stage 524 includes an inductor L coupled between the output node N1 and the VDD power supply voltage rail. 10 In this exemplary embodiment, the output node N1 includes an inductor L. 10 and scaling capacitor C 10 The nodes between. In this configuration, since the output node N1 is inductively coupled to the positive supply voltage node VDD, therefore, the output (scaling) capacitor C... 10 The generated output voltage can rise to a voltage level greater than the positive power supply voltage VDD.

[0078] like Figure 5 As further shown, the filter circuit 530 includes an input directly coupled to the output node N1 of the DAC circuit 520. The filter circuit 530 has a similar... Figure 2A The filter circuit 230 is configured such that the filter circuit 530 is configured to filter an analog baseband voltage signal output at the output node N1 of the DAC circuit 520 and including a voltage level (e.g., average voltage level, peak voltage level, etc.) greater than the positive supply voltage VDD, thereby generating a filtered analog baseband voltage signal at the output node N3 of the filter circuit 530, which includes a voltage level (e.g., average voltage level, peak voltage level, etc.) greater than the positive supply voltage VDD. Figure 5 In an exemplary embodiment, the input of the filter circuit 530 is directly coupled (e.g., directly DC coupled) to the output node N1 of the DAC circuit 520, wherein the filter circuit 530 is configured to filter the analog voltage output of the DAC circuit 520 without requiring DC level shifting of the analog voltage signal at the input of the filter circuit 530.

[0079] Figure 5 The filter circuit 530 is similar to Figure 2A The filter circuit 230, but includes an "inverting" circuit configuration that implements NMOS transistors 532, 533, and 535, instead of Figure 2A The filter circuit 230 includes PMOS transistors 232, 233, and 235, and the current mirror circuit 531 includes a reference current source 534 coupled to the VDD power rail. It should be understood that... Figure 5 The low-pass filter circuit 530 is similar to Figure 2A The low-pass filter circuit 230 operates in a manner that, except that the filtered voltage waveform output at the output node N3 has a voltage level greater than the positive supply voltage VDD (e.g., peak voltage level, average voltage level, etc.).

[0080] It should be understood that Figure 3The modulation circuit 300 can be modified to have an "inverted" circuit configuration to allow the output voltage of the output stage 340 to have a peak voltage level extending above the positive supply voltage rail VDD and an average voltage level of approximately 0V. Specifically, the modulation circuit 300 can be modified by replacing the PMOS transistors 312, 314, 322, 324, 332, 334, 336, and 338 with NMOS transistors, connecting the DC bias stage 310 to the VSS power supply trunk, and connecting the signal output stage 340 to the VDD power supply rail. In this inverted circuit configuration of the modulation circuit, the mixer stage 330 will... Figure 5 The output node N3 of the filter circuit 530 is directly applied to the baseband signal input and the filtered analog baseband voltage waveform of the processing stage 320, which is then mixed with the local oscillator signal input to the mixer stage 330. Simultaneously, it allows the output voltage V at the first node N1 and the second node N2 of the signal output stage 340 to be mixed. OUT It swings above the positive supply voltage rail VDD. In this configuration, the inductive coupling of nodes N1 and N2 to the VDD rail via inductors 342 and 346 will allow the output voltage V on nodes N1 and N2 to oscillate. OUT The peak voltage level oscillates above the VDD power rail.

[0081] It should be understood, for example Figure 2A , Figure 3 and Figure 5 The exemplary embodiments of the DAC, filter, and modulation circuitry shown allow for increased signal processing with voltage swings greater than those of the VDD and VSS power rails. In conventional systems, when lower supply voltages (e.g., lower VDD) are used, the difference between the positive and negative power rails decreases, which reduces the circuit's dynamic signal processing capability. However, as noted above, the exemplary embodiments described herein implement isolated intermediate nodes that allow the output voltages generated by the various signal processing stages (e.g., DAC and filter stages) to swing above or below the VDD rail, thereby allowing the signal processing stages to process analog signals with peak-to-peak signal amplitudes greater than those that would otherwise be limited by the VDD and VSS power rails.

[0082] Figure 6A A multi-channel transmitter according to an exemplary embodiment of the present disclosure is schematically illustrated. Specifically, Figure 6A A transmitter 600 is schematically shown comprising multiple (c) transmitter channels 600-1, 600-2, ..., 600-c. The number of transmitter channels c will vary depending on the application. In some embodiments, each transmitter channel 600-1, 600-2, ..., 600-c includes a similar circuit configuration. For example, in some embodiments, such as... Figure 6AAs shown, each transmitter channel 600-1, 600-2, ..., 600-c includes... Figure 1 The single-channel transmitter 100 shown has the same channel architecture and can achieve, for example, Figure 2A , Figure 2B , Figure 3 and / or Figure 5 The diagram shows the DAC circuit, filter circuit, and modulation circuit.

[0083] Figure 6A An exemplary embodiment is schematically illustrated in which different transmitter channels 600-1, 600-2, ..., 600-c are configured to operate at different center frequencies. More specifically, in some embodiments, the modulation stage 140 in transmitter channel 600-1 is configured to perform IQ modulation using the LO frequency of LO1, while the modulation stages 140 in transmitter channels 600-2, ..., 600-c are configured to perform IQ modulation using different LO frequencies LO2, ..., LO-c greater than LO1. This allows the multi-channel transmitter 600 to simultaneously transmit the information content of the digital IQ baseband signals input to each transmitter channel 600-1, 600-2, ..., 600-c to different nodes configured to operate at different receiver center frequencies.

[0084] like Figure 6A As further shown, antennas 610-1, 610-2, ..., 610-c are coupled to corresponding outputs of transmitter channels 600-1, 600-2, ..., 600-c. In some embodiments, antennas 610-1, 610-2, ..., 610-c include individual antennas having corresponding antenna bandwidths corresponding to the RF output signal frequencies of the different transmitter channels 600-1, 600-2, ..., 600-c. In other embodiments, transmitter channels 600-1, 600-2, ..., 600-c are coupled to a single broadband antenna element having an antenna bandwidth configured to efficiently radiate energy at the RF output signal frequencies of the different transmitter channels 600-1, 600-2, ..., 600-c.

[0085] Figure 6B The diagram schematically illustrates an LO signal generator circuit 620 according to an exemplary embodiment of the present disclosure, which can be implemented to generate a signal for... Figure 6ADifferent LO signals for a multi-channel transmitter. In some embodiments, the LO signal generator circuit 620 includes a phase-locked loop (PLL) circuit 622 and multiple frequency multiplier circuits 624-2, ..., 624-c coupled to the output of the PLL circuit 622. The PLL circuit 622 is configured to receive a reference clock signal (REF CLK) as input and generate a first local oscillator signal LO1 applied to the LO1 port of transmitter channel 600-1 of transmitter 600. The LO1 signal is used to generate local quadrature signals LO1_I and LO1_Q for modulation stage 140 of transmitter channel 600-1 using a local quadrature phase shifter circuit. Figure 6B As further shown, the first local oscillator signal LO1 is input to each frequency multiplier circuit 624-2, ..., 624-c, which generates corresponding LO signals LO2, ..., LO-c. These LO signals are used by the corresponding transmitter channels 600-2, ..., 600-c to generate local quadrature signals for the corresponding modulation stage 140.

[0086] Figure 7 A multi-channel transmitter according to an exemplary embodiment of the present disclosure is schematically illustrated. Specifically, Figure 7 A transmitter 700 is schematically shown comprising multiple (c) transmitter channels 700-1, 700-2, ..., 700-c. The number of transmitter channels c will vary depending on the application. In some embodiments, each transmitter channel 700-1, 700-2, ..., 700-c includes a similar transmitter circuit configuration, wherein each transmitter channel 700-1, 700-2, ..., 700-c includes... Figure 1 The single-channel transmitter 100 shown has the same channel architecture and can achieve Figure 2A , Figure 2B , Figure 3 and / or Figure 5 The diagram shows the DAC circuit, filter circuit, and modulation circuit.

[0087] like Figure 7As further shown, individual antenna elements 710-1, 710-2, ..., 710-c are coupled to the corresponding outputs of transmitter channels 700-1, 7002, ..., 700-c. In some embodiments, antenna elements 710-1, 710-2, ..., 710-c form an antenna array to realize a phased array antenna system, wherein the radiation pattern of each individual antenna element 710-1, 710-2, ..., 710-c is advantageously combined with adjacent antennas to form an effective radiation pattern called the main lobe. Using a phased array antenna configuration, the main radiation lobe transmits energy in a desired direction (e.g., beam scanning). On the other hand, the radiation patterns of each individual antenna element 710-1, 710-2, ..., 710-c adversely interfere with each other in undesirable directions, forming nulls and sidelobes. At this point, the antenna array is designed to maximize the energy radiated in the main lobe while reducing the energy radiated in the sidelobes to an acceptable level. The direction of the main lobe of radiation can be manipulated by changing the phase of the RF output signal, which is fed from the corresponding outputs of transmitter channels 700-1, 700-2, ..., 700-c to each individual antenna element 710-1, 700-2, ..., 710-c.

[0088] In some embodiments, the necessary phase delay of the RF output signals from transmitter channels 700-1, 700-2, ..., 700-c is achieved in the digital domain by adding a delay to the digital IQ baseband signals of the DAC stage 120 input to transmitter channels 700-1, 700-2, ..., 700-c. For example, as... Figure 7 As shown, transmitter channel 700-1 receives digital baseband signals I1 and Q1, transmitter channel 700-2 receives digital baseband signals I2 and Q2, and transmitter channel 700-c receives digital baseband signal I... C and Q C And so on. The digital baseband signals I1 / Q1, I2 / Q2, ..., I received by the corresponding transmitter channels 700-1, 700-2, ..., 700-c are... C / Q C The information content includes the same IQ baseband signal, but each transmitter channel 700-1, 700-2, ..., 700-c receives a different delayed version of the digital IQ baseband signal. The phase delay in the digital domain results in multiple corresponding phase-delayed RF output signals being generated by the respective transmitter channels 700-1, 700-2, ..., 700-c. These RF output signals are output to the antenna array (710-1, 710-2, ..., 710-c), thereby generating a directional radiation beam radiated from the antenna array.

[0089] Figure 8A sensor node for implementing a transmitter according to an exemplary embodiment of the present disclosure is schematically shown. More specifically, Figure 8 A sensor node 800 is schematically shown, comprising an antenna system 810, one or more receivers 820 (e.g., single-channel or multi-channel receivers), one or more transmitters 830 (e.g., single-channel or multi-channel transmitters), one or more digital processors 840, one or more sensors 850, a memory 860, a power management system 870, and a clock signal generator 880. In some embodiments, the sensor node 800 includes a node in a sensor network configured to collect and process sensor information and communicate with other nodes in the network (e.g., sensor nodes, computing nodes, etc.).

[0090] Antenna system 810 includes one or more antenna elements (e.g., broadband antennas, narrowband antenna elements, antenna arrays, etc.), antenna feed elements and networks, duplexers, etc. In some embodiments, antenna system 810 includes printed antenna elements or discrete components, such as whip antennas. Receiver 820 and transmitter 830 together provide a transceiver system coupled to antenna system 810. In some embodiments, the methods discussed above (e.g., Figure 1 , Figure 6A and Figure 7 Transmitter 830 is implemented using one of the exemplary transmitter architectures (e.g., etc.).

[0091] The digital processor 840 includes one or more processors, such as a CPU, microcontroller, digital signal processor, ASIC, FPGA, etc., configured to control the operation of the sensor node 800 and its components, and to collect and process sensor data. Specifically, in some embodiments, the digital processor 840 includes a microcontroller configured to generate inputs to, for example... Figure 1 The digital control signals of each signal processing stage of the transmitter are shown to configure the hardware configuration of these stages to change operating parameters, such as adjusting the gain and controlling the LO frequency.

[0092] Sensor 850 is used to capture data within a given environment. For example, sensor 850 includes hardware devices that generate measurable signals in response to changes in physical conditions such as temperature, pressure, humidity, light, etc. In some embodiments, sensor 850 generates analog signals, which are then digitized and processed by a digital signal processor. In some embodiments, this is achieved by converting digital sensor data into digital IQ baseband signals (e.g., via...). Figure 1 The component 110 converts the digital IQ baseband signal into an analog baseband voltage signal and optionally upconverts the analog baseband voltage signal to a higher transmission frequency, thereby generating an RF output signal via transmitter 830 for wireless transmission via antenna system 810, transmitting sensor data to a remote node.

[0093] The memory 860 includes volatile memory (such as RAM, cache) and non-volatile memory used by the digital processor 840, such as flash memory for storing sensor and application-related data and for storing software or code for programming and controlling the operation and function of the sensor node 800.

[0094] The power management system 870 includes various components such as power supplies (e.g., batteries, capacitors), voltage regulation circuitry, and power management systems (e.g., dynamic power management (DPM) systems or dynamic voltage scaling (DVS) systems), wherein the dynamic power management (DPM) system is configured to power off currently inactive and unused components of the sensor node 800, and the DVS system is configured to adjust the operating power level and / or operating frequency within the sensor node 800 to reduce power consumption.

[0095] Clock signal generator 880 includes various components and circuitry to generate and distribute clock signals for operating sensor node 800. For example, in some embodiments, clock signal generator 880 implements, as... Figure 6B The LO clock signal generator system 620 shown is illustrated.

[0096] Figure 9 A computing system including a network of sensor nodes implementing a transmitter is schematically illustrated according to an exemplary embodiment of the present disclosure. More specifically, Figure 9 This is a high-level schematic diagram of a computing system 900, which includes a sensor network 910, a communication network 930, a computing platform 940, and a remote node management and configuration system 950. The computing platform 940 and the remote node management and configuration system 950 are coupled to the sensor network 910 via the communication network 930. The communication network 930 may include, for example, global computer networks such as the Internet, wide area networks (WANs), local area networks (LANs), satellite networks, telephone or cable networks, cellular networks, wireless networks (such as Wi-Fi or WiMAX), or various portions or combinations of these and other types of networks.

[0097] Sensor network 910 includes multiple sensor nodes 911, 912, 913, 914, 915, 916, 917, and 918, and a gateway 920. Sensor nodes 911, 912, 913, 914, 915, 916, 917, and 918 collectively generate data, which is transmitted to computing platform 940 and used thereto to execute one or more applications. In some embodiments, sensor nodes 911, 912, 913, 914, 915, 916, 917, and 918 each include components such as... Figure 8The sensor node framework is shown. In some embodiments, the sensor network 910 deploys wireless sensor nodes to enable a given Internet of Things (IoT) application.

[0098] Computing platform 940 includes one or more application server nodes and a data storage system, wherein the application server nodes host one or more applications that process data generated by sensor nodes of sensor network 910 to provide one or more services. In some embodiments, computing platform 940 includes an IoT cloud computing system configured to support one or more IoT application domains (e.g., healthcare, energy, manufacturing, etc.). Computing platform 940 manages and processes IoT data received from sensor nodes of sensor network 910 for a given application domain or from multiple sensor networks for different application domains. For IoT applications, computing platform 940 performs data processing and storage functions to support one or more IoT cloud computing applications.

[0099] The remote node management and configuration system 950 allows a sensor network administrator to remotely configure sensor nodes in the sensor network 910. This configuration includes the configuration of reconfigurable hardware within the sensor nodes, as well as the software / firmware configuration of the sensor nodes. For example, in some embodiments, the remote node management and configuration system 950 is configured to allow an administrator to command the microcontroller of a sensor node to selectively configure the signal processing stage of the sensor node's transmitter as needed for a given application or deployment environment.

[0100] Exemplary embodiments of the present invention can be systems, methods, and / or computer program products at any possible level of technical detail integration. A computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to perform aspects of the present invention.

[0101] Computer-readable storage media can be tangible devices capable of retaining and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable optical disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices such as raised structures in recesses on which instructions are recorded, or punch cards, and any suitable combination of the foregoing. As used herein, computer-readable storage media should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses passing through fiber optic cables), or electrical signals transmitted through wires.

[0102] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a suitable computing / processing device, or downloaded via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network) to an external computer or external storage device. The network may include copper cables, optical fibers, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the suitable computing / processing device.

[0103] Computer-readable program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and procedural programming languages ​​such as "C" or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including local area networks (LANs) or wide area networks (WANs), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs) may execute computer-readable program instructions by utilizing the status information of the computer-readable program instructions to personalize the electronic circuitry in order to perform aspects of this invention.

[0104] Various aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0105] These computer-readable program instructions may be provided to a processor of a computer or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and / or other devices to operate in a particular manner, such that the computer-readable storage medium in which the instructions are stored includes an article of writing comprising instructions for implementing aspects of the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0106] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer-implemented process, such that the instructions, which execute on the computer, other programmable apparatus or other device, perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0107] The block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the block diagram may represent a module, segment, or portion of instructions comprising one or more executable instructions for implementing a specified logical function(s). In some alternative implementations, the functions indicated in the blocks may occur in a different order than indicated in the figures. For example, two blocks shown consecutively may actually be performed as a single step, executed simultaneously, substantially simultaneously, with partial or complete time overlap, or these blocks may sometimes be executed in reverse order, depending on the functions involved. It will also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0108] refer to Figure 10 These concepts are illustrated to schematically depict an exemplary architecture of a computing node according to exemplary embodiments of the present disclosure, which can host and execute programs for managing and configuring sensor nodes, including transmitter systems. In some embodiments, Figure 10 This schematically illustrates the configuration for hosting and execution. Figure 9 The remote node management and configuration system 950 compute nodes 1000. For example... Figure 10 As shown, computing node 1000 includes computer system / server 1012, which can operate with many other general-purpose or special-purpose computing system environments or configurations. Examples of known computing systems, environments, and / or configurations suitable for use with computer system / server 1012 include, but are not limited to, personal computer systems, server computer systems, thin clients, fat clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of the above systems or devices.

[0109] Computer system / server 1012 can be described in the general context of computer system executable instructions (such as program modules) executed by the computer system. Typically, program modules can include routines, programs, objects, components, logic, data structures, etc., that perform specific tasks or implement specific abstract data types. Computer system / server 1012 can be implemented in a distributed cloud computing environment, where tasks are performed by remote processing devices linked via a communication network. In a distributed cloud computing environment, program modules can reside in local and remote computer system storage media, including memory storage devices.

[0110] exist Figure 10In the diagram, the computer system / server 1012 in computing node 1000 is shown in the form of a general-purpose computing device. The components of the computer system / server 1012 may include, but are not limited to, one or more processors or processing units 1016, system memory 1028, and a bus 1018 that couples various system components, including system memory 1028, to processor 1016.

[0111] Bus 1018 represents one or more of several types of bus architectures, including memory buses or memory controllers, peripheral buses, accelerated graphics ports, and processor or local buses using any of a variety of bus architectures. By way of example and not limitation, these architectures include the Industry Standard Architecture (ISA) bus, the Micro Channel Architecture (MCA) bus, the Enhanced ISA (EISA) bus, the Video Electronics Standards Association (VESA) local bus, and the Peripheral Component Interconnect (PCI) bus.

[0112] Computer system / server 1012 typically includes various computer system readable media. Such media can be any available media that can be accessed by computer system / server 1012, and it includes volatile and non-volatile media, removable and non-removable media.

[0113] System memory 1028 may include computer system readable media in the form of volatile memory, such as RAM 1030 and / or cache memory 1032. Computer system / server 1012 may also include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 1034 may be provided for reading from and writing to non-removable, non-volatile magnetic media (not shown and generally referred to as "hard disk drives"). Although not shown, disk drives for reading from and writing to removable, non-volatile disks (e.g., "floppy disks") and optical disk drives for reading from or writing to removable, non-volatile optical disks such as CD-ROMs, DVD-ROMs, or other optical media may be provided. In such instances, each may be connected to bus 1018 via one or more data media interfaces. As depicted and described herein, memory 1028 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of embodiments of the invention.

[0114] By way of example and not limitation, a program / utility 1040 having a set (at least one) of program modules 1042, along with an operating system, one or more applications, other program modules, and program data, may be stored in memory 1028. Each of the operating system, one or more applications, other program modules, and program data, or some combination thereof, may include an implementation of a networking environment. Program modules 1042 typically perform functions and / or methods as described herein in embodiments of this disclosure.

[0115] The computer system / server 1012 can also communicate with one or more external devices 1014, such as a keyboard, pointing device, display 1024, etc.; one or more devices that enable a user to interact with the computer system / server 1012; and / or any device (e.g., a network card, modem, etc.) that enables the computer system / server 1012 to communicate with one or more other computing devices. This communication can occur via input / output (I / O) interface 1022. Furthermore, the computer system / server 1012 can communicate with one or more networks (such as a local area network (LAN), a general wide area network (WAN), and / or a public network (e.g., the Internet) via network adapter 1020. As depicted, network adapter 1020 communicates with other components of the computer system / server 1012 via bus 1018. It should be understood that, although not shown, other hardware and / or software components can be used in conjunction with the computer system / server 1012. Examples include, but are not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, SSD drives, and data archive storage systems.

[0116] Furthermore, it should be understood that although this disclosure includes a detailed description of cloud computing, the implementation of the teachings recorded herein is not limited to a cloud computing environment. Rather, embodiments of the invention can be implemented in conjunction with any other type of computing environment now known or developed hereafter.

[0117] Cloud computing is a service delivery model that enables convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, storage, applications, virtual machines, and services) that can be rapidly provisioned and released with minimal management effort or interaction with service providers. This cloud model may include at least five features, at least three service models, and at least four deployment models.

[0118] The features are as follows:

[0119] On-demand self-service: Cloud consumers can unilaterally and automatically provide computing power, such as server time and network storage, as needed, without requiring manual interaction with the service provider.

[0120] Wide network access: Capabilities are available on the network and accessed through standard mechanisms that facilitate the use of heterogeneous thin or fat client platforms (e.g., mobile phones, laptops, and PDAs).

[0121] Resource pooling: A provider's computing resources are pooled to serve multiple consumers using a multi-tenant model, where different physical and virtual resources are dynamically allocated and reallocated based on demand. Location independence has significance because consumers typically do not control or know the exact location of the resources provided, but can specify the location at a higher level of abstraction (e.g., country, state, or data center).

[0122] Rapid and flexible: Capabilities can be provided quickly and flexibly, in some cases automatically, to rapidly expand outward and rapidly release inward. For consumers, the capabilities available for provision often appear unlimited and can be purchased at any time and in any quantity.

[0123] Measuring services: Cloud systems automatically control and optimize resource usage by leveraging metering capabilities at a level of abstraction appropriate to the service type (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported, providing transparency to both the providers and consumers of the services being utilized.

[0124] The service model is as follows:

[0125] Software as a Service (SaaS): The capability offered to consumers is the ability to use the provider's applications running on cloud infrastructure. Applications can be accessed from various client devices through thin client interfaces such as web browsers (e.g., web-based email). Consumers do not manage or control the underlying cloud infrastructure, including the network, servers, operating system, storage, or even individual application capabilities, with the possible exception of limited user-specific application configuration settings.

[0126] Platform as a Service (PaaS): This provides consumers with the ability to deploy applications created or acquired by the consumer onto cloud infrastructure using programming languages ​​and tools supported by the provider. Consumers do not manage or control the underlying cloud infrastructure, including networks, servers, operating systems, or storage, but they have control over the deployed applications and the configuration of possible application hosting environments.

[0127] Infrastructure as a Service (IaaS): This provides consumers with the capability to deliver processing, storage, networking, and other basic computing resources that enable them to deploy and run arbitrary software, which may include operating systems and applications. Consumers do not manage or control the underlying cloud infrastructure, but they do have control over the operating system, storage, deployed applications, and possibly limited control over chosen networking components (e.g., host firewalls).

[0128] The deployment model is as follows:

[0129] Private cloud: Cloud infrastructure operated solely by an organization. It can be managed by the organization or a third party and can exist on-site or off-site.

[0130] Community cloud: Cloud infrastructure shared by several organizations and supporting a specific community with shared concerns (e.g., tasks, security requirements, policies, and compliance considerations). It can be managed by an organization or a third party and can exist on-site or off-site.

[0131] Public cloud: Cloud infrastructure available to the general public or large industrial groups and owned by organizations that sell cloud services.

[0132] Hybrid cloud: A cloud infrastructure is a combination of two or more clouds (private, community, or public) that remain a single entity but are bound together by standardized or proprietary technologies that enable data and applications to be ported (e.g., cloud bursting for load balancing between clouds).

[0133] Cloud computing environments are service-oriented, focusing on statelessness, loose coupling, modularity, and semantic interoperability. At the heart of cloud computing is the infrastructure of a network of interconnected nodes.

[0134] Now for reference Figure 11 The diagram illustrates an illustrative cloud computing environment 1100. As shown, the cloud computing environment 1100 includes one or more cloud computing nodes 1150 to which local computing devices used by cloud consumers can communicate. These local computing devices include, for example, personal digital assistants (PDAs) or cellular phones 1154A, desktop computers 1154B, laptop computers 1154C, and / or automotive computer systems 1154N. The nodes 1150 can communicate with each other. They can be physically or virtually grouped (not shown) in one or more networks, such as private clouds, community clouds, public clouds, or hybrid clouds, or combinations thereof, as described above. This allows the cloud computing environment 1100 to provide infrastructure, platform, and / or software as a service, without requiring cloud consumers to maintain resources on their local computing devices. It should be understood that... Figure 11The types of computing devices 1154A-1154N shown are for illustrative purposes only, and computing node 1150 and cloud computing environment 1100 can communicate with any type of computerized device on any type of network and / or network-addressable connection (e.g., using a web browser).

[0135] Now for reference Figure 12 This shows the cloud computing environment 1100 ( Figure 11 This provides a set of functional abstractions. It should be understood beforehand that... Figure 12 The components, layers, and functions shown are for illustrative purposes only, and embodiments of the invention are not limited thereto. As depicted, the following layers and corresponding functions are provided:

[0136] The hardware and software layer 1260 includes hardware and software components. Examples of hardware components include: a host 1261; a server 1262 based on a RISC (Reduced Instruction Set Computer) architecture; a server 1263; a blade server 1264; a storage device 1265; and a network and network components 1266. In some embodiments, the software components include network application server software 1267 and database software 1268.

[0137] The virtualization layer 1270 provides an abstraction layer from which the following examples of virtual entities can be provided: virtual server 1271; virtual storage 1272; virtual network 1273, including virtual private network; virtual application and operating system 1274; and virtual client 1275.

[0138] In one example, management layer 1280 provides the functionality described below: Resource Provisioning 1281 provides dynamic procurement of computing resources and other resources used to perform tasks within the cloud computing environment. Metering and Pricing 1282 provides cost tracking when utilizing resources in the cloud computing environment, as well as billing or invoicing for consuming these resources. In one example, these resources may include application software licenses. Security provides authentication for cloud consumers and tasks, as well as protection for data and other resources. User Portal 1283 provides access to the cloud computing environment for consumers and system administrators. Service Level Management 1284 provides cloud resource allocation and management to ensure that required service levels are met. Service Level Agreement (SLA) Planning and Fulfillment 1285 provides pre-scheduling and procurement of cloud resources, where future needs are anticipated according to the SLA.

[0139] Workload layer 1290 provides examples of functions that can leverage a cloud computing environment. Examples of workloads and functions that can be provided from this layer include: mapping and navigation 1291; software development and lifecycle management 1292; virtual classroom education delivery 1293; data analysis and processing 1294; transaction processing 1295; and various functions 1296 for selectively configuring the signal processing stage of transmitters and other components of sensor nodes and other devices within the sensor network.

[0140] Various embodiments of this disclosure have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, practical applications of technology available on the market, or technical improvements, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0141] Various embodiments of this disclosure have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, practical applications of technology available on the market, or technical improvements, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A signal processing apparatus, comprising: Multiple signal processing stages are configured to convert digital baseband signals into analog radio frequency (RF) signals for transmission, wherein the multiple signal processing stages are also configured to be operatively coupled to a positive supply voltage and a negative supply voltage. At least one of the plurality of signal processing stages is configured to generate and output an analog voltage signal, wherein a positive supply voltage and a negative supply voltage supply power the at least one signal processing stage, and the analog voltage signal includes a voltage level less than the negative supply voltage. The at least one signal processing stage includes: A digital-to-analog converter (DAC) stage is configured to convert the digital baseband signal into an analog baseband voltage signal at the output node of the DAC stage, wherein the analog baseband voltage signal includes a voltage level less than the negative power supply voltage; and A filter stage, including an input node coupled to the output node of the DAC stage, wherein the filter stage is configured to filter the analog baseband voltage signal and generate a filtered analog baseband voltage signal at the output node of the filter stage, wherein the filtered analog baseband voltage signal includes a voltage level less than the negative power supply voltage.

2. The apparatus of claim 1, wherein the voltage level of the analog voltage signal includes at least one of the following: an average voltage level less than the negative power supply voltage; and a peak voltage level less than the negative power supply voltage.

3. The apparatus according to claim 1, wherein: The analog baseband voltage signal includes a first average voltage level that is less than the negative power supply voltage; and The filtered analog baseband voltage signal includes a second average voltage level that is lower than the negative power supply voltage.

4. The apparatus of claim 1, wherein the DAC stage comprises: A voltage-mode output stage includes a plurality of output stages coupled in parallel to the output node of the DAC stage, wherein each of the plurality of output stages includes an inverter and a capacitor coupled between the output of the inverter and the output node of the DAC stage; as well as An output capacitor is coupled between the output node of the DAC stage and the negative power supply voltage node.

5. The apparatus of claim 4, wherein the capacitor of the output stage comprises one of the following: a binary weighted capacitance value; and a unary weighted capacitance value.

6. The apparatus of claim 1, wherein the filter stage comprises an analog dual quadratic low-pass filter, wherein the analog dual quadratic low-pass filter comprises: A transistor includes a gate terminal, a first source / drain terminal, and a second source / drain terminal, wherein the gate terminal is coupled to the output node of the filter stage, wherein the first source / drain terminal is coupled to the positive feedback path of the analog double-secondary low-pass filter, and the second source / drain terminal is coupled to a negative power supply voltage node. A first resistor is coupled between the output node of the DAC stage and the feedback node of the analog double quadratic low-pass filter; A second resistor is coupled between the feedback node and the output node of the filter stage; A first capacitor is coupled in the feedback path between the feedback node and the first source / drain terminal of the transistor; as well as A second capacitor is coupled between the output node of the filter stage and the negative power supply voltage node.

7. The apparatus of claim 1, wherein the at least one signal processing stage further comprises a modulation stage, the modulation stage including an input coupled to the output node of the filter stage, wherein the modulation stage is configured to mix the filtered analog baseband voltage signal output from the filter stage with a local oscillator (LO) signal to generate a modulated voltage signal, wherein the modulated voltage signal includes a peak voltage level less than the negative power supply voltage.

8. A signal processing apparatus, comprising: Multiple signal processing stages are configured to convert digital baseband signals into analog radio frequency (RF) signals for transmission, wherein the multiple signal processing stages are also configured to be operatively coupled to a positive supply voltage and a negative supply voltage. At least one of the plurality of signal processing stages is configured to generate and output an analog voltage signal, wherein a positive supply voltage and a negative supply voltage power the at least one signal processing stage, and the analog voltage signal includes a voltage level greater than the positive supply voltage. The at least one signal processing stage includes: A digital-to-analog converter (DAC) stage is configured to convert the digital baseband signal into an analog baseband voltage signal at the output node of the DAC stage, wherein the analog baseband voltage signal includes a voltage level greater than the positive power supply voltage; and A filter stage, including an input node coupled to the output node of the DAC stage, wherein the filter stage is configured to filter the analog baseband voltage signal and generate a filtered analog baseband voltage signal at the output node of the filter stage, wherein the filtered analog baseband voltage signal includes a voltage level greater than the positive power supply voltage.

9. A sensor node, comprising: At least one sensor device is configured to generate sensor data; as well as A transmitter is configured to transmit the sensor data to a remote node, wherein the transmitter includes multiple signal processing stages configured to convert digital baseband signals into analog radio frequency (RF) signals for transmission, and wherein the multiple signal processing stages are also configured to be operatively coupled to a positive supply voltage and a negative supply voltage. At least one of the plurality of signal processing stages is configured to generate and output an analog voltage signal, wherein a positive supply voltage and a negative supply voltage supply power the at least one signal processing stage, and the analog voltage signal includes a voltage level less than the negative supply voltage. The at least one signal processing stage of the transmitter includes: A digital-to-analog converter (DAC) stage is configured to convert the digital baseband signal into an analog baseband voltage signal at the output node of the DAC stage, wherein the analog baseband voltage signal includes a voltage level less than the negative power supply voltage; as well as A filter stage, including an input node coupled to the output node of the DAC stage, wherein the filter stage is configured to filter the analog baseband voltage signal and generate a filtered analog baseband voltage signal at the output node of the filter stage, wherein the filtered analog baseband voltage signal includes a voltage level less than the negative power supply voltage.

10. The sensor node of claim 9, wherein the voltage level of the analog voltage signal includes at least one of the following: an average voltage level less than the negative power supply voltage; and a peak voltage level less than the negative power supply voltage.

11. The sensor node of claim 9, wherein the DAC stage comprises: A voltage-mode output stage includes a plurality of output stages coupled in parallel to the output node of the DAC stage, wherein each of the plurality of output stages includes an inverter and a capacitor coupled between the output of the inverter and the output node of the DAC stage; as well as An output capacitor is coupled between the output node of the DAC stage and the negative power supply voltage node. The capacitor in the output stage includes one of the following: a binary weighted capacitance value; and a unary weighted capacitance value.

12. The sensor node of claim 9, wherein the filter stage comprises an analog dual quadratic low-pass filter, wherein the analog dual quadratic low-pass filter comprises: A transistor includes a gate terminal, a first source / drain terminal, and a second source / drain terminal, wherein the gate terminal is coupled to the output node of a filter stage, wherein the first source / drain terminal is coupled to the positive feedback path of the analog double-secondary low-pass filter, and the second source / drain terminal is coupled to a negative power supply voltage node including the negative power supply voltage. A first resistor is coupled between the output node of the DAC stage and the feedback node of the analog double quadratic low-pass filter; A second resistor is coupled between the feedback node and the output node of the filter stage; A first capacitor is coupled in the feedback path between the feedback node and the first source / drain terminal of the transistor; as well as A second capacitor is coupled between the output node and the negative power supply voltage node of the filter stage.

13. The sensor node of claim 9, wherein the at least one signal processing stage of the transmitter further comprises a modulation stage, the modulation stage including an input coupled to the output node of the filter stage, wherein the modulation stage is configured to mix the filtered analog baseband voltage signal output from the filter stage with a local oscillator (LO) signal to generate a modulated voltage signal, wherein the modulated voltage signal includes a peak voltage level less than the negative power supply voltage.

14. A sensor node, comprising: At least one sensor device is configured to generate sensor data; as well as A transmitter is configured to transmit the sensor data to a remote node, wherein the transmitter includes multiple signal processing stages configured to convert digital baseband signals into analog radio frequency (RF) signals for transmission, and wherein the multiple signal processing stages are also configured to be operatively coupled to a positive supply voltage and a negative supply voltage. At least one of the plurality of signal processing stages is configured to generate and output an analog voltage signal, wherein a positive power supply voltage and a negative power supply voltage power the at least one signal processing stage, and the analog voltage signal includes a voltage level greater than the positive power supply voltage; The at least one signal processing stage of the transmitter includes: A digital-to-analog converter (DAC) stage is configured to convert the digital baseband signal into an analog baseband voltage signal at the output node of the DAC stage, wherein the analog baseband voltage signal includes a voltage level greater than the positive power supply voltage; as well as A filter stage, including an input node coupled to the output node of the DAC stage, wherein the filter stage is configured to filter the analog baseband voltage signal and generate a filtered analog baseband voltage signal at the output node of the filter stage, wherein the filtered analog baseband voltage signal includes a voltage level greater than the positive power supply voltage.

15. A signal processing method, comprising: Digital baseband signals are converted into analog radio frequency (RF) signals for transmission through multiple signal processing stages, wherein the multiple signal processing stages are operatively coupled to a positive supply voltage and a negative supply voltage. The digital baseband signal is converted into an analog RF signal for transmission. At least one signal processing stage from the plurality of signal processing stages generates and outputs an analog voltage signal, wherein a positive power supply voltage and a negative power supply voltage power the at least one signal processing stage, and the analog voltage signal includes a voltage level lower than the negative power supply voltage. The process of converting the digital baseband signal into the analog RF signal for transmission includes: The digital baseband signal is converted into an analog baseband voltage signal at the output node of the DAC stage via a digital-to-analog converter (DAC) stage, wherein the analog baseband voltage signal includes an average voltage level less than the negative power supply voltage; and The analog baseband voltage signal is filtered by a filter stage to generate a filtered analog baseband voltage signal at the output node of the filter stage, wherein the filtered analog baseband voltage signal includes an average voltage level less than the negative power supply voltage.

16. The method of claim 15, wherein converting the digital baseband signal into the analog baseband voltage signal at the output node of the DAC stage comprises: A digital signal is input to a plurality of output stages that are coupled in parallel to the output node of the DAC stage, wherein each of the plurality of output stages includes an inverter and a capacitor coupled between the output of the inverter and the output node of the DAC stage; In response to inputting the digital signal to at least a portion of the inverter, a voltage is generated across at least a portion of the capacitor in the output stage; as well as The output capacitor coupled between the output node and the negative power supply voltage node of the DAC stage is charged using the voltage generated by the output stage to generate the analog baseband voltage signal.

17. The method of claim 15, wherein converting the digital baseband signal into the analog RF signal for transmission further comprises: The filtered analog baseband voltage signal is mixed with a local oscillator (LO) signal by a modulation stage to generate a modulated voltage signal, wherein the modulated voltage signal includes a peak voltage that is less than the negative power supply voltage.

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