An FPGA resource partitioning method based on flow graph partitioning

Abstract

The application discloses an FPGA resource partitioning method based on flow graph partitioning, abstracts multiple design modules and their connection relationship into multiple RLMs and multiple signal edges, groups to obtain multiple RLM grouping nodes and multiple groups of grouped signal edges, and forms a flow graph with the multiple RLM grouping nodes and the multiple groups of grouped signal edges; the volume of the FPGA is divided into multiple storage units, the multiple RLM grouping nodes, the multiple groups of grouped signal edges, the multiple storage units and the flow graph are displayed through a flow graph partitioning interface; multiple RLM grouping nodes and multiple groups of signal edges are partitioned into the multiple storage units through an interactive event, and whether the partitioning is reasonable is checked according to a resource constraint condition; if the partitioning is reasonable, a partitioning configuration file corresponding to the multiple RLMs is output. The method simplifies the connection relationship between real modules and real signals, enriches the interactive operation capability of the flow graph, improves the partitioning efficiency and enhances user experience.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, and in particular to an FPGA resource partitioning method based on flow graph partitioning. Background Technology

[0002] In integrated circuit design hardware simulation, engineers typically establish mapping relationships between design modules, signals, ports, and the FPGA manually to complete the FPGA design resource partitioning. This manual method is feasible when the number of design modules is small, but it increases the probability of errors and becomes inefficient when the number of design modules is large. This process usually requires consideration of many factors and processing work, making it very time-consuming and labor-intensive. Therefore, it is necessary to improve the existing methods of manually partitioning flow graphs. Summary of the Invention

[0003] To address the technical problem of high error probability and low efficiency caused by manual editing when the number of design modules increases, this invention instantiates and abstracts design modules into RLMs (Reusable Logic Modules). The signal connection relationships between multiple design modules are abstracted into signal edges between multiple RLMs. The FPGA logic is divided into multiple memory cells. Only the signal connection relationships between multiple RLMs and between multiple memory cells are considered, ignoring the internal details of the RLMs. Multiple RLMs and signal edges are dragged into multiple memory cells to complete the logical division of multiple design modules. Finally, the integrated circuit design is simulated to verify the user's integrated circuit design.

[0004] The purpose of this invention is to provide an FPGA resource partitioning method based on flow graph partitioning, comprising the following steps:

[0005] S1. Abstract the user's multiple design modules into multiple RLMs, and abstract the signal connection relationship between multiple design modules into signal edges between multiple RLMs. Group the multiple RLMs according to the RLM type to obtain multiple RLM group nodes. Group multiple signal edges according to the signal edge type to obtain multiple groups of grouped signal edges. The multiple RLM group nodes and the multiple groups of grouped signal edges constitute a flow graph.

[0006] S2. Create attribute lists for multiple RLMs and attribute lists for multiple signal edges, and display the attribute lists for multiple RLMs, the attribute lists for multiple signal edges, and the flow graph through the flow graph partitioning interface.

[0007] S3. The volume of multiple FPGAs is abstractly divided into several storage units. Attribute lists of multiple FPGAs and several storage units are created. The attribute lists of several storage units, multiple FPGAs, and several storage units are displayed through a flow graph partitioning interface.

[0008] S4. Through the interaction events of the attribute lists of multiple RLMs, the attribute lists of multiple signal edges, the attribute list of FPGA, and the attribute list of storage units, the multiple RLM grouping nodes and the multiple grouped signal edges are divided into several storage units to obtain the partitioning configuration files corresponding to multiple RLMs.

[0009] S5. Check whether the partitioning of multiple RLM grouping nodes and signal edges after multiple groups is reasonable according to resource constraints. If the partitioning is reasonable, output the partitioning configuration file corresponding to multiple RLMs.

[0010] Preferably, the nodes in the flow graph in S1 correspond to RLM packet nodes, and the multiple edges in the flow graph correspond to signal edges between multiple RLM packet nodes.

[0011] Preferably, the flow graph partitioning interface in S2 specifically includes a toolbar, a storage cell panel, an attribute panel, and a flow graph. The toolbar is located at the top of the flow graph partitioning interface, the storage cell panel is located on the right side of the flow graph partitioning interface, the attribute panel is located at the bottom of the flow graph partitioning interface, and the flow graph is located in the middle of the flow graph partitioning interface.

[0012] Preferably, the attribute list of RLM in S2 includes: RLM group node name, storage unit to be partitioned, group ID, RLM group list, and RLM resource usage details.

[0013] Preferably, the attribute list of the signal edge in S2 includes: signal edge name, group name, and RLM connection relationship.

[0014] Preferably, the attribute list of the storage cell in S3 includes: storage cell name, FPGA name, FPGA utilization rate, and RLM list.

[0015] Preferably, the interactive events in S4 include listening to flow graph operation events and listening to toolbar events.

[0016] Preferably, in S4, multiple RLM group nodes and multiple groups of grouped signal edges are divided into several storage units. Specifically, this means adding multiple RLM group nodes to several storage units through an add operation, or deleting the RLM group nodes to be deleted from the corresponding storage units through a delete operation.

[0017] Preferably, the resource constraints in S5 include: whether all RLMs in the RLM group node are added to the storage unit, whether the occupation of various RLM resources exceeds the FPGA volume, whether the port type of the signal edge meets the preset rules, and whether the storage unit identifier status meets the requirements.

[0018] Preferably, the preset rules specifically include: cross-board signals only support GT port connection, tightly coupled signals only support LVDS port connection, loosely coupled signals support GT port or LVDS port connection, GT port can only transmit messages, LVDS direct connection automatically assigns ports, and LVDS with the same number on the same FPGA can only have one message transmission mode.

[0019] The aforementioned FPGA resource partitioning method based on flow graph partitioning abstracts multiple user design modules into multiple Resource Management Modules (RLMs), and the signal connections between these design modules into signal edges between the RLMs. The RLMs are grouped according to their types to obtain multiple RLM group nodes. Similarly, multiple signal edges are grouped according to their types to obtain multiple groups of grouped signal edges. These RLM group nodes and grouped signal edges constitute a flow graph. Attribute lists for the RLMs and signal edges are created, and the attribute lists for the RLM group nodes, signal edges, and flow graph are then connected via a flow graph. The flowchart partitioning interface is displayed. The volume of the FPGA is abstractly divided into several storage units. An attribute list for the FPGA and attribute lists for each storage unit are created and displayed through the flowchart partitioning interface. Interactive events are performed using these attribute lists to partition multiple RLM grouping nodes and multiple groups of grouped signal edges into several storage units, resulting in partitioning configuration files for multiple RLMs. The partitioning of multiple RLM grouping nodes and multiple groups of grouped signal edges is checked against resource constraints to determine its rationality. If the partitioning is rational, the partitioning configuration files for multiple RLMs are output. This method establishes a many-to-one mapping relationship between RLMs and storage units, simplifying the connection relationships between real modules and real signals, enriching the interactive operation capabilities of the flowchart, and improving both partitioning efficiency and user experience. Attached Figure Description

[0020] Figure 1 This is a flowchart of an FPGA resource partitioning method based on flow graph partitioning in one embodiment of the present invention;

[0021] Figure 2 This is an example diagram of a flow graph partitioning interface in one embodiment of the present invention. Detailed Implementation

[0022] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings.

[0023] An FPGA resource partitioning method based on flow graph partitioning, specifically including:

[0024] S1. Abstract the user's multiple design modules into multiple RLMs, and abstract the signal connection relationship between multiple design modules into signal edges between multiple RLMs. Group the multiple RLMs according to the RLM type to obtain multiple RLM group nodes. Group multiple signal edges according to the signal edge type to obtain multiple groups of grouped signal edges. The multiple RLM group nodes and the multiple groups of grouped signal edges constitute a flow graph.

[0025] S2. Create attribute lists for multiple RLMs and attribute lists for multiple signal edges, and display the attribute lists for multiple RLMs, the attribute lists for multiple signal edges, and the flow graph through the flow graph partitioning interface.

[0026] S3. The volume of multiple FPGAs is abstractly divided into several storage units. Attribute lists of multiple FPGAs and several storage units are created. The attribute lists of several storage units, multiple FPGAs, and several storage units are displayed through a flow graph partitioning interface.

[0027] S4. Through the interaction events of the attribute lists of multiple RLMs, the attribute lists of multiple signal edges, the attribute list of FPGA, and the attribute list of storage units, the multiple RLM grouping nodes and the multiple grouped signal edges are divided into several storage units to obtain the partitioning configuration files corresponding to multiple RLMs.

[0028] S5. Check whether the partitioning of multiple RLM grouping nodes and signal edges after multiple groups is reasonable according to resource constraints. If the partitioning is reasonable, output the partitioning configuration file corresponding to multiple RLMs.

[0029] Specifically, see Figure 1 , Figure 1 This is a flowchart of an FPGA resource partitioning method based on flow graph partitioning in one embodiment of the present invention.

[0030] First, the user's design modules are abstracted into RLMs, with one design module corresponding to one RLM, resulting in multiple RLMs. These multiple RLMs form an RLM list. Based on the type of the design module, the multiple RLMs in the RLM list are grouped, with each group of RLMs corresponding to an RLM group node, resulting in multiple RLM group nodes. The x-axis and y-axis coordinates of each RLM on the flow graph are calculated using the force-guided layout algorithm. The position of the RLM group node is the center of the positions of all RLMs within the group. The signal connection relationships between different design modules are abstracted into signal edges between corresponding RLMs. Multiple signal edges are grouped according to the signal type, resulting in multiple groups of grouped signal edges. The multiple RLM group nodes and the multiple groups of grouped signal edges constitute the flow graph.

[0031] Then, create multiple attribute lists for RLMs and multiple attribute lists for signal edges, and display the attribute lists for multiple RLMs, multiple attribute lists for signal edges, and the flow graph through the flow graph partitioning interface.

[0032] Next, for multiple FPGAs on a motherboard, the volume of each FPGA is abstractly divided into several storage units. Attribute lists for multiple FPGAs and several storage units are created. The attribute lists for multiple FPGAs, several storage units, and several storage units are displayed through a flow graph partitioning interface.

[0033] Interacting with the above attribute lists (RLM attribute list, signal edge attribute list, FPGA attribute list, and storage unit attribute list) divides multiple RLM grouping nodes and multiple grouped signal edges into several storage units, constructs the mapping relationship between multiple RLM grouping nodes and FPGA, and obtains the partitioning configuration file corresponding to the RLM list composed of multiple RLMs.

[0034] Check whether the mapping relationship between multiple RLM group nodes and several storage units is reasonable based on resource constraints. If the mapping relationship meets the resource constraints, the partitioning is reasonable, and the partitioning configuration file corresponding to multiple RLMs is output.

[0035] In one embodiment, the nodes in the flow graph in S1 correspond to RLM packet nodes, and the multiple edges in the flow graph correspond to signal edges between multiple RLM packet nodes.

[0036] Specifically, the flow graph consists of multiple nodes and multiple edges. The nodes in the flow graph correspond to RLM packet nodes, and the edges in the flow graph correspond to signal edges between RLM packet nodes.

[0037] The attributes of nodes in a flow graph include: node name, node color, node area, node shape, and node type.

[0038] The colors of the RLMs that have been partitioned in the RLM group node are filled with the colors of the storage units to which they belong after partitioning; the RLMs that have not been partitioned are filled with white.

[0039] The node area can be calculated from the radius of the RLM group node, which is the sum of the radii of all RLMs within the group. The radius of the RLM is directly proportional to the total LUTS (total number of table lookups) resource usage; the larger the total LUTS resource usage, the larger the RLM radius, and vice versa.

[0040] Since RLMs are divided into two types, ordinary and user-defined, RLMs of the same type are grouped together to form an RLM group before dividing multiple RLMs. RLMs are represented by circles in the flow graph, and RLM group nodes are represented by rectangles in the flow graph. The mouse hover state and rectangle size of RLM group nodes are different for different types of RLMs.

[0041] The properties of edges in a flow graph include: edge width, edge color, edge length, and edge direction.

[0042] In a flow graph, solid lines represent signal edges. The width of a signal edge is calculated based on the bit width of the signal. The width of a signal edge is proportional to the bit width of each signal that makes up the signal edge: the larger the bit width of the signal, the larger the width of the corresponding signal edge; conversely, the smaller the bit width of the signal, the smaller the width of the corresponding signal edge.

[0043] The specific settings for edge colors in a flow graph are as follows: undivided edges are set to gray; divided edges are filled with a color (e.g., selected highlight blue);

[0044] The length of the edges in the flow graph corresponds to the distance between RLM group nodes, which is used to represent the loose coupling of signals: a long distance indicates loose coupling between signals, and a short distance indicates tight coupling between signals;

[0045] In a flow graph, the direction of the edges is indicated by arrows, representing the direction of signal transmission.

[0046] In one embodiment, the flow graph partitioning interface in S2 specifically includes a toolbar, a storage cell panel, an attribute panel, and a flow graph. The toolbar is located at the top of the flow graph partitioning interface, the storage cell panel is located on the right side of the flow graph partitioning interface, the attribute panel is located at the bottom of the flow graph partitioning interface, and the flow graph is located in the middle of the flow graph partitioning interface.

[0047] Specifically, see Figure 2 , Figure 2 This is an example diagram of a flow graph partitioning interface in one embodiment of the present invention.

[0048] Figure 2 The flowchart partitioning interface shown includes a toolbar and a storage cell panel (corresponding to...). Figure 2 The right side includes the SLICE panel, the attribute panel, and the flow graph, where:

[0049] The toolbar is located at the top of the flow graph partitioning interface. The toolbar includes operation buttons such as zoom in, zoom out, scale to a suitable size, force-guided algorithm layout, filter, search, save, and refresh. Clicking the "Zoom In" button zooms in on the flow graph; clicking the "Zoom Out" button zooms in on the flow graph; clicking the "Scale to a Suitable Size" button scales the flow graph to a suitable size; clicking the "Force-Guided Algorithm Layout" recalculates the layout positions of the RLMs in the flow graph; clicking the "Filter" button hides filtered nodes or signal edges in the flow graph; clicking the "Search" button quickly finds and locates a specific RLM node or signal edge; clicking the "Save" button saves the currently edited node or signal edge; and clicking the "Refresh" button refreshes the recalculated positions of the RLM group nodes in the flow graph.

[0050] The storage unit panel is located on the right side of the flow diagram partitioning interface, and includes FPGA rack hierarchy information, a list of storage units under the FPGA, and allocated RLMs.

[0051] The FPGA rack hierarchy information describes the number of FPGAs and the location number of the motherboard to which each FPGA belongs; the list of storage units under the FPGA describes the abstract division of the volume of each FPGA into several storage units, and the corresponding list of storage units; the allocated RLM indicates a storage unit that has been allocated to the FPGA.

[0052] The attribute panel is located at the bottom of the flow graph partitioning interface and includes the RLM attribute panel, signal edge attribute panel, memory cell attribute panel, and FPGA attribute panel.

[0053] The flow graph is located in the middle of the flow graph partitioning interface and includes multiple RLM grouping nodes and multiple grouped signal edges.

[0054] In one embodiment, the attribute list of the RLM in S2 includes: RLM group node name, storage unit to be partitioned, group ID, RLM group list, and RLM resource usage details.

[0055] Specifically, see Figure 2 The RLM attribute list information is divided into an RLM attribute panel at the bottom of the interface via a flow graph (corresponding to...). Figure 2 The RLM Properties section displays the following fields:

[0056] Group ID, representing the ID of the RLM group node, is denoted by ID;

[0057] RLM group node name: represented by name;

[0058] The proposed storage units: represented by the name and number of the storage units;

[0059] RLM group list: Represents the RLMs in the RLM group nodes, such as rlm1, rlm2, rlm3, etc.;

[0060] The details of RLM resource usage are shown in the table below:

[0061] TotalLUTS Total number of lookup tables 100 LogicLUTS Equivalent logical lookup table number 100 LUTRAMS Used as a storage unit lookup table number 100 SRLS Number of shift registers 0 FFS Number of registers 0 RAM18 18-block memory 0 RAM36 36 blocks of memory 10 URAM High-speed memory 10 DSPBlocks Number of dedicated processors 10 Trigger Number of trigger signals 1 Monitor Number of sampled signals 2

[0062] In one embodiment, the attribute list of the signal edge in S2 includes: signal edge name, group name, and RLM connection relationship.

[0063] Specifically, see Figure 2 The signal edge attribute information is displayed in the signal edge attribute panel at the bottom of the flow graph partitioning interface (corresponding to...). Figure 2 The Signal Properties section displays the following fields:

[0064] Signal name: Represented by signal(id);

[0065] Group names: Represented by RLM Group1, RLM Group2, etc.;

[0066] Total bit width: Represents the total bit width of the signal, expressed as a number such as 120 (hypothetical value);

[0067] RLM connection relationship: RLM1-RLM2

[0068] Single10->single20 bit width: 1 (hypothetical value) Signal group name: group1

[0069] Single11->single21 bit width: 64 (hypothetical value) Signal group name: group1

[0070] RLM connection relationship: RLM3–RLM4

[0071] Single11 <- single21 Bit width: 64 (hypothetical value) Signal group name: group2

[0072] Single11 <- single21 Bit width: 64 (hypothetical value) Signal group name: group2.

[0073] In one embodiment, the list of attributes of the storage cell in S3 includes: storage cell name, FPGA name, FPGA utilization, and RLM list.

[0074] Specifically, the attribute information of the storage unit is displayed in the storage unit attribute panel at the bottom of the flow graph partitioning interface (corresponding to...). Figure 2 The Slice Properties section displays the following fields:

[0075] Storage unit name: represented by name;

[0076] Storage unit ID: Represented by ID;

[0077] FPGA Name: Represented by FPGA Name;

[0078] FPGA utilization: expressed as a percentage, e.g., 83% (hypothetical value);

[0079] RLM list: The RLMs in it are represented by rlm1, rlm2, ... etc.;

[0080] The RLM resource usage statistics are shown in the table below:

[0081] TotalLUTS Total number of lookup tables 100 LogicLUTS Equivalent logical lookup table number 100 LUTRAMS Used as a storage unit lookup table number 100 SRLS Number of shift registers 0 FFS Number of registers 0 RAM18 18-block memory 0 RAM36 36 blocks of memory 10 URAM High-speed memory 10 DSPBlocks Number of dedicated processors 10 Trigger Number of trigger signals 1 Monitor Number of sampled signals 2 Global Global resource count 5

[0082] In one embodiment, the interactive events in S4 include listening to flow graph operation events and listening to toolbar events.

[0083] Specifically, when the interaction event is a listener for flow graph operation events, the events for selecting nodes or edges include mouse hover, highlighting, dragging, box selection, and right-click. Since not all attributes of a node or edge can be displayed in the flow graph, more attributes need to be displayed by adding an attribute panel. This can be done by binding the browser's click and right-click events and registering the corresponding handling functions. When a click occurs, the function is triggered to activate the attribute panel.

[0084] Commonly used mouse events for flow graph manipulation include:

[0085] 1) Click on a node in the flow graph and select the RLM group node (if there is only one RLM in the RLM group node, selecting the RLM group node means selecting that one RLM in the RLM group node);

[0086] 2) Click on an edge in the flow graph and select the signal edge;

[0087] 3) Use the mouse to select the target area in the flow graph, selecting multiple RLM nodes;

[0088] 4) Press the space bar on your keyboard to start dragging the RLM node to the storage cell panel, and release the mouse to stop dragging;

[0089] 5) Click the rectangle in the flow graph, select the RLM group node, and drag it out or into the storage cell panel.

[0090] When the interaction event is a toolbar event listener, a button function can be registered via command line mode, and the button function will be triggered when the button is clicked.

[0091] In one embodiment, in S4, multiple RLM group nodes and multiple groups of grouped signal edges are divided into several storage units. Specifically, multiple RLM group nodes are added to several storage units through an add operation, or the RLM group nodes to be deleted are deleted from the corresponding storage units through a delete operation.

[0092] Specifically, the volume of the FPGA is abstractly divided into several storage cells, and each row in the storage cell panel on the right side of the flow graph partitioning interface is assumed to be a storage cell; the RLM grouping node is assigned to one storage cell in the FPGA (the storage cell corresponds to...). Figure 2 This establishes a many-to-one mapping relationship between the RLM and the storage unit (SLICE).

[0093] The add operation refers to adding the RLM from the RLM group node to the storage unit, which can be done in the following three ways:

[0094] 1) Click to select the RLM group node, drag the RLM group node into the storage unit, and add all the RLMs in the RLM group node to the storage unit;

[0095] 2) Select multiple RLMs in the same RLM group node, press the space bar, and drag the selected RLMs into the storage unit;

[0096] 3) Click to select an RLM in the RLM group node, and click the "+" button next to the storage unit to add the selected RLM to the storage unit.

[0097] The deletion operation refers to removing the RLM group node to be deleted from its respective storage unit on the storage unit panel. This can be done in the following three ways:

[0098] 1) Select the storage cell containing the RLM group node to be deleted, and click the [-] button next to the storage cell to delete the selected RLM group node from the current storage cell;

[0099] 2) Select the storage unit containing the RLM group node to be deleted, select the RLM group node to be deleted, and drag the RLM group node to be deleted from the storage unit. At this time, all RLM blocks in the RLM group node to be deleted are deleted from the storage unit.

[0100] 3) Select the storage cell containing the RLM group nodes to be deleted, and click the button next to the storage cell. The button deletes all RLMs in the current storage unit.

[0101] In one embodiment, the resource constraints in S4 include: whether all RLMs in the RLM group node are added to the storage unit, whether the RLM resource occupancy exceeds the FPGA capacity, whether the port type of the signal edge meets the preset rules, and whether the storage unit identifier status meets the requirements.

[0102] In one embodiment, the preset rules specifically include: cross-board signals only support GT port connections, tightly coupled signals only support LVDS port connections, loosely coupled signals support GT port or LVDS port connections, GT ports can only transmit messages, LVDS direct connections are automatically assigned ports, and LVDS with the same number on the same FPGA can only have one message transmission mode.

[0103] Specifically, after allocating multiple RLM group nodes to multiple storage units, it is necessary to check whether the allocation is reasonable based on resource constraints. These resource constraints include:

[0104] 1) Have all RLMs in the RLM group node been added to the storage unit?

[0105] 2) Whether the resource occupancy of RLM exceeds the capacity of FPGA. Specifically, a threshold for FPGA resource utilization is preset. The resource occupancy of RLM is checked according to the preset threshold. If the resource occupancy of RLM exceeds 70% of the preset threshold for FPGA resource utilization, it is considered that the FPGA resource utilization does not meet the requirements. The FPGA utilization that does not meet the requirements is marked with red text.

[0106] 3) Whether the port connection type of the signal side meets the preset rules. The preset rules specifically include: cross-board connection only supports GT ports (i.e., high-speed transceiver ports); tight coupling only supports LVDS ports (i.e., low-voltage differential signal ports), while loose coupling supports both GT ports and LVDS ports; GT ports can only transmit messages; LVDS ports are directly connected to automatically assigned ports (ports automatically assigned through a port allocation algorithm); LVDS ports with the same number on the same FPGA can only have one message transmission mode and cannot conflict with each other.

[0107] 4) Does the storage cell identifier status meet the requirements? Check the partitioning status of the storage cell. The title (i.e., the name of the storage cell) is indicated by color: blue title indicates editing is in progress; red title indicates a verification error, requiring the user to check the storage cell or FPGA resource status; green title indicates verification passed.

[0108] The partitioning results are checked according to the above constraints. If the check fails, the partitioning needs to be modified until the modified partitioning passes the check. The partitioning configuration file that passes the check is then output.

[0109] The aforementioned FPGA resource partitioning method based on flow graph partitioning abstracts multiple user design modules into multiple Resource Management Modules (RLMs), and the signal connections between these design modules into signal edges between the RLMs. The RLMs are grouped according to their types to obtain multiple RLM group nodes. Similarly, multiple signal edges are grouped according to their types to obtain multiple groups of grouped signal edges. These RLM group nodes and grouped signal edges constitute a flow graph. Attribute lists for the RLMs and signal edges are created, and the attribute lists for the RLM group nodes, signal edges, and flow graph are then connected via a flow graph. The flowchart partitioning interface is displayed. The volume of the FPGA is abstractly divided into several storage units. An attribute list for the FPGA and attribute lists for each storage unit are created and displayed through the flowchart partitioning interface. Interactive events are performed using these attribute lists to partition multiple RLM grouping nodes and multiple groups of grouped signal edges into several storage units, resulting in partitioning configuration files for multiple RLMs. The partitioning of multiple RLM grouping nodes and multiple groups of grouped signal edges is checked against resource constraints to determine its rationality. If the partitioning is rational, the partitioning configuration files for multiple RLMs are output. This method establishes a many-to-one mapping relationship between RLMs and storage units, simplifying the connection relationships between real modules and real signals, enriching the interactive operation capabilities of the flowchart, and improving both partitioning efficiency and user experience.

[0110] The above provides a detailed description of the FPGA resource partitioning method based on flow graph partitioning provided by this invention. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this invention.

Claims

1. A method for partitioning FPGA resources based on flow graph partitioning, characterized in that, The method includes the following steps: S1. Abstract the user's multiple design modules into multiple RLMs, and abstract the signal connection relationship between the multiple design modules into signal edges between the multiple RLMs. Group the multiple RLMs according to the RLM type to obtain multiple RLM grouping nodes. Group multiple signal edges according to the signal edge type to obtain multiple groups of grouped signal edges. The multiple RLM grouping nodes and the multiple groups of grouped signal edges constitute a flow graph. S2. Create multiple attribute lists of the RLM and multiple attribute lists of the signal edges, and display the multiple attribute lists of the RLM, the multiple attribute lists of the signal edges, and the flow graph through the flow graph partitioning interface; S3. The volume of multiple FPGAs is abstractly divided into several storage units, and attribute lists of multiple FPGAs and several storage units are created. The attribute lists of several storage units, multiple FPGAs, and several storage units are displayed through the flow graph partitioning interface. S4. By interacting with the attribute lists of multiple RLMs, the attribute lists of multiple signal edges, the attribute list of the FPGA, and the attribute list of the storage unit, multiple RLM grouping nodes and multiple groups of grouped signal edges are divided into several storage units to obtain the partitioning configuration files corresponding to multiple RLMs. S5. Check whether the partitioning of multiple RLM grouping nodes and multiple groups of signal edges after grouping is reasonable according to resource constraints. If the partitioning is reasonable, output the partitioning configuration file corresponding to multiple RLMs.

2. The FPGA resource partitioning method based on flow graph partitioning as described in claim 1, characterized in that, The nodes in the flow graph described in S1 correspond to RLM packet nodes, and the multiple edges in the flow graph correspond to signal edges between multiple RLM packet nodes.

3. The FPGA resource partitioning method based on flow graph partitioning as described in claim 2, characterized in that, The flow graph partitioning interface described in S2 specifically includes a toolbar, a storage cell panel, an attribute panel, and a flow graph. The toolbar is located at the top of the flow graph partitioning interface, the storage cell panel is located on the right side of the flow graph partitioning interface, the attribute panel is located at the bottom of the flow graph partitioning interface, and the flow graph is located in the middle of the flow graph partitioning interface.

4. The FPGA resource partitioning method based on flow graph partitioning as described in claim 3, characterized in that, The RLM attribute list described in S2 includes: RLM group node name, storage unit to be partitioned, group ID, RLM group list, and RLM resource usage details.

5. The FPGA resource partitioning method based on flow graph partitioning as described in claim 4, characterized in that, The attribute list of the signal edge described in S2 includes: signal edge name, group name, and RLM connection relationship.

6. The FPGA resource partitioning method based on flow graph partitioning as described in claim 5, characterized in that, The attribute list of the storage cell described in S3 includes: storage cell name, FPGA name, FPGA utilization, and RLM list.

7. The FPGA resource partitioning method based on flow graph partitioning as described in claim 6, characterized in that, The interactive events in S4 include listening to flow graph operation events and listening to toolbar events.

8. The FPGA resource partitioning method based on flow graph partitioning as described in claim 7, characterized in that, In step S4, multiple RLM group nodes and multiple groups of grouped signal edges are divided into several storage units. Specifically, this means adding multiple RLM group nodes to several storage units through an add operation, or deleting RLM group nodes to be deleted from their corresponding storage units through a delete operation.

9. The FPGA resource partitioning method based on flow graph partitioning as described in claim 8, characterized in that, The resource constraints in S5 include: whether all RLMs in the RLM group node are added to the storage unit, whether the RLM resource occupancy exceeds the FPGA capacity, whether the port type of the signal edge meets the preset rules, and whether the storage unit identifier status meets the requirements.

10. The FPGA resource partitioning method based on flow graph partitioning as described in claim 9, characterized in that, The preset rules specifically include: cross-board signals only support GT port connections, tightly coupled signals only support LVDS port connections, loosely coupled signals support GT port or LVDS port connections, GT ports can only transmit messages, LVDS direct connections are automatically assigned ports, and LVDS with the same number on the same FPGA can only have one message transmission mode.

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