A memory wiring design structure, method and electronic device

Abstract

The application discloses a memory wiring design structure, a method and an electronic device. The memory wiring design structure comprises a memory control module, a fan-out line, a main trunk line, a plurality of branch lines and a plurality of memory modules. The output end of the memory control module is connected with the input end of the fan-out line. The output end of the fan-out line is connected with the input end of the main trunk line. The output end of the main trunk line is connected with the input end of the first branch line and the second branch line respectively. The output end of the first branch line is connected with the input end of the first memory module. The output end of the second branch line is connected with the input end of the second memory module. The application can break the original memory bus FLY-BY serial design mode through a double-wing symmetric expansion technology, parallel control and connection of the memory bus, equal control of the memory modules and equal expansion of two groups of memory modules under single-channel memory.

Description

Technical Field

[0001] This application belongs to the field of electronic technology, and in particular relates to a memory wiring design structure, method and electronic device. Background Technology

[0002] With the rapid development of information technology and the computer industry, the demand for large-scale server in-memory computing and high-performance in-memory computing is increasing in sectors such as government, finance, and energy.

[0003] The memory module (DDR, Double Data Rate) bus, as a high-speed data transmission bus of the system, is the working bus and link connecting the central processing unit and memory modules, and plays a very important role in the system performance. The DDR bus has also evolved from the initial DDR to DDR2, DDR3, DDR4, and DDR5, and the speed has increased from the initial 200MHz to 5600MHz. DDR is mainly used as an external cache for the processor to achieve a rapid improvement in data processing performance.

[0004] Currently, DDR bus, as a cost-effective caching solution, is mainly used in server motherboard-level designs. A single board supports 24 or 32 channels, with each channel supporting two memory slots simultaneously. This multi-channel, multi-slot approach expands system memory, increasing server memory storage capacity and density. To improve memory operating speed, DDR routing technologies such as FLY-BY serial routing and piano key patterns have been developed to continuously increase the DDR bus operating frequency to meet the high-performance computing requirements of the system.

[0005] In the current design, the DDR bus on the SMT of the server motherboard uses a FLY-BY serial method. One DDR bus is serially connected to two memory slots. Then, the access time delay between the two memory modules is adjusted by firmware to control the two memory modules. By dynamically adjusting the memory termination resistance value, signal reflection processing is achieved, ultimately doubling the system memory. Since this method is a simple point-to-point connection method, it can effectively reduce the workload of board design, but software cooperation is required to realize the memory expansion function.

[0006] However, with the continuous improvement of DDR bus operating speed, existing technology has two main drawbacks: First, handling the access latency of two memory modules in software and controlling the termination resistors in software essentially increases memory expansion capabilities by consuming processor computing power, while the actual operating bandwidth of the memory is only about 80% of the theoretical bandwidth. Second, when two memory modules are connected to a single channel, the memory operating frequency will be reduced by default to ensure stability in order to balance the synchronous operation of the two memory modules and consider memory reflection at the near end. Based on these two drawbacks, the existing DDR bus design has seriously affected the performance of system memory and the overall system functionality. Summary of the Invention

[0007] To address the problems of existing technologies, this application provides a memory wiring design structure, method, and electronic device. The memory wiring design structure includes a memory control module, fan-out lines, a main trunk line, several branch fin lines, and several memory modules. The output terminal of the memory control module is connected to the input terminal of the fan-out lines, and the output terminal of the fan-out lines is connected to the input terminal of the main trunk line. The output terminal of the main trunk line is connected to the input terminals of a first branch fin line and a second branch fin line, respectively. The output terminal of the first branch fin line is connected to the input terminal of a first memory module, and the output terminal of the second branch fin line is connected to the input terminal of a second memory module. This application, through dual-fin symmetrical expansion technology, breaks the original FLY-BY serial design method of the memory bus, enabling parallel control and connection of the memory bus, achieving peer-to-peer control of memory modules, thereby realizing equal expansion of two sets of memory modules under a single-channel memory configuration.

[0008] The technical solution is as follows:

[0009] Firstly, a memory routing design structure includes a memory control module, fan-out lines, a main trunk line, several branch lines, and several memory modules.

[0010] The output terminal of the memory control module is connected to the input terminal of the fan-out line, the output terminal of the fan-out line is connected to the input terminal of the main line, and the output terminal of the main line is connected to the input terminals of the first branch fin line and the second branch fin line respectively.

[0011] The output end of the first finned wire is connected to the input end of the first memory module, and the output end of the second finned wire is connected to the input end of the second memory module.

[0012] In some embodiments, the memory wiring design structure further includes branch points.

[0013] The splitting point is connected between the output end of the main line and the input ends of the first splitting line and the second splitting line.

[0014] In some embodiments, the memory control module is used to control read and write operations on the plurality of memory modules;

[0015] The fan-out line is used to lead the clock signal line and / or control signal line and / or data signal line of the memory bus from the pins of the memory control module;

[0016] The backbone is used to transmit signals between the memory control module and the plurality of memory modules; the branching points are used to forward signals from the backbone to the plurality of memory modules;

[0017] The plurality of finned wires are used to transmit signals to the plurality of memory modules at the same time.

[0018] In some embodiments, the impedance value of the fan-out line is within a first threshold range, the trace width of the fan-out line is within a second threshold range, and the trace length of the fan-out line is less than a third threshold; a plurality of impedance compensation units are provided on one side of the fan-out line.

[0019] In some embodiments, the impedance value of the trunk line is within a fourth threshold range, the routing length of the trunk line is within a fifth threshold range, and the routing length error value of the trunk line is within a sixth threshold range.

[0020] In some embodiments, the drilling of the finned point is designed by back drilling or hollowing out the circuit board reference layer, and the length of the back drill residue of the finned point drilling is less than the seventh threshold range.

[0021] In some embodiments, the impedance value of the finned wire is within a first threshold range, the trace length of the finned wire is within an eighth threshold range, and the trace length error value of the finned wire is within a ninth threshold range; the impedance value, trace length, and trace length error value of each finned wire are the same.

[0022] Secondly, this application also provides a memory routing design method, the method comprising:

[0023] A memory routing design structure is created using a dual-wing symmetrical extension routing method for memory.

[0024] The parameters of each component of the memory wiring design structure are set.

[0025] In some embodiments, the creation of the memory routing design structure through the memory dual-wing symmetrical extension routing method includes:

[0026] Connect the output terminal of the memory control module to the input terminal of the fan-out line, connect the output terminal of the fan-out line to the input terminal of the main line, connect the output terminal of the main line to the input terminal of the fin-splitting point, and connect the output terminal of the fin-splitting point to the input terminals of the first fin-splitting line and the second fin-splitting line respectively.

[0027] Connect the output end of the first finned wire to the input end of the first memory module, and connect the output end of the second finned wire to the input end of the second memory module.

[0028] In some embodiments, setting parameters for each component of the memory wiring design structure includes:

[0029] The impedance value of the fan-out line is set to a first threshold range, the trace width of the fan-out line is set to a second threshold range, and the trace length of the fan-out line is set to be less than a third threshold; several impedance compensation units are set on one side of the fan-out line.

[0030] The impedance value of the trunk line is set to a fourth threshold range, the routing length of the trunk line is set to a fifth threshold range, and the routing length error value of the trunk line is set to a sixth threshold range.

[0031] The drilling holes for the fin points are designed by back drilling or hollowing out the circuit board reference layer, and the length of the back drilling residue of the fin point drilling holes is set to be less than the seventh threshold range.

[0032] The impedance value of the finned wire is set to a first threshold range, the trace length of the finned wire is set to an eighth threshold range, and the trace length error value of the finned wire is set to a ninth threshold range; the impedance value, trace length, and trace length error value of each finned wire are set to be the same.

[0033] Thirdly, this application also provides an electronic device, which includes a memory wiring design circuit and other electronic components, wherein the memory wiring design circuit includes a memory wiring design structure as described in any of the first aspects.

[0034] The beneficial effects of the technical solutions disclosed in the embodiments of this application are:

[0035] This application provides a memory routing design structure, method, and electronic device. The memory routing design structure includes a memory control module, fan-out lines, a main trunk line, several branch fin lines, and several memory modules. The output terminal of the memory control module is connected to the input terminal of the fan-out lines, and the output terminal of the fan-out lines is connected to the input terminal of the main trunk line. The output terminal of the main trunk line is connected to the input terminals of a first branch fin line and a second branch fin line, respectively. The output terminal of the first branch fin line is connected to the input terminal of a first memory module, and the output terminal of the second branch fin line is connected to the input terminal of a second memory module. This application can break the original FLY-BY serial design method of the memory bus through dual-fin symmetrical expansion technology, and control and connect the memory bus in parallel to achieve peer control of memory modules, thereby realizing the equal expansion of two sets of memory modules under a single-channel memory.

[0036] The technical solutions disclosed in this application can continuously improve the operating frequency of memory. By proposing a high-speed memory design scheme based on dual-wing symmetrical expansion technology, the contradiction between high-speed signals and server board design is resolved, thereby improving the read and write performance of memory.

[0037] The technical solution disclosed in this application proposes a high-speed memory bus design method based on dual-wing symmetrical extension technology, which can solve two problems in the design process of high-speed links in SMTDDR bus: first, how to achieve time consistency between the DDR bus and the two memory modules through the dual-wing symmetrical DDR routing scheme design, avoiding memory access latency and dynamic control, and reducing processor computational losses; second, how to achieve complete consistency between the DDR bus and the two memory modules through the dual-wing symmetrical DDR routing scheme design, realizing complete equivalence of the two memory modules on a single channel, and avoiding speed reduction problems due to serial connection of the two memory modules.

[0038] The dual-wing symmetrical DDR bus topology disclosed in this application can effectively solve the drawbacks of access time delay and dynamic control in the original topology, thus effectively improving the read and write efficiency of the DDR bus. Furthermore, the dual-wing symmetrical DDR bus topology method disclosed in this application reduces signal transmission attenuation through impedance matching, effectively reducing signal reflection problems caused by the dual-wing structure. Attached Figure Description

[0039] The above features and advantages of this application can be better understood after reading the detailed description of the embodiments of this disclosure in conjunction with the following accompanying drawings. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0040] Figure 1 A structural diagram of the memory wiring design described in this application is shown;

[0041] Figure 2 A parameter setting diagram of the memory wiring design structure described in this application is shown;

[0042] Figure 3 A flowchart of the memory routing design method described in this application is shown;

[0043] Figure 4 This paper presents a diagram illustrating the effect of memory expansion using the dual-wing symmetrical design of this application.

[0044] Figure 5 A structural diagram of the memory wiring design apparatus described in this application is shown;

[0045] Figure 6 Exemplary systems provided for this application that can be used to implement the various embodiments described in this application. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0047] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. In the description of this application, "a plurality of" or "several" means two or more, unless otherwise explicitly defined.

[0048] Example 1

[0049] This application provides a memory routing design structure, such as... Figure 1 As shown, the memory wiring design structure includes a memory control module (CPU), fan-out lines, a main trunk line, several branch fin lines, and several memory modules.

[0050] The output terminal of the memory control module is connected to the input terminal of the fan-out line, the output terminal of the fan-out line is connected to the input terminal of the main line, and the output terminal of the main line is connected to the input terminals of the first branch fin line and the second branch fin line respectively.

[0051] The output end of the first finned wire is connected to the input end of the first memory module, and the output end of the second finned wire is connected to the input end of the second memory module.

[0052] In this embodiment, the memory wiring design structure further includes branching points.

[0053] The splitting point is connected between the output end of the main line and the input ends of the first splitting line and the second splitting line.

[0054] In this embodiment, the memory control module is used to control read and write operations on the plurality of memory modules;

[0055] The fan-out line is used to lead the clock signal line and / or control signal line and / or data signal line of the memory bus from the pins of the memory control module;

[0056] The backbone is used to transmit signals between the memory control module and the plurality of memory modules; the branching points are used to forward signals from the backbone to the plurality of memory modules;

[0057] The plurality of finned wires are used to transmit signals to the plurality of memory modules at the same time.

[0058] Specifically, the memory routing design structure of this application includes a memory control module, a first memory module, a second memory module, fan-out lines, a main trunk line, branch points, and two branch lines. The memory control module includes a memory controller, which provides the driver for the DDR bus during operation and is responsible for reading and writing operations to the memory module. The memory module provides the physical storage space for system operation and is responsible for storing data that the system can read and write quickly. The fan-out lines are responsible for leading out from the pins of the memory control module, ensuring that the clock, control, and data signal lines of the memory bus can be properly routed out from the dense chip area. The main trunk line is the main routing line connecting the memory control module and the memory module, enabling the parallel and rapid transmission of signals from the DDR bus group to the device end (memory module). The branch points enable the signal splitting and forwarding from the main trunk line to the two memory modules, achieving smooth signal conversion and transmission through back drilling, isolated reference layers, etc. The two branch lines achieve complete separation of the signal link, enabling the signals to be transmitted to the memory module synchronously.

[0059] In this embodiment, as Figure 2 As shown, the impedance value of the fan-out line is within a first threshold range, the trace width of the fan-out line is within a second threshold range, and the trace length of the fan-out line is less than a third threshold; several impedance compensation units are provided on one side of the fan-out line.

[0060] In this embodiment, the impedance value of the trunk line is within a fourth threshold range, the routing length of the trunk line is within a fifth threshold range, and the routing length error value of the trunk line is within a sixth threshold range.

[0061] In this embodiment, the drilling of the wing point is designed by back drilling or hollowing out the circuit board reference layer, and the length of the back drilling residue of the wing point drilling is less than the seventh threshold range.

[0062] Specifically, at the signal initiation design end, 120 sets of DDR bus signals are fanned out through signal lines with a 50-ohm impedance value and a trace width of 4 mils. The trace length of the fan-out signal lines is controlled to be within 500 mils. This low-width, short-length, low-impedance, and high-density fan-out method realizes the output of the DDR memory bus while reducing the impedance loss of the fan-out lines.

[0063] In the main trunk routing area, DDR bus routing is completed with the shortest distance through 40-ohm impedance control. By matching the 2-inch trace length and 10-mil length error, equal length passage within the DDR bus group is achieved, reducing the impedance of the main trunk, increasing the width of the DDR bus, reducing signal attenuation, and providing more design margin for the back-end fin area design. At the same time, the trace width of the main trunk here is about 6 mils.

[0064] In the finned routing area, the DDR bus is routed through the main line to the area between the two memory modules. The finned signal lines are separated into two groups through drilling and symmetrically connected to the two memory modules. The drilling at the finned points requires back drilling and a design method of hollowing out the reference layer to achieve impedance matching between the front and back ends, ensuring that the signal is smoothly transmitted from the main line to the two finned lines through the finned points, reducing signal reflection.

[0065] The first threshold range is approximately 50 ohms; the second threshold range is approximately 4 mils; the third threshold range is 500 mils; the fourth threshold range is approximately 40 ohms; the fifth threshold range is approximately 2 inches; the sixth threshold range is approximately 10 mils; and the seventh threshold range is approximately 5 mils.

[0066] The impedance compensation unit is used to compensate for the impedance of the fan-out line.

[0067] In this embodiment, the impedance value of the finned wire is within a first threshold range, the routing length of the finned wire is within an eighth threshold range, and the routing length error value of the finned wire is within a ninth threshold range; the impedance value, routing length, and routing length error value of each finned wire are the same.

[0068] Specifically, the branch wire adopts a 50-ohm impedance value, the wiring length is designed to be 0.5 inches with a wiring length error of 2 mils, and both ends are strictly designed to be of equal length and width to ensure the consistency of the link design.

[0069] Understandably, by fixing the DDR bus design parameters, the memory bus based on the dual-wing symmetrical expansion technology can achieve consistent length and signal loss between the memory controller and two different memory modules. The dual-wing symmetrical expansion technology can achieve completely consistent transmission delay and matching impedance. After power-on, the relevant configuration is directly fixed according to the design parameters, avoiding the software involvement of the memory controller during DDR bus transmission, reducing the loss of this part of the computing performance, and improving memory performance.

[0070] The eighth threshold range is approximately 0.5 inches; the ninth threshold range is approximately 2 mils; the impedance values ​​of the fan-out line, main line, and branch line are determined by the CPU's driving capability or CPU performance.

[0071] The beneficial effects of the technical solutions disclosed in the embodiments of this application are:

[0072] This application provides a memory routing design structure, method, and electronic device. The memory routing design structure includes a memory control module, fan-out lines, a main trunk line, several branch fin lines, and several memory modules. The output terminal of the memory control module is connected to the input terminal of the fan-out lines, and the output terminal of the fan-out lines is connected to the input terminal of the main trunk line. The output terminal of the main trunk line is connected to the input terminals of a first branch fin line and a second branch fin line, respectively. The output terminal of the first branch fin line is connected to the input terminal of a first memory module, and the output terminal of the second branch fin line is connected to the input terminal of a second memory module. This application can break the original FLY-BY serial design method of the memory bus through dual-fin symmetrical expansion technology, and control and connect the memory bus in parallel to achieve peer control of memory modules, thereby realizing the equal expansion of two sets of memory modules under a single-channel memory.

[0073] The technical solutions disclosed in this application can continuously improve the operating frequency of memory. By proposing a high-speed memory design scheme based on dual-wing symmetrical expansion technology, the contradiction between high-speed signals and server board design is resolved, thereby improving the read and write performance of memory.

[0074] The technical solution disclosed in this application proposes a high-speed memory bus design method based on dual-wing symmetrical extension technology, which can solve two problems in the design process of high-speed links in SMTDDR bus: first, how to achieve time consistency between the DDR bus and the two memory modules through the dual-wing symmetrical DDR routing scheme design, avoiding memory access latency and dynamic control, and reducing processor computational losses; second, how to achieve complete consistency between the DDR bus and the two memory modules through the dual-wing symmetrical DDR routing scheme design, realizing complete equivalence of the two memory modules on a single channel, and avoiding speed reduction problems due to serial connection of the two memory modules.

[0075] Example 2

[0076] This application provides a memory routing design method, such as Figure 3 As shown, the method includes:

[0077] Step S1: Create a memory routing design structure using a dual-wing symmetrical extension routing method.

[0078] Specifically, by using a memory bus based on dual-wing symmetrical expansion technology, the length and signal loss of the memory controller to the two different memory modules are made consistent. Based on dual-wing symmetrical expansion technology, the transmission delay and matching impedance can be made completely consistent. After power-on, the relevant configuration is directly fixed according to the design parameters, avoiding the software involvement of the memory controller during DDR bus transmission, reducing the loss of this part of the computing performance, and improving memory performance.

[0079] Step S1 also includes:

[0080] Step S11: Connect the output terminal of the memory control module to the input terminal of the fan-out line, connect the output terminal of the fan-out line to the input terminal of the main line, connect the output terminal of the main line to the input terminal of the fin-splitting point, and connect the output terminal of the fin-splitting point to the input terminals of the first fin-splitting line and the second fin-splitting line respectively.

[0081] Connect the output end of the first finned wire to the input end of the first memory module, and connect the output end of the second finned wire to the input end of the second memory module.

[0082] Step S2: Set the parameters for each component of the memory wiring design structure.

[0083] Step S2 also includes:

[0084] Step S21: Set the impedance value of the fan-out line to a first threshold range, set the trace width of the fan-out line to a second threshold range, and set the trace length of the fan-out line to be less than a third threshold; set several impedance compensation units on one side of the fan-out line.

[0085] The impedance value of the trunk line is set to a fourth threshold range, the routing length of the trunk line is set to a fifth threshold range, and the routing length error value of the trunk line is set to a sixth threshold range.

[0086] The drilling holes for the fin points are designed by back drilling or hollowing out the reference layer of the circuit board, and the length of the back drilling residue of the fin point drilling holes is set to be less than the seventh threshold range.

[0087] The impedance value of the finned wire is set to a first threshold range, the trace length of the finned wire is set to an eighth threshold range, and the trace length error value of the finned wire is set to a ninth threshold range; the impedance value, trace length, and trace length error value of each finned wire are set to be the same.

[0088] Specifically, such as Figure 4 As shown, Figure 4 This diagram illustrates the effect of a dual-wing symmetrical memory expansion design. The fan-out area employs a low-resistance, high-density design, while the main line area utilizes low-loss design and a design approach that matches the error value of the trace length. The wing-shaped areas use CPU impedance matching, and a symmetrical routing design is employed. This high-speed memory bus design method based on dual-wing symmetrical expansion technology can solve two problems in the design process of high-speed links in SMTDDR buses: First, how to achieve time consistency between the DDR bus and the two memory modules through a dual-wing symmetrical DDR routing scheme, avoiding memory access latency and dynamic control, and reducing processor computational overhead; second, how to achieve complete consistency between the DDR bus and the two memory modules through a dual-wing symmetrical DDR routing scheme, ensuring complete equivalence of the two memory modules on a single channel and avoiding speed reduction issues caused by serial connections between the two memory modules.

[0089] The purpose of back drilling is to drill out vias that do not serve any connection or transmission function, thereby avoiding reflection, scattering, and delay in high-speed signal transmission, which can cause signal distortion. In addition to design, board material, transmission lines, connectors, and chip packaging, vias have a significant impact on signal integrity.

[0090] This application creates a memory routing design structure by using a dual-wing symmetrical expansion routing method. By setting parameters for each component of the memory routing design structure, the original FLY-BY serial design method of the memory bus can be broken through the dual-wing symmetrical expansion technology. The memory bus can be controlled and connected in parallel to achieve equal control of the memory modules, thereby realizing equal expansion of two sets of memory modules under a single-channel memory.

[0091] The memory routing design method provided in this application embodiment can be improved and optimized in several ways without departing from the technical solution of this application, and these improvements and optimizations should also be considered within the protection scope of this application.

[0092] The beneficial effects of the technical solutions disclosed in the embodiments of this application are:

[0093] The technical solution disclosed in this application proposes a high-speed memory bus design method based on dual-wing symmetrical extension technology, which can solve two problems in the design process of high-speed links in SMTDDR bus: first, how to achieve time consistency between the DDR bus and the two memory modules through the dual-wing symmetrical DDR routing scheme design, avoiding memory access latency and dynamic control, and reducing processor computational losses; second, how to achieve complete consistency between the DDR bus and the two memory modules through the dual-wing symmetrical DDR routing scheme design, realizing complete equivalence of the two memory modules on a single channel, and avoiding speed reduction problems due to serial connection of the two memory modules.

[0094] The dual-wing symmetrical DDR bus topology disclosed in this application can effectively solve the drawbacks of access time delay and dynamic control in the original topology, thus effectively improving the read and write efficiency of the DDR bus. Furthermore, the dual-wing symmetrical DDR bus topology method disclosed in this application reduces signal transmission attenuation through impedance matching, effectively reducing signal reflection problems caused by the dual-wing structure.

[0095] Example 3

[0096] This application provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it can perform the following memory wiring design method:

[0097] A memory routing design structure is created using a dual-wing symmetrical extension routing method for memory.

[0098] The parameters of each component of the memory wiring design structure are set.

[0099] The beneficial effects of the technical solutions provided in this application are:

[0100] The technical solutions disclosed in this application can continuously improve the operating frequency of memory. By proposing a high-speed memory design scheme based on dual-wing symmetrical expansion technology, the contradiction between high-speed signals and server board design is resolved, thereby improving the read and write performance of memory.

[0101] The technical solution disclosed in this application proposes a high-speed memory bus design method based on dual-wing symmetrical extension technology, which can solve two problems in the design process of high-speed links in SMTDDR bus: first, how to achieve time consistency between the DDR bus and the two memory modules through the dual-wing symmetrical DDR routing scheme design, avoiding memory access latency and dynamic control, and reducing processor computational losses; second, how to achieve complete consistency between the DDR bus and the two memory modules through the dual-wing symmetrical DDR routing scheme design, realizing complete equivalence of the two memory modules on a single channel, and avoiding speed reduction problems due to serial connection of the two memory modules.

[0102] Example 4

[0103] This application provides a memory wiring design device, such as Figure 5 As shown, the device includes a creation module and a setting module.

[0104] In this embodiment, a creation module is used to create a memory routing design structure using a memory double-wing symmetrical extension routing method;

[0105] The configuration module is used to set parameters for each component of the memory wiring design structure.

[0106] In this embodiment, a creation module is used to connect the output terminal of the memory control module to the input terminal of the fan-out line, connect the output terminal of the fan-out line to the input terminal of the trunk line, connect the output terminal of the trunk line to the input terminal of the fin point, and connect the output terminal of the fin point to the input terminals of the first fin line and the second fin line respectively.

[0107] Connect the output end of the first finned wire to the input end of the first memory module, and connect the output end of the second finned wire to the input end of the second memory module.

[0108] In this embodiment, the setting module is further configured to set the impedance value of the fan-out line to a first threshold range, set the trace width of the fan-out line to a second threshold range, set the trace length of the fan-out line to be less than a third threshold, and set a plurality of impedance compensation units on one side of the fan-out line.

[0109] The impedance value of the trunk line is set to a fourth threshold range, the routing length of the trunk line is set to a fifth threshold range, and the routing length error value of the trunk line is set to a sixth threshold range.

[0110] The drilling holes for the fin points are designed by back drilling or hollowing out the reference layer of the circuit board, and the length of the back drilling residue of the fin point drilling holes is set to be less than the seventh threshold range.

[0111] The impedance value of the finned wire is set to a first threshold range, the trace length of the finned wire is set to an eighth threshold range, and the trace length error value of the finned wire is set to a ninth threshold range; the impedance value, trace length, and trace length error value of each finned wire are set to be the same.

[0112] The beneficial effects of the technical solutions provided in this application are:

[0113] The technical solution disclosed in this application proposes a high-speed memory bus design method based on dual-wing symmetrical extension technology, which can solve two problems in the design process of high-speed links in SMTDDR bus: first, how to achieve time consistency between the DDR bus and the two memory modules through the dual-wing symmetrical DDR routing scheme design, avoiding memory access latency and dynamic control, and reducing processor computational losses; second, how to achieve complete consistency between the DDR bus and the two memory modules through the dual-wing symmetrical DDR routing scheme design, realizing complete equivalence of the two memory modules on a single channel, and avoiding speed reduction problems due to serial connection of the two memory modules.

[0114] Example 5

[0115] This application provides a computer storage medium, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, it performs the following steps:

[0116] A memory routing design structure is created using a dual-wing symmetrical extension routing method for memory.

[0117] The parameters of each component of the memory wiring design structure are set.

[0118] In some embodiments, the creation of the memory routing design structure through the memory dual-wing symmetrical extension routing method includes:

[0119] Connect the output terminal of the memory control module to the input terminal of the fan-out line, connect the output terminal of the fan-out line to the input terminal of the main line, connect the output terminal of the main line to the input terminal of the fin-splitting point, and connect the output terminal of the fin-splitting point to the input terminals of the first fin-splitting line and the second fin-splitting line respectively.

[0120] Connect the output end of the first finned wire to the input end of the first memory module, and connect the output end of the second finned wire to the input end of the second memory module.

[0121] In some embodiments, setting parameters for each component of the memory wiring design structure includes:

[0122] The impedance value of the fan-out line is set to a first threshold range, the trace width of the fan-out line is set to a second threshold range, and the trace length of the fan-out line is set to be less than a third threshold; several impedance compensation units are set on one side of the fan-out line.

[0123] The impedance value of the trunk line is set to a fourth threshold range, the routing length of the trunk line is set to a fifth threshold range, and the routing length error value of the trunk line is set to a sixth threshold range.

[0124] The drilling holes for the fin points are designed by back drilling or hollowing out the circuit board reference layer, and the length of the back drilling residue of the fin point drilling holes is set to be less than the seventh threshold range.

[0125] The impedance value of the finned wire is set to a first threshold range, the trace length of the finned wire is set to an eighth threshold range, and the trace length error value of the finned wire is set to a ninth threshold range; the impedance value, trace length, and trace length error value of each finned wire are set to be the same.

[0126] Figure 6 This is an exemplary system provided as Embodiment 5 of the present application, which can be used to implement the various embodiments described in this application;

[0127] like Figure 6 As shown, in some embodiments, the system can function as any of the aforementioned devices for memory routing design in each of the various embodiments. In some embodiments, the system may include one or more computer-readable media (e.g., system memory or NVM / storage device) having a result and one or more processors (e.g., one or more processors) coupled to the one or more computer-readable media and configured to execute the result to implement the module thereby performing the actions described in this application.

[0128] The beneficial effects of the technical solutions provided in this application are:

[0129] The technical solution disclosed in this application can break the original FLY-BY serial design of the memory bus through the double-wing symmetrical expansion technology, and control and connect the memory bus in parallel to realize the equal control of the memory modules, thereby realizing the equal expansion of two sets of memory modules under a single channel memory.

[0130] The technical solutions disclosed in this application can continuously improve the operating frequency of memory. By proposing a high-speed memory design scheme based on dual-wing symmetrical expansion technology, the contradiction between high-speed signals and server board design is resolved, thereby improving the read and write performance of memory.

[0131] Example 6

[0132] This application provides an electronic device, which includes a memory wiring design circuit and other electronic components. The memory wiring design circuit includes a memory wiring design structure, which includes a memory control module, fan-out lines, a main line, several branch lines, and several memory modules.

[0133] The output terminal of the memory control module is connected to the input terminal of the fan-out line, the output terminal of the fan-out line is connected to the input terminal of the main line, and the output terminal of the main line is connected to the input terminals of the first branch fin line and the second branch fin line respectively.

[0134] The output end of the first finned wire is connected to the input end of the first memory module, and the output end of the second finned wire is connected to the input end of the second memory module.

[0135] In some embodiments, the memory wiring design structure further includes branch points.

[0136] The splitting point is connected between the output end of the main line and the input ends of the first splitting line and the second splitting line.

[0137] In some embodiments, the memory control module is used to control read and write operations on the plurality of memory modules;

[0138] The fan-out line is used to lead the clock signal line and / or control signal line and / or data signal line of the memory bus from the pins of the memory control module;

[0139] The backbone is used to transmit signals between the memory control module and the plurality of memory modules; the branching points are used to forward signals from the backbone to the plurality of memory modules;

[0140] The plurality of finned wires are used to transmit signals to the plurality of memory modules at the same time.

[0141] In some embodiments, the impedance value of the fan-out line is within a first threshold range, the trace width of the fan-out line is within a second threshold range, and the trace length of the fan-out line is less than a third threshold; a plurality of impedance compensation units are provided on one side of the fan-out line.

[0142] In some embodiments, the impedance value of the trunk line is within a fourth threshold range, the routing length of the trunk line is within a fifth threshold range, and the routing length error value of the trunk line is within a sixth threshold range.

[0143] In some embodiments, the drilling of the finned point is designed by back drilling or hollowing out the circuit board reference layer, and the length of the back drill residue of the finned point drilling is less than the seventh threshold range.

[0144] In some embodiments, the impedance value of the finned wire is within a first threshold range, the trace length of the finned wire is within an eighth threshold range, and the trace length error value of the finned wire is within a ninth threshold range; the impedance value, trace length, and trace length error value of each finned wire are the same.

[0145] The technical solutions disclosed in this application can solve two problems in the design process of high-speed links for SMTDDR buses: first, how to achieve time consistency between the DDR bus and the two memory modules through a double-wing symmetrical DDR routing scheme design, avoiding memory access latency and dynamic control, and reducing processor computational losses; second, how to achieve complete consistency between the DDR bus and the two memory modules through a double-wing symmetrical DDR routing scheme design, achieving complete equivalence between the two memory modules on a single channel, and avoiding speed reduction problems caused by serial access of the two memory modules.

[0146] All of the above-mentioned optional technical solutions can be combined in any way to form the optional embodiments of this application, and will not be described in detail here.

[0147] Although preferred embodiments have been described in this application, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of this application.

[0148] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

[0149] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0150] The contents not described in detail in this specification are existing technologies known to those skilled in the art.

Claims

1. A memory wiring design structure, characterized in that, The memory wiring design structure includes a memory control module, fan-out lines, main lines, branch points, several branch lines, and several memory modules. The output terminal of the memory control module is connected to the input terminal of the fan-out line, the output terminal of the fan-out line is connected to the input terminal of the main line, and the output terminal of the main line is connected to the input terminals of the first branch fin line and the second branch fin line respectively. The output end of the first finned wire is connected to the input end of the first memory module, and the output end of the second finned wire is connected to the input end of the second memory module. The impedance value of the fan-out line is within a first threshold range, the trace width of the fan-out line is within a second threshold range, and the trace length of the fan-out line is less than a third threshold. Several impedance compensation units are provided on one side of the fan-out line, and the impedance compensation units are used to compensate for the impedance of the fan-out line. The impedance value of the trunk line is within the fourth threshold range, the routing length of the trunk line is within the fifth threshold range, and the routing length error value of the trunk line is within the sixth threshold range. The drilling of the wing point is designed by back drilling or hollowing out the circuit board reference layer, and the length of the back drilling residue of the wing point drilling is less than the seventh threshold range. The impedance value of the finned wire is within the first threshold range, the routing length of the finned wire is within the eighth threshold range, and the routing length error value of the finned wire is within the ninth threshold range; the impedance value, routing length, and routing length error value of each finned wire are the same. The impedance values ​​of the fan-out line, main line, and branch fin line are determined by the processor's driving capability or processor performance.

2. The memory wiring design structure according to claim 1, characterized in that, The splitting point is connected between the output end of the main line and the input ends of the first splitting line and the second splitting line.

3. The memory wiring design structure according to claim 2, characterized in that, The memory control module is used to control read and write operations on the plurality of memory modules; The fan-out line is used to lead the clock signal line and / or control signal line and / or data signal line of the memory bus from the pins of the memory control module; The backbone is used to transmit signals between the memory control module and the plurality of memory modules; the branching points are used to forward signals from the backbone to the plurality of memory modules; The plurality of finned wires are used to transmit signals to the plurality of memory modules at the same time.

4. A memory routing design method, applied to the memory routing design structure as described in any one of claims 1-3, characterized in that, The method includes: A memory routing design structure is created using a symmetrical double-wing extension routing method for memory. The parameters of each component of the memory wiring design structure are set.

5. The memory routing design method according to claim 4, characterized in that, The memory routing design structure created by the memory double-wing symmetrical extension routing method includes: Connect the output terminal of the memory control module to the input terminal of the fan-out line, connect the output terminal of the fan-out line to the input terminal of the main line, connect the output terminal of the main line to the input terminal of the fin-splitting point, and connect the output terminal of the fin-splitting point to the input terminals of the first fin-splitting line and the second fin-splitting line respectively. Connect the output end of the first finned wire to the input end of the first memory module, and connect the output end of the second finned wire to the input end of the second memory module.

6. The memory routing design method according to claim 4, characterized in that, The parameter setting of each component of the memory wiring design structure includes: The impedance value of the fan-out line is set to a first threshold range, the trace width of the fan-out line is set to a second threshold range, and the trace length of the fan-out line is set to be less than a third threshold; several impedance compensation units are set on one side of the fan-out line. The impedance value of the trunk line is set to a fourth threshold range, the routing length of the trunk line is set to a fifth threshold range, and the routing length error value of the trunk line is set to a sixth threshold range. The drilling holes for the fin points are designed by back drilling or hollowing out the reference layer of the circuit board, and the length of the back drilling residue of the fin point drilling holes is set to be less than the seventh threshold range. The impedance value of the finned wire is set to a first threshold range, the trace length of the finned wire is set to an eighth threshold range, and the trace length error value of the finned wire is set to a ninth threshold range; the impedance value, trace length, and trace length error value of each finned wire are set to be the same.

7. An electronic device, characterized in that, The electronic device includes a memory wiring design circuit and other electronic components, wherein the memory wiring design circuit includes the memory wiring design structure as described in any one of claims 1-3.

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