Semiconductor structure with pn junction and method for producing the same

Abstract

The application provides a semiconductor structure with a PN junction and a preparation method thereof. The semiconductor structure with the PN junction of the application changes the morphology of a photoresist layer, sets the thickness of the photoresist layer at the edge of an opening to be smaller than the thickness of the photoresist layer in other regions, so that the ion implantation concentration of the corresponding local region at the edge of the opening is small due to the small thickness of the photoresist layer, the ion implantation concentration of the central region of the opening is normal to obtain a normal ion implantation concentration, so that the ion implantation concentration of the PN junction is low, the reverse voltage of the PN junction can be effectively improved, and the occupied area of the PN junction is not increased; meanwhile, the ion implantation concentration of other regions of the well region is normal, so that the electrical property of other devices is not changed.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more particularly to a semiconductor structure having a PN junction and a method for preparing the same. Background Technology

[0002] With the continuous advancement of semiconductor integrated circuit manufacturing technology, the performance of semiconductor devices is constantly improving. The PN junction is the most basic structural unit in semiconductor devices. It has the unidirectional conductivity characteristic of forward conduction and reverse cutoff, which is utilized by many devices in electronic technology (such as semiconductor diodes and bipolar transistors). It is mainly used in rectification, amplification, switching and isolation applications.

[0003] Please see Figure 1 This is a schematic diagram of a typical PN junction. For example... Figure 1 As shown, by employing different doping processes between the isolation structures 19 of the semiconductor substrate 10 (typically silicon, germanium, or silicon carbide), N-type ions are implanted on one side to form an N-well region 11, and P-type ions are implanted on the other side to form a P-well region 12. A space charge region, called a PN junction 13, is formed on both sides of the contact surface 101 between the P-well region 12 and the N-well region 11. The thickness of the space charge region is related to the dopant concentration.

[0004] The reverse breakdown voltage of a PN junction is one of its important parameters, and improving the reverse breakdown voltage of a PN junction is a key focus of semiconductor research and development. Common methods to improve the reverse breakdown voltage of a PN junction include: 1. Reducing the ion implantation concentration of P-type and N-type ions; 2. Increasing the spacing 209 between the P-well region 12 and the N-well region 11, such as... Figure 2 As shown; 3. The ion implantation region is locally segmented to form multiple slots 311 and 321, and then homogenized through thermal diffusion, as shown. Figure 3 As shown.

[0005] Reducing the ion implantation concentration of P-type and N-type ions can effectively improve the reverse breakdown voltage of the PN junction, but it also leads to changes in the electrical properties of other devices, such as alterations in resistance, capacitance, and transistor channel threshold voltage related to the implantation type. Furthermore, reducing the ion implantation concentration makes it difficult to standardize the concentration requirements of different devices for the same ion implantation channel. Figure 2 The method of increasing the spacing shown can effectively improve reverse withstand voltage, but for high withstand voltage requirements, this method will greatly increase the PN junction area. Figure 3 The method shown can also effectively improve reverse breakdown voltage without increasing the area occupied by the PN junction. However, for semiconductor structures with small size, it is not possible to perform finer area division, which limits its implementation process. Summary of the Invention

[0006] The technical problem to be solved by this application is to provide a semiconductor structure with a PN junction and a method for preparing the same, which can obtain a locally low concentration of PN junction without adding any additional processes on the basis of existing processes, thereby effectively improving the reverse breakdown voltage of the PN junction.

[0007] To address the aforementioned problems, this application provides a method for fabricating a semiconductor structure with a PN junction, comprising the following steps: providing a semiconductor substrate having a first region and a second region separated by multiple isolation structures, wherein the surfaces of all the isolation structures are substantially flush with the surface of the semiconductor substrate; forming a first photoresist layer on the surface of the semiconductor substrate, the first photoresist layer having a first opening exposing the first region, the first photoresist layer having a first auxiliary photoresist layer located at the edge of the first opening and a first main photoresist layer adjacent to the first auxiliary photoresist layer, wherein the thickness of the first auxiliary photoresist layer is less than the thickness of the first main photoresist layer; performing ion implantation of a first conductivity type on the semiconductor substrate using the first photoresist layer as a mask to form a first well region and removing the first photoresist layer, wherein the first well region includes the first region after ion implantation and a third region, the third region being located on the side of the isolation structure away from the surface of the semiconductor substrate and adjacent to the first region. The ion implantation concentration in the third region is less than that in the first region. A second photoresist layer is formed on the surface of the semiconductor substrate. The second photoresist layer has a second opening that exposes the second region. The second photoresist layer has a second auxiliary photoresist layer located at the edge of the second opening and a second main photoresist layer adjacent to the second auxiliary photoresist layer. The thickness of the second auxiliary photoresist layer is less than that of the second main photoresist layer. Using the second photoresist layer as a mask, the semiconductor substrate is subjected to ion implantation of a second conductivity type to form a second well region and the second photoresist layer is removed. The second well region includes the second region after ion implantation and a fourth region. The fourth region is located on the side of the isolation structure away from the surface of the semiconductor substrate and is adjacent to the second region. The ion implantation concentration of the fourth region is less than that of the second region. The fourth region is in contact with the third region, thereby forming a PN junction on both sides of the contact surface. The first conductivity type and the second conductivity type are opposite.

[0008] To address the aforementioned issues, this application also provides a semiconductor structure with a PN junction, comprising: a semiconductor substrate having a first region and a second region separated by a plurality of isolation structures; a first well region having a first conductivity type, the first well region comprising the first region after ion implantation and a third region, the third region being located on the side of the isolation structure away from the semiconductor substrate and adjacent to the first region, the ion implantation concentration of the third region being less than the ion implantation concentration of the first region; a second well region having a second conductivity type, the second well region comprising the second region after ion implantation and a fourth region, the fourth region being located on the side of the isolation structure away from the semiconductor substrate and adjacent to the second region, the ion implantation concentration of the fourth region being less than the ion implantation concentration of the second region, the first conductivity type and the second conductivity type being opposite; and a PN junction formed on both sides of the contact surface where the fourth region and the third region are in contact.

[0009] The above technical solution, by changing the morphology of the photoresist layer, achieves a lower ion implantation concentration in the PN junction, which can effectively improve the reverse breakdown voltage of the PN junction without increasing the area occupied by the PN junction; at the same time, the ion implantation concentration in other regions of the well region is normal, avoiding electrical changes to other devices.

[0010] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this application. Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the specific embodiments of this application, the accompanying drawings used in the description of the specific embodiments will be briefly introduced below. Obviously, the drawings described below are only some specific embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of a typical PN junction;

[0013] Figure 2 This is a schematic diagram of an embodiment of improving the reverse breakdown voltage of a PN junction;

[0014] Figure 3 This is a schematic diagram of another embodiment of improving the reverse breakdown voltage of a PN junction;

[0015] Figure 4 A flowchart illustrating the steps of a method for fabricating a semiconductor structure with a PN junction according to an embodiment of this application;

[0016] Figures 5-10 This is a process flow diagram of a method for fabricating a semiconductor structure with a PN junction according to an embodiment of this application. Detailed Implementation

[0017] The technical solutions in the embodiments of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0018] Please refer to the following: Figures 4 to 10 ,in, Figure 4 This is a flowchart illustrating the steps of a method for fabricating a semiconductor structure with a PN junction according to an embodiment of this application. Figures 5-10 This is a process flow diagram of a method for fabricating a semiconductor structure with a PN junction according to an embodiment of this application.

[0019] like Figure 4As shown, the method for fabricating a semiconductor structure with a PN junction according to this application includes the following steps: Step S41, providing a semiconductor substrate, wherein the semiconductor substrate has a first region and a second region separated by a plurality of isolation structures, and the surfaces of all the isolation structures are substantially flush with the surface of the semiconductor substrate; Step S42, forming a first photoresist layer on the surface of the semiconductor substrate, the first photoresist layer having a first opening, the first opening exposing the first region, the first photoresist layer having a first auxiliary photoresist layer located at the edge of the first opening and a first main photoresist layer adjacent to the first auxiliary photoresist layer, and the thickness of the first auxiliary photoresist layer being less than the thickness of the first main photoresist layer; Step S43, using the first photoresist layer as a mask, performing ion implantation of a first conductivity type on the semiconductor substrate to form a first well region and removing the first photoresist layer, wherein the first well region includes the first region after ion implantation and a third region, the third region being located on the side of the isolation structure away from the surface of the semiconductor substrate and adjacent to the first region, the first photoresist layer being... The ion implantation concentration in the third region is less than that in the first region; step S44, a second photoresist layer is formed on the surface of the semiconductor substrate, the second photoresist layer has a second opening, the second opening exposes the second region, the second photoresist layer has a second auxiliary photoresist layer located at the edge of the second opening and a second main photoresist layer adjacent to the second auxiliary photoresist layer, and the thickness of the second auxiliary photoresist layer is less than the thickness of the second main photoresist layer; and step S45, the semiconductor substrate is subjected to second conductivity type ion implantation using the second photoresist layer as a mask to form a second well region and the second photoresist layer is removed, wherein the second well region includes the second region after ion implantation and a fourth region, the fourth region is located on the side of the isolation structure away from the surface of the semiconductor substrate and is adjacent to the second region, the ion implantation concentration of the fourth region is less than that of the second region, the fourth region is in contact with the third region, thereby forming a PN junction on both sides of the contact surface, the first conductivity type and the second conductivity type are opposite.

[0020] Please see Figure 5 In step S41, a semiconductor substrate 40 is provided, wherein the semiconductor substrate 40 has a first region 401 and a second region 402 separated by a plurality of isolation structures 49.

[0021] In this embodiment, the semiconductor substrate 40 can be any one of a silicon (Si) substrate, silicon carbide (SiC), or silicon nitride (SiN). The semiconductor substrate 40 can also be a multilayer structure, such as a silicon / germanium / silicon multilayer. In this embodiment, a silicon substrate is used as an example for illustration.

[0022] In this embodiment, an isolation structure 49 is provided within the semiconductor substrate 40. Two adjacent isolation structures 49 can define corresponding first regions 401 and second regions 402 within the semiconductor substrate 40. In this embodiment, the surfaces of all the isolation structures 49 are substantially flush with the surface of the semiconductor substrate 40. The width of the isolation structure 49 between the first region 401 and the second region 402 is greater than the width of the isolation structures 49 on the other side of the first region 401 and the other side of the second region 402. In this embodiment, the isolation structure 49 can be a shallow trench isolation (STI) structure. A trench is formed by depositing, patterning, and etching a silicon substrate using a silicon nitride mask, and then filling the trench with deposited oxide to form a shallow trench isolation structure for insulating isolation between adjacent regions. Its characteristic is that it can achieve high-density isolation. The isolation structure 49 can be a single-layer or multi-layer composite structure. For example, in some embodiments, the isolation structure 49 is an oxide isolation structure; in other embodiments, the isolation structure 49 is a composite structure of a silicon oxide isolation structure and a nitride isolation structure.

[0023] Please see Figure 6 In step S42, a first photoresist layer 41 is formed on the surface of the semiconductor substrate 40. The first photoresist layer 41 has a first opening 410 that exposes the first region 401. The first photoresist layer 41 has a first auxiliary photoresist layer 411 located at the edge of the first opening 410 and a first main photoresist layer 412 adjacent to the first auxiliary photoresist layer 411. The thickness of the first auxiliary photoresist layer 411 is less than the thickness of the first main photoresist layer 412. The thickness of the photoresist layer is defined as its height in a direction perpendicular to the surface of the semiconductor substrate 40.

[0024] This embodiment modifies the morphology of the photoresist layer, making the thickness of the photoresist layer at the opening edge smaller than that in other areas. This results in a lower ion implantation concentration in the corresponding local area at the opening edge due to the smaller thickness of the photoresist layer, while the ion implantation in the opening center area is normal, thus achieving a normal ion implantation concentration. This achieves the goal of reducing the ion implantation concentration in the local area at the opening edge without affecting the ion implantation concentration in the opening center area.

[0025] In this embodiment, the bottom 4101 of the first opening 410 is the semiconductor substrate 40, and the two opposite sides 4102 and 4103 of the first opening 410 are the first photoresist layer 41. The sides 4102 and 4103 extend away from the semiconductor substrate 40 at an acute angle to its surface. The acute angle (e.g.) Figure 6θ can be between 45 and 75 degrees. The first opening 410 thus formed has a completely penetrating portion and a portion with a gradually changing cross-sectional thickness. The completely penetrating portion corresponds to the first region 401, which can form a well region of normal concentration during subsequent ion implantation; the portion with a gradually changing cross-sectional thickness, because the first photoresist layer 41 is partially retained, will block the implantation of some ions during subsequent ion implantation, resulting in a well region with a lower concentration. The specific parameters of the first opening 410 can be adjusted according to the well region parameters and process conditions, and are not specifically limited here.

[0026] In this embodiment, the cross-section of the first opening 410 is an inverted trapezoid in the direction perpendicular to the surface of the semiconductor substrate 40. That is, the two opposite sides 4102 and 4103 of the first opening 410 are smooth oblique lines, so that the ion implantation concentration in the regions corresponding to the two opposite sides 4102 and 4103 of the first opening 410 gradually changes.

[0027] In this embodiment, the thickness of the first auxiliary photoresist layer 411 gradually decreases in the direction away from the first main photoresist layer 412; thus, the ion implantation concentration in the region corresponding to the first auxiliary photoresist layer 411 gradually decreases in the direction away from the first region. In other embodiments, the first auxiliary photoresist layer 411 and the first main photoresist layer 412 may also form a stepped structure with different thicknesses, so that the obstruction of ion implantation by the first auxiliary photoresist layer 411 is less than that by the first main photoresist layer 412, thereby the region corresponding to the first auxiliary photoresist layer 411 has a lower ion implantation concentration.

[0028] In some embodiments, the step of forming a first photoresist layer 41 on the semiconductor substrate 40 further includes: (1) forming a first photoresist material layer on the semiconductor substrate; (2) forming a pattern of the first opening on the first photoresist material layer by photolithography; and (3) developing the first photoresist material layer to form the first photoresist layer. Specifically, a layer of photoresist is first laid on the surface of the semiconductor substrate, and then a predefined mask (with the pattern of the first opening already defined on the mask) is placed on it. Finally, after irradiation with light of a specific wavelength, the activated photoresist is washed away with a specific liquid. The photoresist is left as a photoresist layer in areas where ion implantation is not required, and the photoresist is removed in areas where ion implantation is required. Photoresist (PR), also known as photoresist, is a photosensitive organic compound whose solubility in a specific liquid (e.g., developer) changes after being irradiated with light of a specific wavelength (e.g., ultraviolet light). Specifically, the photoresist in the illuminated areas becomes activated, and the activated photoresist is particularly easy to wash away with certain chemical liquids; the areas blocked by the mask are not activated because they are not illuminated by the light source, and the unactivated photoresist cannot be washed away.

[0029] Please see Figure 7 In step S43, using the first photoresist layer 41 as a mask, ion implantation of a first conductivity type is performed on the semiconductor substrate 40 to form a first well region 43, and the first photoresist layer 41 is removed. The first well region 43 includes a first region 401 after ion implantation and a third region 431; the third region 431 is located on the side of the isolation structure 49 away from the surface of the semiconductor substrate 40 and is adjacent to the first region 401, and the ion implantation concentration of the third region 431 is lower than the ion implantation concentration of the first region 401.

[0030] Due to the change in photoresist layer morphology, the thickness of the photoresist layer at the opening edge is less than that in other areas, resulting in a lower ion implantation concentration in the third region 431 corresponding to the opening edge, while the ion implantation concentration in the first region 401 corresponding to the opening center is normal (the conventional concentration required for the well region of a semiconductor device). The third region 431, as the region for subsequent PN junction formation, effectively improves the reverse breakdown voltage of the PN junction due to the reduced ion implantation concentration, and this method does not increase the PN junction area. At the same time, the normal ion implantation concentration in the first region 401 avoids electrical changes to other devices.

[0031] In this embodiment, the ion implantation concentration of the third region 431 gradually decreases in the direction away from the first region 401. In other embodiments, the ion implantation concentration of the third region 431 may also be a uniform concentration, and less than the ion implantation concentration of the first region 401.

[0032] In this embodiment, the first conductivity type is N-type. In other embodiments, the first conductivity type may also be P-type.

[0033] Please see Figure 8 In step S44, a second photoresist layer 42 is formed on the surface of the semiconductor substrate 40. The second photoresist layer 42 has a second opening 420 that exposes the second region 402. The second photoresist layer 42 has a second auxiliary photoresist layer 421 located at the edge of the second opening 402 and a second main photoresist layer 422 adjacent to the second auxiliary photoresist layer 421. The thickness of the second auxiliary photoresist layer 421 is less than the thickness of the second main photoresist layer 422. The second photoresist layer 42 can be fabricated using the same process as the first photoresist layer 41, and the shape of the second opening 420 is substantially the same as the shape of the first opening 410.

[0034] Please see Figure 9 In step S45, using the second photoresist layer 42 as a mask, ion implantation of the second conductivity type is performed on the semiconductor substrate 40 to form a second well region 44, and then the second photoresist layer 42 is removed. The second well region 44 includes the second region 402 after ion implantation and a fourth region 441. The fourth region 441 is located on the side of the isolation structure 49 away from the surface of the semiconductor substrate 40 and is adjacent to the second region 402. The ion implantation concentration of the fourth region 441 is lower than that of the second region 402. The fourth region 441 is in contact with the third region 431, thereby forming a PN junction 45 on both sides of the contact surface 450. The first conductivity type and the second conductivity type are opposite.

[0035] Due to the change in photoresist layer morphology, the ion implantation concentrations of the fourth region 441 and the third region 431 are relatively low. As a result, the ion implantation concentration of the PN junction 45 formed on both sides of the contact surface 450 of the fourth region 441 and the third region 431 is reduced, which can effectively improve the reverse breakdown voltage of the PN junction, and this method does not increase the PN junction area. At the same time, the ion implantation concentrations of the first region 401 and the second region 402 are normal, avoiding electrical changes to other devices.

[0036] In this embodiment, the ion implantation concentration of the fourth region 441 gradually decreases in the direction away from the second region 402. In other embodiments, the ion implantation concentration of the fourth region 441 may also be a uniform concentration, and less than the ion implantation concentration of the second region 402.

[0037] In this embodiment, the first conductivity type is N-type and the second conductivity type is P-type. In other embodiments, the first conductivity type may also be P-type and the second conductivity type may be N-type.

[0038] Specifically, after the P-well and N-well regions combine, the N-well region has a majority of free electrons and almost zero holes (minority carriers), while the P-well region has a majority of holes and a minority of free electrons. This creates a concentration difference between electrons and holes at their interface. Due to this concentration difference, some electrons diffuse from the N-well region to the P-well region, and some holes diffuse from the P-well region to the N-well region. This diffusion results in one side of the P-well region losing holes, leaving negatively charged impurity ions, and the other side of the N-well region losing electrons, leaving positively charged impurity ions. Ions in an open-circuit semiconductor cannot move freely and therefore do not participate in conductivity. These immobile charged particles form a space charge region near the interface between the P-well and N-well regions. The thickness of this space charge region depends on the dopant concentration. After the space charge region forms, the interaction between the positive and negative charges creates an internal electric field within it, directed from the positively charged N-well region towards the negatively charged P-well region. Clearly, the direction of this internal electric field is opposite to the direction of carrier diffusion, thus hindering diffusion. On the other hand, this internal electric field causes minority carrier holes in the N-well region to drift towards the P-well region, and minority carrier electrons in the P-well region to drift towards the N-well region; the direction of this drift is exactly opposite to the direction of diffusion. Holes drifting from the N-well region to the P-well region replenish the holes lost in the P-well region at the original contact surface, and electrons drifting from the P-well region to the N-well region replenish the electrons lost in the N-well region at the original contact surface. This reduces the space charge and weakens the internal electric field. Therefore, the result of the drift motion is a narrowing of the space charge region and an enhancement of diffusion. Finally, the diffusion of majority carriers and the drift of minority carriers reach a dynamic equilibrium. A thin layer of ions remains on both sides of the contact surface between the P-well and N-well regions; this space charge region formed by the ion layer is called the PN junction. The direction of the internal electric field of the PN junction is from the N-well region to the P-well region. When a forward voltage is applied, a PN junction exhibits low resistance and a large forward diffusion current; when a reverse voltage is applied, a PN junction exhibits high resistance and a very small reverse drift current, meaning that a PN junction has unidirectional conductivity.

[0039] In some embodiments, the method further includes: heavily doping a portion of the first well region 43 with ions of a first conductivity type from the surface of the first well region 43 to form a first heavily doped region 432 for use as a first lead-out electrode; and heavily doping a portion of the second well region 44 with ions of a second conductivity type from the surface of the second well region 44 to form a second heavily doped region 442 for use as a second lead-out electrode. Specifically, the first heavily doped region 432 is located in the first region 401 after ion implantation, and the surface of the first heavily doped region 431 is substantially flush with the surface of the isolation structure 49. The doping type of the first heavily doped region 432 is the same as the doping type (conductivity type of the implanted ions) of the first region 401, and the doping concentration of the first heavily doped region 432 is greater than the doping concentration of the first region 401, so as to serve as the lead-out electrode of the first well region 43. The second heavily doped region 442 is located in the second region 402, and its surface is substantially flush with the surface of the isolation structure 49. The doping type of the second heavily doped region 442 is the same as that of the second region 402 (conductivity type of implanted ions), and its doping concentration is greater than that of the second region 402, so as to serve as the lead-out electrode of the second well region 44. The parameters of the heavy doping can be adjusted according to the lead-out electrode parameters and process conditions, and are not specifically limited here.

[0040] Based on the same inventive concept, one embodiment of this application also provides a semiconductor structure with a PN junction, wherein the ion implantation concentration of the PN junction is low, which can effectively improve the reverse breakdown voltage of the PN junction without increasing the area occupied by the PN junction; at the same time, the ion implantation concentration in other regions of the well region is normal, avoiding electrical changes to other devices.

[0041] Please see Figure 10 This is a cross-sectional schematic diagram of a semiconductor structure with a PN junction provided in an embodiment of this application. The semiconductor structure with a PN junction described in this embodiment includes: a semiconductor substrate 40, a first well region 43 having a first conductivity type, a second well region 44 having a second conductivity type, and a PN junction 45.

[0042] Specifically, the semiconductor substrate has a first region 401 and a second region 402 separated by multiple isolation structures 49. The first well region 43 includes the first region 401 after ion implantation and a third region 431. The third region 431 is located on the side of the isolation structure 49 away from the surface of the semiconductor substrate 40 and is adjacent to the first region 401. The ion implantation concentration of the third region 431 is lower than that of the first region 401. The second well region 44 includes the second region 402 after ion implantation and a fourth region 441. The fourth region 441 is located on the side of the isolation structure 49 away from the surface of the semiconductor substrate 40 and is adjacent to the second region 402. The ion implantation concentration of the fourth region 441 is lower than that of the second region 402. The PN junction 45 is formed on both sides of the contact surface 450 where the fourth region 441 contacts the third region 431. The first conductivity type and the second conductivity type are opposite. See details. Figures 4 to 10 The method for fabricating the semiconductor structure with a PN junction shown is described below and will not be repeated here.

[0043] In this embodiment, the ion implantation concentration in the third region 431 gradually decreases in the direction away from the first region 401. In some embodiments, the ion implantation concentration in the fourth region 441 gradually decreases in the direction away from the second region 402.

[0044] In this embodiment, the semiconductor structure with a PN junction further includes a first heavily doped region 432 having a first conductivity type and a second heavily doped region 442 having a second conductivity type. The first heavily doped region 432 is located in the first region 401 after ion implantation, and the surface of the first heavily doped region 431 is substantially flush with the surface of the isolation structure 49. The doping type of the first heavily doped region 432 is the same as the doping type (conductivity type of implanted ions) of the first region 401, and the doping concentration of the first heavily doped region 432 is greater than that of the first region 401, serving as the first lead-out electrode of the first well region 43. The second heavily doped region 442 is located in the second region 402, and the surface of the second heavily doped region 442 is substantially flush with the surface of the isolation structure 49. The doping type of the second heavily doped region 442 is the same as the doping type (conductivity type of implanted ions) of the second region 402, and the doping concentration of the second heavily doped region 442 is greater than that of the second region 402, serving as the second lead-out electrode of the second well region 44. The parameters for heavy doping can be adjusted according to the lead-in electrode parameters and process conditions, and no specific limitations are made here.

[0045] In this embodiment, the first conductivity type is N-type and the second conductivity type is P-type. In other embodiments, the first conductivity type may also be P-type and the second conductivity type may be N-type.

[0046] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art. Generally, terms can be understood at least partially from their usage in the context. For example, the term "one or more," as used herein, depends at least partially on the context and can be used to describe any feature, structure, or characteristic in a singular sense, or in a plural sense, to describe a combination of features, structures, or characteristics. Similarly, terms such as "a," "an," or "the" can also be understood, at least partially on the context, to express either a singular or plural usage. Additionally, the term "based on" can be understood not necessarily to express an exclusive set of factors, but rather, alternatively, also at least partially on the context, to allow for the presence of other factors that are not necessarily explicitly described. It should also be noted in this specification that “connection / coupling” refers not only to the direct coupling of one component to another, but also to the indirect coupling of one component to another through an intermediate component.

[0047] It should be noted that the terms "comprising" and "having," and their variations, used in this application are intended to cover non-exclusive inclusion. The terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless explicitly indicated by the context. It should be understood that such data can be used interchangeably where appropriate. Furthermore, the embodiments and features described in these embodiments can be combined with each other unless otherwise specified. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this application. In the various embodiments described above, each embodiment focuses on its differences from other embodiments; similar or identical parts between embodiments can be referred to mutually.

[0048] The above description is only a preferred embodiment of this application. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A method for fabricating a semiconductor structure with a PN junction, characterized in that, Includes the following steps: A semiconductor substrate is provided, wherein the semiconductor substrate has a first region and a second region separated by a plurality of isolation structures, the surfaces of all said isolation structures being substantially flush with the surface of the semiconductor substrate; A first photoresist layer is formed on the surface of the semiconductor substrate. The first photoresist layer has a first opening that exposes the first region. The first photoresist layer has a first auxiliary photoresist layer located at the edge of the first opening and a first main photoresist layer adjacent to the first auxiliary photoresist layer. The thickness of the first auxiliary photoresist layer is less than the thickness of the first main photoresist layer. Using the first photoresist layer as a mask, the semiconductor substrate is subjected to ion implantation of a first conductivity type to form a first well region and the first photoresist layer is removed. The first well region includes the first region after ion implantation and a third region. The third region is located on the side of the isolation structure away from the semiconductor substrate and is adjacent to the first region. The ion implantation concentration of the third region is less than the ion implantation concentration of the first region. A second photoresist layer is formed on the surface of the semiconductor substrate. The second photoresist layer has a second opening that exposes the second region. The second photoresist layer has a second auxiliary photoresist layer located at the edge of the second opening and a second main photoresist layer adjacent to the second auxiliary photoresist layer. The thickness of the second auxiliary photoresist layer is less than the thickness of the second main photoresist layer. Using the second photoresist layer as a mask, the semiconductor substrate is subjected to ion implantation of a second conductivity type to form a second well region, and the second photoresist layer is removed. The second well region includes a second region after ion implantation and a fourth region. The fourth region is located on the side of the isolation structure away from the semiconductor substrate and is adjacent to the second region. The ion implantation concentration of the fourth region is less than that of the second region. The fourth region is in contact with the third region, thereby forming a PN junction on both sides of the contact surface. The first conductivity type and the second conductivity type are opposite.

2. The method according to claim 1, characterized in that, The step of forming the first photoresist layer on the semiconductor substrate further includes: A first photoresist layer is formed on the semiconductor substrate; The pattern of the first opening is formed on the first photoresist material layer by photolithography. The first photoresist material layer is developed to form the first photoresist layer.

3. The method according to claim 1, characterized in that, The bottom of the first opening is the semiconductor substrate, and the two opposite sides of the first opening are the first photoresist layer, which extends away from the semiconductor substrate at an acute angle to the surface of the semiconductor substrate. The shape of the second opening is substantially the same as that of the first opening.

4. The method according to claim 1, characterized in that, In a direction perpendicular to the surface of the semiconductor substrate, the cross-sections of both the first opening and the second opening are inverted trapezoidal.

5. The method according to claim 1, characterized in that, The thickness of the first auxiliary photoresist layer gradually decreases in the direction away from the first main photoresist layer, thereby the ion implantation concentration of the third region gradually decreases in the direction away from the first region; The thickness of the second auxiliary photoresist layer gradually decreases in the direction away from the second main photoresist layer, thereby the ion implantation concentration of the fourth region gradually decreases in the direction away from the second region.

6. The method according to claim 1, characterized in that, The method further includes: A portion of the first well region is heavily doped with ions of a first conductivity type from the surface of the first well region to form a first heavily doped region for use as a first lead-out electrode; A portion of the second well region is heavily doped with ions of a second conductivity type from the surface of the second well region to form a second heavily doped region for use as a second lead-out electrode.

7. The method according to claim 1, characterized in that, The first conductivity type is N-type, and the second conductivity type is P-type.

8. The method according to claim 1, characterized in that, The semiconductor substrate is made of any one of silicon, silicon carbide, or silicon nitride.

9. A semiconductor structure having a PN junction, characterized in that, include: A semiconductor substrate having a first region and a second region separated by a plurality of isolation structures; A first well region having a first conductivity type, the first well region comprising a first region after ion implantation and a third region, the third region being located on the side of the isolation structure away from the semiconductor substrate and adjacent to the first region, the ion implantation concentration of the third region being less than the ion implantation concentration of the first region; A second well region having a second conductivity type, the second well region comprising a second region after ion implantation and a fourth region, the fourth region being located on the side of the isolation structure away from the semiconductor substrate and adjacent to the second region, the ion implantation concentration of the fourth region being less than the ion implantation concentration of the second region, and the first conductivity type and the second conductivity type being opposite; A PN junction is formed on both sides of the contact surface where the fourth region and the third region meet.

10. The semiconductor structure with a PN junction according to claim 9, characterized in that, The ion implantation concentration in the third region gradually decreases in the direction away from the first region; The ion implantation concentration in the fourth region gradually decreases in the direction away from the second region.

11. The semiconductor structure with a PN junction according to claim 9, characterized in that, Also includes: A first heavily doped region having a first conductivity type, the first heavily doped region being located in the first region, and the surface of the first heavily doped region being substantially flush with the surface of the isolation structure, for use as a first lead-out electrode; A second heavily doped region having a second conductivity type is located in the second region, and the surface of the second heavily doped region is substantially flush with the surface of the isolation structure, so as to serve as a second lead electrode.

12. The semiconductor structure with a PN junction according to claim 9, characterized in that, The first conductivity type is N-type, and the second conductivity type is P-type.

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