A method for fabricating a gallium nitride current aperture vertical electron device

Abstract

The present application relates to the technical field of semiconductor devices, in particular to a preparation method of a gallium nitride current aperture vertical electronic device. A defect layer is formed in a gallium nitride single crystal substrate, and a current blocking structure is prepared in each of two preset regions of the gallium nitride single crystal substrate with a preset interval distance. The material of the current blocking structure includes a dielectric material and a super-wide band gap material. The top of the gallium nitride single crystal substrate is bonded with a supporting substrate, and then annealing stripping and polishing are sequentially performed. Then, a gallium nitride channel layer and an aluminum gallium nitride barrier layer are epitaxially formed in sequence, and an electrode layer is prepared. The device prepared by the above method has the characteristics of being able to withstand a larger breakdown voltage and being less likely to occur through leakage.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a method for fabricating a gallium nitride current aperture vertical electronic device. Background Technology

[0002] A GaN current aperture vertical electrotransistor (GaN CAVET), also known as a vertical gallium nitride field-effect transistor (MOSFET), combines the advantages of the high concentration and high mobility of the two-dimensional electron gas in an AlGaN / GaN heterojunction with the high breakdown field strength and high breakdown voltage of vertical GaN devices. When the device is turned on, electrons travel from the source electrode horizontally along the two-dimensional electron gas of the AlGaN / GaN heterojunction to the gate, and vertically to the drain. (See also...) Figure 1 In GaN, p-GaN acts as a current blocking layer, restricting the current flow path. When the device is turned off, the electric field breaks down in the vertical direction, thus the device benefits from a high breakdown voltage in the vertical direction and can significantly reduce the device area and size compared to lateral devices. GaN CAVET devices have many excellent characteristics such as low on-resistance, high breakdown voltage, and high output power.

[0003] In related technologies, the p-GaN current blocking layer of GaN CAVET devices is usually formed by ion implantation, such as by Mg ion implantation. However, the current blocking layer prepared by this method has a low doping concentration and poor performance, which can easily cause serious problems such as device leakage and breakdown. Moreover, the p-GaN current blocking layer itself cannot withstand a large breakdown voltage and is prone to punch-through leakage. Summary of the Invention

[0004] The present invention aims to solve the technical problem of easy leakage and breakdown in GaN CAVET devices obtained by forming a p-GaN current blocking layer by Mg ion implantation in the prior art.

[0005] To address the aforementioned technical problems, this application discloses a method for fabricating a gallium nitride current aperture vertical electronic device, comprising:

[0006] Provide a gallium nitride single crystal substrate;

[0007] A defect layer is formed in a gallium nitride (GaN) single-crystal substrate, and a current blocking structure is fabricated in two predetermined regions of the GaN single-crystal substrate with a predetermined spacing distance. A predetermined region is provided at each of the two opposite ends of the GaN single-crystal substrate. The bottom of the two predetermined regions is at a first predetermined distance from the bottom of the GaN single-crystal substrate. The tops of the two current blocking structures are located on the same plane as the top of the GaN single-crystal substrate. The materials of the current blocking structures include dielectric materials and ultra-wide bandgap materials.

[0008] Provide a supporting substrate;

[0009] The top of the gallium nitride single crystal substrate is bonded to the supporting substrate to obtain the first structure;

[0010] The first structure is subjected to annealing, stripping and polishing processes in sequence to obtain the second structure; the second structure includes a supporting substrate and a first gallium nitride single crystal layer.

[0011] A gallium nitride channel layer and an aluminum gallium nitride barrier layer are sequentially epitaxially grown on the first gallium nitride single crystal layer of the second structure to obtain the third structure.

[0012] A source electrode and a gate electrode are fabricated on the top surface of the third structure, and a drain electrode is fabricated on the bottom surface of the third structure; the top surface of the third structure is close to the aluminum gallium nitride barrier layer.

[0013] In one possible embodiment, when the material of the current blocking structure is a dielectric material, a defect layer is formed in a gallium nitride single crystal substrate, and a current blocking structure is respectively fabricated in two predetermined regions with a predetermined spacing distance on the gallium nitride single crystal substrate, including:

[0014] Ion implantation is performed on a gallium nitride single crystal substrate by means of implantation to form a defect layer in the gallium nitride single crystal substrate;

[0015] The gallium nitride single crystal portion of two predetermined regions of a gallium nitride single crystal substrate was removed using photolithography and etching techniques to obtain the etched structure.

[0016] A dielectric material is grown on the top surface of the etched structure;

[0017] Remove the dielectric material on the injection surface; the top surface of the etched structure is the top surface of the gallium nitride single crystal substrate;

[0018] The top surface of the etched structure is polished to obtain a gallium nitride single crystal substrate with two current blocking structures.

[0019] In one possible embodiment, when the material of the current blocking structure is gallium oxide, an ultrawide bandgap material, a defect layer is formed in a gallium nitride single-crystal substrate, and a current blocking structure is fabricated in two predetermined regions of the gallium nitride single-crystal substrate with a predetermined spacing, including:

[0020] Oxygen ions are implanted from the surface of two preset regions corresponding to the top surface of the gallium nitride single crystal substrate to the two preset regions, so as to form an oxygen ion implantation region in each of the two preset regions with a preset interval distance on the gallium nitride single crystal substrate.

[0021] Annealing was performed on two oxygen ion implantation regions of a gallium nitride single crystal substrate to obtain a gallium nitride single crystal substrate with two current blocking structures.

[0022] Ion implantation is performed on the top surface of the gallium nitride single crystal substrate to form a defect layer within the gallium nitride single crystal substrate.

[0023] In one possible embodiment, the dielectric material includes silicon dioxide, silicon nitride, and aluminum oxide;

[0024] Ultra-wide bandgap materials include gallium oxide.

[0025] In one possible embodiment, the conditions for annealing the oxygen ion implantation region include:

[0026] The annealing atmosphere is a vacuum or nitrogen atmosphere;

[0027] Annealing temperatures range from 600℃ to 1100℃;

[0028] Annealing time ranges from 30 seconds to 10 minutes.

[0029] In one possible embodiment, the conditions for annealing and stripping the first structure include:

[0030] The annealing atmosphere is a vacuum, nitrogen, or argon.

[0031] Annealing temperatures range from 300℃ to 900℃;

[0032] Annealing time ranges from 1 minute to 24 hours.

[0033] In one possible embodiment, the first structure is sequentially subjected to annealing, peeling, and polishing to obtain the second structure, comprising:

[0034] An annealing process is used to peel off the first structure along the defect layer to obtain an initial second structure; the initial second structure includes a supporting substrate and a first gallium nitride single crystal layer.

[0035] The residual defect layer on the initial second structure is removed by polishing technology to obtain the second structure.

[0036] In one possible embodiment, a gallium nitride channel layer and an aluminum gallium nitride barrier layer are sequentially epitaxially grown on the first gallium nitride single crystal layer of the second structure to obtain a third structure, comprising:

[0037] The third structure is obtained by sequentially epitaxially forming a gallium nitride channel layer, an aluminum nitride insertion layer, an aluminum gallium nitride barrier layer, and a gallium nitride cap layer on the first gallium nitride single crystal layer of the second structure.

[0038] In one possible embodiment, the supporting substrate comprises a stack of highly doped and low-doped substrates;

[0039] The top of the gallium nitride single crystal substrate is bonded to a lightly doped substrate.

[0040] In another aspect, this application also discloses a gallium nitride current aperture vertical electronic device, which is prepared using the method described above.

[0041] By adopting the above technical solution, the gallium nitride current aperture vertical electronic device provided in this application has the following beneficial effects:

[0042] A current-blocking structure is fabricated by forming a defect layer in a gallium nitride (GaN) single-crystal substrate and fabricating two predetermined regions with a predetermined spacing on the GaN single-crystal substrate. Two predetermined regions are located at opposite ends of the GaN single-crystal substrate. The bottoms of the two predetermined regions are at a first predetermined distance from the bottom of the GaN single-crystal substrate. The tops of the two current-blocking structures are located on the same plane as the top of the GaN single-crystal substrate. The materials of the current-blocking structures include dielectric materials and ultra-wide bandgap materials. A support substrate is provided. The top of the GaN single-crystal substrate is bonded to the support substrate to obtain a first structure. The first structure is sequentially annealed, peeled off, and polished to obtain a second structure. A GaN channel layer and an aluminum gallium nitride (AlGaN) barrier layer are sequentially epitaxially grown on the first GaN single-crystal layer of the second structure to obtain a third structure. A source electrode and a gate electrode are fabricated on the top surface of the third structure, and a drain electrode is fabricated on the bottom surface of the third structure. The top surface of the third structure is opposite to the bottom surface of the second structure. Thus, the device obtained by the above fabrication method has the advantages of being able to withstand a large breakdown voltage and being less prone to punch-through leakage. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is a schematic diagram of the structure of a prior art gallium nitride current aperture vertical electronic device provided in an embodiment of this application;

[0045] Figure 2 This is a schematic diagram of a process for fabricating a gallium nitride current aperture vertical electronic device provided in an embodiment of this application;

[0046] Figure 3 This is a schematic diagram illustrating the process of fabricating a gallium nitride current aperture vertical electronic device according to an embodiment of this application;

[0047] Figure 4 This is a schematic diagram of the process for preparing a current blocking structure provided in an embodiment of this application.

[0048] The following is supplementary explanation of the attached figures:

[0049] 1-GaN single crystal substrate; 101-Implantation surface; 102-Oxygen ion implantation region; 103-First GaN single crystal layer; 104-Second GaN single crystal layer; 2-Preset region; 3-Current barrier structure; 4-Defect layer; 5-Supporting substrate; 501-Highly doped substrate; 502-Lowly doped substrate; 6-First structure; 7-Second structure; 8-Initial second structure; 9-GaN channel layer; 10-Aluminum nitride insertion layer; 11-Aluminum gallium nitride barrier layer; 12-GaN cap layer; 13-Third structure. Detailed Implementation

[0050] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0051] The term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of this application. In the description of this application, it should be understood that the terms "upper," "lower," "top," "bottom," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein.

[0052] For the purposes of the detailed description below, it should be understood that the invention may take various alternative variations and sequences of steps unless expressly stated otherwise. Furthermore, except in any operational instance, or otherwise indicated, all figures representing the amounts of ingredients used, for example, in the specification and claims, should be understood to be modified in all cases by the term “about.” Therefore, unless indicated to the contrary, the numerical parameters set forth in the following specification and appended claims are approximations varying with the desired performance to be obtained according to the invention. It is not at all an attempt to limit the application of the doctrine of equivalents to the scope of the claims; each numerical parameter should be interpreted at least according to the number of significant figures reported and by applying ordinary rounding techniques.

[0053] Although the numerical ranges and parameters illustrating the broad scope of the invention are approximate, the values ​​listed in the specific examples are reported as precisely as possible. However, any numerical value inherently contains some error that is necessarily caused by the standard deviation found in their respective test measurements.

[0054] When a numerical range is disclosed herein, the range is considered continuous and includes the minimum and maximum values ​​of the range, as well as every value between the minimum and maximum values. Furthermore, when the range refers to an integer, it includes every integer between the minimum and maximum values ​​of the range. Additionally, when multiple ranges are provided to describe a feature or characteristic, the ranges may be combined. In other words, unless otherwise specified, all ranges disclosed herein should be understood to include any and all subranges to which they are included. For example, a specified range from “1 to 10” should be considered to include any and all subranges between the minimum value 1 and the maximum value 10. Exemplary subranges of the range 1 to 10 include, but are not limited to, 1 to 6.1, 3.5 to 7.8, 5.5 to 10, etc.

[0055] Please see Figure 1 The diagram shows a schematic representation of a prior art gallium nitride current aperture vertical electronic device according to an embodiment of this application. This GaN CAVET device includes a stacked drain electrode, an n-GaN substrate (n-type doped gallium nitride), and an n-type doped gallium nitride core. - -GaN (i.e., n-type lightly doped gallium nitride), p-GaN current blocking layer (p-type doped gallium nitride), GaN, AlGaN, and source / gate electrodes; wherein, GaN and AlGaN form an AlGaN / GaN heterojunction, and electrons are drawn from the source electrode (e.g., ... Figure 1 The S-structure in the AlGaN / GaN heterojunction reaches the gate electrode (e.g., along the horizontal direction of the two-dimensional electron gas) in the AlGaN / GaN heterojunction. Figure 1 In the G structure (as described in the text), p-GaN acts as a current-blocking layer, restricting the current flow path and enabling electrons to reach the drain (e.g., in the vertical direction). Figure 1In GaN CAVET devices, the electric field breaks down vertically when the device is turned off, thus benefiting from a high vertical breakdown voltage and allowing for a significant reduction in device area and size compared to lateral devices. Therefore, GaN CAVET devices possess numerous superior characteristics such as low on-resistance, high breakdown voltage, and high output power. However, in existing technologies, the p-GaN current blocking layer of GaN CAVET devices is mainly prepared using ion implantation or regeneration methods, such as p-GaN current blocking layers formed by Mg ion implantation. However, this method results in low doping concentrations and poor performance in the current blocking layer, easily leading to serious problems such as device leakage and breakdown. Another method is to grow p-GaN followed by GaN vias (e.g.,...). Figure 1 As shown, this could refer to the region between two p-GaN cells (AlGaN / GaN heterojunction). Because p-GaN is grown first, followed by the GaN via growth step, the C-axis of the grown GaN crystal is deviated, resulting in poor crystal quality of the AlGaN / GaN heterojunction and GaN via, forming leakage channels. Furthermore, the p-GaN current-blocking layer itself cannot withstand large drain voltages, easily leading to punch-through leakage. Therefore, this application discloses a method for fabricating a gallium nitride current-aperture vertical electronic device. Please refer to [link to relevant documentation]. Figure 2 The preparation method includes the following steps:

[0056] S201: Provides a gallium nitride single crystal substrate 1 (e.g. Figure 3 The structure shown in Figure (a)).

[0057] In this embodiment, in order to improve the fabrication efficiency, the array-arranged devices can be fabricated on a gallium nitride single crystal wafer, where the gallium nitride single crystal substrate 1 can refer to a gallium nitride single crystal wafer.

[0058] S202: A defect layer 4 is formed in a gallium nitride single crystal substrate 1, and a current blocking structure 3 is respectively fabricated in two preset regions 2 with a preset spacing distance in the gallium nitride single crystal substrate 1; a preset region 2 is respectively provided at two opposite ends of the gallium nitride single crystal substrate 1; the bottom of the two preset regions 2 is at a first preset distance from the bottom of the gallium nitride single crystal substrate 1; the top of the two current blocking structures 3 is located on the same plane as the top of the gallium nitride single crystal substrate 1; the material of the current blocking structure 3 includes dielectric material and ultra-wide bandgap material.

[0059] In one possible embodiment, the dielectric material in step S202 includes silicon dioxide, silicon nitride, and aluminum oxide; the ultrawide bandgap material includes gallium oxide. Depending on the material type of the current blocking structure 3, the methods for fabricating the current blocking structure 3 can be divided into two types: one is using a dielectric growth method (see [link to documentation]). Figure 3 Another method uses ion implantation followed by annealing activation (see [link]). Figure 4 The following will describe the two methods for preparing the current blocking structure 3:

[0060] In one possible embodiment, when the material of the current blocking structure 3 is a dielectric material, the material of the current blocking structure 3 can specifically be silicon dioxide, silicon nitride, or aluminum oxide, etc. A specific implementation of step S202 may include: firstly, performing ion implantation from the implantation surface 101 into the gallium nitride single crystal substrate 1 to form a defect layer 4 (e.g., ...) within the gallium nitride single crystal substrate 1. Figure 3 The structure shown in Figure (b) divides the gallium nitride single crystal substrate 1 into a first gallium nitride single crystal layer 103 and a second gallium nitride single crystal layer 104. The gallium nitride single crystal portions of the two predetermined regions 2 of the gallium nitride single crystal substrate 1 are removed using photolithography and etching techniques to obtain the etched structure (as shown in Figure (b)). Figure 3 The structure shown in Figure (c) is obtained by growing a dielectric material on the top surface of the etched structure. Figure 3 The structure shown in Figure (d) can be obtained by removing the dielectric material on the injection surface 101. Figure 3 The structure shown in Figure (e) can have its top surface etched as follows: Figure 3 The top surface of the gallium nitride single crystal substrate 1 shown in Figure (b) is polished after etching to make the current blocking structure 3 and the injection surface 101 on the same plane, resulting in a gallium nitride single crystal substrate 1 with two current blocking structures 3. Optionally, two preset regions 2 are located in the first gallium nitride single crystal layer 103, and a preset region 2 is provided at each of the two opposite ends of the first gallium nitride single crystal layer 103. The gallium nitride single crystal material in the preset regions 2 is etched away using photolithography and etching techniques to make the first gallium nitride single crystal layer 103 a convex structure. Optionally, a patterned blocking layer can be formed on the gallium nitride single crystal substrate 1 using photolithography. Specifically, the exposed part can be etched away using an ion beam etching technique, and then the blocking layer can be removed to complete the etching, which has the advantages of high etching controllability and high etching pattern resolution. Optionally, the polishing technique can be chemical mechanical polishing; the above-mentioned method for removing the dielectric material on the injection surface 101 includes ion beam etching or chemical wet etching. Alternatively, the methods for growing the growing medium material include, but are not limited to, plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, and atomic layer deposition.

[0061] It should be noted that the above mainly describes the method of first preparing the defect layer 4 and then preparing the current blocking structure 3. In practice, depending on the needs, it is also possible to first prepare the current blocking structure 3 and then perform ion implantation to form the defect layer 4. However, in this embodiment, since the surface layer of the entire substrate contains two different materials, namely gallium nitride and other dielectric materials (such as silicon dioxide), ion implantation can be performed separately. Thus, the ion implantation conditions for gallium nitride implanted into the substrate and the ion implantation conditions for silicon dioxide implanted into the substrate are different, so as to form a uniform defect layer 4.

[0062] In another possible embodiment, see Figure 4 When the material of the current blocking structure 3 is gallium oxide, an ultra-wide bandgap material, the specific implementation of step S202 may include: using a gallium nitride single crystal substrate 1 (such as...) Figure 4 In the structure shown in Figure (a), oxygen ions are implanted into the surfaces of the two preset regions 2 on the top surface of the structure, so that an oxygen ion implantation region 102 is formed in each of the two preset regions 2 with a preset spacing distance on the gallium nitride single crystal substrate 1. Figure 4 The structure shown in Figure (b) is used to anneal and activate the two oxygen ion implantation regions 102 of the gallium nitride single crystal substrate 1, thereby obtaining the gallium nitride single crystal substrate 1 with two current blocking structures 3 (as shown in Figure (b)). Figure 4 The structure shown in Figure (c) is as follows; ion implantation is performed from the top surface of the gallium nitride single crystal substrate 1 to form a defect layer 4 (such as...) within the gallium nitride single crystal substrate 1. Figure 4 (The structure shown in Figure (d)). Optionally, during oxygen ion implantation, it is necessary to first determine two preset regions 2 for implantation, so that oxygen ions can be implanted from the corresponding surface regions on the top surface of the gallium nitride single crystal substrate 1 to form oxygen ion implantation regions 102 in the two preset regions 2. The depth of oxygen ion implantation can be set as needed.

[0063] Optionally, oxygen ion implantation conditions include: oxygen ion implantation energy of 1 keV to 1000 keV; and oxygen ion implantation dose of 1 × 10⁻⁶. 15 cm -2 ~1×10 18 cm -2 Optionally, a multiple injection scheme can be selected, such as injecting 1×10 at 5keV. 15 cm -2 Then, inject 1×10 at 20keV. 16 cm -2 To improve the injection effect.

[0064] In one possible embodiment, the annealing conditions for the oxygen ion implantation region 102 include: an annealing atmosphere of vacuum or nitrogen; an annealing temperature of 600°C to 1100°C, such as 600°C, 700°C, 800°C, 900°C, and 1100°C; and an annealing time of 30 seconds to 10 minutes, such as 30 seconds, 1 minute, 3 minutes, 5 minutes, 7 minutes, and 10 minutes.

[0065] It is understood that the ion implantation methods for forming the defect layer 4 include hydrogen ion implantation, helium ion implantation, and hydrogen-helium ion co-implantation. When hydrogen ion implantation is used for the gallium nitride single crystal substrate 1, the implantation energy ranges from 10 keV to 5 MeV, and the implantation dose is 1 × 10⁻⁶. 17 cm -2 ~1×10 18 cm -2 The position of the defect layer 4 can be adjusted as needed. Whether using the aforementioned dielectric growth method or the oxygen ion implantation + annealing activation method, compared with the existing technology of using Mg ion implantation to form a p-GaN current blocking layer and the p-GaN growth method, both have the advantage of simple fabrication processes. Furthermore, the fabricated current blocking structure has a better current constraint effect and is more resistant to breakdown voltage (the breakdown voltage of the current blocking structure in this application is approximately 2 to 3 times that of the existing P-GaN breakdown voltage), avoiding problems such as leakage and breakdown caused by traditional methods.

[0066] S203: Provides a support substrate 5.

[0067] In one possible embodiment, the supporting substrate 5 comprises a stacked highly doped substrate 501 and a low-doped substrate 502 (e.g., Figure 3 The structure shown in Figure (g) shows that the top of the gallium nitride single crystal substrate 1 is bonded to the low-doped substrate 502.

[0068] The supporting substrate 5 can be a wide-bandgap / ultra-wide-bandgap semiconductor material formed by one or more of silicon carbide, gallium oxide, diamond, and aluminum nitride, which will significantly improve the device breakdown voltage. Silicon carbide, diamond, and aluminum nitride also have extremely high thermal conductivity, which can improve the heat dissipation capability and performance of GaN CAVET devices. Optionally, in the prior art, the thickness is usually below 500 micrometers, while in this application, the thickness of the highly doped substrate 501 can be set to be greater than 500 micrometers, thereby further improving the device breakdown voltage.

[0069] S204: The top of the gallium nitride single crystal substrate 1 is bonded to the supporting substrate 5 to obtain the first structure 6 (e.g., Figure 3 The structure shown in Figure (h)).

[0070] The bonding method can be either hydrophilic direct bonding or surface-activated bonding.

[0071] Optionally, hydrophilic direct bonding may specifically include the following steps:

[0072] 1) Activate the two wafers to be bonded (e.g., gallium nitride single crystal substrate 1 and supporting substrate 5), specifically by using one or a combination of nitrogen plasma, argon plasma, and oxygen plasma. The purpose is to remove contaminants and the native oxide layer from the wafer surface and open the dangling bonds on the wafer surface.

[0073] 2) Clean the two activated wafers to be bonded so that -OH is attached to the wafer surface.

[0074] 3) Pressure bonding of two wafers.

[0075] Optionally, the wafer to be bonded can be cleaned before step 1) above to remove contaminants such as dirt and particles from the wafer surface.

[0076] Surface activation bonding may specifically include the following steps:

[0077] Two wafers to be bonded are placed in an ultra-high vacuum environment, and their surfaces are activated using argon plasma, followed by direct bonding under pressure. Alternatively, the two wafers are placed in an ultra-high vacuum environment, and their surfaces are activated using argon plasma. Then, a nano-Si dielectric layer is sputtered onto the wafer surface, the nano-Si layer is activated by argon plasma, and direct bonding is performed under pressure.

[0078] S205: The first structure 6 is subjected to annealing, peeling, and polishing processes in sequence to obtain the second structure 7 (e.g., Figure 3 The structure shown in Figure (j) is a second structure 7, which includes a supporting substrate 5, two current blocking structures 3 and a first gallium nitride single crystal layer 103.

[0079] In one possible embodiment, step S205 involves sequentially annealing and polishing the first structure 6 to obtain the second structure 7, including: using an annealing process to peel the first structure 6 along the defect layer 4 to obtain the initial second structure 8 (see [link to relevant documentation]). Figure 3 Figure (i) shows the initial second structure 8, which includes a supporting substrate 5, two current blocking structures 3, a first gallium nitride single crystal layer 103, and a residual defect layer 4. The residual defect layer 4 on the initial second structure 8 is removed by polishing to obtain the second structure 7. Optionally, the polishing technique for removing the defect layer 4 can be one or a combination of chemical mechanical polishing, ion beam etching, mechanical polishing, and chemical wet etching.

[0080] In one possible embodiment, the conditions for annealing and stripping the first structure 6 include: an annealing atmosphere of vacuum, nitrogen, or argon; an annealing temperature ranging from 300°C to 900°C, such as 300°C, 500°C, 700°C, 800°C, and 900°C; and an annealing time ranging from 1 minute to 24 hours, such as 1 minute, 10 minutes, 30 minutes, 1 hour, 3 hours, 5 hours, 12 hours, and 24 hours.

[0081] The second structure 7 prepared based on the above steps has excellent single crystal quality because the gallium nitride single crystal layer is directly peeled off from the gallium nitride single crystal substrate 1. This avoids the leakage problem caused by the low crystal quality of the regrowth method and further improves the leakage protection performance. As a result, the performance and reliability of the device can be greatly improved. The peeled gallium nitride single crystal substrate 1 can be recycled after surface treatment, which can also greatly reduce the material cost of expensive gallium nitride single crystals.

[0082] S206: On the first gallium nitride single crystal layer of the second structure 7, a gallium nitride channel layer 9 and an aluminum gallium nitride barrier layer 11 are sequentially epitaxially grown to obtain the third structure 13 (e.g., ...). Figure 3 The structure shown in Figure (k)).

[0083] In one possible embodiment, step S206 may be implemented by sequentially epitaxially extending a gallium nitride channel layer 9, an aluminum nitride insertion layer 10, an aluminum gallium nitride barrier layer 11, and a gallium nitride cap layer 12 on the top surface of the second structure 7 to obtain the third structure 13.

[0084] The aluminum nitride (A) intercalation layer 10 increases the channel electron density and suppresses the infiltration of two-dimensional electron gas into the gallium nitride (GaN) aluminum barrier layer, thereby improving channel electron mobility. The gallium nitride (GaN) cap layer 12 effectively reduces the resistance of the ohmic contact. Under the influence of polarization, the GaN cap layer can improve 2DEG mobility at the cost of a slight decrease in carrier concentration, and also increases the Schottky contact barrier on the AlGaN / GaN heterojunction structure, thus significantly reducing the gate leakage current. It can also improve the overall surface and material properties of the AlGaN / GaN heterojunction structure, thereby enhancing device reliability.

[0085] S207: A source electrode and a gate electrode are fabricated on the top surface of the third structure 13, and a drain electrode is fabricated on the bottom surface of the third structure 13 to obtain the target device (e.g., Figure 3 The structure shown in Figure (l) is shown in the middle; the top surface of the third structure 13 is close to the aluminum gallium nitride barrier layer.

[0086] Specifically, the source electrode, drain electrode, and gate electrode can be prepared using common metal electrode fabrication processes, such as sequentially performing photolithography, metal growth, and metal lift-off processes to obtain the metal electrodes.

[0087] This application also discloses a gallium nitride current aperture vertical electronic device, which is prepared using the above-described method. The obtained gallium nitride current aperture vertical electronic device can be as follows: Figure 3 The structure shown in Figure (l) specifically comprises, from bottom to top, a drain electrode, a highly doped substrate 501, a lightly doped substrate 502, a first gallium nitride single crystal layer 103, two current blocking structures 3, a gallium nitride channel layer 9, an aluminum nitride insertion layer 10, an aluminum gallium nitride barrier layer 11, a gallium nitride cap layer 12, and a source-gate electrode located within the first gallium nitride single crystal layer 103. The upper surfaces of the two current blocking structures 3 are at a first predetermined distance from the upper surface of the gallium nitride single crystal substrate 1, and the lower surfaces of the two current blocking structures 3 are on the same plane as the lower surface of the first gallium nitride single crystal layer 103. The materials of the current blocking structures 3 include dielectric materials and ultra-wide bandgap materials. Possible structures for this gallium nitride current aperture vertical electronic device can be found in the fabrication method described above, and will not be repeated here.

[0088] The above description is only an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a gallium nitride current aperture vertical electronic device, characterized in that, include: Provide a gallium nitride single crystal substrate; A defect layer is formed in the gallium nitride single crystal substrate, and a current blocking structure is respectively fabricated in two predetermined regions of the gallium nitride single crystal substrate with a predetermined spacing; each of the predetermined regions is provided at two opposite ends of the gallium nitride single crystal substrate. The bottom of the two preset regions is at a first preset distance from the bottom of the gallium nitride single crystal substrate; The tops of the two current-blocking structures are located on the same plane as the top of the gallium nitride single-crystal substrate; The materials used in the current blocking structure include dielectric materials and ultra-wide bandgap materials; Provide a supporting substrate; The top of the gallium nitride single crystal substrate is bonded to the supporting substrate to obtain the first structure; The first structure is subjected to annealing, peeling, and polishing processes in sequence to obtain the second structure; the second structure includes the supporting substrate and the first gallium nitride single crystal layer. A gallium nitride channel layer and an aluminum gallium nitride barrier layer are sequentially epitaxially grown on the first gallium nitride single crystal layer of the second structure to obtain the third structure; A source electrode and a gate electrode are fabricated on the top surface of the third structure, and a drain electrode is fabricated on the bottom surface of the third structure; the top surface of the third structure is close to the aluminum gallium nitride barrier layer.

2. The preparation method according to claim 1, characterized in that, When the material of the current-blocking structure is a dielectric material, the steps of forming a defect layer in the gallium nitride single-crystal substrate and fabricating a current-blocking structure in two predetermined regions with a predetermined spacing distance on the gallium nitride single-crystal substrate include: Ion implantation is performed on a gallium nitride single crystal substrate via an implantation surface to form the defect layer within the gallium nitride single crystal substrate; The gallium nitride single crystal portion of the two preset regions of the gallium nitride single crystal substrate is removed using photolithography and etching techniques to obtain the etched structure; A dielectric material is grown on the top surface of the etched structure; Remove the dielectric material from the injection surface; the top surface of the etched structure is the top surface of the gallium nitride single crystal substrate; The top surface of the etched structure is polished to obtain a gallium nitride single crystal substrate with two current blocking structures.

3. The preparation method according to claim 1, characterized in that, When the material of the current blocking structure is gallium oxide, an ultra-wide bandgap material, the steps of forming a defect layer in the gallium nitride single crystal substrate and fabricating a current blocking structure in two predetermined regions with a predetermined spacing distance on the gallium nitride single crystal substrate include: Oxygen ions are implanted from the surface of the top surface of the gallium nitride single crystal substrate corresponding to the two preset regions into the two preset regions with a preset interval distance, so as to form an oxygen ion implantation region in each of the two preset regions of the gallium nitride single crystal substrate. Annealing is performed on the two oxygen ion implantation regions of the gallium nitride single crystal substrate to obtain a gallium nitride single crystal substrate with two current blocking structures. Ion implantation is performed on the top surface of the gallium nitride single crystal substrate to form a defect layer within the gallium nitride single crystal substrate.

4. The preparation method according to claim 1, characterized in that, The dielectric material includes silicon dioxide, silicon nitride, and aluminum oxide; The ultrawide bandgap material includes gallium oxide.

5. The preparation method according to claim 3, characterized in that, The conditions for annealing the oxygen ion implantation region include: The annealing atmosphere is a vacuum or nitrogen atmosphere; Annealing temperatures range from 600℃ to 1100℃; Annealing time ranges from 30 seconds to 10 minutes.

6. The preparation method according to claim 1, characterized in that, The conditions for annealing and stripping the first structure include: The annealing atmosphere is a vacuum, nitrogen, or argon. Annealing temperatures range from 300℃ to 900℃; Annealing time ranges from 1 minute to 24 hours.

7. The preparation method according to claim 1, characterized in that, The second structure is obtained by sequentially annealing, peeling, and polishing the first structure, including: An annealing process is used to peel the first structure along the defect layer to obtain an initial second structure; the initial second structure includes the supporting substrate and the first gallium nitride single crystal layer. The residual defect layer on the initial second structure is removed using polishing technology to obtain the second structure.

8. The preparation method according to claim 1, characterized in that, The third structure is obtained by sequentially epitaxially extending a gallium nitride channel layer and an aluminum gallium nitride barrier layer on the first gallium nitride single crystal layer of the second structure, including: The third structure is obtained by sequentially epitaxially forming the gallium nitride channel layer, the aluminum nitride insertion layer, the aluminum gallium nitride barrier layer, and the gallium nitride cap layer on the first gallium nitride single crystal layer of the second structure.

9. The preparation method according to claim 4, characterized in that, The supporting substrate comprises a stacked highly doped substrate and a low doped substrate; The top of the gallium nitride single crystal substrate is bonded to the low-doped substrate.

10. A gallium nitride current aperture vertical electronic device, characterized in that, It is prepared using the method described in any one of claims 1-9.

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