Wafer dicing method and application

Abstract

The application discloses a wafer dicing method and application, wherein the application provides a wafer dicing method, comprising the following steps: providing a first wafer and a second wafer, the surface of the first wafer is provided with a plurality of first areas, each of the first areas is provided with a first quantum circuit and a first interconnection element, the surface of the second wafer is provided with a plurality of second areas, each of the second areas is provided with a second quantum circuit and a second interconnection element; forming a protection structure between the first wafer and the second wafer; pressing the first wafer and the second wafer; and dicing the first wafer and the second wafer. In the application, before dicing, the protection structure is formed between the first wafer and the second wafer, so that the first quantum element, the second quantum element, the first interconnection element and the second interconnection element are protected, thereby effectively ensuring the product quality of the quantum chip.

Description

Technical Field

[0001] This application belongs to the field of quantum computing technology, specifically a wafer dicing method and its application. Background Technology

[0002] A quantum computer is a physical device that performs high-speed mathematical and logical operations, stores and processes quantum information, following the laws of quantum mechanics. The main characteristics of quantum computers include high operating speed, strong information processing capabilities, and a wide range of applications. Compared to conventional computers, the greater the amount of information processed, the more advantageous it is for quantum computers to perform calculations, and the more accurate the calculations are. As the core component of a quantum computer, the number of qubits integrated on a quantum chip is gradually increasing. To achieve large-scale expansion of qubits, stacked interconnect technology can be used to fabricate double-layer stacked quantum chips.

[0003] When using existing wafer dicing methods to process stacked quantum chips, the quantum chips are easily damaged, making it difficult to guarantee the quality of the resulting quantum chips.

[0004] It should be noted that the information disclosed in the background section of this application is intended only to enhance the understanding of the general background of this application, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this application is to provide a wafer dicing method and its application to address the shortcomings of the prior art.

[0006] One embodiment of this application provides a wafer dicing method, including the following steps:

[0007] A first wafer and a second wafer are provided. The surface of the first wafer has a plurality of first regions, each of the first regions having a first quantum circuit and a first interconnection element electrically connected to the first quantum circuit. The surface of the second wafer has a plurality of second regions, each of the second regions having a second quantum circuit and a second interconnection element electrically connected to the second quantum circuit.

[0008] A protective structure is formed between the first wafer and the second wafer, surrounding the first quantum circuit, the first interconnect element, the second quantum circuit, and the second interconnect element;

[0009] The first wafer and the second wafer are pressed together to connect and fix the first interconnect element and the second interconnect element.

[0010] The first wafer and the second wafer are diced to obtain a quantum chip.

[0011] In the wafer dicing method described above, the step of forming a protective structure surrounding the first quantum circuit, the first interconnect element, the second quantum circuit, and the second interconnect element between the first wafer and the second wafer includes:

[0012] A first protective layer is formed on the surface of the first wafer where the first interconnect element is located;

[0013] A second protective layer is formed on the surface of the second wafer where the second interconnect element is located;

[0014] The thickness of the first protective layer is the same as the height of the first interconnecting element, and the thickness of the second protective layer is the same as the height of the second interconnecting element. The first protective layer and the second protective layer together constitute the protective structure.

[0015] In the wafer dicing method described above, the step of forming the first protective layer on the surface of the first wafer where the first interconnect element is located includes:

[0016] A dielectric material is deposited on the surface of the first wafer where the first interconnect element is located to obtain the first protective layer;

[0017] Polish the first protective layer to expose the first interconnect element.

[0018] In the wafer dicing method described above, the step of forming the second protective layer on the surface of the second wafer where the second interconnect element is located includes:

[0019] A dielectric material is deposited on the surface of the second wafer where the second interconnect element is located to obtain the second protective layer;

[0020] Polish the second protective layer to expose the second interconnect element.

[0021] In the wafer dicing method described above, the step of forming a protective structure surrounding the first quantum circuit, the first interconnect element, the second quantum circuit, and the second interconnect element between the first wafer and the second wafer includes:

[0022] A mask layer with a closed pattern is formed on the side of the first wafer facing the second wafer. The closed pattern exposes a portion of the first wafer. The closed pattern is located inside each of the first regions, and each of the closed patterns surrounds a first interconnect element within the first region.

[0023] Deposit sealing material onto the mask layer;

[0024] Remove the mask layer and the sealing material covering the surface of the mask layer to obtain the protective structure.

[0025] In the wafer dicing method described above, the sealing material is indium.

[0026] In the wafer dicing method described above, both the first interconnect element and the second interconnect element are indium pillars.

[0027] In the wafer dicing method described above, the first region is distributed in an array on the surface of the first wafer, and correspondingly, the second region is distributed in an array on the surface of the second wafer.

[0028] In the wafer dicing method described above, the projection of the geometric center of the first region coincides with the projection of the geometric center of the corresponding second region along a direction perpendicular to the first wafer.

[0029] In the wafer dicing method described above, the step of dicing the first wafer and the second wafer includes:

[0030] The first wafer is diced along the edge of the first region, and the second wafer is diced along the edge of the second region.

[0031] In another embodiment of the present invention, the wafer dicing method described above is provided for use in the fabrication of quantum chips.

[0032] Compared with the prior art, this application provides a wafer dicing method, comprising the following steps: providing a first wafer and a second wafer, wherein the surface of the first wafer has a plurality of first regions, each of the first regions having a first quantum circuit and a first interconnecting element electrically connected to the first quantum circuit; the surface of the second wafer has a plurality of second regions, each of the second regions having a second quantum circuit and a second interconnecting element electrically connected to the second quantum circuit; forming a protective structure surrounding the first quantum circuit, the first interconnecting element, the second quantum circuit, and the second interconnecting element between the first wafer and the second wafer; pressing the first wafer and the second wafer together to connect and fix the first interconnecting element and the second interconnecting element; and dicing the first wafer and the second wafer to obtain a quantum chip. In this application, a first region and a second region corresponding to each other are respectively set on a first wafer and a second wafer. The first region and the second region respectively contain a first quantum circuit, a second quantum circuit, a first interconnect element, and a second interconnect element. Then, the first wafer and the second wafer are laminated and then diced to obtain a batch of double-layer stacked quantum chips. Before dicing, a protective structure is formed between the first wafer and the second wafer to protect the first quantum element, the second quantum element, the first interconnect element, and the second interconnect element, so as to avoid contamination or damage to the first quantum element, the second quantum element, the first interconnect element, and the second interconnect element during the dicing process, thereby effectively ensuring the product quality of the quantum chip. Attached Figure Description

[0033] Figure 1 A flowchart of the wafer dicing method provided in this application;

[0034] Figure 2 This is a schematic diagram of the first wafer and the second wafer in the wafer dicing method provided in this application;

[0035] Figure 3 This is a schematic diagram of the bonding process of the first wafer and the second wafer in this application;

[0036] Figure 4 This is a schematic diagram of the first interconnect element and the second interconnect element in this application;

[0037] Figure 5 This is a schematic diagram of the indium wall in another embodiment of this application;

[0038] Figure 6 This is a schematic diagram of the bonding process of the first wafer and the second wafer in another embodiment of this application.

[0039] Explanation of reference numerals in the attached figures:

[0040] 1 – First wafer, 2 – Second wafer, 3 – Indium wall;

[0041] 11 – First region; 12 – First quantum circuit; 13 – First interconnect element; 14 – First protective layer;

[0042] 21 – Second region, 22 – Second quantum circuit, 23 – Second interconnect element, 24 – Second protective layer. Detailed Implementation

[0043] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0044] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the various embodiments of this application to help readers better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments. The division of the various embodiments below is for the convenience of description and should not constitute any limitation on the specific implementation of this application. The various embodiments can be combined with and referenced by each other without contradiction.

[0045] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0046] Additionally, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and / or pattern, it can be located directly on another layer or substrate, and / or intercalation layers may also be present. Furthermore, it should be understood that when a layer is referred to as being "under" another layer, it can be located directly under that layer, and / or one or more intercalation layers may also be present. Additionally, references to "on" and "under" the layers may be made based on the accompanying drawings.

[0047] A quantum computer is a physical device that performs high-speed mathematical and logical operations, stores and processes quantum information, following the laws of quantum mechanics. The main characteristics of quantum computers include high operating speed, strong information processing capabilities, and a wide range of applications. Compared to conventional computers, the greater the amount of information processed, the more advantageous it is for quantum computers to perform calculations, and the more accurate the calculations are. As the core component of a quantum computer, the number of qubits integrated on a quantum chip is gradually increasing. To achieve large-scale expansion of qubits, stacked interconnect technology can be used to fabricate double-layer stacked quantum chips.

[0048] In the mass production process of existing stacked quantum chips, the quantum chips are easily damaged. During the wafer cleaving process, debris and other impurities generated during cleaving can easily remain between the two substrates of the quantum chip, negatively affecting the performance of the quantum chip and making it difficult to guarantee the quality of the quantum chip products.

[0049] Combined with appendix Figure 1 -Appendix Figure 4 As shown in the embodiment of this application, a wafer dicing method includes the following steps:

[0050] S1. A first wafer 1 and a second wafer 2 are provided. The surface of the first wafer 1 has a plurality of first regions 11. Each first region 11 has a first quantum circuit 12 and a first interconnection element 13 electrically connected to the first quantum circuit 12. The surface of the second wafer 2 has a plurality of second regions 21. Each second region 21 has a second quantum circuit 22 and a second interconnection element 23 electrically connected to the second quantum circuit 22.

[0051] In a specific implementation, a first wafer 1 and a second wafer 2 are provided. For example, the materials of the first wafer 1 and the second wafer 2 can be silicon, sapphire, silicon dioxide substrate, gallium nitride substrate, etc. The materials of the first wafer 1 and the second wafer 2 are selected accordingly in different application scenarios, and are not limited to the examples above. In this embodiment, the first wafer 1 and the second wafer 2 can be made of sapphire. Sapphire has a certain degree of transparency, which helps to observe the alignment of certain specific components on the first wafer 1 and the second wafer 2 when adjusting their relative positions.

[0052] A plurality of first regions 11 are defined on the surface of the first wafer 1, and a plurality of second regions 21 are defined on the surface of the second wafer 2. The first regions 11 and the second regions 21 correspond one-to-one. In specific implementation, the surface of the first wafer 1 is divided into a plurality of first regions 11. Preferably, the shape of the first regions 11 can be rectangular. Each first region 11 has the same size, and the first regions 11 are arrayed on the surface of the first wafer 1. Similarly, the second wafer 2 is divided into a plurality of second regions 21 on one side of the first wafer 1. Preferably, the shape of the second regions 21 can be rectangular. Each second region 21 has the same size, and the second regions 21 are arrayed on the surface of the second wafer 2.

[0053] A first quantum circuit 12 is formed in each first region 11, and a second quantum circuit 22 is formed in each second region 21. For example, a coating process can be used to coat a superconducting film on the surfaces of the first wafer 1 and the second wafer 2. Specifically, the superconducting film can be an aluminum film, a niobium film, etc. In ultra-low temperature environments, such as the low-temperature region of a dilution refrigerator, superconducting films such as aluminum films and niobium films can exhibit superconducting properties. Then, an etching process is used to fabricate several first quantum circuits 12 and several second quantum circuits 22 on the superconducting films of the first wafer 1 and the second wafer 2, respectively. Each first quantum circuit 12 is located within a first region 11, and the first quantum circuit 12 is connected to the first region 11. In a one-to-one correspondence, each of the second quantum circuits 22 is located in the second region 21. The second quantum circuits 22 and the second region 21 correspond one-to-one. In specific implementation, a photoresist layer is first spin-coated on the surface of the first wafer 1, and after exposure and development, several circuit patterns corresponding to the first quantum circuits 12 are obtained. The circuit patterns are located in each of the first regions 11. Then, the first quantum circuits 12 are etched out using an etching process. Similarly, a photoresist layer is spin-coated on the surface of the second wafer 2, and after exposure and development, several circuit patterns corresponding to the second quantum circuits 22 are obtained. The circuit patterns are located in each of the second regions 21. Then, the second quantum circuits 22 are etched out using an etching process.

[0054] A first interconnect element 13 is formed in the first region 11, and a second interconnect element 23 is formed in the second region 21. In a specific implementation, a plurality of first interconnect elements 13 are formed in each first region 11, and a plurality of second interconnect elements 23 are formed in each second region 21. The first interconnect elements 13 and the second interconnect elements 23 correspond one-to-one. Furthermore, a portion of the first interconnect elements 13 are electrically connected to the first quantum circuit 12, and a portion of the second interconnect elements 23 are electrically connected to the second quantum circuit 22. For example, the first interconnect elements 13 and the second interconnect elements 23 are both indium pillars.

[0055] S2. A protective structure is formed between the first wafer 1 and the second wafer 2, surrounding the first quantum circuit 12, the first interconnect element 13, the second quantum circuit 22, and the second interconnect element 23. Specifically, the protective structure is formed between the first wafer 1 and the second wafer 2 to protect the first interconnect element 13, the second interconnect element 23, the first quantum circuit 12, and the second quantum circuit 22 from damage. In a specific implementation, the protective structure may be a dielectric layer filled between the first wafer 1 and the second wafer 2, and the dielectric layer covers and wraps the first interconnect element 13, the second interconnect element 23, the first quantum circuit 12, and the second quantum circuit 22.

[0056] By forming a protective structure between the first wafer 1 and the second wafer 2, the first interconnect element 13, the second interconnect element 23, the first quantum circuit 12, and the second quantum circuit 22 are surrounded by the protective structure, thereby effectively protecting the first interconnect element 13, the second interconnect element 23, the first quantum circuit 12, and the second quantum circuit 22 during the subsequent processing, and avoiding damage due to violent destruction or other reasons during the processing.

[0057] S3. Press the first wafer 1 and the second wafer 2 together to connect and fix the first interconnect element 13 and the second interconnect element 23. The first quantum circuit 12 is electrically connected to the second quantum circuit 22 through the first interconnect element 13 and the second interconnect element 23. When pressing the first wafer 1 and the second wafer 2 together, the first interconnect element 13 and the second interconnect element 23 are aligned one by one. The first interconnect element 13 and the second interconnect element are fixed by hot pressing using a wafer bonding machine, thereby keeping the first wafer 1 and the second wafer 2 fixed. The first quantum circuit 12 and the second quantum circuit 22 are electrically connected through the first interconnect element 13 and the second interconnect element 23.

[0058] S4. Divide the first wafer 1 and the second wafer 2 into quantum chips in batches.

[0059] In this embodiment, a first region 11 and a second region 21 corresponding to each other are respectively set on the first wafer 1 and the second wafer 2. A first quantum circuit 12 and a second quantum circuit 22 are then fabricated in the first region 11 and the second region 21, respectively. The first wafer 1 and the second wafer 2 are then laminated and diced to obtain a batch of double-layer stacked quantum chips. Before dicing, a protective structure is formed between the first wafer 1 and the second wafer 2 to protect the first quantum element, the second quantum element, the first interconnect element 13, and the second interconnect element 23. This prevents the first quantum element, the second quantum element, the first interconnect element 13, and the second interconnect element 23 from being contaminated or damaged during the dicing process, thereby effectively ensuring the product quality of the quantum chip.

[0060] In some embodiments of the present invention, the step of forming a protective structure surrounding the first quantum circuit 12, the first interconnect element 13, the second quantum circuit 22, and the second interconnect element 23 between the first wafer 1 and the second wafer 2 includes:

[0061] A first protective layer 14 is formed on the surface of the first wafer 1 where the first interconnect element 13 is located. In a specific implementation, a dielectric material is deposited on the surface of the first wafer 1 where the first interconnect element 13 is located to obtain the first protective layer 14, and then the first protective layer 14 is polished to expose the first interconnect element 13.

[0062] A second protective layer 24 is formed on the surface of the second wafer 2 where the second interconnect element 23 is located. In a specific implementation, a dielectric material is deposited on the surface of the first wafer 1 where the first interconnect element 13 is located to obtain the first protective layer 14. The first protective layer 14 is then polished to expose the first interconnect element 13. The first protective layer 14 and the second protective layer 24 can be made of insulating materials.

[0063] The thickness of the first protective layer 14 is the same as the height of the first interconnect element 13, and the thickness of the second protective layer 24 is the same as the height of the second interconnect element 23. The first protective layer 14 and the second protective layer 24 together constitute the protective structure. For example, a specific method is to use a deposition process to deposit insulating materials on opposite sides of the first wafer 1 and the second wafer 2 to obtain the first protective layer 14 and the second protective layer 24, respectively. Then, the first protective layer 14 and the second protective layer 24 are polished using a CMP polishing process to expose the first interconnect element 13 and the second interconnect element 23. For example, the insulating material can be silicon nitride, silicon dioxide, boron nitride, etc. After polishing, the ends of the first interconnect element 13 and the second interconnect element 23 are flush with the surfaces of the first protective layer 14 and the second protective layer 24, respectively.

[0064] In this embodiment, a first protective layer 14 is formed on the surface of the first wafer 1, and a second protective layer 24 is formed on the surface of the second wafer 2. The first protective layer 14 and the second protective layer 24 are polished using a CMP polishing process to expose the first interconnect element 13 and the second interconnect element 23. This allows the first interconnect element 13 and the second interconnect element 23 to make physical contact during the bonding process of the first wafer 1 and the second wafer 2, thereby enabling the electrical connection between the first interconnect element 13 and the second interconnect element 23.

[0065] Combined with appendix Figure 5 Appendix Figure 6As shown, in some other embodiments of this application, the step of forming a protective structure surrounding the first quantum circuit 12, the first interconnect element 13, the second quantum circuit 22, and the second interconnect element 23 between the first wafer 1 and the second wafer 2 includes:

[0066] A mask layer with a closed pattern is formed on the side of the first wafer 1 facing the second wafer 2. The closed pattern exposes a portion of the first wafer 1. The closed pattern is located inside each of the first regions 11, and each of the closed patterns surrounds the first interconnect element 13 within the first region 11. In a specific implementation, photoresist is spin-coated on the side of the first wafer 1 facing the second wafer 2 to obtain a photoresist layer on the surface of the first wafer 1. Then, the closed pattern is obtained on the photoresist layer through processes such as exposure and development. For example, the closed pattern can be a rectangle, a circle, a polygon, etc. There are several closed patterns. The closed pattern corresponds one-to-one with the first region 11. Each first region 11 has one closed pattern, and each closed pattern is located inside its respective first region 11. The closed pattern exposes a portion of the surface of the first wafer 1.

[0067] Using a deposition process, a sealing material is deposited on the mask layer, with some of the sealing material deposited on the surface of the mask layer and some of the sealing material deposited on the surface of the first wafer 1 exposed by the closed pattern;

[0068] The mask layer and the sealing material covering the surface of the mask layer are removed, thereby retaining the sealing material deposited on the surface of the first wafer 1 to obtain the protective structure. Exemplarily, one specific way is that the protective structure is a rectangular wall structure formed on the surface of the first wafer 1, which surrounds the first interconnect element 13 and the first quantum circuit 12 located in the same first region 11, thereby protecting the first quantum circuit 12 and the first interconnect element 13.

[0069] It should be noted that the height of the indium wall 3 is equal to the sum of the heights of the first interconnect element 13 and the second interconnect element 23. The sealing material can be indium. Indium is used to construct closed indium walls 3 in each first region 11. The first interconnect element 13 and the second interconnect element 23 are both indium pillars. When the first wafer 1 and the second wafer 2 are pressed together, the indium wall 3 is connected to the surface of the second wafer 2. The indium wall 3 is used to construct a closed space between the first region 11 and the second region 21. The first quantum circuit 12, the second quantum circuit 22, the first interconnect element 13, and the second interconnect element 23 are all located in the closed space, thereby protecting the first quantum circuit 12, the second quantum circuit 22, the first interconnect element 13, and the second interconnect element 23 in each first region 11 and the second region 21.

[0070] In this embodiment, an indium wall 3 is constructed on the surface of the first wafer 1 to serve as a protective structure. The indium wall 3 corresponds one-to-one with the first region 11, and an indium wall 3 is formed in each first region 11. The first wafer 1 and the second wafer 2 are then connected together using a wafer bonding machine. The indium wall 3 is used to construct a closed space between the first region 11 and the second region 21, thereby protecting the first quantum circuit 12, the second quantum circuit 22, the first interconnect element 13, and the second interconnect element 23 in each first region 11 and the second region 21. This prevents impurities generated during the dicing of the first wafer 1 and the second wafer 2 from entering the space between the first region 11 and the second region 21 and damaging the quantum circuits. Furthermore, the indium wall 3 can also improve the bonding strength between the first wafer 1 and the second wafer 2, effectively ensuring the normal progress of the dicing operation and guaranteeing the product quality of the quantum chip.

[0071] It should be noted that, in order to facilitate the dicing and cutting of the first wafer 1 and the second wafer 2, the first region 11 is arrayed on the surface of the first wafer 1, and correspondingly, the second region 21 is arrayed on the surface of the second wafer 2. This allows multiple first regions 11 or second regions 21 to be cut in a single cutting process when dicing and cutting the first wafer 1 and the second wafer 2, thereby improving cutting efficiency.

[0072] Furthermore, as an example, the dimensions of each first region 11 and second region 21 are the same, and along the direction perpendicular to the first wafer 1, the projection of the geometric center of the first region 11 coincides with the projection of the geometric center of the corresponding second region 21, so as to facilitate the cutting of the first wafer 1 and the second wafer 2.

[0073] In some embodiments of this application, the step of dicing the first wafer 1 and the second wafer 2 includes:

[0074] The first wafer 1 is diced along the edge of the first region 11, and the second wafer 2 is diced along the edge of the second region 21. For example, a laser dicing machine is used to cut the first wafer 1 and the second wafer 2 respectively, and the dicing depth is precisely adjusted to ensure that the second wafer 2 is not damaged when dicing the first wafer 1, and the first wafer 1 is not damaged when dicing the second wafer 2.

[0075] In another embodiment of the present invention, the wafer dicing method described above is provided for use in the fabrication of quantum chips.

[0076] In conjunction with the above embodiments, the wafer dicing method provided by the present invention, when applied to the fabrication of bilayer quantum chips, can achieve mass production of quantum chips and effectively guarantee the product quality of quantum chips.

[0077] As described herein, the terms “deposition process” and / or “deposition procedure” can refer to any process of growing, coating, depositing and / or otherwise transferring one or more first materials onto one or more second materials. Exemplary deposition processes may include, but are not limited to: physical vapor deposition (“PVD”), chemical vapor deposition (“CVD”), electrochemical deposition (“ECD”), atomic layer deposition (“ALD”), low-pressure chemical vapor deposition (“LPCVD”), plasma-enhanced chemical vapor deposition (“PECVD”), high-density plasma chemical vapor deposition (“HDPCVD”), subatmospheric pressure chemical vapor deposition (“SACVD”), rapid thermochemical vapor deposition (“RTCVD”), in-situ radical-assisted deposition, high-temperature oxide deposition (“HTO”), low-temperature oxide deposition (“LTO”), limited reaction process CVD (“LRPCVD”), ultra-high vacuum chemical vapor deposition (“UHVCVD”), metal-organic chemical vapor deposition (“MOCVD”), physical vapor deposition (“PVD”), chemical oxidation, sputtering, electroplating, evaporation, spin coating, ion beam deposition, electron beam deposition, laser-assisted deposition, chemical solution deposition, combinations thereof, and / or similar methods.

[0078] The above description, based on the embodiments shown in the drawings, details the structure, features, and effects of this application. The above description is only a preferred embodiment of this application, but this application does not limit the scope of implementation to what is shown in the drawings. Any changes made in accordance with the concept of this application, or modifications to equivalent embodiments, that do not exceed the spirit covered by the specification and drawings, should be within the protection scope of this application.

Claims

1. A wafer dicing method, characterized in that, Includes the following steps: A first wafer (1) and a second wafer (2) are provided. The surface of the first wafer (1) has a plurality of first regions (11), each of the first regions (11) having a first quantum circuit (12) and a first interconnecting element (13) electrically connected to the first quantum circuit (12). The surface of the second wafer (2) has a plurality of second regions (21), each of the second regions (21) having a second quantum circuit (22) and a second interconnecting element (23) electrically connected to the second quantum circuit (22). A protective structure is formed between the first wafer (1) and the second wafer (2) to surround the first quantum circuit (12), the first interconnect element (13), the second quantum circuit (22), and the second interconnect element (23). The protective structure encloses or closes the first interconnect element (13), the second interconnect element (23), the first quantum circuit (12), and the second quantum circuit (22). The first wafer (1) and the second wafer (2) are pressed together to connect and fix the first interconnect element (13) and the second interconnect element (23); The first wafer (1) and the second wafer (2) are diced to obtain a quantum chip.

2. The wafer dicing method as described in claim 1, characterized in that, The step of forming a protective structure surrounding the first quantum circuit (12), the first interconnect element (13), the second quantum circuit (22), and the second interconnect element (23) between the first wafer (1) and the second wafer (2) includes: A first protective layer (14) is formed on the surface of the first wafer (1) where the first interconnect element (13) is located; A second protective layer (24) is formed on the surface of the second wafer (2) where the second interconnect element (23) is located; The thickness of the first protective layer (14) is the same as the height of the first interconnecting element (13), and the thickness of the second protective layer (24) is the same as the height of the second interconnecting element (23). The first protective layer (14) and the second protective layer (24) together constitute the protective structure.

3. The wafer dicing method as described in claim 2, characterized in that, The step of forming the first protective layer (14) on the surface of the first wafer (1) where the first interconnect element (13) is located includes: A dielectric material is deposited on the surface of the first wafer (1) where the first interconnect element (13) is located to obtain the first protective layer (14); Polish the first protective layer (14) to expose the first interconnect element (13).

4. The wafer dicing method as described in claim 3, characterized in that, The step of forming the second protective layer (24) on the surface of the second wafer (2) where the second interconnect element (23) is located includes: A dielectric material is deposited on the surface of the second wafer (2) where the second interconnect element (23) is located to obtain the second protective layer (24); Polish the second protective layer (24) to expose the second interconnect element (23).

5. The wafer dicing method as described in claim 1, characterized in that, The step of forming a protective structure surrounding the first quantum circuit (12), the first interconnect element (13), the second quantum circuit (22), and the second interconnect element (23) between the first wafer (1) and the second wafer (2) includes: A mask layer with a closed pattern is formed on the side of the first wafer (1) facing the second wafer (2), the closed pattern exposing a portion of the first wafer (1), the closed pattern being located inside each of the first regions (11), and each of the closed patterns surrounding the first interconnect element (13) within the first region (11). Deposit sealing material onto the mask layer; Remove the mask layer and the sealing material covering the surface of the mask layer to obtain the protective structure.

6. The wafer dicing method as described in claim 5, characterized in that, The sealing material is indium.

7. The wafer dicing method according to any one of claims 1-6, characterized in that, Both the first interconnect element (13) and the second interconnect element (23) are indium pillars.

8. The wafer dicing method as described in claim 7, characterized in that, The first region (11) is distributed in an array on the surface of the first wafer (1), and correspondingly, the second region (21) is distributed in an array on the surface of the second wafer (2).

9. The wafer dicing method as described in claim 8, characterized in that, Along a direction perpendicular to the first wafer (1), the projection of the geometric center of the first region (11) coincides with the projection of the geometric center of the corresponding second region (21).

10. The application of a wafer dicing method as described in any one of claims 1-9 in the fabrication of quantum chips.

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