Semiconductor structure and method of manufacturing a semiconductor structure

Abstract

The present disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a substrate having a first region and a second region; a first gate structure located in the first region and a second gate structure located in the second region, the first gate structure being a high dielectric constant gate structure including a first gate electrode layer and a high dielectric constant layer, the second gate structure including a second gate electrode layer and an oxide insulating layer; an isolation layer and an interlayer dielectric layer located on the first gate structure and the second gate structure, the isolation layer and the interlayer dielectric layer covering a portion of the second gate structure, the substrate, and the first gate structure; and a second contact plug penetrating through the isolation layer and the interlayer dielectric layer and contacting the substrate, the second contact plug being located in the second region and overlapping the second gate structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for fabricating the semiconductor structure. Background Technology

[0002] In the layout design of the core region of Dynamic Random Access Memory (DRAM), such as the HKMG (high-k insulating layer + gate electrode layer) structure, there is a design where the active region (AA) and the gate share a common contact structure, using the gate as a conductor. However, during the etching process of the contact structure, the spacer layer on the sidewall of the Protect Gate (PG) is partially etched, exposing the gate material of the Protect Gate. The HK layer metals, such as lanthanum oxide (LaO) and aluminum oxide (ALO), can contaminate the equipment environment. Furthermore, these HK layer metals falling onto the active region can contaminate the silicon. Additionally, after filling the metal to form the contact plunger, due to the partial etching of the spacer layer on the sidewall of the Protect Gate, and the easily diffused properties of lanthanum and aluminum, these metal materials diffuse into the contact plunger, contaminating it. Summary of the Invention

[0003] A primary objective of this disclosure is to overcome at least one of the deficiencies of the prior art described above and to provide a semiconductor structure that can avoid metal diffusion contamination of the protective gate.

[0004] Another primary objective of this disclosure is to overcome at least one of the deficiencies of the prior art and to provide a method for fabricating a semiconductor structure.

[0005] To achieve the above objectives, the present disclosure adopts the following technical solution:

[0006] According to one aspect of this disclosure, a semiconductor structure is provided, comprising: a substrate having a first region and a second region; a first gate structure located in the first region and a second gate structure located in the second region, the first gate structure being a high-dielectric-constant gate including a first gate electrode layer and a high-dielectric-constant layer, and the second gate structure including a second gate electrode layer and an oxide insulating layer; an isolation layer and an interlayer dielectric layer located on the first gate structure and the second gate structure, the isolation layer and the interlayer dielectric layer covering a portion of the second gate structure, the substrate, and the first gate structure; and a second contact plunger penetrating the isolation layer and the interlayer dielectric layer and contacting the substrate, the second contact plunger being located in the second region and overlapping the second gate structure.

[0007] According to another aspect of this disclosure, a method for fabricating a semiconductor structure is provided, comprising: providing a substrate having a first region and a second region; forming a first gate structure on the first region of the substrate; forming a second gate structure on the second region of the substrate; the first gate structure being a high-dielectric-constant gate, comprising a first gate electrode layer and a high-dielectric-constant layer; and the second gate structure comprising a second gate electrode layer and an oxide insulating layer; forming an isolation layer and an interlayer dielectric layer on the surface of the substrate, the isolation layer and the interlayer dielectric layer covering the substrate, the first gate structure and the second gate structure; removing a portion of the second gate structure, a portion of the isolation layer and the interlayer dielectric layer to form a second contact hole; and filling the second contact hole with a conductive material to form a second contact plunger that partially overlaps with the second gate structure.

[0008] As can be seen from the above technical solutions, the advantages and positive effects of the semiconductor structure and its fabrication method proposed in this disclosure are as follows:

[0009] The semiconductor structure proposed in this disclosure employs a different gate structure for the protective gate located in the second region compared to the other gates located in the first region. Specifically, unlike existing solutions that use a gate electrode layer and a high-dielectric-constant layer to form all gates in all regions, this disclosure uses a gate electrode layer and an oxide insulating layer to form the protective gate in the second region. These two gate structures together constitute the entire gate of the semiconductor structure. Through this design, the gate structure composed of a gate electrode layer and an oxide insulating layer reduces the interconnect area of ​​the upper metal layer while avoiding the problem of HK layer metal diffusion contamination in existing solutions, ensuring that device performance is not affected by contamination. Attached Figure Description

[0010] The various objectives, features, and advantages of this disclosure will become more apparent from the following detailed description of preferred embodiments of the disclosure taken in conjunction with the accompanying drawings. The drawings are merely illustrative illustrations of the disclosure and are not necessarily drawn to scale. In the drawings, the same reference numerals always denote the same or similar parts. Wherein:

[0011] Figure 1 This is a planar schematic diagram of a portion of the semiconductor structure proposed in this disclosure;

[0012] Figure 2 This is a flowchart illustrating the method for fabricating the semiconductor structure proposed in this disclosure;

[0013] Figures 3 to 14 The diagram shows a stacked structure of the semiconductor structure in several steps of an exemplary embodiment of a method for fabricating a semiconductor structure.

[0014] Figures 15 to 27 The diagram shows a stacked structure of the semiconductor structure in several steps of another exemplary embodiment of the method for fabricating a semiconductor structure. Detailed Implementation

[0015] Typical embodiments embodying the features and advantages of this disclosure will be described in detail in the following description. It should be understood that this disclosure can have various variations in different embodiments without departing from the scope of this disclosure, and the descriptions and drawings therein are illustrative in nature and not intended to limit this disclosure.

[0016] In the following description of various exemplary embodiments of this disclosure, reference is made to the accompanying drawings, which form part of this disclosure, and which illustrate by way of example different exemplary structures, systems, and steps that can implement various aspects of this disclosure. It should be understood that other specific embodiments of the components, structures, exemplary devices, systems, and steps may be used, and structural and functional modifications may be made without departing from the scope of this disclosure. Furthermore, while the terms “above,” “between,” “within,” etc., may be used in this specification to describe different exemplary features and elements of this disclosure, these terms are used herein only for convenience, such as the orientation according to the examples described in the accompanying drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of this disclosure.

[0017] See Figure 1 The diagram illustrates a partial planar schematic (i.e., top view) of the semiconductor structure proposed in this disclosure. In this exemplary embodiment, the semiconductor structure proposed in this disclosure is described using a dynamic random access memory (DRAM) as an example. It will be readily understood by those skilled in the art that various modifications, additions, substitutions, deletions, or other changes may be made to the specific embodiments described below to apply the relevant designs of this disclosure to other types of semiconductor structures, and these changes remain within the scope of the principles of the semiconductor structure proposed in this disclosure.

[0018] It should be noted that, Figure 1 Only a portion of the semiconductor structure proposed in this disclosure is shown, specifically including a substrate 100, a first gate structure G1, a second gate structure G2, and a second contact plunger C2. Other figures illustrating process steps are also shown. Figure 9 , Figure 11 , Figure 13 , Figure 22 , Figure 24 and Figure 26 It can be understood as along Figure 1 A cross-sectional view (i.e., a cross section view) of line XX in the diagram, and Figure 10 , Figure 12 , Figure 14 , Figure 23 , Figure 25 and Figure 27 It can be understood as along Figure 1 The diagram shows a cross-sectional view along line YY. Furthermore, since the semiconductor morphology shown in the other figures is largely the same in both the "XX" and "YY" cross-sectional views, the distinction is not made as described above.

[0019] like Figure 1 As shown, and in conjunction with other references Figure 13 , Figure 14 , Figure 26 and Figure 27 As shown, in one embodiment of this disclosure, the semiconductor structure proposed in this disclosure includes a substrate 100, a first gate structure G1 and a second gate structure G2, an isolation layer 600, an interlayer dielectric layer 700, and a second contact plunger C2. The substrate 100 has a first region A and a second region B. The first gate structure G1 is disposed on the first region A of the substrate 100, and the second gate structure G2 is disposed on the second region B of the substrate 100. The first gate structure G1 is a high-dielectric-constant gate, comprising a first gate electrode layer and a high-dielectric-constant layer, and the second gate structure G2 comprises a second gate electrode layer and an oxide insulating layer. The isolation layer 600 and the interlayer dielectric layer 700 are located on the first gate structure G1 and the second gate structure G2, and respectively cover a portion of the second gate structure G2, the substrate 100, and the first gate structure G1. The second contact plunger C2 penetrates the interlayer dielectric layer 700 and the isolation layer 600, the bottom of the second contact plunger C2 contacts the substrate 100, and the second contact plunger C2 is located in the second region B and overlaps with the second gate structure G2. Through the above design, this disclosure adopts a gate structure composed of a gate electrode layer and an oxide insulating layer. While reducing the interconnect area of ​​the upper metal layer, it can also avoid the problem of metal diffusion and contamination in the HK layer in the existing solution, and ensure that the device performance is not affected by contamination.

[0020] like Figure 1 , Figure 13 and Figure 26 As shown, in one embodiment of this disclosure, the semiconductor structure proposed in this disclosure further includes a first contact plunger C1, which penetrates the interlayer dielectric layer 700 and the isolation layer 600. The bottom of the first contact plunger C1 is in contact with the substrate 100, and the first contact plunger C1 and the first gate structure G1 are arranged at intervals.

[0021] In one embodiment of this disclosure, a first contact hole V1 is formed in the interlayer dielectric layer 700 of the first region A and is spaced apart from the first gate structure G1. A second contact hole V2 is formed by removing a portion of the second gate structure G2, a portion of the insulating layer 600, and the interlayer dielectric layer 700. A first contact plunger C1 is disposed in the first contact hole V1. A second contact plunger C2 is disposed in the second contact hole V2.

[0022] like Figure 13 , Figure 14 , Figure 26 and Figure 27 As shown, in one embodiment of this disclosure, the first gate structure G1 includes a high-dielectric-constant layer and a first gate electrode layer. The high-dielectric-constant layer includes a high-dielectric-constant insulating layer 220 and a high-dielectric-constant metal layer. The high-dielectric-constant insulating layer 220 is disposed on the surface of the substrate 100, and the high-dielectric-constant metal layer is disposed on the surface of the high-dielectric-constant insulating layer 220. The first gate electrode layer is disposed on the high-dielectric-constant metal layer. A first dielectric material layer 250 is disposed between each pair of the high-dielectric-constant insulating layer 220, the high-dielectric-constant metal layer, and the first gate electrode layer (see reference for further details). Figure 4 ).

[0023] In one embodiment of this disclosure, the first dielectric material layer 250 may be made of titanium nitride (TiN).

[0024] like Figure 13 , Figure 14 , Figure 26 and Figure 27 As shown, based on the design that the first gate structure G1 includes a high dielectric constant layer, and the high dielectric constant layer includes a high dielectric constant metal layer, in one embodiment of this disclosure, the high dielectric constant metal layer includes, from bottom to top, an aluminum oxide metal layer 230 and a second dielectric material layer 260 (see reference). Figure 3 ) and lanthanum oxide metal layer 240.

[0025] In one embodiment of this disclosure, the second dielectric material layer 260 may be made of titanium nitride.

[0026] like Figure 13 , Figure 14 , Figure 26 and Figure 27 As shown, based on the design of the first gate structure G1 including a first gate electrode layer, in one embodiment of this disclosure, the first gate electrode layer can refer to the remaining first gate material layer 300 shown in the figures, which includes, from bottom to top, a polysilicon layer 310 and a first barrier layer 330 (see reference). Figure 3 ) and metal layer 320.

[0027] In one embodiment of this disclosure, the first barrier layer 330 may be made of titanium nitride.

[0028] like Figure 13 , Figure 14 , Figure 26 and Figure 27 As shown, in one embodiment of this disclosure, an oxide insulating layer 210 covers the surface of a substrate 100. Based on this, a first gate structure G1 and a second gate structure G2 are respectively disposed on the oxide insulating layer 210, and an isolation layer 600 covers the oxide insulating layer 210, the first gate structure G1, and the second gate structure G2. A first contact plunger C1 and a second contact plunger C2 penetrate the isolation layer 600, the interlayer dielectric layer 700, and the oxide insulating layer 210.

[0029] like Figure 13 , Figure 14 , Figure 26 and Figure 27 As shown, based on the design of the semiconductor structure including the oxide insulating layer 210, in one embodiment of this disclosure, the second gate structure G2 may include a second gate electrode layer and the oxide insulating layer 210 below it. The second gate electrode layer may refer to the remaining second gate material layer 400 shown in the figures, which includes a polysilicon layer, a second barrier layer, and a metal layer from bottom to top. Accordingly, this disclosure places the second gate electrode layer on the oxide insulating layer 210, and uses the oxide insulating layer 210 below the second gate electrode layer as part of constituting the second gate structure G2, specifically realizing the design of the "gate structure composed of the gate electrode layer and the oxide insulating layer" of the second gate structure G2 in the second region B.

[0030] like Figure 13 , Figure 14 , Figure 26 and Figure 27 As shown, in one embodiment of this disclosure, the second contact plunger C2 overlaps with the top surface of the first portion of the second gate structure G2 and the first side surface adjacent to the top surface of the first portion. Furthermore, the projection portions of the second contact plunger C2 and the second gate structure G2 onto the substrate 100 coincide.

[0031] like Figure 13 , Figure 14 , Figure 26 and Figure 27 As shown, in one embodiment of this disclosure, a first contact layer 810 is provided between the first contact plunger C1 and the substrate 100, and a second contact layer 820 is provided between the second contact plunger C2 and the substrate 100.

[0032] like Figure 13 , Figure 14As shown, in one embodiment of this disclosure, the isolation layer 600 of the second region B covers the top and side surfaces of the oxide insulating layer 210 and the second gate structure G2. Furthermore, the second gate structure G2 also includes another isolation layer located between the second gate electrode layer and the oxide insulating layer 210. In other words, in Figure 13 and Figure 14 In the illustrated embodiment, the top, side, and bottom surfaces of the second gate structure G2 (which does not include the oxide insulating layer 210 but only the second gate electrode layer) are covered with an isolation layer 600.

[0033] like Figure 26 and Figure 27 As shown, in one embodiment of this disclosure, the second gate structure G2 (which does not include the oxide insulating layer 210, but only includes the second gate electrode layer) can be located on the substrate 100, that is, the isolation layer 600 of the second region B only covers the top and side surfaces of the second gate structure G2, but does not cover the bottom surface of the second gate structure G2.

[0034] like Figure 26 and Figure 27 As shown, in one embodiment of this disclosure, the interlayer dielectric layer 700 is located on the isolation layer 600, and the interlayer dielectric layer 700 covers the isolation layer 600.

[0035] In one embodiment of this disclosure, the first region A and the second region B can both be located in the peripheral circuit region of the semiconductor structure. Based on this, the second region B can be understood as the region in the peripheral circuit region where a protective gate is disposed, i.e., the region where the second gate structure G2 is disposed. Through the above design, this disclosure adopts a design that includes a gate electrode layer and an oxide insulating layer for the protective gate of the peripheral circuit region of the semiconductor structure. This reduces the interconnection area of ​​the upper metal layer while avoiding the problem of metal diffusion contamination in the HK layer of existing solutions, ensuring that the device performance is not affected by contamination.

[0036] It should be noted that the semiconductor structures shown in the accompanying drawings and described in this specification are merely a few examples of many semiconductor structures capable of employing the principles of this disclosure. It should be clearly understood that the principles of this disclosure are by no means limited to any detail or component of the semiconductor structures shown in the accompanying drawings or described in this specification.

[0037] Based on the above detailed description of several exemplary embodiments of the semiconductor structure proposed in this disclosure, the exemplary embodiments of the method for fabricating the semiconductor structure proposed in this disclosure will be described in detail below.

[0038] See Figure 2This illustration represents a flowchart of a method for fabricating a semiconductor structure according to the present disclosure. In this exemplary embodiment, the method for fabricating a semiconductor structure according to the present disclosure is described using an application to a dynamic random access memory as an example. It will be readily understood by those skilled in the art that various modifications, additions, substitutions, deletions, or other changes may be made to the specific embodiments described below to apply the relevant designs of the present disclosure to other types of semiconductor structures, and these changes remain within the scope of the principles of the method for fabricating a semiconductor structure according to the present disclosure.

[0039] like Figure 2 As shown, the method for fabricating the semiconductor structure disclosed herein includes:

[0040] Step S1: Provide a substrate 100, form a first gate structure G1 on a first region A of the substrate 100, and form a second gate structure G2 on a second region B of the substrate 100. The first gate structure G1 is a high-dielectric-constant gate, which includes a first gate electrode layer and a high-dielectric-constant layer. The second gate structure G2 includes a second gate electrode layer and an oxide insulating layer 210.

[0041] Step S2: An isolation layer 600 is formed on the surface of the substrate 100. The isolation layer 600 is located on the first gate structure G1 and the second gate structure G2, and covers the substrate 100, the first gate structure G1 and the second gate structure G2.

[0042] Step S3: An interlayer dielectric layer 700 is formed on the surface of the isolation layer 600. The interlayer dielectric layer 700 is located on the isolation layer 600 and covers the isolation layer 600.

[0043] Step S4: Remove part of the second gate structure G2, part of the isolation layer 600 and the interlayer dielectric layer 700 to form the second contact hole V2;

[0044] Step S5: Fill the second contact hole V2 with conductive material 800 to form a second contact plunger C2 that partially overlaps with the second gate structure G2.

[0045] Through the above process design, unlike existing solutions that use a gate electrode layer and a high-dielectric-constant layer to form the gate in all regions, this disclosure uses a gate electrode layer and an oxide insulating layer to form the gate in the second region of the semiconductor structure. This allows both gate structures to jointly constitute the entire gate of the semiconductor structure. Accordingly, this disclosure, using a gate structure composed of a gate electrode layer and an oxide insulating layer, reduces the interconnect area of ​​the upper metal layer while avoiding the problem of metal diffusion contamination in the HK layer of existing solutions, ensuring that device performance is not affected by contamination.

[0046] See Figures 3 to 14 , Figures 3 to 14The accompanying drawings illustrate, representatively, several steps of a method for fabricating a semiconductor structure, showing a stacked structure of the semiconductor structure. The main process steps of the method for fabricating the semiconductor structure proposed in this disclosure will be described in detail below with reference to the accompanying drawings.

[0047] like Figures 3 to 6 As shown, in one embodiment of this disclosure, step S1 may specifically include the following steps:

[0048] A thin film stack structure is formed on the substrate 100. The thin film stack structure includes an oxide insulating layer 210 and a high dielectric constant layer, with the oxide insulating layer 210 being the bottom layer.

[0049] A first gate material layer 300 is formed on the thin film stacked structure;

[0050] Etching removes part of the first gate material layer 300 and the thin film stack structure to form the first gate structure G1, with the etching stopping at the upper surface of the oxide insulating layer 210;

[0051] A second gate material layer 400 is formed on the oxide insulating layer 210, which covers the first gate structure G1;

[0052] A portion of the second gate material layer 400 is etched away, and the remaining second gate material layer 400 together with the oxide insulating layer 210 constitutes the second gate structure G2.

[0053] like Figure 3 and Figure 4 As shown, in one embodiment of this disclosure, the step of "etching away a portion of the first gate material layer 300 and the thin film stack structure" may specifically include the following steps:

[0054] A first photoresist layer PR1 is deposited on the first gate material layer 300;

[0055] Patterned first photoresist layer PR1;

[0056] Using the patterned first photoresist layer PR1, part of the first gate material layer 300 and the thin film stack structure are etched away to form the first gate structure G1.

[0057] Specifically, such as Figure 3As shown, in one embodiment of this disclosure, through the steps of "forming a thin film stacked structure on a substrate 100, the thin film stacked structure including an oxide insulating layer 210 and a high dielectric constant layer, wherein the oxide insulating layer 210 is the bottommost layer", "forming a first gate material layer 300 on the thin film stacked structure", and "depositing a first photoresist layer PR1 on the first gate material layer 300", the semiconductor structure includes a substrate 100, a thin film stacked structure, a first gate material layer 300, and a first photoresist layer PR1. The thin film stacked structure is located on the surface of the substrate 100. The first gate material layer 300 is located on the surface of the thin film stacked structure. The first photoresist layer PR1 is located on the surface of the first gate material layer 300, and the first photoresist layer PR1 is patterned to form a photolithographic pattern.

[0058] Specifically, such as Figure 3 As shown, in one embodiment of this disclosure, the thin-film stacked structure may include an oxide insulating layer 210 and a high dielectric constant layer formed sequentially from bottom to top on the surface of the substrate 100. The high dielectric constant layer includes a high dielectric constant insulating layer 220 and a high dielectric constant metal layer formed sequentially from bottom to top on the surface of the oxide insulating layer 210. The high dielectric constant metal layer may include two layers, such as an aluminum oxide (AlO) metal layer and a lanthanum oxide (LaO) metal layer. A first dielectric material layer 250 is formed between each pair of the high dielectric constant insulating layer 220, the high dielectric constant metal layer, and the first gate material layer 300, and a second dielectric material layer 260 is formed between the aluminum oxide metal layer 230 and the lanthanum oxide metal layer 240. The materials of the first dielectric material layer 250 and the second dielectric material layer 260 may be, but are not limited to, the same, for example, titanium nitride.

[0059] In one embodiment of this disclosure, the oxide insulating layer 210 may be made of, but is not limited to, silicon oxynitride (SiON).

[0060] Specifically, such as Figure 3 As shown, in one embodiment of this disclosure, the first gate material layer 300 may include a polysilicon layer 310 and a metal layer 310 (e.g., tungsten, W) formed sequentially from bottom to top on the surface of a thin film stack structure (e.g., the topmost barrier material). Additionally, a first barrier layer 330 may be formed between the polysilicon layer 310 and the metal layer 310. The material of the first barrier layer 330 may be, for example, but not limited to, titanium nitride.

[0061] Specifically, such as Figure 4As shown, in one embodiment of this disclosure, in the step of "etching away a portion of the first gate material layer 300 and the thin film stack structure using the patterned first photoresist layer PR1 to form a first gate structure G1", the semiconductor structure includes a substrate 100, the thin film stack structure and the first gate material layer 300 after partial removal by etching, and the remaining first photoresist layer PR1. The remaining thin film stack structure and the first gate material layer 300 together constitute the first gate structure G1, and the remaining first gate material layer 300 is the first gate electrode layer. Furthermore, the etching in the above process stops at the upper surface of the oxide insulating layer 210; that is, the oxide insulating layer 210 is not etched away in the above etching process and remains covering the surface of the substrate 100.

[0062] Specifically, in one embodiment of this disclosure, after the step of "forming the first gate structure G1", a step of removing the remaining first photoresist layer PR1 is further included. For details, please refer to the relevant documentation. Figure 5 .

[0063] like Figure 5 As shown, in one embodiment of this disclosure, prior to the step of "forming a second gate material layer 400 on the oxide insulating layer 210", the following may also be included:

[0064] A mask layer 500 is formed on the surface of the first gate structure G1 and the oxide insulating layer 210.

[0065] Specifically, such as Figure 5 As shown, in one embodiment of this disclosure, in the step of "forming a mask layer 500 on the surface of the first gate structure G1 and the oxide insulating layer 210", the semiconductor structure includes a substrate 100, an oxide insulating layer 210, a first gate structure G1, and a mask layer 500. The mask layer 500 covers the first gate structure G1 and the oxide insulating layer 210.

[0066] In one embodiment of this disclosure, the material of the mask layer 500 may include, but is not limited to, silicon nitride (Si3N4).

[0067] In one embodiment of this disclosure, the process of "etching away a portion of the second gate material layer 400, with the remaining second gate material layer 400 and the oxide insulating layer 210 together constituting the second gate structure G2" may specifically include the following steps:

[0068] A second photoresist layer is deposited on the second gate material layer 400;

[0069] Patterned second photoresist layer;

[0070] Using the patterned second photoresist layer, a portion of the second gate material layer 400 is etched away to form the second gate structure G2.

[0071] Specifically, such as Figure 6 As shown, in one embodiment of this disclosure, in the step of "etching away a portion of the second gate material layer 400 using the patterned second photoresist layer to form a second gate structure G2", the semiconductor structure includes a substrate 100, a first gate structure G1, a mask layer 500, and the second gate material layer 400 removed by etching. The remaining second gate material layer 400 and the underlying oxide insulating layer 210 together constitute the second gate structure G2, and the remaining second gate material layer 400 is the second gate electrode layer. Furthermore, the etching in the above process ends at the upper surface of the mask layer 500; that is, the mask layer 500 is not etched away in the above etching process and remains covering the surfaces of the first gate structure G1 and the oxide insulating layer 210.

[0072] like Figure 7 As shown, in one embodiment of this disclosure, in step S2, the semiconductor structure includes a substrate 100, a first gate structure G1, a second gate structure G2, and an isolation layer 600. In this embodiment, the isolation layer 600 and the mask layer 500 are made of the same material, meaning the material of the isolation layer 600 may include, but is not limited to, silicon nitride. Based on this, Figure 7 The layered structure after the formation of the isolation layer 600 is shown, whereby the isolation layer 600 includes the mask layer 500. Furthermore, after the formation of the isolation layer 600 in step S2, ion implantation can be performed on the source / drain (S / D).

[0073] like Figure 8 As shown, in one embodiment of this disclosure, in step S3, the semiconductor structure includes a substrate 100, a first gate structure G1, a second gate structure G2, an isolation layer 600, and an interlayer dielectric layer 700. The interlayer dielectric layer 700 covers the surface of the isolation layer 600.

[0074] like Figure 9 , Figure 11 and Figure 13 As shown, in one embodiment of this disclosure, after the step of "forming an interlayer dielectric layer 700 on the surface of the isolation layer 600", the following step may be included:

[0075] A first contact hole V1 is formed in the interlayer dielectric layer 700 of the first region A, and the first contact hole V1 is arranged at intervals with the first gate structure G1.

[0076] The first contact hole V1 is filled with conductive material 800 to form the first contact plunger C1.

[0077] like Figure 9As shown, in one embodiment of this disclosure, in step S4, the semiconductor structure includes a substrate 100, a first gate structure G1, a second gate structure G2, an isolation layer 600, and an interlayer dielectric layer 700. The interlayer dielectric layer 700 has a first contact hole V1 formed at a position corresponding to the position between two adjacent first gate structures G1. The top end of the first contact hole V1 opens onto the surface of the interlayer dielectric layer 700, and the lower end of the first contact hole V1 extends and penetrates into the substrate 100. In other words, the first contact hole V1 passes through the oxide insulating layer 210 covering the substrate 100, exposing a portion of the substrate 100. It should be noted that... Figure 9 The stacked structure shown is a cross-sectional view of the semiconductor structure taken from a top-view perspective in a first direction. The first contact hole V1 can be observed from this perspective, but the second contact hole V2 cannot be observed.

[0078] like Figure 10 As shown, in one embodiment of this disclosure, in step S4, a second contact hole V2 is formed in the interlayer dielectric layer 700 of the second region B. The top of the second contact hole V2 opens onto the surface of the interlayer dielectric layer 700, and a portion of the lower end of the second contact hole V2 extends to a portion of the upper surface of the second gate structure G2. Another portion of the lower end of the second contact hole V2 continues to extend and penetrates the substrate 100. In other words, a portion of the second contact hole V2 passes through the isolation layer 600 covering the second gate structure G2, exposing the first portion of the top surface and the first side surface of the second gate structure G2, and another portion of the second contact hole V2 passes through the oxide insulating layer 210 covering the substrate 100, exposing a portion of the substrate 100. Accordingly, the second contact hole V2 can be understood as being formed by removing a portion of the isolation layer 600 covering the surface of the second gate structure G2. It should be noted that... Figure 10 The stacked structure shown is a cross-sectional view of the semiconductor structure taken from a top-view perspective along a second direction, in which the second contact hole V2 can be observed, but the first contact hole V1 cannot be observed.

[0079] like Figures 11 to 14 As shown, in one embodiment of this disclosure, the step of "filling the first contact hole V1 with conductive material 800 and filling the second contact hole V2 with conductive material 800" may specifically include the following steps:

[0080] A conductive material 800 is covered on the interlayer dielectric layer 700, and the conductive material 800 fills the first contact hole V1 and the second contact hole V2.

[0081] Grinding removes the conductive material 800 from the upper surface of the interlayer dielectric layer 700.

[0082] like Figure 11 and Figure 12As shown, in one embodiment of this disclosure, in the step of "covering the interlayer dielectric layer 700 with conductive material 800", the semiconductor structure includes a substrate 100, a first gate structure G1, a second gate structure G2, an isolation layer 600, an interlayer dielectric layer 700, and conductive material 800. The conductive material 800 covers the surface of the interlayer dielectric layer 700 and fills the first contact hole V1 and the second contact hole V2. Since the top surface and first side surface of the first portion of the second gate structure G2 are exposed to the second contact hole V2, the conductive material 800 filling the second contact hole V2 overlaps with the exposed second gate structure G2. Based on this, the second contact plunger C2 coincides with the projection portion of the second gate structure G2 on the substrate 100.

[0083] like Figure 11 and Figure 12 As shown, in one embodiment of this disclosure, before the step of "filling the first contact hole V1 with conductive material 800 and the second contact hole V2 with conductive material 800", the following steps may be included:

[0084] A first contact layer 810 is formed at the bottom of the first contact hole V1, and a second contact layer 820 is formed at the bottom of the second contact hole V2.

[0085] like Figure 11 and Figure 12 As shown, in one embodiment of this disclosure, the conductive material 800 filling the first contact hole V1 and the second contact hole V2 is separated from the exposed substrate 100 by the first contact layer 810 and the second contact layer 820, respectively.

[0086] In one embodiment of this disclosure, the first contact layer 810 and the second contact layer 820 may be made of the same material, but are not limited to, for example, containing cobalt silicide (CoSi). x Specifically, before filling the conductive material 800, cobalt (Co) is first filled at the bottom of the first contact hole V1 and the second contact hole V2. Since the substrate 100 is exposed at the bottom of the first contact hole V1 and the second contact hole V2, the cobalt filled in the above process and the silicon (Si) of the substrate 100 can form cobalt silicide through high temperature.

[0087] like Figure 13 and Figure 14As shown, in one embodiment of this disclosure, in the step of "grinding to remove the conductive material 800 covering the upper surface of the interlayer dielectric layer 700", the semiconductor structure includes a substrate 100, a first gate structure G1, a second gate structure G2, an isolation layer 600, an interlayer dielectric layer 700, and the conductive material 800 remaining after grinding. The portion of the conductive material 800 covering the surface of the interlayer dielectric layer 700 is ground away, and the remaining conductive material 800 fills the first contact hole V1 and the second contact hole V2, thereby forming a first contact plunger C1 and a second contact plunger C2, respectively. This grinding process enables the upper surfaces of the first contact plunger C1 and the second contact plunger C2 to be flush with the upper surface of the interlayer dielectric layer 700.

[0088] It should be noted that this embodiment is illustrated using the example of the first contact plunger C1 and the second contact plunger C2 being made of the same material. In some embodiments, when the first contact plunger C1 and the second contact plunger C2 are made of different materials, the first contact plunger C1 and the second contact plunger C2 can be formed in the first contact hole V1 and the second contact hole V2 respectively through two deposition and grinding processes of conductive materials 800 of different materials, and this is not a limitation.

[0089] See Figures 15 to 27 , Figures 15 to 27 The diagrams illustrate the stacked structure of the semiconductor structure in several steps of another exemplary embodiment of the semiconductor structure fabrication method. In this embodiment, steps S2 to S5 are respectively... Figures 2 to 14 The above-described embodiments are largely the same. The following will describe in detail the process design that distinguishes this embodiment from other embodiments.

[0090] like Figures 15 to 20 As shown, in one embodiment of this disclosure, step S1 may specifically include the following steps:

[0091] A thin film stack structure is formed on the substrate 100. The thin film stack structure includes an oxide insulating layer 210 and a high dielectric constant layer, with the oxide insulating layer 210 being the bottom layer.

[0092] The thin film stack structure located in the second region B is removed by etching, and the etching stops at the upper surface of the oxide insulating layer 210.

[0093] A first gate material layer 300 and a second gate material layer 400 are respectively covered on the oxide insulating layer 210 of the thin film stacked structure and the second region B.

[0094] Etching removes part of the first gate material layer 300 and the thin film stack structure to form the first gate structure G1. The etching stops at the upper surface of the oxide insulating layer 210. Etching removes part of the second gate material layer 400. The remaining second gate material layer 400 and the oxide insulating layer 210 together constitute the second gate structure G2.

[0095] like Figure 15 and Figure 16 As shown, in one embodiment of this disclosure, the step of "etching away the thin film stack structure located in the second region B" may specifically include the following steps:

[0096] A third photoresist layer PR3 is deposited on the thin film stack structure;

[0097] Patterned third photoresist layer PR3;

[0098] Using the patterned third photoresist layer PR3, the thin film stack structure located in the second region B is etched away.

[0099] Specifically, such as Figure 15 As shown, in one embodiment of this disclosure, in the steps of "depositing a third photoresist layer PR3 on a thin film stack structure" and "patterning the third photoresist layer PR3", the semiconductor structure includes a substrate 100, a thin film stack structure, and a third photoresist layer PR3. The thin film stack structure is located on the surface of the substrate 100. The third photoresist layer PR3 is located on the surface of the thin film stack structure, and the third photoresist layer PR3 is patterned to form a photolithographic pattern.

[0100] Specifically, such as Figure 16 As shown, in one embodiment of this disclosure, in the step of "etching away the thin film stack structure located in the second region B using the patterned third photoresist layer PR3", the semiconductor structure includes a substrate 100, the remaining thin film stack structure after etching, and the third photoresist layer PR3. The etching stops at the upper surface of the oxide insulating layer 210, meaning the oxide insulating layer 210 is not removed in the etching process and remains covering the surface of the substrate 100. In other words, except for the oxide insulating layer 210, the portion of the thin film stack structure located in the second region B is etched away, and the remaining thin film stack structure, excluding the oxide insulating layer 210, is located in the first region A. Furthermore, after the etching process is completed, a step of removing the remaining third photoresist layer PR3 is also included.

[0101] Specifically, such as Figure 17As shown, in one embodiment of this disclosure, in the step of "covering a first gate material layer 300 and a second gate material layer 400 on the oxide insulating layer 210 of the thin film stack structure and the second region B respectively", the semiconductor structure includes a substrate 100, the remaining thin film stack structure including all oxide insulating layers 210, a first gate material layer 300, and a second gate material layer 400. The first gate material layer 300 covers the surface of the portion of the thin film stack structure located in the first region A, for example, the surface of the topmost barrier material of the remaining thin film stack structure. The second gate material layer 400 covers the surface of the second region B, i.e., the surface of the oxide insulating layer 210 exposed after partial removal of the thin film stack structure. Furthermore, this embodiment is described using the example of the first gate material layer 300 and the second gate material layer 400 having the same material. For example, the second gate material layer 400 includes a polysilicon layer, a metal layer, and a second barrier layer formed between them; therefore, the first gate material layer 300 and the second gate material layer 400 can be implemented using the same process. In some implementations, when the materials of the first gate material layer 300 and the second gate material layer 400 are different, they can also be implemented by two separate processes, and this is not a limitation.

[0102] like Figures 18 to 20 As shown, in one embodiment of this disclosure, based on the fact that the first gate material layer 300 and the second gate material layer 400 are made of the same material, the step of "etching away a portion of the first gate material layer 300 and the thin film stack structure, and etching away a portion of the second gate material layer 400" may specifically include the following steps:

[0103] A fourth photoresist layer PR4 is deposited on the first gate material layer 300 and the second gate material layer 400;

[0104] Patterned fourth photoresist layer PR4;

[0105] Using the patterned fourth photoresist layer PR4, a portion of the first gate material layer 300 and the thin film stack structure are etched away, while a portion of the second gate material layer 400 is etched away, forming the first gate structure G1 and the second gate structure G2, respectively.

[0106] Specifically, such as Figure 18As shown, in one embodiment of this disclosure, during the steps of "depositing a fourth photoresist layer PR4 on the first gate material layer 300 and the second gate material layer 400" and "patterning the fourth photoresist layer PR4", the semiconductor structure includes a substrate 100, an oxide insulating layer 210, a first gate material layer 300 and a thin film stack structure, a second gate material layer 400, and a patterned fourth photoresist layer PR4. The patterned fourth photoresist layer PR4 is located on both the first gate material layer 300 and the second gate material layer 400.

[0107] Specifically, such as Figure 19 As shown, in one embodiment of this disclosure, in the step of "etching away a portion of the first gate material layer 300 and the thin film stack structure using the patterned fourth photoresist layer PR4, and simultaneously etching away a portion of the second gate material layer 400", the semiconductor structure includes a substrate 100, an oxide insulating layer 210, the remaining first gate material layer 300 and the thin film stack structure after etching, the remaining second gate material layer 400 after etching, and the remaining fourth photoresist layer PR4. The remaining first gate material layer 300 and the thin film stack structure together constitute a first gate structure G1, and the remaining second gate material layer 400 constitutes a second gate structure G2. Furthermore, as... Figure 20 As shown, after the above etching process, there is also a step of removing the remaining fourth photoresist layer PR4.

[0108] Specifically, such as Figure 21 As shown, in one embodiment of this disclosure, in steps S2 and S3, the semiconductor structure includes a substrate 100, a first gate structure G1, a second gate structure G2, an isolation layer 600, and an interlayer dielectric layer 700. The isolation layer 600 covers the first gate structure G1, the second gate structure G2, and a portion of the exposed oxide insulating layer 210. The interlayer dielectric layer 700 covers the isolation layer 600. Furthermore, in step S2, after forming the isolation layer 600 and before forming the interlayer dielectric layer 700, ion implantation can be performed on the source / drain (S / D) electrodes.

[0109] like Figures 22 to 27 As shown, this diagram represents a stacked structure of a semiconductor structure at different angles during several specific process steps in step S4. Specific process design and... Figures 2 to 14 The illustrated embodiments are largely the same and will not be described in detail here.

[0110] It should be noted that the methods for fabricating the semiconductor structures shown in the accompanying drawings and described in this specification are merely a few examples of many fabrication methods that can employ the principles of this disclosure. It should be clearly understood that the principles of this disclosure are by no means limited to any detail or step of the methods for fabricating the semiconductor structures shown in the accompanying drawings or described in this specification.

[0111] In summary, the semiconductor structure proposed in this disclosure employs a different gate structure for the protective gate located in the second region compared to the other gates located in the first region. Specifically, unlike existing solutions that use a gate structure consisting of a gate electrode layer and a high-dielectric-constant layer for all gates in all regions, this disclosure uses a gate structure consisting of a gate electrode layer and an oxide insulating layer for the protective gate in the second region. This allows both gate structures to collectively constitute the entire gate of the semiconductor structure. Through this design, the gate structure consisting of a gate electrode layer and an oxide insulating layer reduces the interconnect area of ​​the upper metal layer while avoiding the problem of metal diffusion contamination in the HK layer of existing solutions, ensuring that device performance is not affected by contamination.

[0112] The foregoing has described and / or illustrated exemplary embodiments of the semiconductor structures and methods for fabricating semiconductor structures proposed in this disclosure. However, the embodiments of this disclosure are not limited to the specific embodiments described herein; rather, components and / or steps of each embodiment may be used independently and separately from other components and / or steps described herein. Each component and / or step of one embodiment may also be used in combination with other components and / or steps of other embodiments. In describing the elements / components / etc. described and / or illustrated herein, the terms “a,” “an,” and “the above” are used to indicate the presence of one or more elements / components / etc. The terms “comprising,” “including,” and “having” are used to indicate an open-ended inclusion and mean that additional elements / components / etc. may exist in addition to those listed. Furthermore, the terms “first” and “second” in the claims and specification are used only as illustrative marks and are not intended to limit the numerical scope of the subject matter.

[0113] Although the semiconductor structure and method of fabrication of the semiconductor structure have been described according to different specific embodiments, those skilled in the art will recognize that modifications may be made to the implementation of the disclosure within the spirit and scope of the claims.

Claims

1. A semiconductor structure comprising: The substrate has a first region and a second region; A first gate structure located in the first region and a second gate structure located in the second region, wherein the first gate structure is a high-dielectric-constant gate and includes a first gate electrode layer and a high-dielectric-constant layer, and the second gate structure includes a second gate electrode layer and an oxide insulating layer; the oxide insulating layer covers the substrate, the first gate structure is disposed on the oxide insulating layer, and the high-dielectric-constant layer is located on the upper surface of the oxide insulating layer. An isolation layer and an interlayer dielectric layer are located on the first gate structure and the second gate structure, and the isolation layer and the interlayer dielectric layer cover a portion of the second gate structure, the substrate and the first gate structure; The second contact plunger penetrates the isolation layer, the interlayer dielectric layer, and the oxide insulating layer and contacts the substrate located between the first gate structure and the second gate structure. The second contact plunger also contacts the side surface and part of the top surface of the second gate electrode layer.

2. The semiconductor structure according to claim 1, wherein, The high dielectric constant layer comprises: A high dielectric constant insulating layer is disposed on the surface of the substrate; and A high dielectric constant metal layer is disposed on the high dielectric constant insulating layer; The first gate electrode layer is disposed on the high dielectric constant metal layer; A first dielectric material layer is disposed between each pair of the high dielectric constant insulating layer, the high dielectric constant metal layer, and the first gate electrode layer.

3. The semiconductor structure according to claim 2, wherein: The high dielectric constant metal layer comprises, from bottom to top, an aluminum oxide metal layer, a second dielectric material layer, and a lanthanum oxide metal layer; and / or the first gate electrode layer comprises, from bottom to top, a polysilicon layer, a first barrier layer, and a metal layer.

4. The semiconductor structure according to claim 1, wherein, Also includes: The first contact plunger penetrates the isolation layer and the interlayer dielectric layer and contacts the substrate, and the first contact plunger is arranged at intervals from the first gate structure.

5. The semiconductor structure according to claim 4, wherein, The oxide insulating layer covers the substrate, the first gate structure is disposed on the oxide insulating layer, the isolation layer and the interlayer dielectric layer cover the oxide insulating layer, and the first contact plunger and the second contact plunger penetrate the oxide insulating layer, the isolation layer and the interlayer dielectric layer.

6. The semiconductor structure according to claim 4, wherein: The first contact plunger includes a first contact layer that contacts the substrate; and / or The second contact plunger includes a second contact layer that contacts the substrate.

7. The semiconductor structure according to claim 1, wherein, The second gate structure includes a second gate electrode layer, which comprises, from bottom to top, a polysilicon layer, a second barrier layer, and a metal layer.

8. The semiconductor structure according to claim 1, wherein, The second contact plunger overlaps with the top surface of the first portion of the second gate structure and the first side surface adjacent to the top surface of the first portion, and the second contact plunger coincides with the projection portion of the second gate structure on the substrate.

9. The semiconductor structure according to claim 1, wherein, The second gate structure further includes another isolation layer located between the second gate electrode layer and the oxide insulating layer.

10. The semiconductor structure according to claim 1, wherein, The first region and the second region are located in the peripheral circuit region of the semiconductor structure.

11. A method for fabricating a semiconductor structure, comprising: A substrate is provided having a first region and a second region. A first gate structure is formed on the first region of the substrate, and a second gate structure is formed on the second region of the substrate. The first gate structure is a high-dielectric-constant gate and includes a first gate electrode layer and a high-dielectric-constant layer. The second gate structure includes a second gate electrode layer and an oxide insulating layer. The oxide insulating layer covers the substrate, the first gate structure is disposed on the oxide insulating layer, and the high-dielectric-constant layer is located on the upper surface of the oxide insulating layer. An isolation layer and an interlayer dielectric layer are formed on the surface of the substrate, the isolation layer and the interlayer dielectric layer covering the substrate, the first gate structure and the second gate structure; A second contact hole is formed by removing a portion of the second gate structure, a portion of the isolation layer, a portion of the interlayer dielectric layer, and a portion of the oxide insulating layer. The second contact hole is filled with conductive material to form a second contact plunger that overlaps with the second gate structure. The second contact plunger penetrates the isolation layer, the interlayer dielectric layer and the oxide insulating layer and contacts the substrate located between the first gate structure and the second gate structure. The second contact plunger also contacts the side surface and part of the top surface of the second gate structure.

12. The method for fabricating a semiconductor structure according to claim 11, wherein, The step of forming a first gate structure on a first region of the substrate and forming a second gate structure on a second region of the substrate includes: A thin film stack structure is formed on the substrate, the thin film stack structure comprising an oxide insulating layer and a high dielectric constant layer from bottom to top; A first gate material layer is formed on the thin film stack structure; Etching removes part of the first gate material layer and the thin film stack structure to form the first gate structure, with the etching stopping at the upper surface of the oxide insulating layer; A second gate material layer is formed on the oxide insulating layer, and the second gate material layer covers the first gate structure; A portion of the second gate material layer is etched away, and the remaining second gate material layer, together with the oxide insulating layer, constitutes the second gate structure.

13. The method for fabricating a semiconductor structure according to claim 12, wherein, The step of etching away a portion of the first gate material layer and the thin film stack structure includes: A first photoresist layer is deposited on the first gate material layer; Pattern the first photoresist layer; Using the patterned first photoresist layer, a portion of the first gate material layer and the thin film stack structure are etched away to form the first gate structure.

14. The method for fabricating a semiconductor structure according to claim 12, wherein, Prior to the step of forming a second gate material layer on the oxide insulating layer, the method further includes: A mask layer is formed on the surface of the first gate structure and the oxide insulating layer.

15. The method for fabricating a semiconductor structure according to claim 12, wherein, The step of etching away a portion of the second gate material layer includes: A second photoresist layer is deposited on the second gate material layer; Pattern the second photoresist layer; Using the patterned second photoresist layer, a portion of the second gate material layer is etched away to form the second gate structure.

16. The method for fabricating a semiconductor structure according to claim 11, wherein, The step of forming a first gate structure on a first region of the substrate and forming a second gate structure on a second region of the substrate includes: A thin film stack structure is formed on the substrate, the thin film stack structure comprising an oxide insulating layer and a high dielectric constant layer from bottom to top; The thin film stack structure located in the second region is removed by etching, with the etching stopping at the upper surface of the oxide insulating layer; A first gate material layer is covered on the remaining thin film stack structure, and a second gate material layer is covered on the oxide insulating layer located in the second region; The first gate material layer and the thin film stack structure are etched away to form the first gate structure. The etching stops at the upper surface of the oxide insulating layer. The second gate material layer is etched away, and the remaining second gate material layer and the oxide insulating layer together constitute the second gate structure.

17. The method for fabricating a semiconductor structure according to claim 16, wherein, The step of etching away the thin film stack structure located in the second region includes: A third photoresist layer is deposited on the thin film stack structure; Pattern the third photoresist layer; The patterned third photoresist layer is used to etch away the thin film stack structure located in the second region.

18. The method for fabricating a semiconductor structure according to claim 16, wherein, The first gate material layer and the second gate material layer are made of the same material. The steps of etching away portions of the first gate material layer and the thin film stack structure, and etching away portions of the second gate material layer, include: A fourth photoresist layer is deposited on the first gate material layer and the second gate material layer; Pattern the fourth photoresist layer; Using the patterned fourth photoresist layer, a portion of the first gate material layer and the thin film stack structure are etched away, while a portion of the second gate material layer is etched away, to form the first gate structure and the second gate structure, respectively.

19. The method for fabricating a semiconductor structure according to any one of claims 11 to 18, wherein, Also includes: A first contact hole is formed in the isolation layer and the interlayer dielectric layer located in the first region, and the first contact hole is arranged at a distance from the first gate structure. The first contact hole is filled with conductive material to form a first contact plunger that contacts the substrate.

20. The method for fabricating a semiconductor structure according to claim 19, wherein: The step of filling the first contact hole with conductive material and the second contact hole with conductive material includes: covering the interlayer dielectric layer with conductive material, and filling the first contact hole and the second contact hole with conductive material; Grinding removes the conductive material covering the upper surface of the interlayer dielectric layer; and / or Before the steps of filling the first contact hole with conductive material and filling the second contact hole with conductive material, the method further includes: forming a first contact layer in contact with the substrate at the bottom of the first contact hole, and forming a second contact layer in contact with the substrate at the bottom of the second contact hole.

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