Light emitting diode structure and method of fabricating the same

Abstract

The present application relates to a kind of light-emitting diode structure and its manufacturing method.The present application includes substrate;Buffer layer, first semiconductor layer, positive electrode current barrier layer, negative electrode current barrier layer, first current diffusion layer, etching barrier layer, second current diffusion layer A, second current diffusion layer B, second current diffusion layer C, positive electrode pad, negative electrode pad and insulating passivation layer;Wherein, second current diffusion layer A, second current diffusion layer B and second current diffusion layer C are all distributed with the pit area arranged through respective surface;Second current diffusion layer A, second current diffusion layer B and second current diffusion layer C any layer or the pit area of multiple layers in or upper and lower surface is provided with metal nanoparticle.The present application can improve the current diffusion capacity of LED device, increase the injection efficiency of carrier, and further improve the light extraction efficiency.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a light-emitting diode structure and its fabrication method. Background Technology

[0002] Improving the luminous efficiency of LEDs (Light Emitting Diodes) is highly beneficial for energy conservation and emission reduction. However, with technological advancements and market saturation, enhancing LED luminous efficiency has become increasingly difficult and its effects limited. The external quantum efficiency of an LED consists of three aspects: internal quantum efficiency, light extraction efficiency, and carrier injection efficiency. Currently, researchers primarily focus on improving internal quantum efficiency and light extraction efficiency. However, current LEDs suffer from insufficient current diffusion capabilities, leading to reduced carrier injection efficiency and consequently lower light extraction efficiency. Summary of the Invention

[0003] Therefore, the present invention provides a light-emitting diode structure and a method for manufacturing the same, which improves the current diffusion capability of the LED device, thereby increasing the carrier injection efficiency and thus improving the light extraction efficiency.

[0004] To solve the above-mentioned technical problems, the present invention provides a light-emitting diode structure, comprising: Substrate; A buffer layer is disposed on the surface of the substrate; A first semiconductor layer is disposed on the surface of the buffer layer. The first semiconductor layer is provided with a first step and a second step. The first step and the second step together include a common low step surface and a negative current blocking layer is disposed on the common low step surface. An active layer and a second semiconductor layer are disposed sequentially on the high step surface of the first step and the high step surface of the second step. A positive current blocking layer is disposed on the surface of the second semiconductor layer located on the high step surface of the first step. The positive current blocking layer is provided with a groove that penetrates to the surface of the second semiconductor layer. A first current diffusion layer is disposed on the surface of the second semiconductor layer, and the first current diffusion layer is in contact with the positive current blocking layer; An etch barrier layer is disposed on the surface of the first current diffusion layer; A second current diffusion layer A is disposed on the surface of the etch barrier layer; A second current diffusion layer B is disposed on the bottom surface of the groove; The second current diffusion layer C is disposed on the surface of the negative electrode current blocking layer; A positive electrode pad is disposed on the bottom surface of the groove and is in contact with the second current diffusion layer B and the positive electrode current blocking layer, respectively. The negative electrode pad is disposed on the surface of the common low step surface and is in contact with the second current diffusion layer C and the negative electrode current blocking layer, respectively. An insulating passivation layer is disposed on the surface of the second current diffusion layer A; Among them, the second current diffusion layer A, the second current diffusion layer B and the second current diffusion layer C are all distributed with pit areas that penetrate their respective surfaces; Metal nanoparticles are disposed in or on the upper or lower surfaces of any one or more layers of the second current diffusion layer A, the second current diffusion layer B, and the second current diffusion layer C in the pit area.

[0005] In one embodiment of the present invention, the metal nanoparticles are embedded in the pits by self-assembly.

[0006] In one embodiment of the present invention, the structure of the metal nanoparticles includes spheres, hemispheres, cylinders, and polyhedra.

[0007] In one embodiment of the present invention, the size of the metal nanoparticles is 1~5 nm.

[0008] In one embodiment of the present invention, the thickness of the first current diffusion layer is 2~10 nm.

[0009] In one embodiment of the present invention, the thicknesses of the second current diffusion layer A, the second current diffusion layer B, and the second current diffusion layer C are respectively 20~200nm.

[0010] In one embodiment of the present invention, the etching barrier layer is made of graphene and has 1 to 5 layers.

[0011] In one embodiment of the present invention, a third step is provided at each of the two ends of the first semiconductor layer, and the insulating passivation layer extends from the surface of the second current diffusion layer A to the surfaces of the first step, the second step and the third step.

[0012] In one embodiment of the present invention, a reflective layer is provided on the side of the substrate away from the buffer layer.

[0013] The present invention also provides a method for fabricating a light-emitting diode structure, comprising: An epitaxial wafer is provided, wherein the epitaxial wafer comprises a substrate, a buffer layer, a first semiconductor layer, an active layer and a second semiconductor layer disposed sequentially; A first step and a second step are formed along the surface of the first semiconductor layer on the epitaxial wafer, and a third step is formed at both ends. The first step and the second step together include a common low step surface. A negative current blocking layer is formed on the common low step surface, and a positive current blocking layer is formed on the surface of the second semiconductor layer located on the high step surface of the first step. The positive current blocking layer is provided with a groove that extends to the surface of the second semiconductor layer. A film is deposited on the surface of the second semiconductor layer, and then the film is subjected to rapid thermal annealing to form a first current diffusion layer. An etch barrier layer is coated on the surface of the first current diffusion layer. The etch barrier layer is patterned in a local area by photolithography. Then, the local etch barrier layer is removed by plasma etching technology, and wet etching is performed in the area to remove the local first current diffusion layer. A second current diffusion layer is formed by depositing a film on the surface of the first current diffusion layer and then performing rapid thermal annealing at 300~500℃. Next, the second current diffusion layer is photolithographically etched and wet etching is used to remove localized portions of the second current diffusion layer. Subsequently, a metal film is deposited and then subjected to rapid thermal annealing at 500~650℃. A pit region penetrating the surface is created in the second current diffusion layer, and metal nanoparticles are embedded in the pits by self-assembly. An insulating passivation layer is formed on the surface of the second current diffusion layer, the insulating passivation layer extending to the surfaces of the first step, the second step and the third step; A positive electrode pad and a negative electrode pad are fabricated separately. The positive electrode pad is disposed on the bottom surface of the groove and is in contact with the second current diffusion layer and the positive current blocking layer, respectively. The negative electrode pad is disposed on the surface of the common low step surface and is in contact with the second current diffusion layer and the negative current blocking layer, respectively. The reflective layer is fabricated by grinding and thinning the side of the substrate away from the buffer layer.

[0014] The technical solution of the present invention has the following advantages compared with the prior art: The present invention discloses a light-emitting diode structure and its manufacturing method, which improves the light-emitting diode structure, enhances the transport efficiency and diffusion uniformity of charge carriers inside the device, effectively improves the charge carrier injection efficiency, and thus improves the overall light extraction efficiency of the LED.

[0015] In this invention, the graphene etching barrier layer can effectively prevent the first current diffusion layer from being corroded by acid, ensuring good ohmic contact between it and the second semiconductor layer. It can make full use of the good lateral current diffusion capability of graphene and the local electromagnetic field enhanced by metal nanoparticles to improve the longitudinal current diffusion capability, thereby improving the overall current diffusion capability of the device and reducing the device voltage.

[0016] This invention introduces metal nanoparticles to create a roughened interface in the light-emitting region of the device, thereby enhancing light scattering and improving the light-harvesting efficiency of the device. Attached Figure Description

[0017] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0018] Figure 1 This is a schematic diagram of the light-emitting diode structure in Embodiment 1 of the present invention.

[0019] Figure 1A yes Figure 1 A magnified view of a portion of the image.

[0020] Figure 2 This is a schematic diagram of the light-emitting diode structure in Embodiment 2 of the present invention.

[0021] Figure 3 This is a schematic diagram of the light-emitting diode structure in Embodiment 3 of the present invention.

[0022] Figure 4 This is a schematic diagram of the light-emitting diode structure in Embodiment 4 of the present invention.

[0023] Figure 5 This is a schematic diagram of the light-emitting diode structure in Embodiment 5 of the present invention.

[0024] Figure 6 This is a schematic diagram of the epitaxial wafer in Embodiment Six of the present invention.

[0025] Figure 7 This is a schematic diagram of the Mesa step fabrication in Embodiment Six of the present invention.

[0026] Figure 8 This is a schematic diagram of the fabrication of the current blocking layer in Embodiment Six of the present invention.

[0027] Figure 9 This is a schematic diagram of the fabrication of the first current diffusion layer and the etching barrier layer in Embodiment Six of the present invention.

[0028] Figure 10 This is a schematic diagram of the fabrication of the second current diffusion layer and metal nanoparticles in Embodiment Six of the present invention.

[0029] Figure 11 This is a schematic diagram of the fabrication of the insulating passivation layer and solder pads in Embodiment Six of the present invention.

[0030] Figure 12 This is a schematic diagram of the grinding and thinning process and the fabrication of the back reflector in Embodiment Six of the present invention.

[0031] Explanation of reference numerals in the instruction manual: 1. Substrate; 11. Mirror layer; 2. Buffer layer; 3a, First semiconductor layer; 31a, First step; 31b, Second step; 31c, Third step; 3b, Second semiconductor layer; 4a. Positive current blocking layer; 4b. Negative current blocking layer; 41. Groove; 5. Active layer; 6. First current diffusion layer; 7. Etch the barrier layer; 8. Second current diffusion layer; 81. Second current diffusion layer A; 82. Second current diffusion layer B; 83. Second current diffusion layer C; 84. Cavity region; 85. Metal nanoparticles; 9a, Positive electrode pad; 9b, Negative electrode pad; 10. Insulating passivation layer. Detailed Implementation

[0032] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments described are not intended to limit the present invention.

[0033] In this invention, when directions (up, down, left, right, front, and back) are described, it is only for the purpose of describing the technical solution of this invention, and does not indicate or imply that the technical features referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this invention.

[0034] In this invention, "several" means one or more, "multiple" means two or more, "greater than," "less than," "exceeding," etc., are understood to exclude the stated number; "above," "below," "within," etc., are understood to include the stated number. In the description of this invention, the terms "first" and "second" are used only to distinguish technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0035] In this invention, unless otherwise explicitly defined, the terms "setting," "installing," and "connecting" should be interpreted broadly. For example, they can refer to a direct connection or an indirect connection through an intermediate medium; a fixed connection, a detachable connection, or an integrally formed connection; a mechanical connection, an electrical connection, or a connection capable of mutual communication; or the internal connection of two components or the interaction between two components. Those skilled in the art can reasonably determine the specific meaning of the above terms in this invention based on the specific content of the technical solution.

[0036] Example 1 Reference Figure 1 , Figure 1A As shown, a light-emitting diode structure in this embodiment includes: Substrate 1; Buffer layer 2 is disposed on the surface of the substrate 1; A first semiconductor layer 3a is disposed on the surface of the buffer layer 2. The first semiconductor layer 3a is provided with a first step 31a and a second step 31b. The first step 31a and the second step 31b together include a common low step surface and a negative current blocking layer 4b is disposed on the common low step surface. An active layer 5 and a second semiconductor layer 3b are disposed sequentially on the high step surface of the first step 31a and the high step surface of the second step 31b. A positive current blocking layer 4a is disposed on the surface of the second semiconductor layer 3b located on the high step surface of the first step 31a. The positive current blocking layer 4a is provided with a groove 41 that penetrates to the surface of the second semiconductor layer 3b. A first current diffusion layer 6 is disposed on the surface of the second semiconductor layer 3b, and the first current diffusion layer 6 is in contact with the positive current blocking layer 4a. An etch barrier layer 7 is disposed on the surface of the first current diffusion layer 6; A second current diffusion layer A81 is disposed on the surface of the etch barrier layer 7; The second current diffusion layer B82 is disposed on the bottom surface of the groove 41; The second current diffusion layer C83 is disposed on the surface of the negative electrode current blocking layer 4b; A positive electrode pad 9a is disposed on the bottom surface of the groove 41 and is in contact with the second current diffusion layer B82 and the positive electrode current blocking layer 4a respectively. The negative electrode pad 9b is disposed on the surface of the common low step surface and is in contact with the second current diffusion layer C83 and the negative electrode current blocking layer 4b respectively. An insulating passivation layer 10 is disposed on the surface of the second current diffusion layer A81; Among them, the second current diffusion layer A81, the second current diffusion layer B82 and the second current diffusion layer C83 are all distributed with pit areas 84 that penetrate their respective surfaces.

[0037] In this embodiment, metal nanoparticles 85 are embedded in the pit regions 84 of the second current diffusion layer A81, the second current diffusion layer B82 and the second current diffusion layer C83 through self-assembly.

[0038] In other embodiments, the metal nanoparticles 85 may be disposed within or on the upper or lower surfaces of any one or more of the second current diffusion layers A81, B82, and C83 in the pit region 84. By introducing the metal nanoparticles 85, a roughened interface is formed in the light-emitting region of the device, enhancing light scattering and thereby improving the light-harvesting efficiency of the device.

[0039] In this embodiment, the structure of the metal nanoparticles 85 includes spheres, hemispheres, cylinders, and polyhedra, and the size of the metal nanoparticles 85 is 1~5nm. The pit regions 84 are regularly or irregularly distributed, and the shape and size of the metal nanoparticles 85 in different pit regions 84 can be the same or different, which is not limited here.

[0040] In this embodiment, the thickness of the first current diffusion layer 6 is 2~10nm; the thicknesses of the second current diffusion layer A81, the second current diffusion layer B82 and the second current diffusion layer C83 are 20~200nm respectively.

[0041] In this embodiment, the etching barrier layer 7 is made of graphene and has 1 to 5 layers. By setting the etching barrier layer 7 of graphene, the first current diffusion layer 6 can be effectively prevented from being corroded by acid, ensuring good ohmic contact between it and the second semiconductor layer 3b. It can make full use of the good lateral current diffusion capability of graphene and the local electromagnetic field enhanced by the metal nanoparticles 85 to improve the longitudinal current diffusion capability, thereby improving the overall current diffusion capability of the device and reducing the device voltage.

[0042] In this embodiment, third steps 31c are respectively provided on both sides of the first semiconductor layer 3a, and the insulating passivation layer 10 extends from the surface of the second current diffusion layer A81 to the surfaces of the first step 31a, the second step 31b and the third step 31c.

[0043] In this embodiment, a reflective layer 11 is provided on the side of the substrate 1 away from the buffer layer 2.

[0044] Example 2 Reference Figure 2 As shown, a light-emitting diode structure in this embodiment includes: Substrate 1; Buffer layer 2 is disposed on the surface of substrate 1; A first semiconductor layer 3a is disposed on the surface of the buffer layer 2. The first semiconductor layer 3a is provided with a first step 31a and a second step 31b. The first step 31a and the second step 31b together include a common low step surface and a negative current blocking layer 4b is disposed on the common low step surface. An active layer 5 and a second semiconductor layer 3b are disposed sequentially on the high step surface of the first step 31a and the high step surface of the second step 31b. A positive current blocking layer 4a is disposed on the surface of the second semiconductor layer 3b located on the high step surface of the first step 31a. The positive current blocking layer 4a is provided with a groove 41 that penetrates to the surface of the second semiconductor layer 3b. A first current diffusion layer 6 is disposed on the surface of the second semiconductor layer 3b, and the first current diffusion layer 6 is in contact with the positive current blocking layer 4a. An etch barrier layer 7 is disposed on the surface of the first current diffusion layer 6; A second current diffusion layer A81 is disposed on the surface of the etch barrier layer 7; The second current diffusion layer B82 is disposed on the bottom surface of the groove 41; The second current diffusion layer C83 is disposed on the surface of the negative electrode current blocking layer 4b; A positive electrode pad 9a is disposed on the bottom surface of the groove 41 and is in contact with the second current diffusion layer B82 and the positive electrode current blocking layer 4a respectively. The negative electrode pad 9b is disposed on the surface of the common low step surface and is in contact with the second current diffusion layer C83 and the negative electrode current blocking layer 4b respectively. An insulating passivation layer 10 is disposed on the surface of the second current diffusion layer A81; Among them, the second current diffusion layer A81, the second current diffusion layer B82 and the second current diffusion layer C83 are all distributed with pit areas 84 that penetrate their respective surfaces.

[0045] In this embodiment, metal nanoparticles 85 are embedded in the pit regions 84 of the second current diffusion layer A81, the second current diffusion layer B82, and the second current diffusion layer C83 through self-assembly. Metal nanoparticles 85 are also disposed on the upper surface of the second current diffusion layer A81, and their shape and size may be the same as or different from the metal nanoparticles 85 in the pit regions 84. The remaining structures of this embodiment are the same as in Embodiment 1.

[0046] Example 3 Reference Figure 3 As shown, a light-emitting diode structure in this embodiment includes: Substrate 1; Buffer layer 2 is disposed on the surface of substrate 1; A first semiconductor layer 3a is disposed on the surface of the buffer layer 2. The first semiconductor layer 3a is provided with a first step 31a and a second step 31b. The first step 31a and the second step 31b together include a common low step surface and a negative current blocking layer 4b is disposed on the common low step surface. An active layer 5 and a second semiconductor layer 3b are disposed sequentially on the high step surface of the first step 31a and the high step surface of the second step 31b. A positive current blocking layer 4a is disposed on the surface of the second semiconductor layer 3b located on the high step surface of the first step 31a. The positive current blocking layer 4a is provided with a groove 41 that penetrates to the surface of the second semiconductor layer 3b. A first current diffusion layer 6 is disposed on the surface of the second semiconductor layer 3b, and the first current diffusion layer 6 is in contact with the positive current blocking layer 4a. An etch barrier layer 7 is disposed on the surface of the first current diffusion layer 6; A second current diffusion layer A81 is disposed on the surface of the etch barrier layer 7; The second current diffusion layer B82 is disposed on the bottom surface of the groove 41; The second current diffusion layer C83 is disposed on the surface of the negative electrode current blocking layer 4b; A positive electrode pad 9a is disposed on the bottom surface of the groove 41 and is in contact with the second current diffusion layer B82 and the positive electrode current blocking layer 4a respectively. The negative electrode pad 9b is disposed on the surface of the common low step surface and is in contact with the second current diffusion layer C83 and the negative electrode current blocking layer 4b respectively. An insulating passivation layer 10 is disposed on the surface of the second current diffusion layer A81; Among them, the second current diffusion layer A81, the second current diffusion layer B82 and the second current diffusion layer C83 are all distributed with pit areas 84 that penetrate their respective surfaces.

[0047] In this embodiment, metal nanoparticles 85 are disposed on the upper surface of the second current diffusion layer A81, and metal nanoparticles 85 are embedded in the pit region 84 of the second current diffusion layer C83 by self-assembly. No metal nanoparticles 85 are disposed in the pit region 84 of the second current diffusion layer A81 or the second current diffusion layer B82. The remaining structures of this embodiment are the same as in Embodiment 1.

[0048] Example 4 Reference Figure 4 As shown, a light-emitting diode structure in this embodiment includes: Substrate 1; Buffer layer 2 is disposed on the surface of the substrate 1; A first semiconductor layer 3a is disposed on the surface of the buffer layer 2. The first semiconductor layer 3a is provided with a first step 31a and a second step 31b. The first step 31a and the second step 31b together include a common low step surface and a negative current blocking layer 4b is disposed on the common low step surface. An active layer 5 and a second semiconductor layer 3b are disposed sequentially on the high step surface of the first step 31a and the high step surface of the second step 31b. A positive current blocking layer 4a is disposed on the surface of the second semiconductor layer 3b located on the high step surface of the first step 31a. The positive current blocking layer 4a is provided with a groove 41 that penetrates to the surface of the second semiconductor layer 3b. A first current diffusion layer 6 is disposed on the surface of the second semiconductor layer 3b, and the first current diffusion layer 6 is in contact with the positive current blocking layer 4a. An etch barrier layer 7 is disposed on the surface of the first current diffusion layer 6; A second current diffusion layer A81 is disposed on the surface of the etch barrier layer 7; The second current diffusion layer B82 is disposed on the bottom surface of the groove 41; The second current diffusion layer C83 is disposed on the surface of the negative electrode current blocking layer 4b; A positive electrode pad 9a is disposed on the bottom surface of the groove 41 and is in contact with the second current diffusion layer B82 and the positive electrode current blocking layer 4a respectively. The negative electrode pad 9b is disposed on the surface of the common low step surface and is in contact with the second current diffusion layer C83 and the negative electrode current blocking layer 4b respectively. An insulating passivation layer 10 is disposed on the surface of the second current diffusion layer A81; Among them, the second current diffusion layer A81, the second current diffusion layer B82 and the second current diffusion layer C83 are all distributed with pit areas 84 that penetrate their respective surfaces.

[0049] In this embodiment, metal nanoparticles 85 are disposed on the lower surfaces of the second current diffusion layer A81, the second current diffusion layer B82, and the second current diffusion layer C83, while no metal nanoparticles 85 are disposed within their respective pit regions 84. The remaining structures of this embodiment are the same as those in Embodiment 1.

[0050] Example 5 Reference Figure 5 As shown, a light-emitting diode structure in this embodiment includes: Substrate 1; Buffer layer 2 is disposed on the surface of the substrate 1; A first semiconductor layer 3a is disposed on the surface of the buffer layer 2. The first semiconductor layer 3a is provided with a first step 31a and a second step 31b. The first step 31a and the second step 31b together include a common low step surface and a negative current blocking layer 4b is disposed on the common low step surface. An active layer 5 and a second semiconductor layer 3b are disposed sequentially on the high step surface of the first step 31a and the high step surface of the second step 31b. A positive current blocking layer 4a is disposed on the surface of the second semiconductor layer 3b located on the high step surface of the first step 31a. The positive current blocking layer 4a is provided with a groove 41 that penetrates to the surface of the second semiconductor layer 3b. A first current diffusion layer 6 is disposed on the surface of the second semiconductor layer 3b, and the first current diffusion layer 6 is in contact with the positive current blocking layer 4a. An etch barrier layer 7 is disposed on the surface of the first current diffusion layer 6; A second current diffusion layer A81 is disposed on the surface of the etch barrier layer 7; The second current diffusion layer B82 is disposed on the bottom surface of the groove 41; The second current diffusion layer C83 is disposed on the surface of the negative electrode current blocking layer 4b; A positive electrode pad 9a is disposed on the bottom surface of the groove 41 and is in contact with the second current diffusion layer B82 and the positive electrode current blocking layer 4a respectively. The negative electrode pad 9b is disposed on the surface of the common low step surface and is in contact with the second current diffusion layer C83 and the negative electrode current blocking layer 4b respectively. An insulating passivation layer 10 is disposed on the surface of the second current diffusion layer A81; Among them, the second current diffusion layer A81, the second current diffusion layer B82 and the second current diffusion layer C83 are all distributed with pit areas 84 that penetrate their respective surfaces.

[0051] In this embodiment, metal nanoparticles 85 are disposed on the lower surfaces of the second current diffusion layer A81, the second current diffusion layer B82, and the second current diffusion layer C83, and the metal nanoparticles 85 are embedded in their respective pit regions 84 by self-assembly. The remaining structures of this embodiment are the same as those in Embodiment 1.

[0052] Example 6 This embodiment provides a method for fabricating a light-emitting diode (LED) structure. Taking the structure of Embodiment 1 as an example, the method includes: S1. Provide an epitaxial wafer, wherein the epitaxial wafer includes a substrate 1, a buffer layer 2, a first semiconductor layer 3a, an active layer 5, and a second semiconductor layer 3b sequentially disposed therefrom; (Refer to...) Figure 6 As shown; S2. Fabricating Mesa steps, including fabricating a first step 31a and a second step 31b along the surface of the first semiconductor layer 3a on the epitaxial wafer, and fabricating a third step 31c at both ends, wherein the first step 31a and the second step 31b together include a common low step surface; refer to Figure 7 As shown; S3. A negative current blocking layer 4b is formed on the common low step surface, and a positive current blocking layer 4a is formed on the surface of the second semiconductor layer 3b on the high step surface of the first step 31a. The positive current blocking layer 4a is provided with a groove 41 that extends through to the surface of the second semiconductor layer 3b; Refer to Figure 8 As shown; S4. A film is deposited on the surface of the second semiconductor layer 3b, and then the film is subjected to rapid thermal annealing to form the first current diffusion layer 6. S5. An etch barrier layer 7 is coated on the surface of the first current diffusion layer 6. The etch barrier layer 7 is patterned in a local area using photolithography. Then, the local etch barrier layer 7 is removed using plasma etching technology, and wet etching is performed in this area to remove the local first current diffusion layer 6. (Refer to...) Figure 9 As shown; S6. A film is deposited on the surface of the first current diffusion layer 6, and a second current diffusion layer 8 is formed after rapid thermal annealing at 300~500℃. Next, the second current diffusion layer 8 is photolithographically etched and wet etching is used to remove localized parts of the second current diffusion layer 8. Then, a metal film is deposited and rapid thermal annealing at 500~650℃ is performed. S7. A pit region 84 penetrating the surface is formed in the second current diffusion layer 8, and metal nanoparticles 85 are embedded in the pit by self-assembly. S8. An insulating passivation layer 10 is formed on the surface of the second current diffusion layer 8, the insulating passivation layer 10 extending to the surface of the third step 31c; Refer to Figure 10 As shown; S9. A positive electrode pad 9a and a negative electrode pad 9b are fabricated respectively. The positive electrode pad 9a is disposed on the bottom surface of the groove 41 and contacts the second current diffusion layer 8 and the positive current blocking layer 4a respectively. The negative electrode pad 9b is disposed on the surface of the common low step surface and contacts the second current diffusion layer 8 and the negative current blocking layer 4b respectively. (Refer to...) Figure 11 As shown; S10. After grinding and thinning the side of the substrate 1 away from the buffer layer 2, a reflective mirror layer 11 is fabricated; refer to Figure 12 As shown.

[0053] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A light-emitting diode structure, characterized in that, include: Substrate; A buffer layer is disposed on the surface of the substrate; A first semiconductor layer is disposed on the surface of the buffer layer. The first semiconductor layer is provided with a first step and a second step. The first step and the second step together include a common low step surface and a negative current blocking layer is disposed on the common low step surface. An active layer and a second semiconductor layer are disposed sequentially on the high step surface of the first step and the high step surface of the second step. A positive current blocking layer is disposed on the surface of the second semiconductor layer located on the high step surface of the first step. The positive current blocking layer is provided with a groove that penetrates to the surface of the second semiconductor layer. A first current diffusion layer is disposed on the surface of the second semiconductor layer, and the first current diffusion layer is in contact with the positive current blocking layer; An etch barrier layer is disposed on the surface of the first current diffusion layer; A second current diffusion layer A is disposed on the surface of the etch barrier layer; A second current diffusion layer B is disposed on the bottom surface of the groove; The second current diffusion layer C is disposed on the surface of the negative electrode current blocking layer; A positive electrode pad is disposed on the bottom surface of the groove and is in contact with the second current diffusion layer B and the positive electrode current blocking layer, respectively. The negative electrode pad is disposed on the surface of the common low step surface and is in contact with the second current diffusion layer C and the negative electrode current blocking layer, respectively. An insulating passivation layer is disposed on the surface of the second current diffusion layer A; Among them, the second current diffusion layer A, the second current diffusion layer B and the second current diffusion layer C are all distributed with pit areas that penetrate their respective surfaces; Metal nanoparticles are disposed in or on the upper or lower surfaces of any one or more layers of the second current diffusion layer A, the second current diffusion layer B, and the second current diffusion layer C in the pit area.

2. The light-emitting diode structure according to claim 1, characterized in that, The metal nanoparticles are embedded in the pits through self-assembly.

3. The light-emitting diode structure according to claim 1, characterized in that, The structures of the metal nanoparticles include spheres, hemispheres, cylinders, and polyhedra.

4. A light-emitting diode structure according to claim 1, characterized in that, The size of the metal nanoparticles is 1~5 nm.

5. A light-emitting diode structure according to claim 1, characterized in that, The thickness of the first current diffusion layer is 2~10nm.

6. A light-emitting diode structure according to claim 1, characterized in that, The thicknesses of the second current diffusion layer A, the second current diffusion layer B, and the second current diffusion layer C are respectively between 20 and 200 nm.

7. A light-emitting diode structure according to claim 1, characterized in that, The etching barrier layer is made of graphene and consists of 1 to 5 layers.

8. A light-emitting diode structure according to claim 1, characterized in that, The first semiconductor layer has a third step on each of its two ends, and the insulating passivation layer extends from the surface of the second current diffusion layer A to the surfaces of the first step, the second step and the third step.

9. A light-emitting diode structure according to claim 1, characterized in that, A reflective layer is provided on the side of the substrate away from the buffer layer.

10. A method for fabricating a light-emitting diode structure, characterized in that, include: An epitaxial wafer is provided, wherein the epitaxial wafer comprises a substrate, a buffer layer, a first semiconductor layer, an active layer and a second semiconductor layer disposed sequentially; A first step and a second step are formed along the surface of the first semiconductor layer on the epitaxial wafer, and a third step is formed at both ends. The first step and the second step together include a common low step surface. A negative current blocking layer is formed on the common low step surface, and a positive current blocking layer is formed on the surface of the second semiconductor layer located on the high step surface of the first step. The positive current blocking layer is provided with a groove that extends to the surface of the second semiconductor layer. A film is deposited on the surface of the second semiconductor layer, and then the film is subjected to rapid thermal annealing to form a first current diffusion layer. An etch barrier layer is coated on the surface of the first current diffusion layer. The etch barrier layer is patterned in a local area by photolithography. Then, the local etch barrier layer is removed by plasma etching technology, and wet etching is performed in the area to remove the local first current diffusion layer. A second current diffusion layer is formed by depositing a film on the surface of the first current diffusion layer and then performing rapid thermal annealing at 300~500℃. Next, the second current diffusion layer is photolithographically etched and wet etching is used to remove localized portions of the second current diffusion layer. Subsequently, a metal film is deposited and then subjected to rapid thermal annealing at 500~650℃. A pit region penetrating the surface is created in the second current diffusion layer, and metal nanoparticles are embedded in the pits by self-assembly. An insulating passivation layer is formed on the surface of the second current diffusion layer, the insulating passivation layer extending to the surfaces of the first step, the second step and the third step; A positive electrode pad and a negative electrode pad are fabricated separately. The positive electrode pad is disposed on the bottom surface of the groove and is in contact with the second current diffusion layer and the positive current blocking layer, respectively. The negative electrode pad is disposed on the surface of the common low step surface and is in contact with the second current diffusion layer and the negative current blocking layer, respectively. The reflective layer is fabricated by grinding and thinning the side of the substrate away from the buffer layer.

Images