Discharge circuit and method for voltage transition management

Abstract

Discharge circuits and methods for voltage transition management are disclosed. In one embodiment, a method includes providing a voltage setpoint to a voltage converter, generating an output voltage at a voltage rail with the voltage converter based on the voltage setpoint, providing a first constant current to a first node coupled to a control terminal of an output transistor to turn on the output transistor when the voltage setpoint transitions from a first voltage setpoint to a second voltage setpoint having a lower magnitude than the first voltage setpoint, wherein the output transistor includes a source terminal coupled to a first terminal of a first resistor, and wherein a current path of the output transistor is coupled to the voltage rail, and turning off the output transistor after the output voltage reaches a target output voltage corresponding to the second voltage setpoint.

Description

Technical Field

[0001] This disclosure generally relates to electronic systems and methods, and in specific embodiments, to discharge circuits and methods for voltage transition management. Background Technology

[0002] DC-DC converters are widely used in many applications. Examples of DC-DC converters include non-inverting DC-DC converters, such as buck converters, boost converters, buck-boost converters, and flyback converters, as well as inverting DC-DC converters, such as inverting buck converters, inverting boost converters, and inverting buck-boost converters.

[0003] Some DC-DC converters can dynamically change their output voltage based on a received voltage setpoint. For example, a first voltage setpoint (which can be digital or analog) might indicate 5V. A second voltage setpoint might indicate 20V. Changing the voltage setpoint from the first voltage setpoint to the second voltage setpoint changes the DC-DC converter's output voltage from 5V to 20V.

[0004] In some applications, a rapid voltage transition is desired in the DC-DC converter's output as the voltage setpoint changes. Some DC-DC converters use discharge circuits to facilitate this rapid voltage transition during setpoint changes. For example, Figure 1 An exemplary non-inverting DC-DC converter 102 with a discharge circuit 104 is shown. When the voltage setpoint of the DC-DC converter 102 decreases (e.g., from 20V to 5V), the voltage Vg... 108 The low-to-high transition fully turns on transistor 108 and affects the output voltage V. outp Discharge to promote output voltage V outp The decrease. Once the output voltage V outp To achieve a new target (e.g., 5V), the voltage Vg 108 The voltage transitions from high to low to completely turn off transistor 108 and stop supplying power to the output voltage V. outp Discharge is performed.

[0005] Figure 2 An exemplary inverting DC-DC converter 202 with a discharge circuit 104 is shown. As the voltage setpoint of the DC-DC converter 102 increases (e.g., from -5V to -1V), the voltage Vg... 108 The low-to-high transition fully turns on transistor 108 and affects the output voltage V. outn Discharge to promote output voltage V outn The output voltage V increases. outn To achieve the new target (e.g., -1V), the voltage Vg 108The transition from high to low completely shuts off transistor 108 and stops supplying power to the output voltage V. outn Discharge is performed.

[0006] like Figure 2 As shown, resistor 106 is connected to the drain of transistor 108. Connecting a resistor to the drain of a transistor is a conventional way to connect a resistor (e.g., 106) load to a switch (e.g., 108), which advantageously allows all voltage drops to occur in the resistor (because the resistance of the resistive load is typically much higher than the resistance of the switch). Summary of the Invention

[0007] According to one embodiment, a method includes: providing a voltage setpoint to a voltage converter, wherein the voltage setpoint indicates a target output voltage of the voltage converter; generating an output voltage at a voltage rail using the voltage converter based on the voltage setpoint; providing a first constant current to a first node coupled to a control terminal of an output transistor to turn on the output transistor as the voltage setpoint transitions from a first voltage setpoint to a second voltage setpoint having a lower magnitude than the first voltage setpoint, wherein the output transistor includes a source terminal coupled to a first terminal of a first resistor and a drain terminal coupled to a first terminal of a load, wherein a second terminal of the first resistor is coupled to a second terminal of the load, and wherein a current path of the output transistor is coupled to the voltage rail; and turning off the output transistor after the output voltage reaches a target output voltage corresponding to the second voltage setpoint.

[0008] According to one embodiment, a circuit includes: a voltage converter having an output coupled to a voltage rail and configured to generate an output voltage at the output of the voltage converter based on a voltage setpoint, wherein the voltage setpoint indicates a target output voltage of the voltage converter; an output transistor having a current path coupled to the voltage rail; a first resistor having a first terminal coupled to a source terminal of the output transistor; and control circuitry configured to: provide a voltage setpoint to the voltage converter; when the voltage setpoint changes from a first voltage setpoint to a second voltage setpoint having a lower value than the first voltage setpoint, cause a first constant current to be provided to a first node coupled to a control terminal of the output transistor to turn on the output transistor; and cause the output transistor to turn off after the output voltage reaches a target output voltage corresponding to the second voltage setpoint.

[0009] According to one embodiment, a circuit includes: a voltage converter having an output coupled to a voltage rail and configured to generate an output voltage at the output of the voltage converter based on a voltage setpoint, wherein the voltage setpoint indicates a target output voltage of the voltage converter; an output transistor having a current path coupled to the voltage rail and a control terminal coupled to a first node; a first resistor having a first terminal coupled to a source terminal of the output transistor; a capacitor coupled to the first node; a first transistor having a current path coupled between a first power supply voltage terminal and the first node; and a first current mirror including a second transistor and a third transistor, the second transistor having a current path coupled between the first node and the first node. A current path between the second terminals of a resistor; a fourth transistor having a current path coupled between the first power supply voltage terminal and the current path of the third transistor; a fifth transistor having a current path coupled to the current path of the first transistor; a sixth transistor having a current path coupled to the current path of the fourth transistor; a current source configured to generate a bias current; a seventh transistor having a current path coupled to the current source and a control terminal coupled to the control terminals of the fifth and sixth transistors; and a control circuit configured to: provide a voltage setpoint to a voltage converter and control the first and fourth transistors based on the voltage setpoint. Attached Figure Description

[0010] To gain a more complete understanding of the invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 and Figure 2 An exemplary DC-DC converter with a discharge circuit is shown;

[0012] Figure 3 A schematic diagram of a power management circuit for generating a negative voltage rail according to an embodiment of the present invention is shown;

[0013] Figure 4 An embodiment according to the present invention is shown. Figure 3 The waveform of the power management circuit;

[0014] Figure 5 A schematic diagram of a power management circuit for generating a positive voltage rail according to an embodiment of the present invention is shown;

[0015] Figure 6 An embodiment according to the present invention is shown. Figure 5 The waveform of the power management circuit.

[0016] Unless otherwise specified, corresponding numbers and symbols in the different figures generally refer to corresponding parts. The figures are drawn to clearly illustrate relevant aspects of the preferred embodiments, and the figures are not necessarily drawn to scale. Detailed Implementation

[0017] The manufacture and use of the disclosed embodiments are discussed in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways of making and using the invention and do not limit the scope of the invention.

[0018] The following description illustrates various specific details to provide a thorough understanding of several exemplary embodiments according to the description. These embodiments may be obtained without one or more of these specific details, or by other methods, components, materials, etc. In other instances, known structures, materials, or operations are not shown or described in detail so as not to obscure different aspects of the embodiments. References to "embodiment" in this specification indicate that a particular configuration, structure, or feature described with respect to the embodiment is included in at least one embodiment. Therefore, phrases such as "in one embodiment" that may appear in different places in this specification do not necessarily refer exactly to the same embodiment. Furthermore, in one or more embodiments, specific formations, structures, or features may be combined in any suitable manner.

[0019] Embodiments of the invention will be described in a specific context (e.g., discharge circuits and methods for voltage shift management of the output of a DC-DC converter). Some embodiments can be used with other types of converters, such as AC / DC converters and linear converters.

[0020] In embodiments of the invention, a degraded output transistor is used to discharge the output voltage of the DC-DC converter during a transition of the voltage setpoint to a lower magnitude. In some embodiments, the gate of the output transistor is driven with a constant current to generate a corresponding linear voltage ramp at the gate and source terminals of the degraded transistor, thereby applying a discharge current with a controlled ramp to the output of the DC-DC converter during a transition of the voltage setpoint to a lower magnitude. By applying a discharge current with a controlled ramp to the output of the DC-DC converter, some embodiments advantageously avoid rapid changes in discharge current, thereby reducing or eliminating undesirable voltage variations in the output voltage of the DC-DC converter. In some embodiments, the output transistor remains off during a steady state of the output voltage, or as the magnitude of the output voltage increases, thereby advantageously reducing power consumption. In some embodiments, the activation and deactivation of the output transistor are controlled by the same controller that controls the voltage setpoint of the DC-DC converter.

[0021] Figure 3 A schematic diagram of a power management circuit 300 according to an embodiment of the present invention is shown. The power management circuit 300 provides a negative output voltage V to a load 370. outnIt includes a control circuit 360, an inverting DC-DC converter 350, and a discharge circuit 302. The discharge circuit 302 includes transistors 304, 306, 308, 310, 312, 314, 316, 318, 320, 322, 324, 326, 328, 330, 332, and 334, resistors 336 and 338, a Zener diode 340, a capacitor 342, and a current source 344.

[0022] In some embodiments, the inverting DC-DC converter 350 provides a negative voltage V. outn (Also known as the negative rail), where the negative voltage V outn The value depends on the voltage setpoint S provided by the control circuit 360. setpoint In some embodiments, the inverting DC-DC converter 350 can be implemented in any manner known in the art. For example, in some embodiments, the inverting DC-DC converter 350 can be implemented as an inverting buck converter, an inverting boost converter, or an inverting buck-boost converter. Other implementations are also possible.

[0023] In some embodiments, the inverting DC-DC converter 350 is capable of regulating the output voltage during transitions from a high voltage (e.g., -1V) to a low voltage (e.g., -9V). In some embodiments, the DC-DC converter 350 has a limited ability to regulate the output voltage during transitions from a low voltage (e.g., -9V) to a high voltage (-1V), and may, for example, rely on the load current to discharge the voltage.

[0024] Control circuit 360 provides voltage setpoint S to inverting DC-DC converter 350, for example, based on a request from an external controller (not shown). setpoint The control circuit 360 also controls the voltage Vg. 306 Vg 308 and Vg 310 To control the discharge circuit 302.

[0025] At negative voltage V outn When unchanged or under negative voltage V outn When transitioning to a lower voltage (e.g., from -1V to -9V), the control circuit 360 will adjust the voltage Vg. 310 Maintain a low voltage and set the voltage Vg 306 and Vg 308 Maintaining a high voltage keeps transistor 310 on and transistors 306 and 308 off. Transistor 310 being on causes transistor 330 to transfer current I... bias The image is the current I flowing through transistor 312. 310 Since transistors 312 and 314 form a current mirror (311), the current I... 310Mirrored as current I 314 It pulls down the voltage Vg 304 Because transistor 308 is turned off, the voltage Vg 304 The current is low and transistor 304 is turned off, so that no current flows through transistor 304 (I dis =0mA). Therefore, in some embodiments, at a negative voltage V outn When unchanged or under negative voltage V outn When switching to a lower voltage, transistor 304 does not negatively output voltage V. outn Discharge is performed.

[0026] At negative voltage V outn When transitioning to a higher voltage (e.g., from -9V to -1V), the control circuit will adjust the voltage Vg. 310 The voltage is increased to a high level to turn off transistor 310, and the voltage Vg is increased. 306 and Vg 308 The voltage is reduced to a low level to turn on transistors 306 and 308. Because transistor 306 is turned on, transistor 334 will draw current I. bias The image is the current I flowing through transistor 322. 306 Current I 306 The current I is mirrored by the current mirror 319 (formed by transistors 320 and 322). 320 Its pull-down voltage Vg 324 This causes transistor 324 to turn off.

[0027] Due to the negative voltage V outn When the voltage drops to a lower level, transistor 310 turns off, so the current I... 310 The voltage is zero, which turns off transistor 314. This is because of the negative voltage V... outn When the voltage drops to a lower level, transistor 308 turns on, so transistor 308 will transfer current I. bias The mirror image is current I 308 Its pull-up voltage Vg 304 To turn on transistor 304, for example by passing current I 308 A voltage ramp is created by injecting it into capacitor 342. Voltage Vg 304 The pull-up also turns on transistor 316, which allows current I to flow. 316 Pull-down voltage Vg 324 And this causes (e.g., in cooperation with transistor 320) transistor 324 to turn off and remain off. Figure 3 As shown, in some embodiments, a resistor (336) is connected to the source of transistor 316 to limit the current I. 316 .

[0028] like Figure 3As shown, in some embodiments, activation (conduction) of transistor 306 causes transistor 324 to pull up a voltage Vg on transistor 308. 304 The transistor is turned off at the same time, which advantageously prevents the transistor 324 from pulling up the voltage Vg on the transistor 308. 304 Pull-down voltage Vg 304 (For example, due to voltage Vg) 304 When the voltage Vg increases, transistor 316 turns on, therefore at voltage Vg 304 The pull-up initially cannot help keep transistor 324 off during the initial period.

[0029] After the negative output voltage reaches (e.g., stabilizes to) a new higher voltage (e.g., -1V), the control circuit 360 will adjust the voltage Vg. 310 Reduce to low level and reduce voltage Vg 306 and Vg 308 The voltage is raised to a high level to turn on transistor 310 and turn off transistors 306 and 308. The turning on of transistor 310 and the turning off of transistors 306 and 308 cause current I to rise. 314 Pull-down voltage Vg 304 For example, a voltage ramp is achieved by discharging capacitor 342 with a constant current.

[0030] In some embodiments, current source 344 generates bias current I. bias In some embodiments, the bias current I bias The value is chosen to be at a negative voltage V outn Allowable voltage Vg when switching to a lower voltage 304 The pull-up (e.g., within a predetermined time period), and the negative voltage V outn When unchanged or under negative voltage V outn Allowable voltage Vg when switching to a lower voltage 304 The pull-down (e.g., within a predetermined time period). In some embodiments, the current I bias It is constant during normal operation. In some embodiments, the current I... bias The current is lower when transistor 310 is on and transistors 306 and 308 are off than when transistor 310 is off and transistors 306 and 308 are on. This is achieved by maintaining current I when transistor 310 is on and transistors 306 and 308 are off. bias Lower, some embodiments at negative voltage V outn When unchanged or under negative voltage V outn Switching to a lower voltage has the advantage of reducing power consumption.

[0031] In some embodiments, the Zener diode 340 clamping voltage Vg 304 And prevent voltage Vg 304 Increase the voltage beyond the predetermined value.

[0032] In some embodiments, during normal operation, the negative voltage V outn It can operate between -9V and -1V, and the voltage V IN It can be between, for example, 2.5V and 5V, such as 3.3V. Other voltages can also be used.

[0033] In some embodiments, the power management circuitry 300 is part of a power management integrated circuit (PMIC) for powering an active-matrix organic light-emitting diode (AMOLED)-based display, wherein the load 370 includes multiple AMOLEDs. In such an embodiment, the control circuitry 360 may receive a request from a controller (not shown) to change the voltage setpoint of the DC-DC converter 350 to control the brightness of the AMOLED-based display.

[0034] In some embodiments, transistors 304, 306, 308, 310, 312, 314, 316, 318, 320, 322, 324, 326, 328, 330, 332, and 334 are MOSFETs. Figure 3 As shown, in some embodiments, transistors 304, 306, 308, and 310 are high-voltage transistors, while transistors 312, 314, 316, 318, 320, 322, 324, 326, 328, 330, 332, and 334 are low-voltage transistors. In some embodiments, using high-voltage transistors for transistors 304, 306, 308, and 310 advantageously allows support for a wide voltage range (e.g., V0). IN For example, 5V, and V outn For example, -9V), instead of using high-voltage transistors to implement all transistors, thus advantageously keeping the circuit size relatively small.

[0035] In some embodiments, transistor 328 serves as a power-off switch for completely shutting off discharge circuit 302 (e.g., controlled by control circuit 360). For example, in some embodiments, during the de-energization of discharge circuit 302, control circuit 360 turns on transistor 328, thereby turning off transistors 324, 330, 332, and 334, causing current I... 304 I 306 I 308 I 310 I 314 I 316 and I dis It is zero.

[0036] In some embodiments, the control circuit 360 may be implemented using a custom or general-purpose controller or processor, for example, configured to execute instructions stored in memory. In some embodiments, the control circuit 360 may be implemented using a state machine. Other implementations are also possible.

[0037] like Figure 3 As can be seen, pull-up circuits (including, for example, 344, 324, 332, 334, 308, 306) and pull-down circuits (including, for example, 344, 324, 330, 310, 312, 314) are current-driven, for example, to advantageously obtain a voltage Vg. 304 Controlled slope and avoidance of negative output voltage V outn Rapid current changes. For example, unlike discharge circuit 104 (which has resistor 106 connected to the drain of transistor 108), resistor 338 is connected to the source of transistor 304. At voltage Vg 304 During the pull-up period, transistor 304 begins to conduct, which causes the discharge current I to... dis The increase causes the source voltage Vs304 to increase. Therefore, in some embodiments, the gate-source voltage (Vgs) of transistor 304 remains (e.g., approximately) constant, and the voltage Vs 304 Follow voltage Vg 304 Therefore, in some embodiments, the voltage Vg 304 During the conduction period of transistor 304 (and during the conduction of constant current I) 314 During the turn-off period of transistor 304 discharging capacitor 342, it has a linear ramp shape (e.g., caused by a constant current I). 308 (Caused by charging capacitor 342), and voltage Vs 304 It also has a linear ramp shape during the turn-on period of transistor 304 (and during the turn-off period of transistor 304).

[0038] Figure 4 The waveform 400 of a power management circuit 300 according to an embodiment of the present invention is shown. Curve 402 represents a negative voltage V. outn Voltage setpoint S setpoint Curve 404 represents the negative output voltage V. outn (exist Figure 4 (In the embodiment, it matches curve 402). Curve 410 represents voltage Vg. 310 Curve 412 represents the voltage Vg. 306 Curve 414 represents the voltage Vg. 308 Curve 416 represents the voltage Vg. 304 Curve 418 represents the voltage Vs. 304 Curve 420 represents the discharge current I. dis .

[0039] As shown in curve 404, the control circuit 360 begins to increase the voltage setpoint at time t1. Figure 4 As shown, in some embodiments, the voltage setpoint is increased gradually, for example by a fixed voltage increment (e.g., 50 mV) every 15 μs (other voltage increments or time intervals are also possible), following a sequence starting from the initial voltage V. start to the termination voltage V end Steps (e.g., such as) Figure 4 As shown). In some embodiments, V start and V end These correspond to -9V and -1V respectively. Other voltages can also be used.

[0040] like Figure 4 As shown, at time t1, transistor 310 is off, transistors 306 and 308 are on, and voltage Vg 304 The pull-up process begins, causing the discharge current to increase at a controlled slope. In some embodiments, the discharge current I... dis The slope is higher than the voltage setpoint S setpoint The fastest slope. By making the discharge current I... dis The slope is higher than the voltage setpoint S setpoint The fastest slope, in some embodiments, is advantageously above the voltage setpoint S. setpoint The slope of the slope pulls up the negative output voltage V outn (For example, curve 406 will be followed in the absence of closed-loop operation of the DC-DC converter 350). Because the discharge current I dis Sufficient to reduce voltage V outn Pull up to above the voltage setpoint S setpoint The voltage, so the DC-DC converter 350 can adjust the output voltage V. outn This makes it similar to the voltage setpoint S. setpoint A match is found, as shown by curve 404.

[0041] like Figure 4 As shown, the discharge current I dis The slope of the curve is lower than the slope of the discharge current of the discharge circuit 104, which will pull up the negative output voltage V at a slope higher than that of curve 406. outn And without the closed-loop operation of the DC-DC converter 350, it will follow curve 408. This is achieved by controlling the discharge current I... dis The slope is kept relatively low, and some embodiments advantageously mitigate or avoid overshoot and undershoot occurring at times t1 and t2.

[0042] like Figure 4As shown, in some embodiments, at time t1, transistor 310 is turned off and transistors 306 and 308 are turned on. In some embodiments, after time t1 (e.g., slightly later), transistor 310 is turned off and transistors 306 and 308 are turned off.

[0043] Although the power management circuitry 300 has been described with respect to the inverting DC-DC converter 350, those skilled in the art will know how to adapt the power management circuitry 300 to operate with a non-inverting DC-DC converter that provides a positive voltage rail. For example, in some embodiments, the converter 350 may be implemented using a non-inverting DC-DC converter (e.g., buck, boost, or buck-boost) to produce a positive output voltage relative to ground, and the discharge circuitry 302 may be adapted to be activated during the transition from a high to a low voltage setpoint.

[0044] Figure 5 A schematic diagram of a power management circuit 500 according to an embodiment of the present invention is shown. The power management circuit 500 provides a positive output voltage V to a load 570. outp It includes a control circuit 560, a non-inverting DC-DC converter 550, and a discharge circuit 502. The discharge circuit 502 includes transistors 504, 506, 508, 510, 512, 514, 516, 518, and 520, a resistor 528, a Zener diode, a capacitor 524, and a current source 522.

[0045] The power management circuit 500 operates in a similar manner to the power management circuit 300. However, the power management circuit 500 generates a positive output voltage V. outp (Using a non-inverting DC-DC converter 550) instead of a negative output voltage V outn And in the positive output voltage V outp The discharge circuit 502 is activated when the voltage is switched to a lower voltage (e.g., from 20V to 5V) rather than during the switch to a higher voltage.

[0046] For example, under a positive voltage V outp When unchanged or under positive voltage V outp When transitioning to a higher voltage (e.g., from 5V to 20V), the control circuit 560 will adjust the voltage Vg. 508 Maintain a low voltage and reduce voltage Vg 506 Maintaining a high voltage keeps transistor 508 on and transistor 506 off. Transistor 508 being on causes transistor 512 to transfer current I... bias The image shows the current I flowing through transistor 518. 508 Since transistors 518 and 520 form a current mirror (517), the current I... 508 Mirrored as current I 520 This pulls down the voltage Vg504 This turns off transistor 504 and keeps it off (because transistor 506 is off).

[0047] Under positive voltage V outp When switching to a lower voltage (e.g., from 20V to 5V), the control circuit will adjust the voltage Vg. 508 The voltage is increased to a high level to turn off transistor 508, and the voltage Vg is increased. 506 The voltage is reduced to a low level to turn on transistor 506. With transistor 508 turned off, current I... 520 The current is zero. Because transistor 506 is turned on, transistor 510 will transfer current I... bias The mirror image is current I 506 This is, for example, by using current I 506 The voltage Vg is pulled up by injecting it into capacitor 524 and following the voltage ramp. 504 .

[0048] After the positive output voltage reaches (e.g., stabilizes to) a new lower voltage (e.g., 5V), the control circuit 560 will adjust the voltage Vg. 508 Reduce to low level and reduce voltage Vg 506 The voltage is raised to a high level to turn on transistor 508 and turn off transistor 506, thereby discharging capacitor 524 with a constant current to, for example, pull down voltage Vg by a voltage ramp. 504 .

[0049] In some embodiments, current source 522 operates in a similar manner to current source 344 and can be implemented in a similar manner to current source 344.

[0050] In some embodiments, the Zener diode 526 clamping voltage Vg 504 And prevent voltage Vg 504 Increase the voltage beyond the predetermined value.

[0051] In some embodiments, during normal operation, the positive voltage V outp It can be between 5V and 20V, and the voltage V IN It can be between 2.5V and 5V, such as 3.3V. Other voltages can also be used.

[0052] In some embodiments, the power management circuitry 500 is part of a USB source device for providing USB voltage rails (e.g., supporting voltages of 20V, 15V, 12V, 9V, and / or 5V), wherein the USB source device supports USB power delivery modes and is compatible with any USB standard (such as the USB 3.1 standard) in force as of the effective date of this application, and may include a reversible USB connector without a specific insertion orientation, such as those well known to those skilled in the art as Type-C.

[0053] In some embodiments, transistors 504, 506, 508, 510, 512, 514, 516, 518, and 520 are MOSFETs.

[0054] In some embodiments, transistor 514 serves as a power-off switch for completely shutting off discharge circuit 502 (e.g., controlled by control circuit 560). For example, in some embodiments, during the de-energization of discharge circuit 502, control circuit 560 turns on transistor 514, thereby turning off transistors 510, 512, and 516, causing current I... 506 I 508 I 520 and I dis It is zero.

[0055] In some embodiments, the control circuit 560 may be implemented using a custom or general-purpose controller or processor, for example, configured to execute instructions stored in memory. In some embodiments, the control circuit 560 may be implemented using a state machine. Other implementations are also possible.

[0056] As in Figure 5 As can be seen, and similar to power management circuit 300, pull-up circuits (including, for example, 522, 516, 510, and 506) and pull-down circuits (including, for example, 522, 516, 512, 508, 518, and 512) are current-driven, for example, to advantageously obtain voltage Vg. 504 Controlled slope and avoidance of positive output voltage V outp Rapid current changes on the circuit. For example, unlike discharge circuit 104 (which has resistor 106 connected to the drain of transistor 108), resistor 528 is connected to the source of transistor 504. At voltage Vg 504 During the pull-up period, transistor 504 begins to conduct, thereby causing the discharge current I... dis The increase causes the source voltage Vs to... 504 Increase. Therefore, in some embodiments, the gate-source voltage (Vgs) of transistor 504 remains (e.g., approximately) constant, and the voltage Vs 504 Follow voltage Vg 504 Therefore, in some embodiments, the voltage Vg 504 During the conduction period of transistor 504 (and during the passage of a constant current I) 520 During the discharge of capacitor 524 to turn off transistor 504, it has a linear ramp shape (e.g., caused by a constant current I). 506 (Caused by charging capacitor 524), and voltage Vs 504 It also has a linear ramp shape during the turn-on period of transistor 304 (and during the turn-off period of transistor 504).

[0057] Figure 6 The waveform 600 of a power management circuit 500 according to an embodiment of the present invention is shown. Curve 602 represents a positive voltage V. outp Voltage setpoint S setpoint Curve 604 represents the positive output voltage V. outp (exist Figure 6 (In the embodiment, it matches curve 602). Curve 608 represents voltage Vg. 508 Curve 610 represents the voltage Vg. 506 Curve 616 represents the voltage Vg. 604 Curve 618 represents the voltage Vs. 604 Curve 620 represents the discharge current I. dis .

[0058] As shown in curve 604, control circuit 560 begins to decrease the voltage setpoint at time t3. Figure 6 As shown, in some embodiments, the voltage setpoint is gradually decreased, for example by a fixed voltage decrease (e.g., 50 mV) every 15 μs (other voltage decreases or time intervals are also possible), following a decrease from the initial voltage V. start to the termination voltage V end Steps (e.g., such as) Figure 6 As shown). In some embodiments, V start and V end These correspond to 20V and 5V respectively. Other voltages can also be used.

[0059] like Figure 6 As shown, at time t3, transistor 508 is off, transistor 506 is on, and voltage Vg 504 The pull-up process begins, causing the discharge current to increase at a controlled slope. In some embodiments, the discharge current I... dis The slope ratio of the voltage setpoint S setpoint The fastest slope is steeper. By making the discharge current I... dis The slope ratio of the voltage setpoint S setpoint The fastest slope is steeper, and some embodiments advantageously use a slope higher than the voltage setpoint S. setpoint A steeper slope pulls down the positive output voltage V. outp (For example, curve 506 will be followed in the absence of closed-loop operation of the DC-DC converter 550). Due to the discharge current I dis Sufficient to reduce voltage V outp Pull down below voltage setpoint S setpoint The voltage, so the DC-DC converter 550 can adjust the output voltage V. outp This makes it consistent with the voltage setpoint S setpointA match is found, as shown by curve 604.

[0060] like Figure 6 As shown, the discharge current I dis The slope of the discharge current is not as steep as that of the discharge circuit 104, which will pull down the positive output voltage V with a steeper slope than that of curve 606. outp And it will follow curve 608 without the closed-loop operation of the DC-DC converter 550. By maintaining the discharge current I dis The slope is not too steep, and some embodiments advantageously mitigate or avoid overshoot and undershoot occurring at times t3 and t4.

[0061] like Figure 6 As shown, in some embodiments, at time t3, transistor 508 is turned off and transistor 506 is turned on. In some embodiments, after time t3 (e.g., slightly later), transistor 508 is turned off and transistor 506 is turned off.

[0062] Although the power management circuitry 500 has been described with respect to the non-inverting DC-DC converter 550, those skilled in the art know how to adapt the power management circuitry 500 to operate with an inverting DC-DC converter that provides a negative voltage rail. For example, in some embodiments, the converter 550 may be implemented with an inverting DC-DC converter (e.g., an inverting buck, inverting boost, or inverting buck-boost) to produce a negative output voltage relative to ground, and the discharge circuitry 502 may be adapted to be activated during the transition from a low to a high voltage setpoint.

[0063] Some embodiments offer advantages including providing an accurate voltage output (e.g., negative or positive) that tracks the voltage setpoint during positive and negative transitions, while reducing or eliminating overshoot and undershoot, for example, at the beginning of a voltage transition (e.g., at V). start ) and end (e.g., V) end During this period, some embodiments advantageously achieve accurate voltage output without significantly increasing power consumption, for example by keeping the discharge circuit off during the steady state or when the amplitude at the voltage setpoint increases, and turning the discharge circuit on when the amplitude at the voltage setpoint decreases.

[0064] Exemplary embodiments of the invention are outlined herein. Other embodiments may also be understood from the entirety of the description and claims submitted herein.

[0065] Example 1. A method comprising: providing a voltage setpoint to a voltage converter, wherein the voltage setpoint indicates a target output voltage of the voltage converter; generating an output voltage at a voltage rail using the voltage converter based on the voltage setpoint; as the voltage setpoint transitions from a first voltage setpoint to a second voltage setpoint having a lower magnitude than the first voltage setpoint, providing a first constant current to a first node coupled to a control terminal of an output transistor to turn on the output transistor, wherein the output transistor includes a source terminal coupled to a first terminal of a first resistor and a drain terminal coupled to a first terminal of a load, wherein a second terminal of the first resistor is coupled to a second terminal of the load, and wherein a current path of the output transistor is coupled to a voltage rail; and turning off the output transistor after the output voltage reaches a target output voltage corresponding to the second voltage setpoint.

[0066] Example 2. According to the method of Example 1, wherein turning off the output transistor includes providing a second constant current to the first node, wherein the second constant current has the opposite direction to the first constant current.

[0067] Example 3. According to one of Examples 1 or 2, providing a first constant current to the first node includes: injecting a first constant current into a capacitor coupled to the first node, and providing a second constant current to the first node includes: absorbing a second constant current from the capacitor.

[0068] Example 4. A method according to one of Examples 1 to 3, wherein providing a first constant current includes providing a first constant current using a first transistor having a current path coupled between a first power supply voltage terminal and a first node, and wherein providing a second constant current includes using a second transistor having a current path coupled between the first node and a second terminal of the first resistor.

[0069] Example 5. According to one of Examples 1 to 4, wherein turning off the output transistor includes turning off the first transistor and turning on the third transistor having a current path coupled between the first power supply voltage terminal and the current path of the fourth transistor, the fourth transistor and the second transistor forming a first current mirror.

[0070] Example 6. According to one of Examples 1 to 5, the method further includes turning off a fifth transistor having a current path coupled between the first node and the second terminal of the first resistor when the first transistor is turned on.

[0071] Example 7. According to one of Examples 1 to 6, turning off the fifth transistor includes turning on a sixth transistor having a current path coupled to a second current mirror, the second current mirror being coupled to a control terminal of the fifth transistor.

[0072] Example 8. According to one of Examples 1 to 7, the seventh transistor includes a control terminal coupled to the first node and a current path coupled between the control terminal of the fifth transistor and the second resistor.

[0073] Example 9. According to one of Examples 1 to 8, wherein providing a first constant current to the first node results in a first voltage ramp at the first node and a second voltage ramp at the source terminal of the output transistor.

[0074] Example 10. According to one of Examples 1 to 9, the voltage setpoint is changed from a first voltage setpoint to a second voltage setpoint in discrete voltage steps.

[0075] Example 11. According to one of Examples 1 to 10, wherein the load includes an active matrix organic light-emitting diode (AMOLED).

[0076] Example 12. A method according to one of Examples 1 to 11, wherein generating an output voltage includes generating a negative output voltage.

[0077] Example 13. According to one of Examples 1 to 12, wherein the first voltage setpoint corresponds to -9V and the second voltage setpoint corresponds to -1V.

[0078] Example 14. According to one of Examples 1 to 13, wherein the second terminal of the first resistor is coupled to a voltage rail.

[0079] Example 15. According to one of Examples 1 to 14, wherein a Zener diode is coupled between the control terminal of the output transistor and the second terminal of the first resistor.

[0080] Example 16. A method according to one of Examples 1 to 15, wherein generating an output voltage includes generating a positive output voltage.

[0081] Example 17. According to one of Examples 1 to 16, wherein the first voltage setpoint corresponds to 20V and the second voltage setpoint corresponds to 5V.

[0082] Example 18. According to one of Examples 1 to 17, the drain terminal of the output transistor is coupled to a voltage rail.

[0083] Example 19. A circuit comprising: a voltage converter having an output coupled to a voltage rail and configured to generate an output voltage at the output of the voltage converter based on a voltage setpoint, wherein the voltage setpoint indicates a target output voltage of the voltage converter; an output transistor having a current path coupled to the voltage rail; a first resistor having a first terminal coupled to a source terminal of the output transistor; and control circuitry configured to: provide a voltage setpoint to the voltage converter; cause a first constant current to be provided to a first node of a control terminal of the output transistor to turn on the output transistor as the voltage setpoint transitions from a first voltage setpoint to a second voltage setpoint having a lower amount than the first voltage setpoint; and cause the output transistor to turn off after the output voltage reaches a target output voltage corresponding to the second voltage setpoint.

[0084] Example 20. The circuit according to Example 19 further includes: a capacitor coupled to a first node; a first transistor having a current path coupled between a first power supply voltage terminal and the first node; and a second transistor having a current path coupled between the first node and a second terminal of a first resistor, wherein the control circuit is configured to provide a first constant current to the first node by turning on the first transistor and turning off the second transistor, and wherein the control circuit is configured to turn off the output transistor by turning off the first transistor and turning on the second transistor.

[0085] Example 21. A circuit according to one of Examples 19 or 20, further comprising: a first current mirror including a second transistor and a third transistor; and a fourth transistor having a current path coupled between a first power supply voltage terminal and a current path of the third transistor, wherein the control circuit is configured to turn on the second transistor by turning on the fourth transistor.

[0086] Example 22. A circuit according to one of Examples 19 to 21 further includes: a fifth transistor having a current path coupled between a first node and a second terminal of a first resistor, wherein a control circuit is configured to turn off the fifth transistor when the first transistor is turned on.

[0087] Example 23. A circuit according to one of Examples 19 to 22, further comprising: a second current mirror including a sixth transistor and a seventh transistor, the seventh transistor having a current path coupled to a control terminal of a fifth transistor; and an eighth transistor having a current path coupled to the current path of the sixth transistor, wherein the control circuit is configured to turn off the fifth transistor by turning on the eighth transistor.

[0088] Example 24. A circuit according to one of Examples 19 to 23, further comprising: a ninth transistor having a current path coupled between a control terminal of a fifth transistor and a second terminal of a first resistor; and a second resistor coupled between the current path of the ninth transistor and the second terminal of the first resistor.

[0089] Example 25. A circuit according to one of Examples 19 to 24 further includes a Zener diode coupled between the first node and the second terminal of the first resistor.

[0090] Example 26. A circuit based on one of Examples 19 to 25, wherein the voltage converter is a DC-DC converter.

[0091] Example 27. A circuit based on one of Examples 19 to 26, wherein the DC-DC converter is an inverting DC-DC converter.

[0092] Example 28. A circuit based on one of Examples 19 to 27, wherein the DC-DC converter is a non-inverting DC-DC converter.

[0093] Example 29. A circuit comprising: a voltage converter having an output coupled to a voltage rail and configured to generate an output voltage at the output of the voltage converter based on a voltage setpoint, wherein the voltage setpoint indicates a target output voltage of the voltage converter; an output transistor having a current path coupled to the voltage rail and a control terminal coupled to a first node; a first resistor having a first terminal coupled to a source terminal of the output transistor; a capacitor coupled to the first node; a first transistor having a current path coupled between a first power supply voltage terminal and the first node; a first current mirror including a second transistor and a third transistor, the second transistor having a current path coupled between the first node and the first power supply voltage terminal. A current path between the second terminals of the resistor; a fourth transistor having a current path coupled between the first power supply voltage terminal and the current path of the third transistor; a fifth transistor having a current path coupled to the current path of the first transistor; a sixth transistor having a current path coupled to the current path of the fourth transistor; a current source configured to generate a bias current; a seventh transistor having a current path coupled to the current source and a control terminal coupled to the control terminals of the fifth and sixth transistors; and a control circuit configured to: provide a voltage setpoint to the voltage converter and control the first and fourth transistors based on the voltage setpoint.

[0094] Example 30. The circuit according to Example 29 further includes: an eighth transistor having a current path coupled between a first node and a second terminal of a first resistor; a ninth transistor having a control terminal coupled to the first node and a current path coupled to the control terminal of the eighth transistor; a second current mirror having a tenth transistor and an eleventh transistor, the tenth transistor having a current path coupled to the control terminal of the eighth transistor; a twelfth transistor having a current path coupled to the current path of the eleventh transistor; and a thirteenth transistor having a current path coupled to the current path of the eleventh transistor and a control terminal coupled to the control terminals of the fifth, sixth, and seventh transistors, wherein the control circuit is further configured to control the twelfth transistor based on a voltage setpoint.

[0095] Although the invention has been described with reference to illustrative embodiments, this description is not intended to be limited in meaning. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art after the description has been presented. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A method for voltage transformation management, comprising: Provide a voltage setpoint to the voltage converter, wherein the voltage setpoint indicates the target output voltage of the voltage converter; Based on the voltage setpoint, the voltage converter generates an output voltage at the voltage rail; When the voltage setpoint transitions from a first voltage setpoint to a second voltage setpoint having a lower value than the first voltage setpoint, a first constant current is provided to a first node coupled to a control terminal of the output transistor to turn on the output transistor, wherein the output transistor includes a source terminal coupled to a first terminal of a first resistor and a drain terminal coupled to a first terminal of a load, wherein a second terminal of the first resistor is coupled to a second terminal of the load, and wherein the current path of the output transistor is coupled to the voltage rail; as well as When the voltage setpoint changes from the first voltage setpoint to the second voltage setpoint, the fifth transistor, which has a current path coupled between the first node and the second terminal of the first resistor, is turned off. When the voltage setpoint transitions from the first voltage setpoint to the second voltage setpoint, a seventh transistor is turned on. This seventh transistor includes a control terminal coupled to the first node, and the current path of the seventh transistor is coupled between the control terminal of the fifth transistor and the voltage rail. The output transistor is turned off after the output voltage reaches the target output voltage corresponding to the second voltage set point.

2. The method of claim 1, wherein turning off the output transistor comprises providing a second constant current to the first node, wherein the second constant current has a direction opposite to the first constant current.

3. The method of claim 2, wherein providing the first constant current to the first node comprises: Injecting the first constant current into a capacitor coupled to the first node, and wherein providing the second constant current to the first node includes: absorbing the second constant current from the capacitor.

4. The method of claim 3, wherein providing the first constant current includes providing the first constant current using a first transistor having a current path coupled between a first power supply voltage terminal and the first node, and wherein providing the second constant current includes using a second transistor having a current path coupled between the first node and a second terminal of the first resistor.

5. The method of claim 4, wherein turning off the output transistor comprises turning off the first transistor and turning on a third transistor, the third transistor having a current path coupled between the first power supply voltage terminal and a current path of a fourth transistor, the fourth transistor and the second transistor forming a first current mirror.

6. The method of claim 5, wherein turning off the fifth transistor includes turning on a sixth transistor having a current path coupled to a second current mirror coupled to a control terminal of the fifth transistor, and wherein the seventh transistor is coupled to a current path between the control terminal of the fifth transistor and a second resistor.

7. The method of claim 1, wherein providing the first constant current to the first node results in a first voltage ramp at the first node and a second voltage ramp at the source terminal of the output transistor.

8. The method of claim 1, wherein the voltage setpoint transitions from the first voltage setpoint to the second voltage setpoint in discrete voltage steps.

9. The method of claim 1, wherein generating the output voltage includes generating a negative output voltage, and wherein the first voltage setpoint corresponds to -9V and the second voltage setpoint corresponds to -1V.

10. The method of claim 1, wherein the second terminal of the first resistor is coupled to the voltage rail.

11. The method of claim 1, wherein generating the output voltage includes generating a positive output voltage, and wherein the first voltage setpoint corresponds to 20V and the second voltage setpoint corresponds to 5V.

12. The method of claim 1, wherein the drain terminal of the output transistor is coupled to the voltage rail.

13. A circuit comprising: A voltage converter having an output coupled to a voltage rail and configured to generate an output voltage at the output of the voltage converter based on a voltage setpoint, wherein the voltage setpoint indicates a target output voltage of the voltage converter; The output transistor has a current path coupled to the voltage rail; A first resistor having a first terminal coupled to the source terminal of the output transistor; as well as The fifth transistor has a current path coupled between the first node and the second terminal of the first resistor; The ninth transistor has a current path coupled between the control terminal of the fifth transistor and the second terminal of the first resistor; The control circuit is configured as follows: The voltage setpoint is provided to the voltage converter; When the voltage setpoint transitions from a first voltage setpoint to a second voltage setpoint having a lower value than the first voltage setpoint, a first constant current is provided to the first node coupled to the control terminal of the output transistor to turn on the output transistor. When the voltage setpoint changes from the first voltage setpoint to the second voltage setpoint, the fifth transistor is turned off; When the voltage set point changes from the first voltage set point to the second voltage set point, the ninth transistor is turned on; as well as The output transistor is turned off after the output voltage reaches the target output voltage corresponding to the second voltage setpoint.

14. The circuit of claim 13, further comprising: A capacitor is coupled to the first node; The first transistor has a current path coupled between the first power supply voltage terminal and the first node; as well as The second transistor has a current path coupled between the first node and the second terminal of the first resistor, wherein the control circuit is configured to provide the first constant current to the first node by turning on the first transistor and turning off the second transistor, and wherein the control circuit is configured to turn off the output transistor by turning off the first transistor and turning on the second transistor.

15. The circuit of claim 14, further comprising: The first current mirror includes the second transistor and the third transistor; as well as The fourth transistor has a current path coupled between the first power supply voltage terminal and the current path of the third transistor, wherein the control circuit is configured to turn on the second transistor by turning on the fourth transistor.

16. The circuit of claim 13, further comprising: The second current mirror includes a sixth transistor and a seventh transistor, the seventh transistor having a current path coupled to the control terminal of the fifth transistor; as well as The eighth transistor has a current path coupled to the current path of the sixth transistor, wherein the control circuit is configured to turn off the fifth transistor by turning on the eighth transistor.

17. The circuit of claim 16, further comprising: A second resistor is coupled between the current path of the ninth transistor and the second terminal of the first resistor.

18. The circuit of claim 13, wherein the voltage converter is an inverting DC-DC converter.

19. A circuit comprising: A voltage converter having an output coupled to a voltage rail and configured to generate an output voltage at the output of the voltage converter based on a voltage setpoint, wherein the voltage setpoint indicates a target output voltage of the voltage converter; The output transistor has a current path coupled to the voltage rail and a control terminal coupled to the first node; A first resistor having a first terminal coupled to the source terminal of the output transistor; A capacitor is coupled to the first node; The first transistor has a current path coupled between the first power supply voltage terminal and the first node; A first current mirror includes a second transistor and a third transistor, the second transistor having a current path coupled between the first node and a second terminal of the first resistor; The fourth transistor has a current path coupled between the first power supply voltage terminal and the current path of the third transistor; The fifth transistor has a current path coupled to the current path of the first transistor; The sixth transistor has a current path coupled to the current path of the fourth transistor; A current source is configured to generate a bias current; The seventh transistor has a current path coupled to the current source and a control terminal coupled to the current source and to the control terminals of the fifth and sixth transistors; as well as The eighth transistor has a current path coupled between the first node and the second terminal of the first resistor; The ninth transistor has a control terminal coupled to the first node and a current path coupled to the control terminal of the eighth transistor; The control circuit is configured as follows: Provide the voltage setpoint to the voltage converter. The first transistor and the fourth transistor are controlled based on the voltage setpoint.

20. The circuit of claim 19, further comprising: The second current mirror has a tenth transistor and an eleventh transistor, the tenth transistor having a current path coupled to the control terminal of the eighth transistor; The twelfth transistor has a current path coupled to the current path of the eleventh transistor; as well as The thirteenth transistor has a current path coupled to the current path of the eleventh transistor, and a control terminal coupled to the control terminals of the fifth, sixth, and seventh transistors, wherein the control circuit is further configured to control the twelfth transistor based on the voltage setpoint.

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