Misadjustment cancellation circuit, misadjustment cancellation method, and switching power supply

Abstract

The application provides a kind of unbalance elimination circuit, unbalance elimination method and switching power supply, wherein current generation module generates output current, and the common action of first current mirror module and second current mirror module copies and proportionally processes output current into different size currents, then digital control module generates control signal based on the output result of summation comparator, and sends control signal to correction module, correction module selects correction current from the multiple size currents generated by first current mirror module and second current mirror module under the action of control signal, and corrects direct current unbalance in summation comparator through correction current.The unbalance elimination circuit of the application can correct the direct current unbalance of summation comparator before soft start, and can effectively avoid error correction circuit working in clamping state in low power consumption state, so as to greatly improve the output accuracy and transient response of COT under no load.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, and more specifically, to an offset cancellation circuit, an offset cancellation method, and a switching power supply. Background Technology

[0002] The DC-DC Current-Mode One Cycle Control (COT) architecture is a controller design architecture for switching power supplies. Its key feature is that it can control the stability and accuracy of the power supply output waveform in a single cycle, allowing the power supply to better adapt to different workloads and input voltage variations, thus improving efficiency and reliability.

[0003] Due to the influence of FB half-ripple error in the power supply and the non-ideal factors of the summing comparator, the traditional DC-DC COT architecture introduces an error correction circuit to eliminate the above error effects.

[0004] However, when the error correction circuit operates in clamped mode, it limits the amplitude range of the input signal, thereby limiting the output signal to a certain range. This leads to a decrease in the sensitivity of the circuit, resulting in poor no-load accuracy and transient response. Summary of the Invention

[0005] The purpose of this application is to address the shortcomings of the prior art by providing an offset cancellation circuit, an offset cancellation method, and a switching power supply to solve the problem of poor accuracy and transient response of the COT architecture under no-load conditions in the prior art.

[0006] To achieve the above objectives, the technical solution adopted in this application is as follows:

[0007] In a first aspect, this application provides an offset cancellation circuit, which includes: a current generation module, a first current mirror module, a second current mirror module, a digital control module, and a correction module, wherein:

[0008] The first end of the first current mirror module and the first end of the second current mirror module are respectively connected to the output end of the current generating module; the second end of the first current mirror module is connected to the second end of the second current mirror, the third end of the first current mirror is connected to the first input end of the correction module, and the third end of the second current mirror is connected to the second input end of the correction module.

[0009] The third input terminal of the correction module is connected to the output terminal of the digital control module, and the output terminal of the correction module is used to connect to a summation comparator.

[0010] The first input terminal of the current generation module is connected to the first terminal of the second current mirror, the second input terminal of the current generation module is used to connect to the reference voltage, and the current generation module is used to generate an output current and send the output current to the first current mirror module and the second current mirror module.

[0011] The input terminal of the digital control module is used to connect to the summation comparator, and the digital control module is used to send a control signal to the correction module according to the output result of the summation comparator;

[0012] The correction module is used to control the output current of the first current mirror module and the output current of the second current mirror module under the action of the control signal, and output a correction current to the summation comparator accordingly.

[0013] Optionally, the calibration module includes: a first switching field-effect transistor, a second switching field-effect transistor, a third switching field-effect transistor, a fourth switching field-effect transistor, a fifth switching field-effect transistor, a sixth switching field-effect transistor, a seventh switching field-effect transistor, an eighth switching field-effect transistor, a ninth switching field-effect transistor, and a tenth switching field-effect transistor;

[0014] The source of the first switching field-effect transistor, the source of the second switching field-effect transistor, the source of the third switching field-effect transistor, and the source of the fourth switching field-effect transistor are connected to the third terminal of the first current mirror module. The drain of the first switching field-effect transistor, the drain of the second switching field-effect transistor, the drain of the third switching field-effect transistor, and the drain of the fourth switching field-effect transistor are connected to the source of the fifth switching field-effect transistor and the source of the tenth switching field-effect transistor.

[0015] The source of the sixth, seventh, eighth, and ninth switching field-effect transistors is connected to the third terminal of the second current mirror module, and the drain of the sixth, seventh, eighth, and ninth switching field-effect transistors is connected to the source of the fifth and tenth switching field-effect transistors.

[0016] The gates of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, and tenth switching field-effect transistors are respectively connected to the output terminal of the digital control module.

[0017] Optionally, the drain of the tenth switching field-effect transistor, the drain of the fifth switching field-effect transistor, and the input terminal of the summation comparator are connected.

[0018] Optionally, the current generating module includes: an operational amplifier and a first field-effect transistor;

[0019] One input terminal of the operational amplifier is connected to the first terminal of the second current mirror, the second input terminal of the operational amplifier is used to connect to a reference voltage, and the output terminal of the operational amplifier is connected to the gate of the first field-effect transistor.

[0020] The drain of the first field-effect transistor is connected to the first end of the first current mirror module, and the source of the first field-effect transistor is connected to the first end of the second current mirror.

[0021] Optionally, the first current mirror module includes a first self-biasing unit and a first proportional adjustment unit, and the second current mirror module includes a second self-biasing unit and a second proportional adjustment unit.

[0022] The first end of the first self-biasing unit is connected to the output end of the current generating module, the second end of the first self-biasing unit is connected to the second end of the second self-biasing unit, and the third end of the first self-biasing unit is connected to the first end of the first proportional adjustment unit.

[0023] The second end of the first proportional adjustment unit is connected to the first input end of the correction module;

[0024] The first end of the second self-biasing unit is connected to the output end of the current generating module, and the third end of the second self-biasing unit is connected to the first end of the second proportional adjustment unit.

[0025] The second end of the second proportional adjustment unit is connected to the second input end of the correction module.

[0026] Optionally, the first self-biasing unit includes: a first resistor, a second field-effect transistor, a third field-effect transistor, a fourth field-effect transistor, a fifth field-effect transistor, a sixth field-effect transistor, and a seventh field-effect transistor;

[0027] The gates of the second field-effect transistor, the third field-effect transistor, and the fourth field-effect transistor are connected in series and connected to the first end of the first proportional adjustment unit; the gates of the fifth field-effect transistor, the sixth field-effect transistor, and the seventh field-effect transistor are connected in series and connected to the first end of the first proportional adjustment unit.

[0028] The gates of the second field-effect transistor and the third field-effect transistor are also connected to one end of the first resistor, and the other end of the first resistor is connected to the output terminal of the current generation module.

[0029] The source of the second field effect transistor, the source of the third field effect transistor and the source of the fourth field effect transistor are all connected to a power supply, the drain of the second field effect transistor is connected to the source of the fifth field effect transistor, the drain of the third field effect transistor is connected to the source of the sixth field effect transistor, the drain of the fourth field effect transistor is connected to the source of the seventh field effect transistor, and the gate of the fifth field effect transistor and the gate of the sixth field effect transistor are connected to the other end of the first resistor;

[0030] The drain of the sixth field effect transistor, the drain of the seventh field effect transistor are connected to the second end of the second self-biasing unit.

[0031] Optionally, the second self-biasing unit comprises an eighth field effect transistor, a ninth field effect transistor, a tenth field effect transistor, an eleventh field effect transistor, a twelfth field effect transistor and a second resistor;

[0032] Wherein, the drain of the eighth field effect transistor is connected to the drain of the sixth field effect transistor, the source of the eighth field effect transistor is connected to the drain of the ninth field effect transistor, the source of the ninth field effect transistor is connected to the drain of the tenth field effect transistor, and the gate of the eighth field effect transistor, the gate of the ninth field effect transistor, the gate of the tenth field effect transistor, the gate of the eleventh field effect transistor and the first end of the second proportional adjustment unit are connected;

[0033] The drain of the eleventh field effect transistor is connected to the drain of the seventh field effect transistor, the source of the eleventh field effect transistor is connected to the drain of the twelfth field effect transistor, the source of the twelfth field effect transistor and the source of the tenth field effect transistor are grounded, and the gate of the twelfth field effect transistor, the drain of the eleventh field effect transistor and the first end of the second proportional adjustment unit are connected;

[0034] One end of the second resistor is connected to the output end of the current generation module, and the other end of the second resistor is grounded.

[0035] Optionally, the first proportional adjustment unit comprises a plurality of groups of first proportional adjustment branches, each first proportional adjustment branch comprises a first common-source field effect transistor and a first common-gate field effect transistor, the source of the first common-source field effect transistor is connected to a power supply, the drain of the first common-source field effect transistor is connected to the source of the first common-gate field effect transistor, and the drain of the first common-gate field effect transistor is connected to the first input end of the correction module;

[0036] The gates of the first common-source field effect transistors in each of the first proportional adjustment branches are connected in series and connected to the third end of the first self-biasing unit, and the gates of the first common-gate field effect transistors in each of the first proportional adjustment branches are connected in series and connected to the third end of the first self-biasing unit.

[0037] Optionally, the second proportional adjustment circuit includes multiple sets of second proportional adjustment branches, each of which includes a second common-source field-effect transistor and a second common-gate field-effect transistor. The source of the second common-source field-effect transistor is grounded, the drain of the second common-source field-effect transistor is connected to the source of the second common-gate field-effect transistor, and the drain of the second common-gate field-effect transistor is connected to the second input terminal of the correction module.

[0038] The gates of the second common-source field-effect transistors in each of the second proportional adjustment branches are connected in series and connected to the third terminal of the second self-biasing unit. The gates of the second common-gate field-effect transistors in each of the second proportional adjustment branches are connected in series and connected to the third terminal of the second self-biasing unit.

[0039] Secondly, this application provides an offset cancellation method applied to the offset cancellation circuit described in the first aspect above, the method comprising:

[0040] The current generation module generates an output current, and the output current is converted into different magnitudes of output current through the first current mirror module and the second current mirror module;

[0041] The digital control module sends a control signal to the correction module based on the output of the summation comparator;

[0042] The correction module controls the output current of the first current mirror module and the output current of the second current mirror module under the action of the control signal, and outputs a correction current to the summation comparator to correct the DC offset of the summation comparator.

[0043] Thirdly, this application provides a switching power supply including the offset cancellation circuit described in the first aspect above.

[0044] The beneficial effects of this application are as follows: The offset cancellation circuit of this application can correct the DC offset of the summing comparator before soft-start, and can effectively avoid the error correction circuit from operating in a clamped state under low power consumption, thus greatly improving the output accuracy and transient response of the COT under no-load conditions. Furthermore, the first and second current mirror modules in this application can generate currents of different magnitudes, thus enabling more precise control of the correction current and improving the accuracy of the current and the precision of the correction. Attached Figure Description

[0045] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 A schematic diagram of the architecture of an offset cancellation circuit provided in an embodiment of this application is shown;

[0047] Figure 2 This illustration shows a structural schematic diagram of a correction module in an offset cancellation circuit provided in an embodiment of this application;

[0048] Figure 3 This illustration shows a schematic diagram of the current generation module in an offset cancellation circuit provided in an embodiment of this application;

[0049] Figure 4 This paper shows a schematic diagram of the structure of a first current mirror module and a second current mirror module in an offset cancellation circuit provided in an embodiment of this application;

[0050] Figure 5 This illustration shows a schematic diagram of the structure of a first self-biasing unit in a first current mirror module according to an embodiment of this application;

[0051] Figure 6 This illustration shows a schematic diagram of the structure of a first self-biasing unit and a second self-biasing unit provided in an embodiment of this application;

[0052] Figure 7 This paper shows a schematic diagram of the structure of a first proportional adjustment unit provided in an embodiment of this application;

[0053] Figure 8 This paper shows a schematic diagram of the structure of a second proportional adjustment unit provided in an embodiment of this application;

[0054] Figure 9 This illustration shows a structural diagram of an offset cancellation circuit current generation module, a first current mirror module, a second current mirror module, and a correction module provided in an embodiment of this application.

[0055] Figure 10 This paper shows a schematic diagram of the structure of a digital control circuit for offset cancellation provided in an embodiment of this application;

[0056] Figure 11 A flowchart of an imbalance elimination method provided in an embodiment of this application is shown. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the accompanying drawings in this application are for illustrative and descriptive purposes only and are not intended to limit the scope of protection of this application. Furthermore, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate operations implemented according to some embodiments of this application. It should be understood that the operations in the flowcharts may not be implemented in sequence, and steps without logical contextual relationships may be reversed or implemented simultaneously. In addition, those skilled in the art, guided by the content of this application, may add one or more other operations to the flowcharts, or remove one or more operations from the flowcharts.

[0058] Furthermore, the described embodiments are merely some, not all, of the embodiments of this application. The components of the embodiments of this application described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0059] It should be noted that the term "comprising" will be used in the embodiments of this application to indicate the presence of the features declared thereafter, but does not exclude the addition of other features.

[0060] In existing technologies, error correction circuits are introduced to eliminate errors caused by non-ideal factors in the DC-DC COT architecture. However, when the chip is in an idle state, the error correction circuit operates in a clamped state. Clamping is a controllable switch that can limit the amplitude or range of a signal in the circuit. In error correction circuits, clamping is typically used to limit the amplitude of the input signal to ensure the stability and accuracy of the output signal. However, when the error correction circuit operates in clamped state, it limits the amplitude range of the input signal, thus keeping the output signal within a certain limited range.

[0061] Specifically, the no-load accuracy decreases because the clamp trims the input signal, resulting in a certain error between the output signal and the input signal. Poor transient response is mainly due to the clamp limiting the signal, which slows down the circuit's response speed and makes the response curve less smooth. This leads to a slower response to rapidly changing signals, resulting in output signal errors or instability.

[0062] It is evident that the error correction circuit operating in clamped state will reduce the circuit's sensitivity, and due to the error in the output voltage, the chip's no-load accuracy and transient response will be poor in no-load conditions.

[0063] Therefore, improving the transient response and accuracy of the DC-DC COT architecture under no-load conditions has become an urgent problem to be solved.

[0064] Based on the above problems, this application proposes an offset cancellation circuit, which corrects the DC offset of the summing comparator before soft start, thereby avoiding the error correction circuit from operating in a clamped state in low power mode, and greatly improving the output accuracy and transient response of the COT architecture under no-load conditions.

[0065] Next, combine Figure 1 The given schematic diagram further illustrates the offset cancellation circuit of this application, which can be applied to the summation comparator 105.

[0066] like Figure 1 As shown, the offset cancellation circuit of this application includes: a current generation module 100, a first current mirror module 101, a second current mirror module 102, a digital control module 104, and a correction module 103, wherein:

[0067] The first end of the first current mirror module 101 and the first end of the second current mirror module 102 are respectively connected to the output end of the current generating module 100; the second end of the first current mirror module 101 is connected to the second end of the second current mirror; the third end of the first current mirror is connected to the first input end of the correction module 103; and the third end of the second current mirror is connected to the second input end of the correction module 103.

[0068] Optionally, the first current mirror module 101 and the second current mirror module 102 can together form a complete current mirror, wherein the first current mirror module 101 is connected to the power supply and the second current mirror module 102 is grounded. The first current mirror module 101 and the second current mirror module 102 work together to realize the replication of the current and proportionally change its size.

[0069] The third input terminal of the correction module 103 is connected to the output terminal of the digital control module 104, and the output terminal of the correction module 103 is used to connect to the summation comparator 105.

[0070] As one possible implementation, the correction module 103 in this application can be connected to the summation comparator 105 as the output terminal of the offset elimination circuit. In this case, under the control signal generated by the digital control module 104, the correction module 103 can output a correction current based on the correction current generated in the first current mirror module 101 and the second current mirror module 102 to obtain the corrected voltage, and output the corrected voltage to the summation comparator 105 to realize the correction of the DC offset of the summation comparator 105.

[0071] As another possible implementation, the offset cancellation circuit in this application can also work as a separate module. In this case, the offset cancellation circuit can correct the DC offset in the circuit, obtain the corrected voltage, and output it to other modules.

[0072] The first input terminal of the current generation module 100 is connected to the first terminal of the second current mirror, the second input terminal of the current generation module 100 is used to connect to the reference voltage, and the current generation module 100 is used to generate an output current and send the output current to the first current mirror module 101 and the second current mirror module 102.

[0073] Optionally, the current generation module 100 can generate an output current and send the output current to the first current mirror module 101 and the second current mirror module 102, so that the first current mirror module 101 and the second current mirror module 102 can replicate and proportionally change the size of the output current to provide the current required for correction to the correction module 103.

[0074] The input terminal of the digital control module 104 is used to connect to the summation comparator 105, and the digital control module 104 is used to send control signals to the correction module 103 according to the output result of the summation comparator 105.

[0075] Optionally, the input terminal of the digital control module 104 can be connected to the output terminal of the summation comparator 105 to obtain the current magnitude in the summation comparator 105, and determine the magnitude of the correction current required to correct the DC offset of the summation comparator 105 based on the current magnitude in the summation comparator 105, so as to send a control signal to the correction module 103.

[0076] Optionally, the input signals of the digital control module 104 may include a CLK signal and an enable signal. The CLK signal may be provided by an oscillator circuit connected to the digital control module 104. Under the combined action of the CLK signal and the enable signal, the digital control module 104 may generate a control signal based on the output result of the summation comparator 105 and send the control signal to the correction module 103.

[0077] The correction module 103 is used to control the output current of the first current mirror module 101 and the output current of the second current mirror module 102 under the action of the control signal, and outputs the correction current to the summation comparator 105 accordingly.

[0078] It is worth noting that this application only uses the DC offset of the summation comparator 105 as an example for illustration. Those skilled in the art can also connect the output of the offset elimination circuit of this application to other modules and use the output of the module as the input of the digital control module 104 to correct the DC offset of the module. This application only provides an example of correcting the DC offset in the summation comparator 105, and other implementations are not limited here.

[0079] In this embodiment, the current generation module 100 generates an output current. The output current is copied and proportionally processed into different magnitudes by the combined action of the first current mirror module 101 and the second current mirror module 102. Subsequently, the digital control module 104 generates a control signal based on the output result of the summation comparator 105 and sends the control signal to the correction module 103. Under the action of the control signal, the correction module 103 selects a correction current from the various magnitudes of current generated by the first current mirror module 101 and the second current mirror module 102, and corrects the DC offset in the summation comparator 105 through the correction current.

[0080] The offset cancellation circuit of this application can correct the DC offset of the summing comparator before soft-start, and can effectively prevent the error correction circuit from operating in a clamped state under low power consumption, thus greatly improving the output accuracy and transient response of the COT under no-load conditions. Furthermore, the first and second current mirror modules in this application can generate currents of different magnitudes, thus enabling more precise control of the correction current and improving the accuracy of the current and the precision of the correction.

[0081] The following is a further description of the internal structure of the correction module 103 in this application, such as Figure 2 As shown, the correction module 103 of this application includes: a first switching field-effect transistor DB0, a second switching field-effect transistor DB1, a third switching field-effect transistor DB2, a fourth switching field-effect transistor DB3, a fifth switching field-effect transistor DB4, a sixth switching field-effect transistor D0, a seventh switching field-effect transistor D1, an eighth switching field-effect transistor D2, a ninth switching field-effect transistor D3, and a tenth switching field-effect transistor D4.

[0082] Among them, the first switching field-effect transistor DB0, the second switching field-effect transistor DB1, the third switching field-effect transistor DB2, and the fourth switching field-effect transistor DB3 can be NMOS, and the sixth switching field-effect transistor D0, the seventh switching field-effect transistor D1, the eighth switching field-effect transistor D2, and the ninth switching field-effect transistor D3 can be PMOS. The NMOS and PMOS can be in one-to-one correspondence, that is, the number of NMOS and the number of PMOS are the same.

[0083] The source of the first switching field-effect transistor DB0, the source of the second switching field-effect transistor DB1, the source of the third switching field-effect transistor DB2, and the source of the fourth switching field-effect transistor DB3 are connected to the third terminal of the first current mirror module 101. The drain of the first switching field-effect transistor DB0, the drain of the second switching field-effect transistor DB1, the drain of the third switching field-effect transistor DB2, and the drain of the fourth switching field-effect transistor DB3 are connected to the source of the fifth switching field-effect transistor DB4 and the source of the tenth switching field-effect transistor D4.

[0084] The source of the sixth switching field-effect transistor D0, the source of the seventh switching field-effect transistor D1, the source of the eighth switching field-effect transistor D2, and the source of the ninth switching field-effect transistor D3 are connected to the third terminal of the second current mirror module 102. The drain of the sixth switching field-effect transistor D0, the drain of the seventh switching field-effect transistor D1, the drain of the eighth switching field-effect transistor D2, and the drain of the ninth switching field-effect transistor D3 are connected to the source of the fifth switching field-effect transistor DB4 and the source of the tenth switching field-effect transistor D4.

[0085] It is worth noting that the fifth switching field-effect transistor DB4 and the tenth switching field-effect transistor D4 in this application can be composed of an NMOS and a PMOS. The source of the NMOS transistor is connected to the drain of the first switching field-effect transistor DB0, the drain of the second switching field-effect transistor DB1, the drain of the third switching field-effect transistor DB2, and the drain of the fourth switching field-effect transistor DB3. The source of the PMOS transistor is connected to the drain of the sixth switching field-effect transistor D0, the drain of the seventh switching field-effect transistor D1, the drain of the eighth switching field-effect transistor D2, and the drain of the ninth switching field-effect transistor D3.

[0086] Optionally, in the fifth switching field-effect transistor DB4 and the tenth switching field-effect transistor D4, the drains of the NMOS and PMOS are connected and connected to the ECON and ICAL terminals. The ECON and ICAL terminals can be connected as the output terminals of the correction module 103 and the input terminals of the summing comparator 105 to provide the corrected voltage to the summing comparator 105, so as to realize the DC offset correction of the summing comparator 105.

[0087] The gates of the first switching field-effect transistor DB0, the second switching field-effect transistor DB1, the third switching field-effect transistor DB2, the fourth switching field-effect transistor DB3, the fifth switching field-effect transistor DB4, the sixth switching field-effect transistor D0, the seventh switching field-effect transistor D1, the eighth switching field-effect transistor D2, the ninth switching field-effect transistor D3, and the tenth switching field-effect transistor D4 are respectively connected to the output terminal of the digital control module 104.

[0088] Optionally, the digital control module 104 can be connected to the gates of the first switching field-effect transistor DB0, the second switching field-effect transistor DB1, the third switching field-effect transistor DB2, the fourth switching field-effect transistor DB3, the fifth switching field-effect transistor DB4, the sixth switching field-effect transistor D0, the seventh switching field-effect transistor D1, the eighth switching field-effect transistor D2, the ninth switching field-effect transistor D3, and the tenth switching field-effect transistor D4, respectively, to control the conduction of the switching field-effect transistors according to the control signal sent by the digital control module 104, so as to obtain a correction current indicating the magnitude of the control signal.

[0089] In the fifth switching field-effect transistor DB4 and the tenth switching field-effect transistor D4 of this application, the gates of the NMOS and PMOS can both be connected to the output terminal of the digital control module 104.

[0090] The drain of the tenth switching field-effect transistor D4, the drain of the fifth switching field-effect transistor DB4, and the input of the summation comparator 105 are connected.

[0091] Optional, refer to Figure 2 The drains of the tenth switching field-effect transistor D4 and the fifth switching field-effect transistor DB4 can be used as the output terminals of the offset cancellation circuit of this application, namely the ECON and ICAL terminals in the figure, and connected to the input terminal of the summation comparator 105.

[0092] It is worth noting that the number of switching effect transistors in this application can be the same as the current quantity after proportional scaling of the first current mirror module 101 and the second current mirror module 102. For example, assuming that the current magnitude generated by the first current mirror module 101 and the second current mirror module 102 includes five types, then... Figure 2 The structure of the correction module 103 shown can be adjusted so that if the number of currents after the first current mirror module 101 and the second current mirror module 102 are scaled up or down proportionally, the number of switching field-effect transistors in the correction module 103 can be increased or decreased accordingly.

[0093] The current generation module 100 in this application will be described next, such as... Figure 3As shown, the current generation module 100 of this application includes an operational amplifier and a first field-effect transistor M1.

[0094] One input terminal of the operational amplifier is connected to the first terminal of the second current mirror, the second input terminal of the operational amplifier is used to connect to the reference voltage, and the output terminal of the operational amplifier is connected to the gate of the first field-effect transistor M1.

[0095] The drain of the first field-effect transistor M1 is connected to the first terminal of the first current mirror module 101, and the source of the first field-effect transistor M1 is connected to the first terminal of the second current mirror.

[0096] In this application, the reference voltage is converted into output current through an operational amplifier and a first field-effect transistor M1, and the first field-effect transistor M1 can achieve constant current and improve the stability of output current.

[0097] Optional, refer to Figure 3 The operational amplifier in the diagram forms an op-amp clamp. By adding a clamping circuit, the output voltage of the amplifier can be kept within the correct level of its power supply, avoiding output limitation. When the amplifier output exceeds the power supply range of the clamping circuit, it will be clipped, ensuring that the voltage is always kept within an appropriate range. In this way, the offset cancellation circuit can more effectively eliminate offsets such as bias and gain offset, improving the accuracy and stability of the circuit.

[0098] The structure of the first current mirror module 101 of this application will be described next, as follows: Figure 4 As shown, the first current mirror module 101 includes a first self-biasing unit 1011 and a first proportional adjustment unit 1012, and the second current mirror module 102 includes a second self-biasing unit 1021 and a second proportional adjustment unit 1022.

[0099] The first end of the first self-biasing unit 1011 is connected to the output end of the current generating module 100, the second end of the first self-biasing unit 1011 is connected to the second end of the second self-biasing unit 1021, and the third end of the first self-biasing unit 1011 is connected to the first end of the first proportional adjustment unit 1012.

[0100] The second end of the first proportional adjustment unit 1012 is connected to the first input end of the correction module 103.

[0101] The first end of the second self-biasing unit 1021 is connected to the output end of the current generating module 100, and the third end of the second self-biasing unit 1021 is connected to the first end of the second proportional adjustment unit 1022.

[0102] The second end of the second proportional adjustment unit 1022 is connected to the second input end of the correction module 103.

[0103] Optionally, the first current mirror module 101 and the second current mirror module 102 together form the current mirror circuit in this application. The first self-biasing unit 1011 and the second self-biasing unit 1021 are connected to form the self-biasing circuit in the current mirror circuit formed by the first current mirror module 101 and the second current mirror module 102, which is used to generate bias current and transmit the generated bias current to the first proportional adjustment unit 1012 and the second proportional adjustment unit 1022 respectively.

[0104] Optionally, the first proportional adjustment unit 1012 can convert the current transmitted by the first self-biasing unit 1011 into multiple currents of different magnitudes and transmit them to the correction module 103 via different branches.

[0105] Reference Figure 2 The correction module 103 includes ten switching field-effect transistors, wherein the first switching field-effect transistor DB0, the second switching field-effect transistor DB1, the third switching field-effect transistor DB2 and the fourth switching field-effect transistor DB3 respectively control the conduction or disconnection of the current of a branch. Therefore, the number of branches can correspond to the number of switching field-effect transistors.

[0106] It should be noted that in this application, the first self-biasing unit 1011 and the first proportional adjustment unit 1012 are connected to a power supply, while the second self-biasing unit 1021 and the second proportional adjustment unit 1022 are grounded.

[0107] like Figure 5 The diagram shown is a structural schematic of the first self-biasing unit 1011 provided in this application. (Refer to...) Figure 5 The first self-biasing unit 1011 includes: a first resistor R1, a second field-effect transistor M2, a third field-effect transistor M3, a fourth field-effect transistor M4, a fifth field-effect transistor M5, a sixth field-effect transistor M6, and a seventh field-effect transistor M7.

[0108] Among them, the second field-effect transistor M2, the third field-effect transistor M3, the fourth field-effect transistor M4, the fifth field-effect transistor M5, the sixth field-effect transistor M6, and the seventh field-effect transistor M7 are all NMOS transistors. The second field-effect transistor M2, the third field-effect transistor M3, and the fourth field-effect transistor M4 are common-source field-effect transistors, while the fifth field-effect transistor M5, the sixth field-effect transistor M6, and the seventh field-effect transistor M7 are common-gate field-effect transistors.

[0109] The gates of the second field-effect transistor M2, the third field-effect transistor M3, and the fourth field-effect transistor M4 are connected in series and connected to the first terminal of the first proportional adjustment unit 1012. The gates of the fifth field-effect transistor M5, the sixth field-effect transistor M6, and the seventh field-effect transistor M7 are connected in series and connected to the first terminal of the first proportional adjustment unit 1012.

[0110] The gates of the second field-effect transistor M2 and the third field-effect transistor M3 are also connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to the output terminal of the current generation module 100.

[0111] The sources of the second field-effect transistor M2, the third field-effect transistor M3, and the fourth field-effect transistor M4 are all connected to the power supply. The drain of the second field-effect transistor M2 is connected to the source of the fifth field-effect transistor M5. The drain of the third field-effect transistor M3 is connected to the source of the sixth field-effect transistor M6. The drain of the fourth field-effect transistor M4 is connected to the source of the seventh field-effect transistor M7. The gates of the fifth field-effect transistor M5 and the sixth field-effect transistor M6 are connected to the other end of the first resistor R1.

[0112] The drain of the sixth field-effect transistor M6, the drain of the seventh field-effect transistor M7, and the second terminal of the second self-biasing unit 1021 are connected.

[0113] like Figure 6 The diagram shown is a structural schematic of the second self-biasing unit 1021 provided in this application. (Refer to...) Figure 6 The second self-biasing unit 1021 includes an eighth field-effect transistor M8, a ninth field-effect transistor M9, a tenth field-effect transistor M10, an eleventh field-effect transistor M11, a twelfth field-effect transistor M12, and a second resistor R2.

[0114] Among them, the drain of the eighth field-effect transistor M8 is connected to the drain of the sixth field-effect transistor M6, the source of the eighth field-effect transistor M8 is connected to the drain of the ninth field-effect transistor M9, the source of the ninth field-effect transistor M9 is connected to the drain of the tenth field-effect transistor M10, and the gates of the eighth field-effect transistor M8, the ninth field-effect transistor M9, the tenth field-effect transistor M10, the eleventh field-effect transistor M11, and the first terminal of the second proportional adjustment unit 1022 are connected.

[0115] The drain of the eleventh field-effect transistor M11 is connected to the drain of the seventh field-effect transistor M7, the source of the eleventh field-effect transistor M11 is connected to the drain of the twelfth field-effect transistor M12, the source of the twelfth field-effect transistor M12 is grounded to the source of the tenth field-effect transistor M10, and the gate of the twelfth field-effect transistor M12, the drain of the eleventh field-effect transistor M11, and the first terminal of the second proportional adjustment unit 1022 are connected.

[0116] One end of the second resistor R2 is connected to the output terminal of the current generating module 100, and the other end of the second resistor R2 is grounded.

[0117] Optionally, the first self-biasing unit 1011 and the second self-biasing unit 1021 can jointly form a biasing circuit and generate a bias current, which is then transmitted to the first proportional adjustment unit 1012 and the second proportional adjustment unit 1022 to generate currents of different magnitudes.

[0118] In this embodiment, the operational amplifier clamping in the current generation module 100 can make the voltage drop across the second resistor R2 a reference voltage. The reference voltage is divided by the resistance, thereby generating a current across the resistor. The generated current passes through the first self-biasing unit 1011 and the second self-biasing unit 1021, and is transmitted to the first proportional adjustment unit 1012 and the second proportional adjustment unit 1022. Different magnitudes of correction current are generated proportionally. Then, the correction module 103 controls the switching of the switching field-effect transistor to conduct the correction current of the same magnitude as indicated by the control signal, and uses the correction current to correct the DC offset.

[0119] Next, combine Figure 7 The first proportional adjustment unit 1012 in this application will be described as follows: Figure 7 As shown, the first proportional adjustment unit 1012 includes multiple sets of first proportional adjustment branches. Each first proportional adjustment branch includes a first common-source field-effect transistor and a first common-gate field-effect transistor. The source of the first common-source field-effect transistor is connected to the power supply, the drain of the first common-source field-effect transistor is connected to the source of the first common-gate field-effect transistor, and the drain of the first common-gate field-effect transistor is connected to the first input terminal of the correction module 103.

[0120] Reference Figure 7 The figure includes four sets of first proportional adjustment branches. Each set of first proportional adjustment branches includes two NMOS transistors, of which the first common source field-effect transistors include S1, S2, S3 and S4, and the first common gate field-effect transistors include G1, G2, G3 and G4.

[0121] The gates of the first common-source field-effect transistors in each of the first proportional adjustment branches are connected in series and connected to the third terminal of the first self-biasing unit 1011. The gates of the first common-gate field-effect transistors in each of the first proportional adjustment branches are connected in series and connected to the third terminal of the first self-biasing unit 1011.

[0122] Reference Figure 7 The gates of the first common-source field-effect transistors in each of the first proportional adjustment units 1012 are connected in series and are connected to the gates of the second field-effect transistor M2, the third field-effect transistor M3 and the fourth field-effect transistor M4 in the first self-biasing unit 1011. The gates of the first common-gate field-effect transistors in each of the first proportional adjustment units 1012 are connected in series and are connected to the gates of the fifth field-effect transistor M5, the sixth field-effect transistor M6 and the seventh field-effect transistor M7 in the first self-biasing unit 1011.

[0123] The following is a further explanation of the second proportional adjustment unit 1022 mentioned above, such as... Figure 8As shown, the second proportional adjustment circuit includes multiple sets of second proportional adjustment branches. Each second proportional adjustment branch includes a second common-source field-effect transistor and a second common-gate field-effect transistor. The source of the second common-source field-effect transistor is grounded, the drain of the second common-source field-effect transistor is connected to the source of the second common-gate field-effect transistor, and the drain of the second common-gate field-effect transistor is connected to the second input terminal of the correction module 103.

[0124] Reference Figure 8 The figure includes four sets of second proportional adjustment branches. Each set of second proportional adjustment branches includes two PMOS transistors, of which the second common source field-effect transistors include K1, K2, K3 and K4, and the second common gate field-effect transistors include Q1, Q2, Q3 and Q4.

[0125] The gates of the second common-source field-effect transistors in each of the second proportional adjustment branches are connected in series and connected to the third terminal of the second self-biasing unit 1021. The gates of the second common-gate field-effect transistors in each of the second proportional adjustment branches are connected in series and connected to the third terminal of the second self-biasing unit 1021.

[0126] Reference Figure 8 The gates of the second common-source field-effect transistors in each of the second proportional adjustment units 1022 are connected in series and to the gates of the eighth field-effect transistor M8, the ninth field-effect transistor M9, the tenth field-effect transistor M10, and the eleventh field-effect transistor M11 in the second self-biasing unit 1021. The gates of the second common-gate field-effect transistors in each of the second proportional adjustment branches are connected in series and to the gate of the twelfth field-effect transistor M12 in the second self-biasing unit 1021.

[0127] Optionally, the source of each second common-gate field-effect transistor in the second proportional adjustment unit 1022 is grounded, and the source of each first common-source field-effect transistor in the first proportional adjustment unit 1012 is connected to the power supply.

[0128] like Figure 9 and Figure 10 The diagram shown is a schematic diagram of the offset cancellation circuit provided in this application, wherein... Figure 9 The offset elimination circuit includes a current generation module 100, a first current mirror module 101, a second current mirror module 102, and a correction module 103. Figure 10 The given module is the digital control module 104 for the offset cancellation circuit.

[0129] Reference Figure 9When the offset cancellation circuit starts working, the operational amplifier clamps the voltage drop across the second resistor R2 on the lower left side to the reference voltage. The reference voltage is divided by the resistance, thus generating a current across the resistor. This current is then mirrored proportionally by the first current mirror module 101 to generate a correction current. The ratio of DB3:DB2:DB1:DB0 is 8:4:2:1, where DB3 is the most significant bit, controlling a current of magnitude I, and DB0 is the least significant bit, controlling a current of magnitude I / 8. DB3, DB2, DB1, and DB0 control the PMOS-based switch, while D3, D2, D1, and D0 control the NMOS-based switch. The directions of DB3, DB2, DB1, and DB0 are opposite to those of D3, D2, D1, and D0.

[0130] Reference Figure 10 The output terminal ENOUT of the summation comparator 105 is connected to the input terminal of Mux so that Mux can determine the switching field-effect transistor that needs to be turned on based on the output result of the summation comparator 105.

[0131] The CLK signal is generated by an oscillator circuit. Figure 10 The bottommost input signal is CLK. When the falling edge of CLK arrives, the CLK signal passes through digital logic to the D flip-flop. The EN signal enables the CLK signal of the D flip-flop, making it low. The output signals of the D flip-flop are sent to the register, outputting signals D4, D3, D2, D1, and D0, and connected to the gates of the corresponding field-effect transistors in the correction module 103. After passing through an inverter, DB4, DB3, DB2, DB1, and DB0 are obtained and connected to the gates of the corresponding field-effect transistors in the correction module 103. The D4 signal, based on the voltage difference between ECON and ICAL, controls the polarity of the output voltage by controlling the direction of the current in the control resistor R0, thereby determining the offset correction direction. The switching field-effect transistors D3, D2, D1, and D0 correct the offset voltage in different steps according to the magnitude of the voltage difference between ECON and ICAL. After 6.5 complete CLK signals, the offset correction ends.

[0132] This application also provides an imbalance elimination method, applied to the above-mentioned... Figure 9 and Figure 10 The offset cancellation circuit shown below will be combined with... Figure 11 The method for eliminating imbalance in this application will be further explained.

[0133] S1101: The current generation module generates an output current and converts the output current into different magnitudes through the first current mirror module and the second current mirror module.

[0134] Optional, refer to Figure 9The current generation module 100 uses an operational amplifier to clamp the voltage drop across the second resistor R2 to a reference voltage Vref. The reference voltage is divided by the resistance, thereby generating a current across the second resistor. The current is then converted into different magnitudes of output current through the first current mirror module 101 and the second current mirror module 102.

[0135] Reference Figure 9 The first current mirror module 101 and the second current mirror module 102 convert the output current into four different sizes of output current. Taking the first current mirror module 101 as an example, the output currents of DB3, DB2, DB1 and DB0 are I / 8, I / 4, I / 2 and I, respectively.

[0136] S1102: The digital control module sends a control signal to the correction module based on the output of the summation comparator.

[0137] Optional, refer to Figure 10 The output of the summation comparator 105 can be connected to the digital control module 104. The digital control module 104 can then automatically determine the required correction current based on the output of the summation comparator 105, and... Figure 10 The logic circuit in the digital control module sends a control signal to the correction module 103 to turn the switching field-effect transistors in the first current mirror module 101 and the second current mirror module 102 on or off.

[0138] S1102: Under the action of the control signal, the correction module controls the output current of the first current mirror module and the output current of the second current mirror module, and outputs the correction current to the summation comparator to correct the DC offset of the summation comparator.

[0139] Optionally, after receiving the control signal, the correction module 103 can control the switching field-effect transistors in the first current mirror module 101 and the second current mirror module 102 to turn on or off under the action of the control signal, so as to generate a correction current of the magnitude indicated by the control signal.

[0140] For example, assuming that the digital control module 104 determines that the required current is I / 8 based on the output of the summation comparator 105, the digital control module 104 can send a control signal to the correction module 103. The correction module 103 will then turn on the fourth switching field-effect transistor DB3 and the fifth switching field-effect transistor DB4 under the action of the control signal to output the corresponding correction current.

[0141] It is worth noting that, Figure 9 The switching MOSFETs DB<3:0> and D<3:0> are used to control the generation of correction currents of different magnitudes, while DB4 and D4 are used to control the direction of the generated correction currents.

[0142] This application also provides a switching power supply, which includes the offset cancellation circuit described in this application.

[0143] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the circuit described above can be referred to the corresponding process in the foregoing embodiments, and will not be repeated here. In the several embodiments provided in this application, it should be understood that the disclosed offset cancellation circuit and switching power supply can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection can be through some communication interfaces; the indirect coupling or communication connection of devices or modules can be electrical, mechanical, or other forms.

[0144] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. An offset cancellation circuit, characterized in that, The offset cancellation circuit includes: a current generation module, a first current mirror module, a second current mirror module, a digital control module, and a correction module, wherein: The first end of the first current mirror module and the first end of the second current mirror module are respectively connected to the output end of the current generating module; the second end of the first current mirror module is connected to the second end of the second current mirror module, and the third end of the first current mirror module is connected to the first input end of the correction module; the third end of the second current mirror module is connected to the second input end of the correction module. The third input terminal of the correction module is connected to the output terminal of the digital control module, and the output terminal of the correction module is used to connect to a summation comparator. The first input terminal of the current generation module is connected to the first terminal of the second current mirror module, the second input terminal of the current generation module is used to connect to the reference voltage, and the current generation module is used to generate an output current and send the output current to the first current mirror module and the second current mirror module. The input terminal of the digital control module is used to connect to the summation comparator, and the digital control module is used to send a control signal to the correction module according to the output result of the summation comparator; The correction module is used to control the output current of the first current mirror module and the output current of the second current mirror module under the action of the control signal, and output a correction current to the summation comparator accordingly.

2. The offset cancellation circuit according to claim 1, characterized in that, The correction module includes: a first switching field-effect transistor, a second switching field-effect transistor, a third switching field-effect transistor, a fourth switching field-effect transistor, a fifth switching field-effect transistor, a sixth switching field-effect transistor, a seventh switching field-effect transistor, an eighth switching field-effect transistor, a ninth switching field-effect transistor, and a tenth switching field-effect transistor; The source of the first switching field-effect transistor, the source of the second switching field-effect transistor, the source of the third switching field-effect transistor, and the source of the fourth switching field-effect transistor are connected to the third terminal of the first current mirror module. The drain of the first switching field-effect transistor, the drain of the second switching field-effect transistor, the drain of the third switching field-effect transistor, and the drain of the fourth switching field-effect transistor are connected to the source of the fifth switching field-effect transistor and the source of the tenth switching field-effect transistor. The source of the sixth, seventh, eighth, and ninth switching field-effect transistors is connected to the third terminal of the second current mirror module, and the drain of the sixth, seventh, eighth, and ninth switching field-effect transistors is connected to the source of the fifth and tenth switching field-effect transistors. The gates of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, and tenth switching field-effect transistors are respectively connected to the output terminal of the digital control module.

3. The offset cancellation circuit according to claim 2, characterized in that, The drain of the tenth switching field-effect transistor, the drain of the fifth switching field-effect transistor, and the input of the summation comparator are connected.

4. The offset cancellation circuit according to claim 1, characterized in that, The current generation module includes: an operational amplifier and a first field-effect transistor; One input terminal of the operational amplifier is connected to the first terminal of the second current mirror module, the second input terminal of the operational amplifier is used to connect to the reference voltage, and the output terminal of the operational amplifier is connected to the gate of the first field-effect transistor. The drain of the first field-effect transistor is connected to the first terminal of the first current mirror module, and the source of the first field-effect transistor is connected to the first terminal of the second current mirror module.

5. The offset cancellation circuit according to claim 1, characterized in that, The first current mirror module includes a first self-biasing unit and a first proportional adjustment unit, and the second current mirror module includes a second self-biasing unit and a second proportional adjustment unit. The first end of the first self-biasing unit is connected to the output end of the current generating module, the second end of the first self-biasing unit is connected to the second end of the second self-biasing unit, and the third end of the first self-biasing unit is connected to the first end of the first proportional adjustment unit. The second end of the first proportional adjustment unit is connected to the first input end of the correction module; The first end of the second self-biasing unit is connected to the output end of the current generating module, and the third end of the second self-biasing unit is connected to the first end of the second proportional adjustment unit. The second end of the second proportional adjustment unit is connected to the second input end of the correction module.

6. The offset cancellation circuit according to claim 5, characterized in that, The first self-biasing unit includes: a first resistor, a second field-effect transistor, a third field-effect transistor, a fourth field-effect transistor, a fifth field-effect transistor, a sixth field-effect transistor, and a seventh field-effect transistor; The gates of the second field-effect transistor, the third field-effect transistor, and the fourth field-effect transistor are connected in series and connected to the first end of the first proportional adjustment unit; the gates of the fifth field-effect transistor, the sixth field-effect transistor, and the seventh field-effect transistor are connected in series and connected to the first end of the first proportional adjustment unit. The gates of the second field-effect transistor and the third field-effect transistor are also connected to one end of the first resistor, and the other end of the first resistor is connected to the output terminal of the current generation module. The sources of the second, third, and fourth field-effect transistors are all connected to a power supply. The drain of the second field-effect transistor is connected to the source of the fifth field-effect transistor. The drain of the third field-effect transistor is connected to the source of the sixth field-effect transistor. The drain of the fourth field-effect transistor is connected to the source of the seventh field-effect transistor. The gates of the fifth and sixth field-effect transistors are connected to the other end of the first resistor. The drain of the sixth field-effect transistor, the drain of the seventh field-effect transistor, and the second terminal of the second self-biasing unit are connected.

7. The offset cancellation circuit according to claim 6, characterized in that, The second self-biased unit includes an eighth field-effect transistor, a ninth field-effect transistor, a tenth field-effect transistor, an eleventh field-effect transistor, a twelfth field-effect transistor, and a second resistor; The drain of the eighth field-effect transistor is connected to the drain of the sixth field-effect transistor, the source of the eighth field-effect transistor is connected to the drain of the ninth field-effect transistor, the source of the ninth field-effect transistor is connected to the drain of the tenth field-effect transistor, and the gates of the eighth, ninth, tenth, and eleventh field-effect transistors are connected to the first terminal of the second proportional adjustment unit. The drain of the eleventh field-effect transistor is connected to the drain of the seventh field-effect transistor, the source of the eleventh field-effect transistor is connected to the drain of the twelfth field-effect transistor, the source of the twelfth field-effect transistor is grounded to the source of the tenth field-effect transistor, and the gate of the twelfth field-effect transistor, the drain of the eleventh field-effect transistor, and the first terminal of the second proportional adjustment unit are connected. One end of the second resistor is connected to the output terminal of the current generating module, and the other end of the second resistor is grounded.

8. The offset cancellation circuit according to claim 5, characterized in that, The first proportional adjustment unit includes multiple sets of first proportional adjustment branches. Each first proportional adjustment branch includes a first common-source field-effect transistor and a first common-gate field-effect transistor. The source of the first common-source field-effect transistor is connected to the power supply, the drain of the first common-source field-effect transistor is connected to the source of the first common-gate field-effect transistor, and the drain of the first common-gate field-effect transistor is connected to the first input terminal of the correction module. The gates of the first common-source field-effect transistors in each of the first proportional adjustment branches are connected in series and connected to the third terminal of the first self-biasing unit; the gates of the first common-gate field-effect transistors in each of the first proportional adjustment branches are connected in series and connected to the third terminal of the first self-biasing unit. The second proportional adjustment unit includes multiple sets of second proportional adjustment branches. Each second proportional adjustment branch includes a second common-source field-effect transistor and a second common-gate field-effect transistor. The source of the second common-source field-effect transistor is grounded, the drain of the second common-source field-effect transistor is connected to the source of the second common-gate field-effect transistor, and the drain of the second common-gate field-effect transistor is connected to the second input terminal of the correction module. The gates of the second common-source field-effect transistors in each of the second proportional adjustment branches are connected in series and connected to the third terminal of the second self-biasing unit. The gates of the second common-gate field-effect transistors in each of the second proportional adjustment branches are connected in series and connected to the third terminal of the second self-biasing unit.

9. A method for eliminating imbalance, characterized in that, The method, applied to the offset cancellation circuit as described in any one of claims 1-8, comprises: The current generation module generates an output current, and the output current is converted into different magnitudes of output current through the first current mirror module and the second current mirror module; The digital control module sends a control signal to the correction module based on the output of the summation comparator; The correction module controls the output current of the first current mirror module and the output current of the second current mirror module under the action of the control signal, and outputs a correction current to the summation comparator to correct the DC offset of the summation comparator.

10. A switching power supply, characterized in that, Includes the offset cancellation circuit as described in any one of claims 1-8.

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