An ultra-wideband high-efficiency power amplifier with dissimilar gate biasing

Abstract

The application discloses a kind of dissimilation grid bias ultra-wideband high-efficiency power amplifier, applied to microwave integrated circuit technical field.The application includes front-stage amplification circuit, intermediate-stage amplification circuit and end-stage amplification circuit;Front-stage amplification circuit amplifies input end signal and carries out grid voltage regulation, and the output signal of front-stage is further amplified and output.The application realizes the function of giving different grid bias voltage to three-stage transistor by the action of grid voltage dividing resistor, and achieves the characteristics of simultaneously realizing in-band high power output and high efficiency.

Description

Technical Field

[0001] This invention relates to the field of microwave integrated circuit technology, and more specifically to a heterogeneous gate biased ultrawideband high-efficiency power amplifier. Background Technology

[0002] Power amplifiers (PAs), as the core final-stage components of the transmit link, play a crucial role in the operational range of the entire wireless system. Ultra-wideband, high-power, and high-efficiency power amplifiers can meet the requirements of integrated electronic warfare systems.

[0003] With the development of integrated electronic warfare systems, multifunctional modules, including electronic warfare modules and communication modules, will be integrated together. However, low-efficiency high-power amplifiers will release a lot of heat, and the heat dissipation capacity of high-density integrated electronic warfare systems is relatively poor, which will lead to the deterioration of the performance of various functional modules in the system. In order to solve this problem, this invention proposes an ultra-wideband high-efficiency power amplifier with heterogeneous gate bias, which can effectively alleviate the heat dissipation problem.

[0004] In 2022, QORVO, an American company, launched the QPA1013D product, which can achieve saturated output power of 39.9–42.5 dBm and power-added efficiency (PAE) of 17%–27% in the 6–18-GHz band; however, its lowest in-band efficiency is only 17%, which cannot meet the requirements of high-density integrated electronic warfare systems.

[0005] In 2022, QORVO, an American company, launched the TGA2963 product, which can achieve saturated output power of 43.2–46.1 dBm and power-added efficiency (PAE) of 19%–30% in the 6–18-GHz frequency band. This power amplifier chip achieves a minimum in-band output power of 20W, but its minimum PAE of 19% still leads to a large amount of heat accumulation, which cannot meet the usage requirements.

[0006] In 2022, QORVO, an American company, launched the TGA2963-CP product, which can achieve saturated output power of 42.8–45.6 dBm and power-added efficiency (PAE) of 17%–27% in the 6–18 GHz band. While achieving high power, its efficiency is low, which will still have a significant negative impact on other functional modules of the integrated electronic warfare system.

[0007] Therefore, proposing a heterogeneous gate-biased ultrawideband high-efficiency power amplifier to solve the difficulties existing in the prior art is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0008] In view of this, the present invention provides an ultrawideband high-efficiency power amplifier with heterogeneous gate bias to solve the technical problems existing in the prior art.

[0009] To achieve the above objectives, the present invention provides the following technical solution:

[0010] A heterogeneous gate-biased ultrawideband high-efficiency power amplifier includes a preamplifier circuit, an intermediate amplifier circuit, and a final amplifier circuit; the preamplifier circuit amplifies the input signal and adjusts the gate voltage, and further amplifies and outputs the output signal of the preamplifier.

[0011] Optionally, the preamplifier circuit includes: a first DC blocking capacitor C0, a first matching capacitor C1, a second matching capacitor C2, a third matching capacitor C3, a fourth matching capacitor C5, a first stabilizing structure capacitor C4; a first input matching microstrip line L1, a second input matching microstrip line L2, a third input matching microstrip line L3, a fourth input matching microstrip line L4, a first gate bias inductor L3'; a stabilizing structure resistor R1; and a preamplifier transistor T1.

[0012] Optionally, one end of the first DC blocking capacitor C0 serves as the input port for the RF signal, and the other end is connected to one end of the first input matching microstrip line L1 and the first matching capacitor C1, with the other end of the first matching capacitor C1 grounded; one end of the second matching capacitor C2 is connected to the first input matching microstrip line L1 and the second input matching microstrip line L2, with the other end of the second matching capacitor C2 grounded; one end of the third matching capacitor C3 is connected to the second input matching microstrip line L2 and the third input matching microstrip line L3, with the other end of the third matching capacitor C3 grounded; the stabilizing structure resistor R1 and the first stabilizing structure capacitor C4 are connected in parallel, with one end connected to the third input matching microstrip line L3 and the first gate bias inductor L3' at a common connection point, and the other end connected to the fourth input matching microstrip line L4 and the fourth matching capacitor C5 at a common connection point; the gate of the front-stage transistor T1 is connected to the fourth input matching microstrip line L4, the drain terminal is connected to the intermediate stage amplifier circuit, and the source is grounded.

[0013] Optionally, the intermediate stage amplifier circuit includes: fifth matching microstrip line L5, sixth matching microstrip line L6, seventh matching microstrip line L7, eighth matching microstrip line L8, ninth matching microstrip line L9, and tenth matching microstrip line L1. 10 Position inductance L 11 Second gate bias inductor L7'; second DC blocking capacitor C6, third DC blocking capacitor C9, fourth DC blocking capacitor C9', fifth matching capacitor C7, sixth matching capacitor C 10 The second stabilizing capacitor C8; the first gate bias voltage divider resistor R. G1 Second gate bias voltage divider resistor R G2Intermediate stage transistor T2, stability resistor R3, first even-mode oscillation suppression resistor R2, second even-mode oscillation suppression resistor R4, third even-mode oscillation suppression resistor R5.

[0014] Optionally, one end of the second DC blocking capacitor C6 is connected to the common junction of the fifth matching microstrip line L5 and the sixth matching microstrip line L6, and the other end of the second DC blocking capacitor C6 is connected to the common junction of one end of the fifth matching capacitor C7 and one end of the seventh matching microstrip line L7. The other end of the fifth matching capacitor C7 is grounded, and the other end of the sixth matching microstrip line L6 serves as the drain bias input port of the first-stage transistor. The other end of the seventh matching microstrip line L7 is connected to the common junction of one end of the second gate bias inductor L7', the second stabilizing structure capacitor C8, and the first even-mode oscillation suppression resistor R2. The other end of the second gate bias inductor L7' is connected to the first gate bias voltage divider resistor R. G1 Second gate bias voltage divider resistor R G2 One end is connected to the common contact point, and the first gate bias voltage divider resistor R G1 The other end is grounded, and the second gate bias voltage divider resistor R G2 The other end is connected to the position inductor L 11 The second gate bias inductor L7' is connected to the common junction. The stability resistor R3 and the second stability structure capacitor C8 are connected in parallel, and the other end of the parallel connection is connected to the gate of the intermediate stage transistor T2. The first even-mode oscillation suppression resistor R2 is connected in parallel between the seventh matching microstrip line L7 and the common junction of the stability structure in both branches. The second even-mode oscillation suppression resistor R4 is connected in parallel between the drain of the intermediate stage transistor T2 and the common junction of the eighth matching microstrip line L8 in both branches. The other end of the eighth matching microstrip line L8 is connected to the common junction of the ninth matching microstrip line L9 and the third DC blocking capacitor C9. The other end of the ninth matching microstrip line L9 serves as the input port for the gate bias current of the intermediate stage transistor T2. The other end of the third DC blocking capacitor C9 is connected to the sixth matching capacitor C 10 10th Matching Microstrip Line L 10 Common contact connection, sixth matching capacitor C 10 The other end is grounded; the third even-mode oscillation suppression resistor R5 is connected in parallel to the tenth matching microstrip line L of the two branches. 10 Bias inductor L 11 Between the gate common junction of intermediate stage transistor T2 and the gate of intermediate stage transistor T2, one end of the fourth DC blocking capacitor C9' is connected to the ninth matching microstrip line L9, and the other end of the fourth DC blocking capacitor C9' is grounded.

[0015] Optionally, the final stage amplifier circuit includes: a final stage transistor T3, and an eleventh matching microstrip line L. 12 12th Matching Microstrip Line L 13 Thirteenth Matching Microstrip Line L 14 Fourteenth matching microstrip line L 15 The fifteenth matching microstrip line L 16The sixteenth matching microstrip line L 17 The seventeenth matching microstrip line L 18 The eighteenth matching microstrip line L 19 ; Seventh matching capacitor C 11 Eighth matching capacitor C 12 Ninth matching capacitor C 13 10th matching capacitor C 14 Eleventh matching capacitor C 15 The fifth DC blocking capacitor C 16 The sixth DC blocking capacitor C B3 Decoupling capacitor C Q3 .

[0016] Optional, eleventh matching microstrip line L 12 One end is connected to the drain of the final stage transistor T3, and the eleventh matching microstrip line L 12 The other end is matched with the twelfth microstrip line L 13 One end is connected to the twelfth matching microstrip line L. 13 The other end is matched with the thirteenth microstrip line L 14 One end, the fourteenth matching microstrip line L 15 Common connection point, thirteenth matching microstrip line L 14 The other end is connected to the sixth DC blocking capacitor C B3 Connection, decoupling capacitor C Q3 The other end is grounded, and the sixth DC blocking capacitor C B3 The other end is grounded, and the fourteenth matching microstrip line L 15 The other end is matched with the seventh capacitor C. 11 One end, the fifteenth matching microstrip line L 16 Common contact connection, seventh matching capacitor C 11 The other end is grounded, and the fifteenth matching microstrip line L 16 The other end is matched with the eighth capacitor C. 12 One end, the sixteenth matching microstrip line L 17 Common contact connection, eighth matching capacitor C 12 The other end is grounded, and the sixteenth matching microstrip line L 17 The other end is matched with the ninth capacitor C. 13 One end, the seventeenth matching microstrip line L 18 Common contact connection, ninth matching capacitor C 13 The other end is grounded, and the seventeenth matching microstrip line L 18 The other end is matched with the tenth capacitor C. 14 The eighteenth matching microstrip line L 19 Common connection, eighteenth matching microstrip line L 19 The other end is connected to the fifth DC blocking capacitor C 16 One end, the eleventh matching capacitor C15 Common contact connection, fifth DC blocking capacitor C 16 The other end serves as a radio frequency signal.

[0017] As can be seen from the above technical solution, compared with the prior art, the present invention discloses an ultra-wideband high-efficiency power amplifier with heterogeneous gate bias. Its beneficial effects are: by the action of the gate voltage divider resistor, the function of giving different gate bias voltages to the three-stage transistor is realized, achieving the characteristics of simultaneously realizing high power output and high efficiency in the band, and solving the problem of heat dissipation in high-density integrated electronic warfare systems. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0019] Figure 1 A structural block diagram of a heterogeneous gate biased ultrawideband high-efficiency power amplifier provided by the present invention;

[0020] Figure 2 This is a schematic diagram of the structure provided for an embodiment of the present invention;

[0021] Figure 3 A structural schematic diagram provided for comparison of the present invention;

[0022] Figure 4 The efficiency simulation results are shown in the figure provided for the embodiments of the present invention;

[0023] Figure 5 A comparison diagram of the efficiency simulation results of the embodiments and comparative examples provided by the present invention is shown.

[0024] Figure 6 The output power simulation results are shown in the figure provided for the embodiments of the present invention. Detailed Implementation

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] See Figure 1As shown, this invention discloses an ultrawideband high-efficiency power amplifier with heterogeneous gate bias, including a preamplifier circuit, an intermediate amplifier circuit, and a final amplifier circuit; the preamplifier circuit amplifies the input signal and adjusts the gate voltage, and further amplifies and outputs the output signal of the preamplifier.

[0027] Furthermore, the preamplifier circuit includes: a first DC blocking capacitor C0, a first matching capacitor C1, a second matching capacitor C2, a third matching capacitor C3, a fourth matching capacitor C5, a first stabilizing structure capacitor C4; a first input matching microstrip line L1, a second input matching microstrip line L2, a third input matching microstrip line L3, a fourth input matching microstrip line L4, a first gate bias inductor L3'; a stabilizing structure resistor R1; and a preamplifier transistor T1.

[0028] Furthermore, one end of the first DC blocking capacitor C0 serves as the input port for the RF signal, and the other end is connected to one end of the first input matching microstrip line L1 and the first matching capacitor C1, with the other end of the first matching capacitor C1 grounded; one end of the second matching capacitor C2 is connected to the first input matching microstrip line L1 and the second input matching microstrip line L2, with the other end of the second matching capacitor C2 grounded; one end of the third matching capacitor C3 is connected to the second input matching microstrip line L2 and the third input matching microstrip line L3, with the other end of the third matching capacitor C3 grounded; the stabilizing structure resistor R1 and the first stabilizing structure capacitor C4 are connected in parallel, with one end connected to the third input matching microstrip line L3 and the first gate bias inductor L3' at a common connection point, and the other end connected to the fourth input matching microstrip line L4 and the fourth matching capacitor C5 at a common connection point; the gate of the front-stage transistor T1 is connected to the fourth input matching microstrip line L4, the drain terminal is connected to the intermediate stage amplifier circuit, and the source is grounded.

[0029] Furthermore, the intermediate stage amplifier circuit includes: the fifth matching microstrip line L5, the sixth matching microstrip line L6, the seventh matching microstrip line L7, the eighth matching microstrip line L8, the ninth matching microstrip line L9, and the tenth matching microstrip line L1. 10 Position inductance L 11 Second gate bias inductor L7'; second DC blocking capacitor C6, third DC blocking capacitor C9, fourth DC blocking capacitor C9', fifth matching capacitor C7, sixth matching capacitor C 10 The second stabilizing capacitor C8; the first gate bias voltage divider resistor R. G1 Second gate bias voltage divider resistor R G2 Intermediate stage transistor T2, stability resistor R3, first even-mode oscillation suppression resistor R2, second even-mode oscillation suppression resistor R4, third even-mode oscillation suppression resistor R5.

[0030] Furthermore, one end of the second DC blocking capacitor C6 is connected to the common junction of the fifth matching microstrip line L5 and the sixth matching microstrip line L6, and the other end of the second DC blocking capacitor C6 is connected to the common junction of one end of the fifth matching capacitor C7 and one end of the seventh matching microstrip line L7. The other end of the fifth matching capacitor C7 is grounded, and the other end of the sixth matching microstrip line L6 serves as the drain bias input port of the first-stage transistor. The other end of the seventh matching microstrip line L7 is connected to the common junction of one end of the second gate bias inductor L7', the second stabilizing structure capacitor C8, and the first even-mode oscillation suppression resistor R2. The other end of the second gate bias inductor L7' is connected to the first gate bias voltage divider resistor R. G1 Second gate bias voltage divider resistor R G2 One end is connected to the common contact point, and the first gate bias voltage divider resistor R G1 The other end is grounded, and the second gate bias voltage divider resistor R G2 The other end is connected to the position inductor L 11 The second gate bias inductor L7' is connected to the common junction. The stability resistor R3 and the second stability structure capacitor C8 are connected in parallel, and the other end of the parallel connection is connected to the gate of the intermediate stage transistor T2. The first even-mode oscillation suppression resistor R2 is connected in parallel between the seventh matching microstrip line L7 and the common junction of the stability structure in both branches. The second even-mode oscillation suppression resistor R4 is connected in parallel between the drain of the intermediate stage transistor T2 and the common junction of the eighth matching microstrip line L8 in both branches. The other end of the eighth matching microstrip line L8 is connected to the common junction of the ninth matching microstrip line L9 and the third DC blocking capacitor C9. The other end of the ninth matching microstrip line L9 serves as the input port for the gate bias current of the intermediate stage transistor T2. The other end of the third DC blocking capacitor C9 is connected to the sixth matching capacitor C 10 10th Matching Microstrip Line L 10 Common contact connection, sixth matching capacitor C 10 The other end is grounded; the third even-mode oscillation suppression resistor R5 is connected in parallel to the tenth matching microstrip line L of the two branches. 10 Bias inductor L 11 Between the gate common junction of intermediate stage transistor T2 and the gate of intermediate stage transistor T2, one end of the fourth DC blocking capacitor C9' is connected to the ninth matching microstrip line L9, and the other end of the fourth DC blocking capacitor C9' is grounded.

[0031] Specifically, one end of the second DC blocking capacitor C6 is connected to the common connection point of the fifth matching microstrip line L5 and the sixth matching microstrip line L6, and the other end of the second DC blocking capacitor C6 is connected to the common connection point of one end of the fifth matching capacitor C7 and one end of the seventh matching microstrip line L7, which serves to isolate the drain bias of the first-stage transistor from the gate bias of the second-stage transistor.

[0032] Furthermore, the final stage amplifier circuit includes: a final stage transistor T3, and an eleventh matching microstrip line L. 12 12th Matching Microstrip Line L 13 Thirteenth Matching Microstrip Line L14 Fourteenth matching microstrip line L 15 The fifteenth matching microstrip line L 16 The sixteenth matching microstrip line L 17 The seventeenth matching microstrip line L 18 The eighteenth matching microstrip line L 19 ; Seventh matching capacitor C 11 Eighth matching capacitor C 12 Ninth matching capacitor C 13 10th matching capacitor C 14 Eleventh matching capacitor C 15 The fifth DC blocking capacitor C 16 The sixth DC blocking capacitor C B3 Decoupling capacitor C Q3 .

[0033] Furthermore, the eleventh matching microstrip line L 12 One end is connected to the drain of the final stage transistor T3, and the eleventh matching microstrip line L 12 The other end is matched with the twelfth microstrip line L 13 One end is connected to the twelfth matching microstrip line L. 13 The other end is matched with the thirteenth microstrip line L 14 One end, the fourteenth matching microstrip line L 15 Common connection point, thirteenth matching microstrip line L 14 The other end is connected to the sixth DC blocking capacitor C B3 Connection, decoupling capacitor C Q3 The other end is grounded, and the sixth DC blocking capacitor C B3 The other end is grounded, and the fourteenth matching microstrip line L 15 The other end is matched with the seventh capacitor C. 11 One end, the fifteenth matching microstrip line L 16 Common contact connection, seventh matching capacitor C 11 The other end is grounded, and the fifteenth matching microstrip line L 16 The other end is matched with the eighth capacitor C. 12 One end, the sixteenth matching microstrip line L 17 Common contact connection, eighth matching capacitor C 12 The other end is grounded, and the sixteenth matching microstrip line L 17 The other end is matched with the ninth capacitor C. 13 One end, the seventeenth matching microstrip line L 18 Common contact connection, ninth matching capacitor C 13 The other end is grounded, and the seventeenth matching microstrip line L 18 The other end is matched with the tenth capacitor C. 14 The eighteenth matching microstrip line L 19Common connection, eighteenth matching microstrip line L 19 The other end is connected to the fifth DC blocking capacitor C 16 One end, the eleventh matching capacitor C 15 Common contact connection, fifth DC blocking capacitor C 16 The other end serves as a radio frequency signal.

[0034] In a specific embodiment, this embodiment provides a heterogeneous gate-biased ultrawideband high-efficiency power amplifier circuit structure, including transistors, matching microstrip lines, matching capacitors, stabilization capacitors, gate bias voltage divider resistors, stabilization resistors, even-mode oscillation suppression resistors, gate bias inductors, and DC blocking capacitors. In each stage of the amplifier circuit, impedance transformation is performed using a combination of matching capacitors and matching microstrip lines. Simultaneously, stabilization capacitors, resistors, and even-mode oscillation suppression resistors are used to improve the overall circuit stability. In the intermediate stage amplifier circuit, this embodiment uses resistors to divide the gate bias of the second and third stage transistors, achieving both high power output and high power-added efficiency.

[0035] Simulation results show that the heterogeneous gate biased ultrawideband high-efficiency power amplifier can achieve an output power of 43.3-45 dBm and a power-added efficiency (PAE) of 30%-40% in the 6–18-GHz band, while balancing high output power and high efficiency.

[0036] like Figure 2 This is a heterogeneous gate bias ultrawideband high-efficiency power amplifier circuit structure. Through the action of the gate voltage divider resistor, the gate bias voltage of the first-stage transistor is -1.7V, the gate bias voltage of the second-stage transistor is -1.5V, and the gate bias voltage of the final-stage transistor is -1.9V. The gate bias voltages of the three stages of transistors are all different. This makes the final-stage transistor operate in a Class AB bias state that is closer to Class B bias, thereby improving efficiency while meeting the output power requirements. The second-stage transistor operates in a Class AB bias state that is closer to Class A bias, providing sufficient drive power for the final-stage transistor. Ultimately, the goal of achieving both output power and efficiency is achieved.

[0037] For specific circuit implementation, see Figure 3 As shown, the first gate bias voltage divider resistor R G1 Second gate bias voltage divider resistor R G2 To achieve different gate bias voltages for the second and third stage transistors; the eleventh matching microstrip line L 12 12th Matching Microstrip Line L 13 Thirteenth Matching Microstrip Line L 14 Fourteenth matching microstrip line L 15 The fifteenth matching microstrip line L 16 The sixteenth matching microstrip line L 17The seventeenth matching microstrip line L 18 The eighteenth matching microstrip line L 19 The seventh matching capacitor C 11 Eighth matching capacitor C 12 Ninth matching capacitor C 13 10th matching capacitor C 14 Eleventh matching capacitor C 15 This achieves the impedance transformation function, enabling the load impedance of the final stage transistor to be transformed from 50 ohms to the optimal load impedance within the frequency band. The thirteenth matching microstrip line L... 14 While achieving impedance matching, it also serves as the DC bias power supply for the drain of the final-stage transistor T3. Decoupling capacitor C... Q3 To avoid external bias circuitry from participating in the matching, the fifth DC blocking capacitor C 16 The sixth DC blocking capacitor C B3 It serves to block DC current, ensuring that the drain bias can be input to the transistor drain.

[0038] In the intermediate stage amplifier circuit, the fifth matching microstrip line L5, the sixth matching microstrip line L6, the seventh matching microstrip line L7, the eighth matching microstrip line L8, the ninth matching microstrip line L9, and the tenth matching microstrip line L... 10 The second DC blocking capacitor C6, the third DC blocking capacitor C9, the fifth matching capacitor C7, and the sixth matching capacitor C 10 To achieve impedance transformation, the sixth matching microstrip line L6 and the ninth matching microstrip line L9 also serve as the DC bias inputs for the drains of transistors T1 and T2. The position inductor L... 11 The second gate bias inductor L7' provides DC bias to the gate while achieving RF isolation through its high impedance. Due to its parallel connection with the matching circuit, it does not significantly affect impedance transformation. The second DC blocking capacitor C6 isolates the drain and gate biases of transistors T1 and T2, while the third DC blocking capacitor C9 isolates the drain and gate biases of transistors T2 and T3. The second and third even-mode oscillation suppression resistors R4 and R5 suppress self-oscillations caused by amplitude-phase inconsistencies between branches and provide DC bias power to the drain and gate. The stability resistor R3 is connected in parallel with the second stabilizing capacitor C8 and then in series with it in the matching circuit, improving circuit stability while minimizing performance loss. The fourth DC blocking capacitor C9' prevents the drain DC bias current from leaking to ground.

[0039] In the preamplifier circuit, the first input matching microstrip line L1, the second input matching microstrip line L2, the third input matching microstrip line L3, the fourth input matching microstrip line L4, and the first matching capacitor C1, the second matching capacitor C2, the third matching capacitor C3, and the fourth matching capacitor C5 can transform the 50-ohm port impedance to the optimal source impedance of transistor T1. The first DC blocking capacitor C0 can prevent DC bias leakage at the gate. The stability resistor R1 and the first stabilizing structure capacitor C4 can effectively improve the stability of the amplifier. The first gate bias inductor L3' can achieve DC bias input at the gate of transistor T1 while preventing RF signal leakage.

[0040] The drain bias voltage of the transistors is 28V.

[0041] Comparative Example 1:

[0042] This comparative example provides a 6-18-GHz power amplifier without a heterogeneous gate bias voltage design, which provides a fixed -1.7V bias voltage at the gate of each stage transistor. Simulation results show that its in-band power-added efficiency is 25%-40%, which is still insufficient to meet the requirements of integrated electronic warfare systems.

[0043] The simulation results of the power-added efficiency in the 6-18-GHz band of Example 1 are as follows: Figure 4 As shown, it achieves a power-added efficiency of 30%-40% within the band, which is a significant improvement compared to Comparative Example 1.

[0044] A comparison of the power-added efficiency simulation results of Example 1 and Comparative Example 1 is shown below. Figure 5 As shown, the design in Example 1 has efficiency advantages across the entire frequency band.

[0045] See Figure 6 The simulation results of the saturated output power in the band shown in Example 1 can be seen. It can be seen that a saturated output power of 43.3-45.5dBm can be achieved in the 6-18-GHz band.

[0046] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0047] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A heterogeneous gate-biased ultrawideband high-efficiency power amplifier, characterized in that, It includes a preamplifier circuit, an intermediate amplifier circuit, and a final amplifier circuit; the preamplifier circuit amplifies the input signal and adjusts the gate voltage, and further amplifies and outputs the output signal of the preamplifier circuit. The intermediate stage amplifier circuit includes: fifth matching microstrip line L5, sixth matching microstrip line L6, seventh matching microstrip line L7, eighth matching microstrip line L8, ninth matching microstrip line L9, and tenth matching microstrip line L1. 10 Bias inductor L 11 Second gate bias inductor L7'; second DC blocking capacitor C6, third DC blocking capacitor C9, fourth DC blocking capacitor C9', fifth matching capacitor C7, sixth matching capacitor C 10 The second stabilizing capacitor C8; the first gate bias voltage divider resistor R. G1 Second gate bias voltage divider resistor R G2 Intermediate stage transistor T2, stability resistor R3, first even-mode oscillation suppression resistor R2, second even-mode oscillation suppression resistor R4, third even-mode oscillation suppression resistor R5; One end of the second DC blocking capacitor C6 is connected to the common junction of the fifth matching microstrip line L5 and the sixth matching microstrip line L6. The other end of the second DC blocking capacitor C6 is connected to the common junction of one end of the fifth matching capacitor C7 and one end of the seventh matching microstrip line L7. The other end of the fifth matching capacitor C7 is grounded. The other end of the sixth matching microstrip line L6 serves as the drain bias input port of the first-stage transistor. The other end of the seventh matching microstrip line L7 is connected to the common junction of one end of the second gate bias inductor L7', the second stable structure capacitor C8, and the first even-mode oscillation suppression resistor R2. The other end of the second gate bias inductor L7' is connected to the first gate bias voltage divider resistor R. G1 Second gate bias voltage divider resistor R G2 One end is connected to the common contact point, and the first gate bias voltage divider resistor R G1 The other end is grounded, and the second gate bias voltage divider resistor R G2 The other end is connected to the bias inductor L 11 V G The common contact point is connected to the second stable structure capacitor C8. The stability resistor R3 and the second stable structure capacitor C8 are connected in parallel, and the other end of the parallel connection is connected to the gate of the intermediate stage transistor T2. The first even-mode oscillation suppression resistor R2 is connected between the seventh matching microstrip line L7 and the common contact point of the stability structure in both branches. The second even-mode oscillation suppression resistor R4 is connected between the drain of the intermediate stage transistor T2 and the common contact point of the eighth matching microstrip line L8 in both branches. The other end of the eighth matching microstrip line L8 is connected to the common contact point of the first and ninth matching microstrip lines L9 and the third DC blocking capacitor C9. The other end of the first and ninth matching microstrip lines L9 serves as the input port of the drain bias current of the intermediate stage transistor T2. The other end of the third DC blocking capacitor C9 is connected to the sixth matching capacitor C 10 10th Matching Microstrip Line L 10 Common contact connection, sixth matching capacitor C 10 The other end is grounded; the third even-mode oscillation suppression resistor R5 is connected to the tenth matching microstrip line L of the two branches. 10 Bias inductor L 11 Between the gate common junction of the final stage transistor T3 and the fourth DC blocking capacitor C9', one end of the fourth DC blocking capacitor C9' is connected to the second and ninth matching microstrip lines L9, and the other end of the fourth DC blocking capacitor C9' is grounded.

2. The heterogeneous gate biased ultrawideband high-efficiency power amplifier according to claim 1, characterized in that, The preamplifier circuit includes: a first DC blocking capacitor C0, a first matching capacitor C1, a second matching capacitor C2, a third matching capacitor C3, a fourth matching capacitor C5, a first stabilizing structure capacitor C4; a first input matching microstrip line L1, a second input matching microstrip line L2, a third input matching microstrip line L3, a fourth input matching microstrip line L4, a first gate bias inductor L3'; a stabilizing structure resistor R1; and a preamplifier transistor T1.

3. The heterogeneous gate biased ultrawideband high-efficiency power amplifier according to claim 2, characterized in that, One end of the first DC blocking capacitor C0 serves as the input port for the RF signal, and the other end is connected to one end of the first input matching microstrip line L1 and the first matching capacitor C1. The other end of the first matching capacitor C1 is grounded. One end of the second matching capacitor C2 is connected to the first input matching microstrip line L1 and the second input matching microstrip line L2, and the other end of the second matching capacitor C2 is grounded. One end of the third matching capacitor C3 is connected to the second input matching microstrip line L2 and the third input matching microstrip line L3, and the other end of the third matching capacitor C3 is grounded. The stabilizing structure resistor R1 and the first stabilizing structure capacitor C4 are connected in parallel. One end of R1 is connected to the third input matching microstrip line L3 and the first gate bias inductor L3' at a common connection point, and the other end is connected to the fourth input matching microstrip line L4 and the fourth matching capacitor C5 at a common connection point. The gate of the front-stage transistor T1 is connected to the fourth input matching microstrip line L4, the drain terminal is connected to the intermediate stage amplifier circuit, and the source is grounded.

4. The heterogeneous gate biased ultrawideband high-efficiency power amplifier according to claim 1, characterized in that, The final stage amplifier circuit includes: final stage transistor T3, eleventh matching microstrip line L 12 12th Matching Microstrip Line L 13 Thirteenth Matching Microstrip Line L 14 Fourteenth matching microstrip line L 15 The fifteenth matching microstrip line L 16 The sixteenth matching microstrip line L 17 The seventeenth matching microstrip line L 18 The eighteenth matching microstrip line L 19 ; Seventh matching capacitor C 11 Eighth matching capacitor C 12 Ninth matching capacitor C 13 10th matching capacitor C 14 Eleventh matching capacitor C 15 The fifth DC blocking capacitor C 16 The sixth DC blocking capacitor C B3 Decoupling capacitor C Q3 .

5. A heterogeneous gate-biased ultrawideband high-efficiency power amplifier according to claim 4, characterized in that, Eleventh Matching Microstrip Line L 12 One end is connected to the drain of the final stage transistor T3, and the eleventh matching microstrip line L 12 The other end is matched with the twelfth microstrip line L 13 One end is connected to the twelfth matching microstrip line L. 13 The other end is matched with the thirteenth microstrip line L 14 One end, the fourteenth matching microstrip line L 15 Common connection point, thirteenth matching microstrip line L 14 The other end is connected to the sixth DC blocking capacitor C B3 Connection, decoupling capacitor C Q3 The other end is grounded, and the sixth DC blocking capacitor C B3 The other end is grounded, and the fourteenth matching microstrip line L 15 The other end is matched with the seventh capacitor C. 11 One end, the fifteenth matching microstrip line L 16 Common contact connection, seventh matching capacitor C 11 The other end is grounded, and the fifteenth matching microstrip line L 16 The other end is matched with the eighth capacitor C. 12 One end, the sixteenth matching microstrip line L 17 Common contact connection, eighth matching capacitor C 12 The other end is grounded, and the sixteenth matching microstrip line L 17 The other end is matched with the ninth capacitor C. 13 One end, the seventeenth matching microstrip line L 18 Common contact connection, ninth matching capacitor C 13 The other end is grounded, and the seventeenth matching microstrip line L 18 The other end is matched with the tenth capacitor C. 14 The eighteenth matching microstrip line L 19 Common connection, eighteenth matching microstrip line L 19 The other end is connected to the fifth DC blocking capacitor C 16 One end, the eleventh matching capacitor C 15 Common contact connection, fifth DC blocking capacitor C 16 The other end serves as the radio frequency signal.

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