A programmable xor gate trng circuit based on multi-phase sampling

Abstract

The application discloses a programmable XOR gate TRNG circuit based on multi-phase sampling, comprising an oscillation circuit, an entropy sampling circuit and a phase-locked loop, the oscillation circuit is used to generate a random oscillation output signal, comprising M basic oscillation units arranged in parallel, the basic oscillation unit is a double-output XOR gate unit based on LUT6-2; the entropy sampling circuit is used to sample the oscillation signal generated by the oscillation circuit to obtain an original random sequence, comprising N D flip-flops arranged in parallel, and a multi-input XOR gate connected with the output ends of all the D flip-flops; the phase-locked loop is used to generate sampling clocks of multiple different phases. The application can improve the universality and hardware utilization rate of the TRNG, improve the precision of the TRNG, enhance the randomness, and reduce the overhead.

Description

Technical Field

[0001] This invention relates to the fields of chip security and encryption protection technology, and in particular to a programmable XOR gate TRNG circuit based on multi-phase sampling. Background Technology

[0002] With the rise of cloud computing and IoT devices, information security has become a major concern. Random numbers used to create random keys, parameters in challenge-response protocols, padding values, and initialization vectors are crucial for security. Random numbers can be categorized into pseudo-random numbers and true random numbers. Pseudo-random numbers (PRNs) reduce attack complexity due to the periodicity and predictability of their output sequences generated by deterministic algorithms. In highly reliable encryption systems, true random number generators (TRNGs) using uncertain physical sources have become the preferred choice.

[0003] The performance metrics of TRNG (True Random Number Generator) include throughput, hardware resource consumption, and random number statistics. TRNGs strictly meet statistical requirements, exhibiting unpredictability by utilizing random physical processes as entropy sources to generate random numbers. Depending on the physical source, TRNGs can be divided into analog TRNGs and digital TRNGs. The entropy sources of analog TRNGs originate from thermal noise, photoelectric effects, and magnetic tunnel junctions, etc. Continuous values ​​generated by analog devices are quantized into a random bit stream using comparators or chaotic mechanisms; however, this process is very complex and costly due to equipment and process limitations. The entropy sources of digital TRNGs mainly originate from jitter (usually caused by electrical noise) and metastability (usually due to input signals and clock signals violating setup and hold times). The randomness of the entropy sources is extracted and quantized through sampling circuits to obtain the original bit stream. As a semi-custom circuit, the field-programmable gate array (FPGA) has gradually become the mainstream platform for TRNG design due to its low cost and ease of implementation.

[0004] Ring oscillator (RO)-based TRNGs are a commonly used random number generation method. They primarily utilize the clock jitter generated by the RO as a random source, offering advantages such as relatively simple structure, ease of implementation in integrated circuits, and the ability to achieve different random performance and anti-interference characteristics by increasing the number of ring oscillators and adjusting parameters. However, implementing RO TRNGs in FPGAs typically incurs high hardware overhead. Specifically, to achieve a certain level of randomness, hundreds of ring oscillators need to be connected in parallel, resulting in significant hardware resource consumption. Summary of the Invention

[0005] This invention aims to at least solve one of the technical problems existing in the prior art. To this end, this invention proposes a programmable XOR gate TRNG circuit based on multi-phase sampling, which can improve the versatility and hardware utilization of TRNGs, increase the accuracy of TRNGs, enhance randomness, and reduce overhead.

[0006] According to an embodiment of the present invention, a programmable XOR gate TRNG circuit based on multi-phase sampling includes:

[0007] An oscillation circuit for generating irregular oscillation output signals includes M parallel basic oscillation units, wherein the basic oscillation unit is a dual-output XOR gate unit based on LUT6-2.

[0008] An entropy sampling circuit is used to sample the oscillation signal generated by the oscillation circuit to obtain the original random sequence. It includes N parallel D flip-flops and a multi-input XOR gate connected to the output of all the D flip-flops.

[0009] Phase-locked loop (PLL) is used to generate sampling clocks with multiple different phases;

[0010] Wherein, the number of D flip-flops N≥4, the number of basic oscillation units M is half of the number of D flip-flops N rounded up, and the input D terminals of all D flip-flops are connected one-to-one with the output terminals of the basic oscillation units; the number of phases of the sampling clock generated by the phase-locked loop is consistent with the number of D flip-flops, and the clock input of the D flip-flops is connected one-to-one with the output terminals of the phase-locked loop.

[0011] According to an embodiment of the present invention, a programmable XOR gate TRNG circuit based on multi-phase sampling improves the versatility of TRNG and enhances hardware utilization through its unique structure. The entropy source circuit of TRNG can be successfully constructed using only a single configurable logic block. Furthermore, the accuracy of TRNG is improved and the randomness is enhanced by the multi-phase fine-grained sampling mechanism, and the purpose of reducing TRNG overhead is effectively achieved.

[0012] In some embodiments of the present invention, the basic oscillation unit includes a first XOR gate and a second XOR gate. One input terminal of the first XOR gate and one input terminal of the second XOR gate are connected and serve as the input port in of the basic oscillation unit. The other input terminal of the first XOR gate is connected to the output terminal of the first XOR gate, and the other input terminal of the second XOR gate is connected to the output terminal of the second XOR gate. The output terminals of the first XOR gate and the second XOR gate are the two output terminals of the basic oscillation unit, respectively connected to the input D terminals of the two D flip-flops.

[0013] In some embodiments of the present invention, the two output terminals of the i-th basic oscillation unit of the oscillation circuit are respectively connected to the input D terminals of the i*2-1 and i*2-th D flip-flops of the entropy sampling circuit, where i represents the sequence number of the basic oscillation unit, 1≤i≤M; the input terminals of all the basic oscillation units are connected to the CTL port.

[0014] In some embodiments of the present invention, the clock input of the j-th D flip-flop of the entropy sampling circuit is connected to the j-th output of the phase-locked loop. Multiple D flip-flops are driven by clocks of different phases output by the phase-locked loop to obtain the original random number. The outputs of the multiple D flip-flops are passed through a multi-input XOR gate to obtain the final random number output. j represents the sequence number of the D flip-flops.

[0015] In some embodiments of the present invention, the number of different phase sampling clocks output by the phase-locked loop is consistent with the number N of the D flip-flops, and the k-th phase output by the phase-locked loop is... Phase degree, k represents the index of the D flip-flop, 1≤k≤N.

[0016] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the XOR programming unit;

[0018] Figure 2 This is a schematic diagram of the dual-output XOR gate unit based on LUT6_2 of the present invention;

[0019] Figure 3 This is a schematic diagram illustrating the basic principle of multi-phase sampling in this invention;

[0020] Figure 4 This is a schematic diagram of the programmable XOR gate TRNG circuit based on multi-phase sampling of the present invention;

[0021] Figure 5 This is a schematic diagram of the randomness test results of the present invention;

[0022] Figure 6 This is a schematic diagram of the temperature-voltage resistance test results of the present invention.

[0023] In the picture:

[0024] Oscillating circuit 10; basic oscillation unit 11; first XOR gate 111; second XOR gate 112; first basic oscillation unit 11-1; second basic oscillation unit 11-2;

[0025] Entropy sampling circuit 20; D flip-flop 21; first D flip-flop 211; second D flip-flop 212; third D flip-flop 213; fourth D flip-flop 214; multi-input XOR gate 22;

[0026] Phase-locked loop 30. Detailed Implementation

[0027] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0028] The following disclosure provides numerous different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of the invention. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.

[0029] To facilitate understanding, let's first briefly introduce existing true random number generators. A true random number generator (TRNG) is a device used to generate random numbers. Its output random numbers are based on physical random phenomena or processes that possess inherent randomness. Unlike pseudo random number generators (PRNGs), TRNGs do not generate random numbers through computation or predictable methods; instead, they originate from unpredictable physical processes.

[0030] The following is for reference. Figures 1-6 A programmable XOR gate TRNG circuit based on multi-phase sampling according to an embodiment of the present invention is described, comprising: an oscillation circuit 10, an entropy sampling circuit 20, and a phase-locked loop (PLL) 30. The oscillation circuit 10 is used to generate a random oscillation output signal; the entropy sampling circuit 20 is used to sample the oscillation signal generated by the oscillation circuit 10 to obtain an original random sequence; and the PLL 30 is used to generate sampling clocks with multiple different phases to provide sampling clocks to the entropy sampling circuit 20.

[0031] Reference Figures 1 to 4As shown, the oscillation circuit 10 includes M parallel basic oscillation units 11. Each basic oscillation unit 11 is a dual-output XOR gate unit based on LUT6-2, and the input terminals of all basic oscillation units 11 are connected to the CTL port. The entropy sampling circuit 20 includes N parallel D flip-flops 21 and a multi-input XOR gate 22 connected to the output terminals of all D flip-flops 21. The number of D flip-flops 21, N ≥ 4, and the number of basic oscillation units 11, M, is half the number of D flip-flops 21, rounded up. The input terminals D of all D flip-flops 21 are connected one-to-one with the output terminals of the basic oscillation units 10. For example, when there is an even number of D flip-flops 21, the output terminals of all basic oscillation units 10 are connected one-to-one with the D flip-flops 21; when there is an odd number of D flip-flops 21, one output terminal of one of the basic oscillation units 10 is left unused. The phase-locked loop 30 generates a sampling clock with the same number of phases as the number of D flip-flops 21, and the clock inputs of the D flip-flops 21 are connected one-to-one with the output terminals of the phase-locked loop 30.

[0032] It is understood that this invention employs a multi-phase fine-grained sampling mechanism for sampling, such as... Figure 3 As shown, the basic idea is to divide the jittered square wave signal into N equal parts and then sample each part. In the single-phase jitter test model, the jitter can be obtained by directly performing in-phase and neutral-phase integration on the output of the jitter signal source. Therefore, for the N-phase jitter test model, the jitter can be obtained by performing in-phase and in-phase integration on the N delayed signals respectively and then summing them. Specifically, in the single-phase jitter test model, only one point needs to be sampled in each sampling period of the jittered square wave signal; while in the N-phase jitter test model, N delays send a signal to each sampling point in each sampling period, and the difference between each sampling point is T. s / N(T s (This refers to the sampling period). Jitter is obtained by performing mid-phase integration and in-phase integration on N delayed signals respectively, and then summing them. Utilizing an N-phase jitter model, its jitter sampling accuracy is N times that of single-phase jitter sampling, representing an N-fold fine-grained jitter sampling mechanism that significantly improves the accuracy of the TRNG. Simultaneously, the basic oscillation unit is a dual-output XOR gate unit based on LUT6-2. Using LUT6_2 to implement the basic components required in the TRNG design fully utilizes the LUT resources of each SLICE, improving the versatility of the TRNG and enhancing hardware utilization to a certain extent.

[0033] At the same time, such as Figure 4As shown, the proposed invention uses a dual-output XOR gate entropy source, where each XOR gate unit is connected to a D flip-flop 21. Finally, the outputs of multiple D flip-flops 21 are XORed to produce a random sequence. It is important to note that the sampling clock for each D flip-flop 21 is different, controlled by multiple clocks of different phases generated by a phase-locked loop (PLL) 30. The multi-phase sampling clocks generated by the PLL 30 correspond one-to-one with the multi-phase jitter model in multi-phase fine-grained sampling; that is, the number of phases of the sampling clocks generated by the PLL 30 is consistent with the number of D flip-flops 21, and the clock inputs of the D flip-flops 21 are connected one-to-one with the outputs of the PLL 30.

[0034] Considering that this invention utilizes jitter as an entropy source, and that jitter can cause glitches in the output signal, thus affecting the circuit's function, this invention employs a closed-loop phase adjustment circuit with a phase-locked loop (PLL) 30 to ensure stable pulse output even in the presence of jitter. Simultaneously, by using the PLL 30 to generate sampling clocks of different phases, multi-phase sampling of the jitter circuit is performed, significantly increasing the probability of jitter sampling and ensuring the output of the random sequence.

[0035] To reduce bias and improve robustness, this invention performs an XOR operation on the output bits of multiple basic units to produce a bit whose entropy is not less than the entropy of any input bit; that is, as long as one unit produces an output with high entropy, the final output will have high entropy.

[0036] According to an embodiment of the present invention, a programmable XOR gate TRNG circuit based on multi-phase sampling improves the versatility of TRNG and enhances hardware utilization through its unique structure. The entropy source circuit of TRNG can be successfully constructed using only a single configurable logic block. Furthermore, the accuracy of TRNG is improved and the randomness is enhanced by the multi-phase fine-grained sampling mechanism, and the purpose of reducing TRNG overhead is effectively achieved.

[0037] In some embodiments of the present invention, reference is made to... Figure 1 , Figure 2 and Figure 4 As shown, the basic oscillation unit 11 includes a first XOR gate 111 and a second XOR gate 112. One input terminal of the first XOR gate 111 and one input terminal of the second XOR gate 112 are connected and serve as the input port in of the basic oscillation unit 11. The other input terminal of the first XOR gate 111 is connected to the output terminal of the first XOR gate 111, and the other input terminal of the second XOR gate 112 is connected to the output terminal of the second XOR gate 112. The output terminals of the first XOR gate 111 and the second XOR gate 112 are the two output terminals of the basic oscillation unit, which are respectively connected to the input D terminals of the two D flip-flops 21.

[0038] like Figure 1The programmable unit shown is based on an XOR gate design. When CTL=0, the gate circuit becomes a single inverter loop; when CTL=1, the gate circuit becomes a bistable loop. By controlling the CTL port, it can be ensured that the inverter loop is not in an oscillating state when the circuit requires a "sleep" state.

[0039] In some embodiments of the present invention, the two output terminals of the i-th basic oscillation unit 11 of the oscillation circuit 10 are respectively connected to the input D terminals of the i*2-1 and i*2-th D flip-flops 21 of the entropy sampling circuit 20, where i represents the sequence number of the basic oscillation unit 10, 1≤i≤M; the input terminals of all basic oscillation units 10 are connected to the CTL port. By controlling the CTL port, the circuit status can be controlled.

[0040] It is understandable that a basic oscillation unit 10 can be connected to two D flip-flops 21. By numbering the basic oscillation units 10, the connection relationship of multiple D flip-flops 21 can be defined. For example, suppose there are two basic oscillation units 11, namely the first basic oscillation unit 11-1 and the second basic oscillation unit 11-2; and four D flip-flops 21, namely the first D flip-flop 211, the second D flip-flop 212, the third D flip-flop 213, and the fourth D flip-flop 214. The first output terminal of the first basic oscillation unit 11-1 is connected to the input D terminal of the first D flip-flop 211, the second output terminal of the first basic oscillation unit 11-1 is connected to the input D terminal of the second D flip-flop 212, the first output terminal of the second basic oscillation unit 11-2 is connected to the input D terminal of the third D flip-flop 213, and the second output terminal of the second basic oscillation unit 11-2 is connected to the input D terminal of the fourth D flip-flop 214.

[0041] In some embodiments of the present invention, the clock input terminal of the j-th D flip-flop 21 of the entropy sampling circuit 20 is connected to the j-th output terminal of the phase-locked loop 30. Multiple D flip-flops 21 are driven by clocks of different phases output by the phase-locked loop 30 to obtain the original random number. The outputs of multiple D flip-flops 21 are passed through a multi-input XOR gate 22 to obtain the final random number output. j represents the sequence number of the D flip-flop 21.

[0042] Understandably, the sampling clock of the D flip-flop 21 is controlled by the phase-locked loop 30, and different outputs of the phase-locked loop 30 can be connected to the clock inputs of different D flip-flops 21. For example, for four D flip-flops 21, the clock input of the first D flip-flop 211 is connected to the first output CLK1 of the phase-locked loop 30, the clock input of the second D flip-flop 212 is connected to the second output CLK2 of the phase-locked loop 30, the clock input of the first third D flip-flop 213 is connected to the third output CLK3 of the phase-locked loop 30, and the clock input of the fourth D flip-flop 214 is connected to the fourth output CLK4 of the phase-locked loop 30.

[0043] In some embodiments of the present invention, the number of different phase sampling clocks output by the phase-locked loop 30 is consistent with the number N of the D flip-flops 21, and the k-th phase output by the phase-locked loop 30 is... Phase degree, k represents the sequence number of D flip-flop 21, 1≤k≤N.

[0044] For example, assuming there are four D flip-flops 21, the phase-locked loop 30 will have four sampling clocks with different phases: 0 degrees, 90 degrees, 180 degrees, and 270 degrees, to perform multi-phase sampling of the jitter circuit. Assuming there are five D flip-flops 21, the phase-locked loop 30 will have five sampling clocks with different phases: 0 degrees, 72 degrees, 144 degrees, 216 degrees, and 288 degrees. And so on, the phase of the phase-locked loop sampling clock is adjusted accordingly based on the number of D flip-flops 21.

[0045] The following is a reference appendix. Figures 1 to 6 The programmable XOR gate TRNG circuit based on multi-phase sampling of the present invention will be described in detail below. It is to be understood that the following description is intended to explain the invention and should not be construed as limiting it.

[0046] Example 1

[0047] Reference Figure 4 As shown, there are two basic oscillation units 11, four D flip-flops 21, and four output terminals with different phases in the phase-locked loop 30. The input terminals (D terminals) of the four D flip-flops 21 are connected to the four output terminals of the two basic oscillation units 11 respectively. The clock input terminals of the four D flip-flops 21 are connected to the four output terminals with different phases in the phase-locked loop 30 respectively. The four sampling clocks with different phases generated by the phase-locked loop 30 are the 0-degree phase sampling clock, the 90-degree phase sampling clock, the 180-degree phase sampling clock, and the 270-degree phase sampling clock, respectively, to perform four-phase sampling of the jitter circuit.

[0048] The proposed programmable XOR gate TRNG circuit based on multi-phase sampling was implemented on an AMD Xilinx Virtex-7 FPGA development board. Statistical analysis was performed by extracting multiple sets of 1M bits of data, including randomness testing and temperature-voltage resistance testing.

[0049] Specifically, the randomness test of this invention adopts the NIST SP 800-22 test. NIST SP 800-22 is a random number testing standard published by NIST. It evaluates the entropy source simply and effectively by simultaneously calculating multiple bits of data, optimizing the statistical test formula, and reducing computational complexity. It contains 15 random test items. This test mainly verifies the randomness of the random sequences generated by the proposed TRNG under normal operating voltage and temperature.

[0050] To ensure the accuracy of the experimental data and avoid the randomness of data from a single development board, the test was conducted on two development boards: a Xilinx Virtex-6 and a Xilinx Artix-7. The experiment was repeated 100 times on each board, with a sample size of 1MB for each test. The test results are as follows: Figure 5 As shown, the P-value is an indicator of the randomness of the sequence (for each test result, a P-value greater than 0.01 indicates good randomness of the tested random sequence. Of course, a larger P-value indicates better randomness and is more reliable for hardware security applications). Prop represents the probability of passing a test item (the probability of passing the test out of 100 tests). Figure 5 As shown, all test items passed the NIST SP 800-22 test with large p-values, and the Prop values ​​were close to 100%. This indicates that the random sequences generated by this TRNG structure have good randomness.

[0051] A superior TRNG can still generate high-quality random sequences under harsh environmental changes. To verify that the TRNG circuit system proposed in this invention can operate under different environmental conditions, a wide range of temperature and voltage settings were tested in this paper.

[0052] Specifically, the test temperature ranges from 0°C to 80°C in 20°C steps, and the voltage ranges from 0.8V to 1.2V in 0.2V steps. Compared to the previous method of using the NIST SP800-22 test P-value as the evaluation result, this test uses the average of the number of test items across 100 data sets generated by the Xilinx Virtex-6 FPGA under different temperatures and voltages as the evaluation metric. Figure 5 The radar chart shown has axes representing different temperatures, different colors representing corresponding voltages, and numbers on the axes representing the average proportions of NIST SP 800-22 under different operating conditions.

[0053] As can be seen, the pass rate is highest at a standard 1V voltage. The pass rate varies with temperature. Under normal temperature conditions (20℃), the pass rate is highest at 99%. As the temperature gradually increases, the pass rate decreases.

[0054] Therefore, the M_DXCO TRNG proposed in this invention can maintain an average throughput of over 93% and has a certain tolerance to temperature and voltage. In other words, the TRNG proposed in this invention can effectively and stably generate high-quality random numbers under the influence of changes in ambient temperature and voltage.

[0055] Furthermore, based on the proposed multi-phase fine-grained jitter sampling mechanism, it was found that many random sequences obtained through three-phase sampling failed the NIST SP800-22 test when selecting the phase level. When selecting four-phase or higher levels, all random sequences passed the test, with four-phase being the optimal choice.

[0056] In summary, this invention utilizes a multi-phase fine-grained sampling mechanism to effectively capture circuit jitter with high accuracy. It employs a closed-loop phase adjustment circuit with a phase-locked loop to ensure stable pulse output even with jitter, increasing the probability of jitter sampling and guaranteeing the output of random sequences. The circuit system's structure is based on an innovative programmable XOR gate unit, and the entropy source circuit of the TRNG can be constructed using only a single configurable logic block, effectively reducing the hardware overhead of the RO TRNG.

[0057] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0058] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0059] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0060] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0061] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0062] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A programmable XOR gate TRNG circuit based on multi-phase sampling, characterized in that, include: An oscillation circuit for generating irregular oscillation output signals includes M parallel basic oscillation units, wherein the basic oscillation unit is a dual-output XOR gate unit based on LUT6-2. An entropy sampling circuit is used to sample the oscillation signal generated by the oscillation circuit to obtain the original random sequence. It includes N parallel D flip-flops and a multi-input XOR gate connected to the output of all the D flip-flops. Phase-locked loop (PLL) is used to generate sampling clocks with multiple different phases; Wherein, the number of D flip-flops N≥4, the number of basic oscillation units M is half of the number of D flip-flops N rounded up, and the input D terminals of all D flip-flops are connected one-to-one with the output terminals of the basic oscillation units; the number of phases of the sampling clock generated by the phase-locked loop is consistent with the number of D flip-flops, and the clock input of the D flip-flops is connected one-to-one with the output terminals of the phase-locked loop.

2. The programmable XOR gate TRNG circuit based on multi-phase sampling according to claim 1, characterized in that, The basic oscillation unit includes a first XOR gate and a second XOR gate. One input terminal of the first XOR gate and one input terminal of the second XOR gate are connected and serve as the input port in of the basic oscillation unit. The other input terminal of the first XOR gate is connected to the output terminal of the first XOR gate, and the other input terminal of the second XOR gate is connected to the output terminal of the second XOR gate. The output terminals of the first XOR gate and the second XOR gate are the two output terminals of the basic oscillation unit, which are respectively connected to the input terminals D of the two D flip-flops.

3. The programmable XOR gate TRNG circuit based on multi-phase sampling according to claim 2, characterized in that, The two output terminals of the i-th basic oscillation unit of the oscillation circuit are connected to the input D terminals of the i*2-1 and i*2-th D flip-flops of the entropy sampling circuit, respectively, where i represents the sequence number of the basic oscillation unit, and 1≤i≤M.

4. The programmable XOR gate TRNG circuit based on multi-phase sampling according to claim 2, characterized in that, The clock input of the j-th D flip-flop in the entropy sampling circuit is connected to the j-th output of the phase-locked loop. Multiple D flip-flops are driven by clocks of different phases output by the phase-locked loop to obtain the original random number. The outputs of the multiple D flip-flops are passed through a multi-input XOR gate to obtain the final random number output. j represents the sequence number of the D flip-flop.

5. A programmable XOR gate TRNG circuit based on multi-phase sampling according to claim 1, characterized in that, The number of different phase sampling clocks output by the phase-locked loop is consistent with the number N of the D flip-flops. The k-th phase output by the phase-locked loop is... Phase degree, k represents the index of the D flip-flop, 1≤k≤N.

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