A high-precision phase adjustment system and method based on delay line

Abstract

The application relates to a high-precision phase adjustment system and method based on a delay line, which comprises a local atomic clock, a PLL phase-locked loop, a TDC phase detector, an FPGA phase detector, a phase detection processor, a delay line phase modulation module and a clock output circuit; the PLL phase-locked loop processes a clock output by the local atomic clock to provide a working clock for the TDC phase detector and the FPGA phase detector; the TDC phase detector performs phase detection on a frequency division clock output by the FPGA phase detector and an external clock input, and outputs a phase detection result to the phase detection processor; the phase detection processor processes a collected phase detection value to obtain a phase modulation value, and analyzes and judges whether coarse adjustment or fine adjustment is performed on the phase modulation value and then outputs. The application adopts the delay line adjustment technology, so that the phase adjustment of the equipment can reach the ps level, thereby improving the synchronization precision between the equipment.

Description

Technical Field

[0001] This invention relates to the field of phase adjustment technology, and in particular to a high-precision phase adjustment system and method based on delay lines. Background Technology

[0002] With the development of society, the construction of national defense has put forward increasingly higher requirements for time and frequency accuracy. The accuracy of traditional time and frequency synchronization equipment is generally tens of nanoseconds, which no longer meets the accuracy requirements of national defense construction. Moreover, traditional phase adjustment technology uses FPGA adjustment, but due to the resource clock limitation of FPGA, the phase adjustment range is limited.

[0003] Patent CN113938128A discloses a phase adjustment method, apparatus, terminal device, and storage medium, comprising: acquiring the input frequency of an input signal; adjusting the output frequency of an output signal according to the input frequency; acquiring the phase difference between the input and output signals when the output frequency is the same as the input frequency; and adjusting the output frequency of the output signal according to a preset rule when a zero-crossing point of the input signal is detected, so that the phase difference between the input and output signals is 0. In this embodiment, when an input signal is detected, the output signal frequency is first adjusted to match the input signal frequency, then the output signal frequency is finely adjusted, waiting for the zero-crossing points of the input and output signals to coincide, and finally the output signal frequency is restored to achieve phase synchronization. However, this method only proposes a phase adjustment method, performing phase adjustment after detecting the phase difference between the input and output signals, but does not explain how to adjust when the phase deviation is at the ps level.

[0004] Patent CN109981091A discloses a high-precision phase adjustment device for a microstrip delay line, comprising a delay line microstrip board. The delay line microstrip board is equipped with a first microstrip delay component, a second microstrip delay component, a third microstrip delay component, a fourth microstrip delay component, and a fifth microstrip delay component. The first microstrip delay component tests and adjusts a 1λ-bit delay state and the ground state; the second microstrip delay component tests and adjusts a 2λ-bit delay state and the ground state; the third microstrip delay component tests and adjusts a 4λ-bit delay state and the ground state; the fourth microstrip delay component tests and adjusts an 8λ-bit delay state and the ground state; and the fifth microstrip delay component tests and adjusts an 8λ-bit delay state and the ground state. Adjacent microstrip delay components are connected via microstrip transmission lines. This invention achieves high-precision phase adjustment within 45 degrees of the delay line phase through flexible combination and phase adjustment of the various microstrip delay components. The patent proposes a method for adjusting the phase using delay lines. However, this method uses multiple sets of delay lines. In the time-frequency domain, if the error of the predecessor is introduced into the error of the next stage, it will cause a loss of output accuracy and increase the cost. Therefore, this method is not suitable for high-precision time-frequency phase adjustment.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide a high-precision phase adjustment system and method based on delay lines, thus solving the deficiencies in the prior art.

[0007] The objective of this invention is achieved through the following technical solution: a high-precision phase adjustment system based on a delay line, comprising: a local atomic clock, a PLL phase-locked loop, a TDC phase detector, an FPGA phase detector, a phase detector processor, a delay line phase adjustment module, and a clock output circuit; The PLL phase-locked loop processes the clock output from the local atomic clock to provide the working clock for the TDC phase detector and the FPGA phase detector. The TDC phase detector performs phase detection by comparing the frequency-divided clock output from the FPGA phase detector with the input external clock, and outputs the phase detection result to the phase detection processor. The phase detector processor processes the acquired phase detection values ​​to obtain phase modulation values, analyzes and judges the phase modulation values, and performs coarse adjustment through the FPGA phase detector or fine adjustment through the delay line phase modulation module based on the analysis and judgment results. When the phase detector's analysis and judgment result meets the requirements for fine-tuning the system phase, the delay line phase adjustment module uses a delay line for fine-tuning and outputs the result through a clock output circuit. The FPGA phase detector is used to output a frequency-divided clock to the TDC phase detector, and when the phase detector processor analyzes and judges that the coarse adjustment is satisfied, it first performs a coarse adjustment on the system phase and then a fine adjustment, and outputs the clock output circuit.

[0008] The FPGA phase detector includes an FPGA phase tuner and a frequency divider; the frequency divider outputs a divided clock to the TDC phase detector; when the phase detector processor calculates and analyzes the acquired phase values ​​and the coarse adjustment is satisfied, the FPGA phase tuner first performs coarse adjustment on the system phase and then fine adjustment, and outputs the clock output circuit.

[0009] The phase detection processor includes a low-pass filter processor and a Kalman filter processor. The acquired data is first passed through the low-pass filter processor to remove outliers in the acquired phase detection data, and then passed through the Kalman filter processor to reduce noise. The two filter processors reduce noise and jitter interference caused by the device, thereby restoring the true phase detection data. The model of the low-pass filter processor is as follows: ,in, This is the current sampled value. This is the value from the previous sample. This is the output value from the previous low-pass filter. This is the current low-pass filter output value. Indicates the sampling time. The filter time constant is used to ensure that low-frequency signals can pass through normally, while high-frequency signals exceeding the set threshold are blocked or weakened. This ensures that the acquired phase detection values ​​fluctuate within the preset range, eliminates outliers, and guarantees the phase detection accuracy of the device.

[0010] The gain equation of the Kalman filter processor is: H is the observation matrix, and R is the covariance matrix of the measurement noise; the output equation is: The optimal value of the state change at time k is calculated based on the predicted value of the state change and the actual phase detection value; the covariance equation is: Solving for the covariance matrix at time k prepares for obtaining the Kalman output value at time k, where I is the identity matrix; noise is removed by the Kalman filter processor to restore the true data and reduce the influence of noise and interference.

[0011] The delay line phase modulation module includes a programmable gate circuit and a multiplexer matrix connected to the programmable gate circuit. Ten data selection inputs D are also connected to the programmable gate circuit for selection, and are latched on the chip by a high-level signal on the LEN latch enable control. The desired delay can be selected through these data selection inputs D.

[0012] A high-precision phase adjustment method based on a delay line, the method comprising a phase detection value acquisition step and a phase adjustment value analysis and judgment step; the phase adjustment value analysis and judgment step includes: Calculate the phase adjustment value Value and determine whether the phase adjustment value Value is greater than the preset value. If it is greater than the preset value, use the FPGA phase detector to perform coarse phase adjustment, and the phase adjustment value is Value - Value%10. If fine adjustment is then performed through the delay line phase adjustment module, the fine adjustment phase adjustment value is Value%10. If it is less than the preset value, the phase adjustment module of the delay line will be used directly for fine adjustment, and the phase adjustment value will be Value.

[0013] The phase detection value acquisition step includes: The local atomic clock outputs a 10MHz clock signal to the PLL phase-locked loop, which provides the operating clock for the TDC phase detector and the FPGA phase detector. The TDC phase detector uses the divided clock output from the frequency divider in the FPAG phase detector and the input external clock to perform phase detection, and sends the detected phase value to the phase detection processor. The phase detector processor processes the acquired phase detection values ​​to calculate the system phase adjustment value.

[0014] The present invention has the following advantages: a high-precision phase adjustment system and method based on delay lines, which uses delay line adjustment technology to enable the phase adjustment of the equipment to reach the picosecond level, thereby improving the synchronization accuracy between the equipment; the delay line adopts a software control and hardware adjustment method, which reduces the difficulty of engineering implementation and enhances the reliability of the equipment. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the system of the present invention; Figure 2 This is a schematic diagram of the delay line phase modulation module; Figure 3 Select the phase adjustment plot corresponding to the input D value for different data; Figure 4 This is a schematic diagram of the phase adjustment process of the present invention. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of this application provided below with reference to the accompanying drawings is not intended to limit the scope of protection of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application. The present invention will be further described below with reference to the accompanying drawings.

[0017] like Figure 1 As shown, one embodiment of the present invention relates to a high-precision phase adjustment system based on a delay line, which includes: a local atomic clock, a PLL phase-locked loop, a TDC phase detector, an FPGA phase detector, a phase detector processor, a delay line phase adjustment module, and a clock output circuit. Furthermore, the PLL processes the 10MHz clock output from the local atomic clock to provide the operating clock for the TDC phase detector and the FPGA phase detector; wherein, the PLL provides the FPGA with a 100MHz operating clock.

[0018] Furthermore, the TDC phase detector uses the 1PPS divider in the FPGA phase detector to output a divided clock and compare it with the input external clock for phase detection, and outputs the phase detection result to the phase detection processor. The TDC phase detector adopts a dual-channel measurement mode with a measurement accuracy of 90ps and an offset adjustment range of ±35mV, which ensures that the front-end acquisition accuracy can reach the ps level, providing high-precision input data for subsequent phase adjustment.

[0019] Furthermore, the phase detector processor processes the acquired phase detection values ​​to obtain phase modulation values, analyzes and judges the phase modulation values, and performs coarse adjustment through the FPGA phase detector or fine adjustment through the delay line phase modulation module based on the analysis and judgment results. Furthermore, when the phase detector's analysis and judgment result meets the requirements for fine-tuning the system phase, the delay line phase adjustment module uses a delay line for fine-tuning and outputs the result through a clock output circuit. Furthermore, the FPGA phase detector is used to output a frequency-divided clock to the TDC phase detector, and when the phase detector processor analyzes and judges that the coarse adjustment is satisfied, it first performs coarse adjustment on the system phase and then fine adjustment, and outputs the clock through the clock output circuit, so that the output accuracy of the system can be guaranteed to be high-precision output within a few nanoseconds.

[0020] Furthermore, the FPGA phase detector includes an FPGA phase modulator and a 1PPS frequency divider. The frequency divider outputs a divided clock to the TDC phase detector. When the phase detector processor calculates and analyzes the acquired phase values ​​to meet the coarse adjustment requirements, the FPGA phase modulator first performs coarse adjustment of the system phase and then fine adjustment, outputting the result through a clock output circuit. This ensures that the system's output accuracy is within a few nanoseconds. The phase adjustment accuracy of the FPGA phase modulator is 10ns.

[0021] Furthermore, the phase detection processor includes a low-pass filter processor and a Kalman filter processor. The acquired data is first passed through the low-pass filter processor to remove outliers in the acquired phase detection data, and then passed through the Kalman filter processor to reduce noise. The two filter processors reduce noise and jitter interference caused by the device, thereby restoring the true phase detection data. The model for the low-pass filter processor is as follows: ,in, This is the current sampled value. This is the value from the previous sample. This is the output value from the previous low-pass filter. This is the current low-pass filter output value. Indicates the sampling time. The filter time constant is used to ensure that low-frequency signals can pass through normally, while high-frequency signals exceeding the set threshold are blocked or weakened. This ensures that the acquired phase detection values ​​fluctuate within the preset range, eliminates outliers, and guarantees the phase detection accuracy of the device.

[0022] The gain equation for the Kalman filter processor is as follows: H is the observation matrix, and R is the covariance matrix of the measurement noise; the output equation is: The optimal value of the state change at time k is calculated based on the predicted value of the state change and the actual phase detection value; the covariance equation is: Solving for the covariance matrix at time k prepares for obtaining the Kalman output value at time k, where I is the identity matrix; noise is removed and the true data is restored through the Kalman filter processor. When the measurement variance is known, the Kalman filter can update and process the data in real time from a series of data containing measurement noise, reducing the impact of noise and interference.

[0023] like Figure 2 As shown, the delay line phase modulation module includes a programmable gate circuit and a multiplexer matrix connected to the programmable gate circuit. Ten data selection inputs D are also connected to the programmable gate circuit for selection, and are latched on the chip by a high-level signal on the LEN latch enable control. The desired delay can be selected through these data selection inputs D.

[0024] like Figure 3 As shown, to control the delay data to 160ps, the D(9:0) value needs to be written as 0000010000, and D10(LEN) needs to be written as 1. The output signal will then be delayed by 160ps relative to the input signal. This ensures that the device can perform phase adjustment at the ps level. The digital resolution of the delay line is 10ps, the adjustment range is 0 to 10.4ns, and the required delay is input by 10 data D[9,0] and controlled by LEN, thus ensuring that the system has a ps-level 0 adjustment.

[0025] like Figure 4 As shown, another embodiment of the present invention relates to a high-precision phase adjustment method based on a delay line, the adjustment method including a phase detection value acquisition step and a phase adjustment value analysis and judgment step; The phase detection value acquisition steps include: The local atomic clock outputs a 10MHz clock signal to the PLL phase-locked loop, which provides the operating clock for the TDC phase detector and the FPGA phase detector. The TDC phase detector uses the divided clock output from the frequency divider in the FPAG phase detector and the input external clock to perform phase detection, and sends the detected phase value to the phase detection processor. The phase detector processor processes the acquired phase detection values ​​to calculate the system phase adjustment value.

[0026] The phase modulation value analysis and judgment steps include: Calculate the phase adjustment value Value and determine whether the phase adjustment value Value is greater than the preset value. If it is greater than the preset value, use the FPGA phase detector to perform coarse phase adjustment, and the phase adjustment value is Value - Value%10. If fine adjustment is then performed through the delay line phase adjustment module, the fine adjustment phase adjustment value is Value%10. If the value is less than the preset value, the delay line phase adjustment module is used for fine-tuning, with the phase adjustment value being Value. This ensures that the system performs phase adjustment at the ps level, improving the accuracy of the equipment.

[0027] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A high-precision phase adjustment system based on a delay line, characterized in that: It includes: Local atomic clock, PLL phase-locked loop, TDC phase detector, FPGA phase detector, phase detector processor, delay line phase modulation module and clock output circuit; The PLL phase-locked loop processes the clock output from the local atomic clock to provide the working clock for the TDC phase detector and the FPGA phase detector. The TDC phase detector performs phase detection by comparing the frequency-divided clock output from the FPGA phase detector with the input external clock, and outputs the phase detection result to the phase detection processor. The phase detector processor processes the acquired phase detection values ​​to obtain phase modulation values, analyzes and judges the phase modulation values, and performs coarse adjustment through the FPGA phase detector or fine adjustment through the delay line phase modulation module based on the analysis and judgment results. When the phase detector's analysis and judgment result meets the requirements for fine-tuning the system phase, the delay line phase adjustment module uses a delay line for fine-tuning and outputs the result through a clock output circuit. The FPGA phase detector is used to output a frequency-divided clock to the TDC phase detector, and when the phase detector processor analyzes and judges that the coarse adjustment is satisfied, it first performs coarse adjustment on the system phase and then fine adjustment, and outputs the clock output circuit. The phase detection processor includes a low-pass filter processor and a Kalman filter processor. The acquired data is first passed through the low-pass filter processor to remove outliers in the acquired phase detection data, and then passed through the Kalman filter processor to reduce noise. The two filter processors reduce noise and jitter interference caused by the device, thereby restoring the true phase detection data. The model of the low-pass filter processor is as follows: ,in, This is the current sampled value. This is the value from the previous sample. This is the output value of the previous low-pass filter. This is the current low-pass filter output value. Indicates the sampling time. The filter time constant is used to ensure that low-frequency signals can pass through normally, while high-frequency signals exceeding the set threshold are blocked or weakened. This ensures that the acquired phase detection values ​​fluctuate within the preset range, eliminates outliers, and guarantees the phase detection accuracy of the device. The gain equation of the Kalman filter processor is: H is the observation matrix, and R is the covariance matrix of the measurement noise; the output equation is: The optimal value of the state change at time k is calculated based on the predicted value of the state change and the actual phase detection value; the covariance equation is: Solving for the covariance matrix at time k prepares for obtaining the Kalman output value at time k, where I is the identity matrix; noise is removed by the Kalman filter processor to restore the true data and reduce the influence of noise and interference.

2. The high-precision phase adjustment system based on a delay line according to claim 1, characterized in that: The FPGA phase detector includes an FPGA phase tuner and a frequency divider; the frequency divider outputs a divided clock to the TDC phase detector; when the phase detector processor calculates and analyzes the acquired phase values ​​and the coarse adjustment is satisfied, the FPGA phase tuner first performs coarse adjustment on the system phase and then fine adjustment, and outputs the clock output circuit.

3. The high-precision phase adjustment system based on a delay line according to claim 1, characterized in that: The delay line phase modulation module includes a programmable gate circuit and a multiplexer matrix connected to the programmable gate circuit. Ten data selection inputs D are also connected to the programmable gate circuit for selection, and are latched on the chip by a high-level signal on the LEN latch enable control. The desired delay can be selected through these data selection inputs D.

4. A high-precision phase adjustment method based on delay lines, characterized in that: The high-precision phase adjustment system based on a delay line according to any one of claims 1 to 3, wherein the adjustment method includes a phase detection value acquisition step and a phase adjustment value analysis and judgment step; the phase adjustment value analysis and judgment step includes: Calculate the phase adjustment value Value and determine whether the phase adjustment value Value is greater than the preset value. If it is greater than the preset value, use the FPGA phase detector to perform coarse phase adjustment, and the phase adjustment value is Value - Value%10. If fine adjustment is then performed through the delay line phase adjustment module, the fine adjustment phase adjustment value is Value%10. If it is less than the preset value, the phase adjustment module of the delay line will be used directly for fine adjustment, and the phase adjustment value will be Value.

5. The high-precision phase adjustment method based on a delay line according to claim 4, characterized in that: The phase detection value acquisition step includes: The local atomic clock outputs a 10MHz clock signal to the PLL phase-locked loop, which provides the operating clock for the TDC phase detector and the FPGA phase detector. The TDC phase detector uses the divided clock output from the frequency divider in the FPAG phase detector and the input external clock to perform phase detection, and sends the detected phase value to the phase detection processor. The phase detector processor processes the acquired phase detection values ​​to calculate the system phase adjustment value.

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